AD8108_05 [ADI]
325 MHz, 8 Ã 8 Buffered Video Crosspoint Switches; 325兆赫， 8 ？ 8缓冲视频交叉点开关
| 型号： | AD8108_05 |
| 厂家： | 
ADI |
| 描述： | 325 MHz, 8 Ã 8 Buffered Video Crosspoint Switches |
| 文件： | 总33页 (文件大小：994K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
325 MHz, 8 × 8 Buffered Video
Crosspoint Switches
AD8108/AD8109
FUNCTIONAL BLOCK DIAGRAM
EATURES
SER/PAR D0 D1 D2 D3
8 × 8 high speed nonblocking switch arrays
AD8108: G = 1
A0
A1
AD8109: G = 2
Serial or parallel programming of switch array
CLK
A2
32-BIT SHIFT REGISTER
WITH 4-BIT
PARALLEL LOADING
Serial data out allows daisy-chaining of multiple 8 × 8 arrays
to create larger switch arrays
Output disable allows connection of multiple devices
Pin-compatible with AD8110/AD8111 16 × 8 switch arrays
For 16 × 16 arrays see AD8116
Complete solution
DATA
OUT
DATA IN
UPDATE
32
SET INDIVIDUAL
OR RESET ALL
OUTPUTS
PARALLEL LATCH
32
CE
RESET
TO "OFF"
8
DECODE
Buffered inputs
8 4:8 DECODERS
Eight output amplifiers
AD8108 (G = 1)
OUTPUT
BUFFER
G = +1
AD8108/AD8109
64
G = +2
AD8109 (G = 2)
Drives 150 Ω loads
Excellent video performance
60 MHz 0.1 dB gain flatness
0.02%/0.02° differential gain/differential phase error
(RL = 150 Ω)
SWITCH
MATRIX
8 OUTPUTS
8 INPUTS
Excellent ac performance
−3 dB bandwidth: 325 MHz (AD8108), 250 MHz (AD8109)
Slew rate: 400 V/μs (AD8108), 480 V/μs (AD8109)
Low power of 45 mA
Low all hostile crosstalk of −83 dB @ 5 MHz
Reset pin allows disabling of all outputs (connected through
a capacitor to ground provides power-on reset capability)
Figure 1. Functional Block Diagram
Excellent ESD rating: exceeds 4000 V human body model
80-lead LQFP (12 mm × 12 mm)
and 0.02°, respectively, along with 0.1 dB flatness out to 60 MHz,
make the AD8108/AD8109 ideal for video signal switching.
APPLICATIONS
The AD8108 and AD8109 include eight independent output
buffers that can be placed into a high impedance state for paral-
leling crosspoint outputs so that off channels do not load the
output bus. The AD8108 has a gain of 1, while the AD8109
offers a gain of 2. They operate on voltage supplies of 5 V
while consuming only 45 mA of idle current. The channel
switching is performed via a serial digital control (which can
accommodate daisy-chaining of several devices) or via a parallel
control allowing updating of an individual output without
re-programming the entire array.
Routing of high speed signals including
Composite video (NTSC, PAL, S, SECAM)
Component video (YUV, RGB)
Compressed video (MPEG, Wavelet)
3-level digital video (HDB3)
GENERAL DESCRIPTION
The AD8108/AD8109 are high speed 8 × 8 video crosspoint
switch matrices. They offer a −3 dB signal bandwidth greater than
250 MHz and channel switch times of less than 25 ns with 1%
settling. With −83 dB of crosstalk and −98 dB isolation (@5 MHz),
the AD8108/AD8109 are useful in many high speed applications.
The differential gain and differential phase of better than 0.02%
The AD8108/AD8109 is packaged in an 80-lead LQFP package
and is available over the extended industrial temperature range
of −40°C to +85°C.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
© 2005 Analog Devices, Inc. All rights reserved.
IMPORTANT LINKS for the AD8108_8109*
Last content update 08/23/2013 02:21 pm
PARAMETRIC SELECTION TABLES
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DOCUMENTATION
AN-282: Fundamentals of Sampled Data Systems
Data-acquisition system uses fault protection
CMOS Switches Offer High Performance in Low Power, Wideband
Applications
DESIGN SUPPORT
Submit your support request here:
Linear and Data Converters
Embedded Processing and DSP
Enhanced Multiplexing for MEMS Optical Cross Connects
FOR THE AD8108
AN-214: Ground Rules for High Speed Circuits
Telephone our Customer Interaction Centers toll free:
Americas:
Europe:
China:
1-800-262-5643
00800-266-822-82
4006-100-006
1800-419-0108
8-800-555-45-90
EVALUATION KITS & SYMBOLS & FOOTPRINTS
India:
View the Evaluation Boards and Kits page for the AD8108
Russia:
View the Evaluation Boards and Kits page for the AD8109
Symbols and Footprints for the AD8108
Quality and Reliability
Lead(Pb)-Free Data
Symbols and Footprints for the AD8109
SAMPLE & BUY
AD8108
AD8109
View Price & Packaging
Request Evaluation Board
Request Samples
Check Inventory & Purchase
Find Local Distributors
* This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet.
Note: Dynamic changes to the content on this page (labeled 'Important Links') does not
constitute a change to the revision number of the product data sheet.
This content may be frequently modified.
AD8108/AD8109
TABLE OF CONTENTS
AD8108/AD8109—Specifications ................................................. 3
Power-On
....................................................................... 19
RESET
Timing Characteristics (Serial) .................................................. 5
Timing Characteristics (Parallel) ............................................... 6
Absolute Maximum Ratings............................................................ 8
Maximum Power Dissipation ..................................................... 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Typical Performance Characteristics ........................................... 11
I/O Schematics................................................................................ 17
Theory of Operation ...................................................................... 18
Applications................................................................................. 18
Gain Selection............................................................................. 19
Creating Larger Crosspoint Arrays.......................................... 20
Multichannel Video ................................................................... 21
Crosstalk...................................................................................... 22
PCB Layout...................................................................................... 24
Evaluation Board ............................................................................ 28
Control the Evaluation Board from a PC................................ 28
Overshoot of PC Printer Ports’ Data Lines............................. 28
Outline Dimensions....................................................................... 30
Ordering Guide .......................................................................... 30
REVISION HISTORY
9/05—Rev. A to Rev. B
Updated Format.................................................................. Universal
Change to Absolute Maximum Ratings..........................................8
Changes to Maximum Power Dissipation Section........................8
Change to Figure 4 ............................................................................8
Updated Outline Dimensions........................................................30
Changes to Ordering Guide ...........................................................30
1/02—Rev. 0 to Rev. A
Universal change in nomenclature from MQFP to LQFP .............
Comment added to OUTLINE DIMENSIONS ..........................27
Revision 0: Initial Version
Rev. B | Page 2 of 32
AD8108/AD8109
AD8108/AD8109—SPECIFICATIONS
VS = 5 V, TA = +25°C, RL = 1 kΩ, unless otherwise noted.
Table 1.
Parameter
Conditions
Min
Typ
Max
Unit
Reference
DYNAMIC PERFORMANCE
−3 dB Bandwidth
200 mV p-p, RL = 150 Ω
2 V p-p, RL = 150 Ω
240/150
325/250
140/160
MHz
MHz
Figure 1,
Figure 13
Figure 1,
Figure 13
Propagation Delay
Slew Rate
Settling Time
2 V p-p, RL = 150 Ω
2 V Step, RL = 150 Ω
0.1%, 2 V Step, RL = 150 Ω
5
ns
V/µs
ns
400/480
40
Figure 15,
Figure 18
Gain Flatness
0.05 dB, 200 mV p-p, RL = 150 Ω
0.05 dB, 2 V p-p, RL = 150 Ω
0.1 dB, 200 mV p-p, RL = 150 Ω
0.1 dB, 2 V p-p, RL = 150 Ω
60/50
60/50
70/65
80/50
MHz
MHz
MHz
MHz
Figure 1,
Figure 13
Figure 1,
Figure 13
Figure 1,
Figure 13
Figure 1,
Figure 13
NOISE/DISTORTION PERFORMANCE
Differential Gain Error
NTSC or PAL, RL = 1 kΩ
NTSC or PAL, RL = 150 Ω
NTSC or PAL, RL = 1 kΩ
NTSC or PAL, RL = 150 Ω
f = 5 MHz
0.01
0.02
0.01
0.02
83/85
%
%
Differential Phase Error
Crosstalk, All Hostile
Degrees
Degrees
dB
Figure 8,
Figure 14
f = 10 MHz
76/83
93/98
15
dB
Figure 8,
Figure 14
Figure 23,
Figure 29
Figure 20,
Figure 26
Off Isolation, Input-Output
Input Voltage Noise
f = 10 MHz, RL =150 Ω,
one channel
0.01 MHz to 50 MHz
dB
nV/√Hz
DC PERFORMANCE
Gain Error
RL = 1 kΩ
0.04/0.1
0.07/0.5
%
RL = 150 Ω
0.15/0.25
%
Gain Matching
No load, channel-channel
RL = 1 kΩ, channel-channel
0.02/1.0
0.09/1.0
%
%
Gain Temperature Coefficient
OUTPUT CHARACTERISTICS
Output Impedance
0.5/8
ppm/°C
DC, enabled
Disabled
0.2
Ω
Figure 24,
Figure 30
Figure 21,
Figure 27
10/0.001
MΩ
Output Disable Capacitance
Output Leakage Current
Output Voltage Range
Output Current
Disabled
Disabled, AD8108 only
No load
2
pF
µA
V
mA
mA
1/NA
3
40
65
2.5
20
Short-Circuit Current
Rev. B | Page 3 of 32
AD8108/AD8109
Parameter
Conditions
Min
Typ
Max
Unit
Reference
INPUT CHARACTERISTICS
Input Offset Voltage
Worst case (all configurations)
Temperature coefficient
5
20
mV
Figure 35,
Figure 41
Figure 36,
Figure 42
12
µV/°C
Input Voltage Range
Input Capacitance
Input Resistance
2.5/ 1.25
3/ 1.5
V
Any switch configuration
Per output selected
2.5
10
2
pF
MΩ
µA
1
Input Bias Current
5
SWITCHING CHARACTERISTICS
Enable On Time
60
ns
Switching Time, 2 V Step
Switching Transient (Glitch)
50% UPDATE to 1% settling
Measured at output
25
ns
20/30
mV p-p
Figure 22,
Figure 28
POWER SUPPLIES
Supply Current
AVCC, outputs enabled, no load
AVCC, outputs disabled
AVEE, outputs enabled, no load
AVEE, outputs disabled
DVCC
33
10
33
10
mA
mA
mA
mA
mA
V
10
Supply Voltage Range
PSRR
4.5 to 5.5
73/78
f = 100 kHz
f = 1 MHz
dB
Figure 19,
Figure 25
55/58
dB
OPERATING TEMPERATURE RANGE
Temperature Range
θJA
Operating (still air)
Operating (still air)
−40 to +85
48
°C
°C/W
Rev. B | Page 4 of 32
AD8108/AD8109
TIMING CHARACTERISTICS (SERIAL)
Table 2. Timing Characteristics
Parameter
Symbol
Min
20
100
20
100
0
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
Serial Data Setup Time
CLK Pulse Width
Serial Data Hold Time
CLK Pulse Separation, Serial Mode
CLK to UPDATE Delay
t1
t2
t3
t4
t5
t6
t7
–
UPDATE Pulse Width
50
CLK to DATA OUT Valid, Serial Mode
Propagation Delay, UPDATE to Switch On or Off
Data Load Time, CLK = 5 MHz, Serial Mode
CLK, UPDATE Rise and Fall Times
RESET Time
180
8
–
–
6.4
100
–
200
Table 3. Logic Levels
VIH
VIL
VOH
VOL
IIH
IIL
IOH
IOL
RESET, SER/PAR
CLK, DATA IN,
CE, UPDATE
RESET, SER/PAR
CLK, DATA IN,
CE, UPDATE
DATA OUT
DATA OUT
RESET, SER/PAR
CLK, DATA IN,
CE, UPDATE
RESET, SER/PAR
CLK, DATA IN,
CE, UPDATE
DATA OUT
DATA OUT
2.0 V min
0.8 V max
2.7 V min
0.5 V max
20 µA max
−400 µA min
−400 µA max
3.0 mA min
t2
t4
1
CLK
0
LOAD DATA INTO
SERIAL REGISTER
ON FALLING EDGE
t1
t3
1
DATA IN
0
OUT7 (D2)
OUT00 (D0)
OUT7 (D3)
t5
t6
1 = LATCHED
UPDATE
TRANSFER DATA FROM SERIAL
REGISTER TO PARALLEL
LATCHES DURING LOW LEVEL
0 = TRANSPARENT
t7
DATA OUT
Figure 2. Timing Diagram, Serial Mode
Rev. B | Page 5 of 32
AD8108/AD8109
TIMING CHARACTERISTICS (PARALLEL)
Table 4. Timing Characteristics
Parameter
Symbol
Min
20
100
20
100
0
Typ
Max
Unit
ns
ns
ns
ns
Data Setup Time
CLK Pulse Width
Data Hold Time
CLK Pulse Separation
CLK to UPDATE Delay
UPDATE Pulse Width
Propagation Delay, UPDATE to Switch On or Off
CLK, UPDATE Rise and Fall Times
RESET Time
t1
t2
t3
t4
t5
t6
–
ns
50
ns
8
ns
–
100
ns
–
200
ns
Table 5. Logic Levels
VIH
VIL
VOH
VOL
IIH
IIL
IOH
IOL
RESET, SER/PAR
CLK, D0, D1, D2,
D3, A0, A1, A2
CE, UPDATE
RESET, SER/PAR
CLK, D0, D1, D2,
D3, A0, A1, A2
CE, UPDATE
DATA OUT
DATA OUT
RESET, SER/PAR
CLK, D0, D1, D2,
D3, A0, A1, A2
CE, UPDATE
RESET SER/PAR
CLK, D0, D1, D2,
D3, A0, A1, A2
CE, UPDATE
DATA OUT
DATA OUT
2.0 V min
0.8 V max
2.7 V min
0.5 V max
20 µA max
−400 µA min
−400 µA max
3.0 mA min
t2
t4
1
CLK
0
t1
t3
1
0
D0–D3
A0–A2
t5
t6
1 = LATCHED
UPDATE
0 = TRANSPARENT
Figure 3. Timing Diagram, Parallel Mode
Rev. B | Page 6 of 32
AD8108/AD8109
Table 6. Operation Truth Table
SER/
PAR
UPDATE
RESET
CE
1
0
CLK DATA IN
DATA OUT
X
Datai-32
Operation/Comment
X
1
X
X
X
1
X
0
No change in logic.
Datai
The data on the serial DATA IN line is loaded into serial register. The
first bit clocked into the serial register appears at DATA OUT 32 clocks
later.
f
0
0
X
1
0
X
D0 … D3, NA in parallel
1
1
0
1
X
X
The data on the parallel data lines, D0 to D3, are loaded into the
32-bit serial shift register location addressed by A0 to A2.
Data in the 32-bit shift register transfers into the parallel latches that
control the switch array. Latches are transparent.
Asynchronous operation. All outputs are disabled. Remainder of logic
is unchanged.
f
A0 … A2
mode
X
X
X…
X
X
X
D0
D1
D2
D3
PARALLEL DATA
(OUTPUT ENABLE)
SER/PAR
S
D1
S
D1
S
D1
S
D1
S
D1
S
D1
S
D1
S
D1
S
D1
S
D1
D Q
CLK
Q
Q
D
Q
Q
DQ
Q
DQ
Q
DQ
Q
DQ
DQ
DQ
Q
DQ
Q
Q
DQ
Q
DATA IN
(SERIAL)
DATA
OUT
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CE
RESET
OUT0 EN
OUT1 EN
OUT2 EN
OUT3 EN
OUT4 EN
OUT5 EN
OUT6 EN
OUT7 EN
A0
A1
A2
D
D
D
D
D
D
D
D
D
D
LE
LE
LE
LE
LE
LE
LE
LE
LE
LE
OUT0
B0
OUT0
B1
OUT0
B2
OUT0
EN
OUT1
B0
OUT6
EN
OUT7
B0
OUT7
B1
OUT7
B2
OUT7
EN
Q
Q
Q
Q
Q
Q
Q
CLR
Q
CLR
Q
CLR Q
DECODE
8
OUTPUT ENABLE
64
SWITCH MATRIX
Figure 4. Logic Diagram
Rev. B | Page 7 of 32
AD8108/AD8109
ABSOLUTE MAXIMUM RATINGS
Table 7.
Parameter
Supply Voltage
Internal Power Dissipation1
AD8108/AD8109 80-Lead Plastic LQFP (ST) 2.6 W
Input Voltage
Output Short-Circuit Duration
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
12.0 V
VS
Observe power
derating curves
−65°C to +125°C
Storage Temperature Range2
1 Specification is for device in free air (TA = 25°C):
80-lead plastic LQFP (ST): θJA = 48°C/W.
2 Maximum reflow temperatures are to JEDEC industry standard J-STD-020.
5.0
MAXIMUM POWER DISSIPATION
T
= 125°C
J
The maximum power that can be safely dissipated by the
AD8108/AD8109 is limited by the associated rise in junction
temperature. The maximum safe junction temperature for
plastic encapsulated devices is determined by the glass transition
temperature of the plastic, approximately 125°C. Temporarily
exceeding this limit may cause a shift in parametric performance
due to a change in the stresses exerted on the die by the package.
Exceeding a junction temperature of 125°C for an extended
period can result in device failure.
4.0
3.0
2.0
1.0
0
While the AD8108/AD8109 are internally short-circuit protected,
this may not be sufficient to guarantee that the maximum junction
temperature (125°C) is not exceeded under all conditions. To
ensure proper operation, it is necessary to observe the maximum
power derating curves shown in Figure 5.
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
AMBIENT TEMPERATURE (°C)
Figure 5. Maximum Power Dissipation vs. Temperature
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. B | Page 8 of 32
AD8108/AD8109
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
IN00
AGND
IN01
CE
PIN 1
2
DATA OUT
CLK
3
4
AGND
IN02
DATA IN
UPDATE
SER/PAR
A0
5
6
AGND
IN03
7
AD8108/AD8109
TOP VIEW
8
AGND
IN04
A1
9
A2
(Not to Scale)
10
11
12
13
14
15
16
17
18
19
20
AGND
IN05
D0
D1
AGND
IN06
D2
D3
AGND
IN07
NC
AGND
AVEE
AVCC
AVCC00
AGND00
OUT00
AGND
AVEE
AVCC
AVCC07
OUT07
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
NC = NO CONNECT
Figure 6. Pin Configuration
Rev. B | Page 9 of 32
AD8108/AD8109
Table 8. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 3, 5, 7, 9, 11, 13, 15
INxx
DATA IN
CLK
DATA OUT
UPDATE
Analog Inputs. xx = Channels 00 through 07.
Serial Data Input, TTL Compatible.
Clock, TTL Compatible. Falling edge triggered.
Serial Data Output, TTL Compatible.
Enable (Transparent) Low. Allows serial register to connect directly to switch matrix. Data
latched when high.
57
58
59
56
61
RESET
CE
Disable Outputs, Active Low.
60
Chip Enable, Enable Low. Must be low to clock in and latch data.
Selects Serial Data Mode, Low or Parallel, High. Must be connected.
Analog Outputs. yy = Channels 00 through 07.
Analog Ground for Inputs and Switch Matrix.
5 V for Digital Circuitry
Ground for Digital Circuitry
55
SER/PAR
OUTyy
AGND
DVCC
DGND
AVEE
AVCC
AGNDxx
AVCCxx/yy
AVEExx/yy
A0
A1
A2
D0
D1
D2
D3
NC
41, 38, 35, 32, 29, 26, 23, 20
2, 4, 6, 8, 10, 12, 14, 16, 46
63, 79
62, 80
17, 45
18, 44
42, 39, 36, 33, 30, 27, 24, 21
43, 37, 31, 25, 19
40, 34, 28, 22
54
53
52
51
50
−5 V for Inputs and Switch Matrix.
+5 V for Inputs and Switch Matrix.
Ground for Output Amp. xx = Output Channels 00 through 07. Must be connected.
+5 V for Output Amplifier that is Shared by Channels xx and yy. Must be connected.
−5 V for Output Amplifier that is Shared by Channels xx and yy. Must be connected.
Parallel Data Input, TTL Compatible (output select LSB).
Parallel Data Input, TTL Compatible (output select).
Parallel Data Input, TTL Compatible (output select MSB).
Parallel Data Input, TTL Compatible (input select LSB).
Parallel Data Input, TTL Compatible (input select).
Parallel Data Input, TTL Compatible (input select MSB).
Parallel Data Input, TTL Compatible (output enable).
No Connect.
49
48
47, 64 to 78
Rev. B | Page 10 of 32
AD8108/AD8109
TYPICAL PERFORMANCE CHARACTERISTICS
5
0.4
0.3
0.2
0.1
0
R
= 150Ω
L
4
3
+50mV
+25mV
2
FLATNESS
0
–25mV
–50mV
1
200mV p-p
–0.1
0
GAIN
–0.2
–0.3
–0.4
–1
–2
–3
2V p-p
10ns/DIV
100k
1M
10M
FREQUENCY (Hz)
100M
1G
Figure 10. AD8108 Step Response, 100 mV Step
Figure 7. AD8108 Frequency Response
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
R
= 1kΩ
L
+1.0V
+0.5V
0
–0.5V
–1.0V
ALL HOSTILE
ADJACENT
10ns/DIV
0.2
1
10
100 200
FREQUENCY (MHz)
Figure 11. AD8108 Step Response, 2 V Step
Figure 8. AD8108 Crosstalk vs. Frequency
–30
ꢀ
R
= 150Ω
2V STEP
L
V
= 2V p-p
R =150Ω
OUT
L
–40
–50
–60
–70
–80
–90
–100
0.2
0.1
2ND HARMONIC
0
–0.1
–0.2
3RD HARMONIC
0
10
20
30
40
10ns/DIV
50
60
70
80
100k
1M
10M
FREQUENCY (Hz)
100M
Figure 9. AD8108 Distortion vs. Frequency
Figure 12. AD8108 Settling Time
Rev. B | Page 11 of 32
AD8108/AD8109
5
0.4
0.3
0.2
0.1
4
3
+50mV
+25mV
2V p-p
2
FLATNESS
200mV p-p
0
–25mV
–50mV
1
0
0
–0.1
GAIN
–0.2
–0.3
–0.4
–1
2V p-p
–2
–3
10ns/DIV
100k
1M
10M
FREQUENCY (Hz)
100M
1G
Figure 13. AD8109 Frequency Response
Figure 16. AD8109 Step Response, 100 mV Step
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
R
= 1kΩ
L
+1.0V
+0.5V
0
–0.5V
–1.0V
ADJACENT
ALL HOSTILE
10ns/DIV
300k
1M
10M
100M 200M
FREQUENCY (Hz)
Figure 17. AD8109 Step Response, 2 V Step
Figure 14. AD8109 Crosstalk vs. Frequency
–30
–40
–50
–60
–70
–80
–90
–100
2V STEP
R
= 150Ω
ꢀ
L
R
= 150Ω
L
V
= 2V p-p
OUT
0.2
0.1
2ND HARMONIC
0
–0.1
–0.2
3RD HARMONIC
0
10
20
30
40
10ns/DIV
50
60
70
80
100k
1M
10M
FREQUENCY (Hz)
100M
Figure 15. AD8109 Distortion vs. Frequency
Figure 18. AD8109 Settling Time
Rev. B | Page 12 of 32
AD8108/AD8109
–30
–40
–50
–60
–70
–80
–90
5
4
3
2
1
0
SWITCHING BETWEEN
TWO INPUTS
R
= 150Ω
L
UPDATE INPUT
10
0
TYPICAL VIDEO OUT (RTO)
–10
50ns/DIV
10k
100k
FREQUENCY (Hz)
1M
10M
Figure 19. AD8108 PSRR vs. Frequency
Figure 22. AD8108 Switching Transient (Glitch)
100
56.3
31.6
17.8
10
–40
–50
–60
–70
–80
–90
–100
V
R
= 2V p-p
= 150Ω
IN
L
–110
–120
–130
5.63
3.16
–140
100k
10
100
1k
10k
100k
1M
10M
1M
10M
100M
500M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 23. AD8108 Off Isolation, Input-Output
Figure 20. AD8108 Voltage Noise vs. Frequency
1M
1k
100
10
100k
10k
1k
1
0.1
100k
100
1
0.1
10
100
500
1M
10M
100M
500M
FREQUENCY (MHz)
FREQUENCY (Hz)
Figure 21. AD8108 Output Impedance, Disabled
Figure 24. AD8108 Output Impedance, Enabled
Rev. B | Page 13 of 32
AD8108/AD8109
–30
5
4
3
2
1
0
R
= 150Ω
SWITCHING BETWEEN
TWO INPUTS
L
–40
–50
–60
–70
–80
–90
UPDATE INPUT
10
0
TYPICAL VIDEO OUT (RTO)
50ns/DIV
–10
10k
100k
FREQUENCY (Hz)
1M
10M
Figure 25. AD8109 PSRR vs. Frequency
Figure 28. AD8109 Switching Transient (Glitch)
100.0
56.3
31.6
17.8
10.0
5.63
3.16
–40
–50
V
R
= 2V p-p
= 150Ω
OUT
L
–60
–70
–80
–90
–100
–110
–120
–130
–140
1M
10
100
1k
10k
100k
1M
10M
100k
10M
100M
500M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 26. AD8109 Voltage Noise vs. Frequency
Figure 29. AD8109 Off Isolation, Input-Output
100k
10k
1k
1k
100
10
100
1
1
0.1
100k
1M
1M
10M
100M
500M
100k
10M
100M
500M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 30. AD8109 Output Impedance, Enabled
Figure 27. AD8109 Output Impedance, Disabled
Rev. B | Page 14 of 32
AD8108/AD8109
1M
100k
10k
1k
V
OUT
1
0
INPUT 1 AT +1V
–1
INPUT 0 AT –1V
5
0
UPDATE
100
30k
50ns/DIV
100k
1M
10M
100M
500M
FREQUENCY (Hz)
Figure 34. AD8108 Switching Time
Figure 31. AD8108 Input Impedance vs. Frequency
900
800
700
600
500
400
300
200
100
0
V
R
= 200mV
= 150Ω
IN
8
6
L
C
= 18pF
L
4
2
C
= 12pF
0
L
–2
–4
–6
–8
30k 100k
1M
10M
100M
1G
3G
–0.020
–0.010
0.000
0.010
0.020
FREQUENCY (Hz)
OFFSET VOLTAGE (V)
Figure 32. AD8108 Frequency Response vs. Capacitive Load
Figure 35. AD8108 Offset Voltage Distribution
2.0
1.5
0.5
V
R
= 200mV
= 150Ω
IN
0.4
0.3
L
C
= 18pF
L
1.0
0.2
0.5
0.1
0
0.0
C
= 12pF
L
–0.1
–0.2
–0.3
–0.5
–1.0
–1.5
–2.0
–0.4
–0.5
30k 100k
1M
10M
FREQUENCY (Hz)
100M
1G
3G
–60
–40
–20
0
20
40
C)
60
80
100
TEMPERATURE (
°
Figure 33. AD8108 Flatness vs. Capacitive Load
Figure 36. AD8108 Offset Voltage Drift vs. Temperature (Normalized at 25°C)
Rev. B | Page 15 of 32
AD8108/AD8109
1M
V
OUT
1
0
100k
10k
1k
INPUT 1 AT +1V
–1
INPUT 0 AT –1V
5
0
UPDATE
100
30k
50ns/DIV
100k
1M
10M
100M
500M
FREQUENCY (Hz)
Figure 40. AD8109 Switching Time
Figure 37. AD8109 Input Impedance vs. Frequency
320
300
280
260
240
220
200
180
160
140
120
100
80
V
R
= 100mV
= 150Ω
8
6
IN
L
C
= 18pF
L
4
2
0
–2
–4
–6
–8
C
= 12pF
L
60
40
0
30k 100k
1M
10M
100M
1G
3G
–0.020
–0.010
0.000
0.010
0.020
FREQUENCY (Hz)
OFFSET VOLTAGE (V)
Figure 38. AD8109 Frequency Response vs. Capacitive Load
Figure 41. AD8109 Offset Voltage Distribution (RTI)
2.0
1.5
V
R
= 100mV
= 150Ω
IN
0.4
0.3
L
1.0
C
= 18pF
L
0.2
0.5
0.1
0.0
0
C
= 12pF
L
–0.1
–0.2
–0.3
–0.4
–0.5
–1.0
–1.5
–2.0
30k 100k
1M
10M
FREQUENCY (Hz)
100M
1G
3G
–60
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 39. AD8109 Flatness vs. Capacitive Load
Figure 42. AD8109 Offset Voltage Drift vs. Temperature (Normalized at 25°C)
Rev. B | Page 16 of 32
AD8108/AD8109
I/O SCHEMATICS
V
V
CC
CC
ESD
ESD
ESD
INPUT
INPUT
ESD
AVEE
DGND
Figure 43. Analog Input
Figure 46. Logic Input
V
V
CC
CC
ESD
2kΩ
ESD
OUTPUT
OUTPUT
1kΩ
(AD8109 ONLY)
ESD
ESD
AVEE
DGND
Figure 44. Analog Output
Figure 47. Logic Output
V
CC
20kΩ
ESD
ESD
DGND
Figure 45. Reset Input
Rev. B | Page 17 of 32
AD8108/AD8109
THEORY OF OPERATION
Serial Programming
The AD8108 (G = 1) and AD8109 (G = 2) share a common core
architecture consisting of an array of 64 transconductance (gm)
input stages organized as eight 8:1 multiplexers with a common
8-line analog input bus. Each multiplexer is basically a folded-
cascode, high impedance voltage feedback amplifier with eight
input stages. The input stages are NPN differential pairs whose
differential current outputs are combined at the output stage,
which contains the high impedance node, compensation and a
complementary emitter follower output buffer. In the AD8108,
the output of each multiplexer is fed back directly to the
inverting inputs of its eight gm stages. In the AD8109, the
feedback network is a voltage divider consisting of two equal
resistors.
The serial programming mode uses the device pins , CLK,
CE
DATA IN,
, and
/PAR. The first step is to assert a
UPDATE
SER
low on
/PAR to enable the serial programming mode.
SER
for the chip must be low to allow data to be clocked into the
device. The signal can be used to address an individual
CE
CE
device when devices are connected in parallel.
The signal should be high during the time that data is
UPDATE
shifted into the device’s serial port. Although the data will still
shift in when is low, the transparent, asynchronous
UPDATE
latches will allow the shifting data to reach the matrix. This will
cause the matrix to try to update to every intermediate state as
defined by the shifting data.
This switched-gm architecture results in a low power crosspoint
switch that is able to directly drive a back terminated video load
(150 Ω) with low distortion (differential gain and differential
phase errors are better than 0.02% and 0.02°, respectively). This
design also achieves high input resistance and low input
capacitance without the signal degradation and power
dissipation of additional input buffers. However, the small input
bias current at any input will increase almost linearly with the
number of outputs programmed to that input.
The data at DATA IN is clocked in at every down edge of CLK.
A total of 32 data bits must be shifted in to complete the
programming. For each of the eight outputs, there are three bits
(D0 to D2) that determine the source of its input followed by
one bit (D3) that determines the enabled state of the output. If
D3 is low (output disabled), the three associated bits (D0 to D2)
do not matter because no input will be switched to that output.
The most significant output address data is shifted in first and is
followed in sequence until the least significant output address
The output disable feature of these crosspoints allows larger
switch matrices to be built by simply busing together the
outputs of multiple 8 × 8 ICs. However, while the disabled
output impedance of the AD8108 is very high (10 MΩ), that of
the AD8109 is limited by the resistive feedback network (which
has a nominal total resistance of 1 kΩ) that appears in parallel
with the disabled output. If the outputs of multiple AD8109s are
connected through separate back termination resistors, the
loading due to these finite output impedances will lower the
effective back termination impedance of the overall matrix.
This problem is eliminated if the outputs of multiple AD8109s
are connected directly and share a single back termination
resistor for each output of the overall matrix. This configuration
increases the capacitive loading of the disabled AD8109s on the
output of the enabled AD8109.
data is shifted in. At this point,
can be taken low,
UPDATE
which will cause the programming of the device according to
the data that was just shifted in. The registers are
UPDATE
is low, they are transparent.
asynchronous, and when
UPDATE
If more than one AD8108/AD8109 device is to be serially
programmed in a system, the DATA OUT signal from one device
can be connected to the DATA IN of the next device to form a
serial chain. All of the CLK,
,
, and
/PAR pins
SER
CE UPDATE
should be connected in parallel and operated as described above.
The serial data is input to the DATA IN pin of the first device of
the chain, and it will ripple on through to the last. Therefore,
the data for the last device in the chain should come at the
beginning of the programming sequence. The length of the
programming sequence will be 32 times the number of devices
in the chain.
APPLICATIONS
The AD8108/AD8109 have two options for changing the
programming of the crosspoint matrix. In the first, a serial word
of 32 bits can be provided that will update the entire matrix
each time. The second option allows for changing a single
output’s programming via a parallel interface. The serial option
requires fewer signals, but requires more time (clock cycles) for
changing the programming, while the parallel programming
technique requires more signals, but can change a single output
at a time and requires fewer clock cycles to complete
programming.
Parallel Programming
While using the parallel programming mode, it is not necessary
to reprogram the entire device when making changes to the
matrix. In fact, parallel programming allows the modification of
a single output at a time. Since this takes only one
CLK/
cycle, significant time savings can be realized by
UPDATE
using parallel programming.
One important consideration in using parallel programming is
that the
signal does not reset all registers in the
RESET
Rev. B | Page 18 of 32
AD8108/AD8109
AD8108/AD8109. When taken low, the
signal will only
RESET
POWER-ON
RESET
set each output to the disabled state. This is helpful during
power-up to ensure that two parallel outputs will not be active
at the same time.
When powering up the AD8108/AD8109, it is usually desirable
to have the outputs come up in the disabled state. When taken
low, the
pin will cause all outputs to be in the disabled
RESET
state. However, the
signal does not reset all registers in
RESET
After initial power-up, the internal registers in the device will
the AD8108/AD8109. This is important when operating in the
parallel programming mode. Please refer to that section for
information about programming internal registers after power-
up. Serial programming will program the entire matrix each
time, so no special considerations apply.
generally have random data, even though the
signal was
RESET
asserted. If parallel programming is used to program one
output, that output will be properly programmed, but the rest of
the device will have a random program state depending on the
internal register content at power-up. Therefore, when using
parallel programming, it is essential that all outputs be
programmed to a desired state after power-up. This will ensure
that the programming matrix is always in a known state. From
then on, parallel programming can be used to modify a single,
or more, output at a time.
Since the data in the shift register is random after power-up, it
should not be used to program the matrix, or the matrix can
enter unknown states. To prevent this, do not apply logic low
signals to both
and
initially after power-up. The
CE
UPDATE
shift register should first be loaded with the desired data, and
then
The
can be taken low to program the device.
In a similar fashion, if both
and
are taken low
UPDATE
UPDATE
CE
after initial power-up, the random power-up data in the shift
register will be programmed into the matrix. Therefore, to
prevent the crosspoint from being programmed into an
pin has a 20 kΩ pull-up resistor to DVDD that can
RESET
be used to create a simple power-up reset circuit. A capacitor
from to ground will hold low for some time
RESET
RESET
unknown state, do not apply low logic levels to both
and
CE
while the rest of the device stabilizes. The low condition will
cause all the outputs to be disabled. The capacitor will then
charge through the pull-up resistor to the high state, thus
allowing full programming capability of the device.
after power is initially applied. Programming the full
UPDATE
shift register one time to a desired state by either serial or
parallel programming after initial power-up will eliminate the
possibility of programming the matrix to an unknown state.
GAIN SELECTION
To change an output’s programming via parallel programming,
The 8 × 8 crosspoints come in two versions, depending on the
desired gain of the analog circuit paths. The AD8108 device is
unity gain and can be used for analog logic switching and other
applications where unity gain is desired. The AD8108 can also
be used for the input and interior sections of larger crosspoint
arrays where termination of output signals is not usually used.
The AD8108 outputs have very high impedance when their
outputs are disabled.
/PAR and
should be taken high and
should be
SER
UPDATE
CE
taken low. The CLK signal should be in the high state. The
address of the output that is to be programmed should be put
on A0 to A2. The first three data bits (D0 to D2) should contain
the information that identifies the input that is programmed to
the output that is addressed. The fourth data bit (D3) will
determine the enabled state of the output. If D3 is low (output
disabled), the data on D0 to D2 does not matter.
The AD8109 can be used for devices that will be used to drive a
terminated cable with its outputs. This device has a built-in gain
of 2 that eliminates the need for a gain-of-2 buffer to drive a
video line. Because of the presence of the feedback network in
these devices, the disabled output impedance is about 1 kΩ.
After the desired address and data signals have been established,
they can be latched into the shift register by a high to low
transition of the CLK signal. The matrix will not be
programmed, however, until the
signal is taken low.
UPDATE
Thus, it is possible to latch in new data for several or all of the
outputs first via successive negative transitions of CLK while
If external amplifiers will be used to provide a G = 2, Analog
Devices’ AD8079 is a fixed gain-of-2 buffer.
is held high, and then have all the new data take effect
UPDATE
when
goes low. This technique should be used when
UPDATE
programming the device for the first time after power-up when
using parallel programming.
Rev. B | Page 19 of 32
AD8108/AD8109
Figure 49 illustrates a 16 × 16 crosspoint array, while a 24 × 24
crosspoint is illustrated in Figure 50. The 16 × 16 crosspoint
requires that each input driver drive two inputs in parallel and
each output be wire-OR’ed with one other output. The 24 × 24
crosspoint requires driving three inputs in parallel and having
the outputs wire-OR’ed in groups of three. It is required of the
system programming that only one output of a wired-OR node
be active at a time.
CREATING LARGER CROSSPOINT ARRAYS
The AD8108/AD8109 are high density building blocks for creating
crosspoint arrays of dimensions larger than 8 × 8. Various features,
such as output disable, chip enable, and gain-of-1 and-2 options,
are useful for creating larger arrays. For very large arrays, they
can be used along with the AD8116, a 16 × 16 video cross-point
device. In addition, systems that require more inputs than
outputs can use the AD8110 and/or the AD8111, which are
(gain-of-1 and gain-of-2) 16 × 8 crosspoint switches.
8
00–07
The first consideration in constructing a larger crosspoint is to
determine the minimum number of devices required. The 8 × 8
architecture of the AD8108/AD8109 contains 64 points, which
is a factor of 16 greater than a 4 × 1 crosspoint. The PC board
area and power consumption savings are readily apparent when
compared to using these smaller devices.
8 × 8
8 × 8
IN 00–07
8
R
TERM
8
8
08–15
8
IN 08–15
8 × 8
8 × 8
8
For a nonblocking crosspoint, the number of points required is
the product of the number of inputs multiplied by the number
of outputs. Nonblocking requires that the programming of a
given input to one or more outputs does not restrict the
availability of that input to be a source for any other outputs.
R
TERM
8
8
OUT 00–07
OUT 08–15
Figure 49. 16 × 16 Crosspoint Array Using Four AD8108s or AD8109s
Some nonblocking crosspoint architectures will require more than
this minimum as calculated above. Also, there are blocking archi-
tectures that can be constructed with fewer devices than this
minimum. These systems have connectivity available on a statis-
tical basis that is determined when designing the overall system.
8
IN 00–07
IN 08–15
IN 16–23
8 × 8
8 × 8
8 × 8
8
8
8
R
8
TERM
The basic concept in constructing larger crosspoint arrays is to
connect inputs in parallel in a horizontal direction and to wire-
OR the outputs together in the vertical direction. The meaning
of horizontal and vertical can best be understood by looking at
a diagram.
8
8 × 8
8 × 8
8 × 8
8
8
8
8
R
TERM
8
An 8 input by 16 output crosspoint array can be constructed as
shown in Figure 48. This configuration parallels two inputs per
channel and does not require paralleling of any outputs. Inputs are
easier to parallel than outputs because there are lower parasitics
involved. For a 16 × 8 crosspoint, the AD8110 (gain of 1) or
AD8111 (gain of 2) device can be used. These devices are
already configured into a 16 × 8 crosspoint in a single device.
8 × 8
8 × 8
8 × 8
8
8
8
8
R
TERM
OUT 00–07
OUT 08–15
OUT 16–23
Figure 50. 24 × 24 Crosspoint Array Using Nine AD8108s or AD8109s
At some point, the number of outputs that are wire-OR’ed
becomes too great to maintain system performance. This will
vary according to which system specifications are most
important. For example, a 64 × 8 crosspoint can be created with
eight AD8108/AD8109s. This design will have 64 separate
inputs and have the corresponding outputs of each device wire-
OR’ed together in groups of eight.
AD8108
OR
AD8109
8
8
8 INPUTS
IN 00–07
AD8108
OR
AD8109
8
ONE
TERMINATION
PER INPUT
8
8
16 OUTPUTS
OUT 00–15
Figure 48. 8 × 16 Crosspoint Array Using Two AD8108s (Unity Gain) or Two
AD8109s (Gain of 2)
Rev. B | Page 20 of 32
AD8108/AD8109
Using additional crosspoint devices in the design can lower the
number of outputs that must be wire-OR’ed together. Figure 51
shows a block diagram of a system using eight AD8108s and
two AD8109s to create a nonblocking, gain-of-2, 64 × 8
crosspoint that restricts the wire-OR’ing at the output to only
four outputs. The rank 1 wire-OR’ed devices are AD8108s,
which have higher disabled output impedance than the
AD8109.
that operates in noisy environments or where common-mode
voltages are present between transmitting and receiving
equipment.
In such systems, the video signals are differential; there is a
positive and negative (or inverted) version of the signals. These
complementary signals are transmitted onto each of the two
wires of the twisted pair, yielding a first-order zero common-
mode signal. At the receive end, the signals are differentially
received and converted back into a single-ended signal.
RANK 1
(64:16)
4
8
IN 00–07
AD8108
AD8108
AD8108
AD8108
AD8108
AD8108
AD8108
AD8108
4
When switching these differential signals, two channels are
required in the switching element to handle the two differential
signals that make up the video channel. Thus, one differential
video channel is assigned to a pair of crosspoint channels, both
input and output. For a single AD8108/AD8109, four
differential video channels can be assigned to the eight inputs
and eight outputs. This will effectively form a 4 × 4 differential
crosspoint switch.
4
4
8
8
8
8
8
8
8
RANK 2
16 × 8 NONBLOCKING
16 × 16 BLOCKING
IN 08–15
IN 16–23
IN 24–31
4
4
4
4
OUT 00–07
NONBLOCKING
AD8109
4
1kΩ
4
4
4
1kΩ
ꢀ
ADDITIONAL
8 OUTPUTS
(SUBJECT TO
BLOCKING)
4
4
4
4
Programming such a device will require that inputs and outputs
be programmed in pairs. This information can be deduced by
inspection of the programming format of the AD8108/AD8109
and the requirements of the system.
IN 32–39
IN 40–47
AD8109
4
4
4
4
1kΩ
1kΩ
4
4
There are other analog video formats requiring more than one
analog circuit per video channel. One 2-circuit format that is
commonly being used in systems such as satellite TV, digital
cable boxes, and higher quality VCRs is called S-video or Y/C
video. This format carries the brightness (luminance or Y)
portion of the video signal on one channel and the color
(chrominance, chroma, or C) on a second channel.
IN 48–55
IN 56–63
4
4
Figure 51. Nonblocking 64 × 8 Array with Gain of 2 (64 × 16 Blocking)
Additionally, by using the lower four outputs from each of the
two rank 2 AD8109s, a blocking 64 × 16 crosspoint array can be
realized. There are, however, some drawbacks to this technique.
The offset voltages of the various cascaded devices will
accumulate, and the bandwidth limitations of the devices will
compound. In addition, the extra devices will consume more
current and take up more board space. Once again, the overall
system design specifications will determine how to make the
various tradeoffs.
Since S-video also uses two separate circuits for one video
channel, creating a crosspoint system requires assigning one
video channel to two crosspoint channels, as in the case of a
differential video system. Aside from the nature of the video
format, other aspects of these two systems will be the same.
There are yet other video formats using three channels to carry
the video information. Video cameras produce RGB (red, green,
blue) directly from the image sensors. RGB is also the usual
format used by computers internally for graphics. RGB can be
converted to Y, R-Y, B-Y format, sometimes called YUV format.
These 3-circuit video standards are referred to as component
analog video.
MULTICHANNEL VIDEO
The excellent video specifications of the AD8108/AD8109 make
them ideal candidates for creating composite video crosspoint
switches. These can be made quite dense by taking advantage of
the AD8108/AD8109’s high level of integration and the fact that
composite video requires only one crosspoint channel per
system video channel. There are, however, other video formats
that can be routed with the AD8108/AD8109 requiring more
than one crosspoint channel per video channel.
The component video standards require three crosspoint
channels per video channel to handle the switching function. In
a fashion similar to the 2-circuit video formats, the inputs and
outputs are assigned in groups of three, and the appropriate
logic programming is performed to route the video signals.
Some systems use twisted-pair wiring to carry video signals.
These systems utilize differential signals and can lower costs
because they use lower cost cables, connectors, and termination
methods. They also have the ability to lower crosstalk and reject
common-mode signals, which can be important for equipment
Rev. B | Page 21 of 32
AD8108/AD8109
a combination of the intrinsic crosstalk of the devices in
addition to the circuit board to which they are mounted. It is
important to try to separate these two areas of crosstalk when
attempting to minimize its effect.
CROSSTALK
Many systems, such as broadcast video, that handle numerous
analog signal channels have strict requirements for keeping the
various signals from influencing any of the others in the system.
Crosstalk is the term used to describe the coupling of the
signals of other nearby channels to a given channel.
In addition, crosstalk can occur among the inputs to a
crosspoint and among the outputs. It can also occur from input
to output. Techniques will be discussed for diagnosing which
part of a system is contributing to crosstalk.
When there are many signals in proximity in a system, as will
undoubtedly be the case in a system that uses the AD8108/
AD8109, the crosstalk issues can be quite complex. A good
understanding of the nature of crosstalk and some definition
of terms is required to specify a system that uses one or more
AD8108/AD8109s.
Measuring Crosstalk
Crosstalk is measured by applying a signal to one or more
channels and measuring the relative strength of that signal on a
desired selected channel. The measurement is usually expressed
as dB down from the magnitude of the test signal. The crosstalk
is expressed by:
Types of Crosstalk
Crosstalk can be propagated by means of any of three methods.
These fall into the categories of electric field, magnetic field,
and sharing of common impedances. This section will explain
these effects.
( )
( )
XT = 20 log10 Asel s Atest s
where s = jω is the Laplace transform variable, Asel(s) is the
amplitude of the crosstalk-induced signal in the selected
channel, and Atest(s) is the amplitude of the test signal. It can be
seen that crosstalk is a function of frequency, but not a function
of the magnitude of the test signal (to first order). In addition,
the crosstalk signal will have a phase relative to the test signal
associated with it.
Every conductor can be both a radiator of electric fields and a
receiver of electric fields. The electric field crosstalk mechanism
occurs when the electric field created by the transmitter
propagates across a stray capacitance (e.g., free space) and
couples with the receiver and induces a voltage. This voltage is
an unwanted crosstalk signal in any channel that receives it.
A network analyzer is most commonly used to measure
crosstalk over a frequency range of interest. It can provide both
magnitude and phase information about the crosstalk signal.
Currents flowing in conductors create magnetic fields that
circulate around the currents. These magnetic fields will then
generate voltages in any other conductors whose paths they
link. The undesired induced voltages in these other channels are
crosstalk signals. The channels that crosstalk can be said to have
a mutual inductance that couples signals from one channel to
another.
As a crosspoint system or device grows larger, the number of
theoretical crosstalk combinations and permutations can
become extremely large. For example, in the case of the 8 × 8
matrix of the AD8108/AD8109, we can examine the number of
crosstalk terms that can be considered for a single channel, say
IN00 input. IN00 is programmed to connect to one of the
AD8108/AD8109 outputs where the measurement can be made.
The power supplies, grounds, and other signal return paths of a
multichannel system are generally shared by the various
channels. When a current from one channel flows in one of
these paths, a voltage that is developed across the impedance
becomes an input crosstalk signal for other channels that share
the common impedance.
We can first measure the crosstalk terms associated with driving
a test signal into each of the other seven inputs one at a time.
We can then measure the crosstalk terms associated with
driving a parallel test signal into all seven other inputs taken
two at a time in all possible combinations, and then three at a
time, etc., until there is only one way to drive a test signal into
all seven other inputs.
All these sources of crosstalk are vector quantities, so the
magnitudes cannot simply be added together to obtain the total
crosstalk. In fact, there are conditions where driving additional
circuits in parallel in a given configuration can actually reduce
the crosstalk.
Each of these cases is legitimately different from the others and
might yield a unique value depending on the resolution of the
measurement system, but it is hardly practical to measure all
these terms and then to specify them. In addition, this describes
the crosstalk matrix for just one input channel. A similar
crosstalk matrix can be proposed for every other input. In
addition, if the possible combinations and permutations for
connecting inputs to the other (not used for measurement)
outputs are taken into consideration, the numbers rather
Areas of Crosstalk
For a practical AD8108/AD8109 circuit, it is required that it be
mounted to some sort of circuit board to connect it to power
supplies and measurement equipment. Great care has been
taken to create a characterization board (also available as an
evaluation board) that adds minimum crosstalk to the intrinsic
device. This, however, raises the issue that a system’s crosstalk is
Rev. B | Page 22 of 32
AD8108/AD8109
quickly grow to astronomical proportions. If a larger crosspoint
array of multiple AD8108/AD8109s is constructed, the numbers
grow larger still.
Effect of Impedances on Crosstalk
The input side crosstalk can be influenced by the output
impedance of the sources that drive the inputs. The lower the
impedance of the drive source, the lower the magnitude of the
crosstalk. The dominant crosstalk mechanism on the input side
is capacitive coupling. The high impedance inputs do not have
significant current flow to create magnetically induced
crosstalk. However, significant current can flow through the
input termination resistors and the loops that drive them. Thus,
the PC board on the input side can contribute to magnetically
coupled crosstalk.
Obviously, some subset of all these cases must be selected to be
used as a guide for a practical measure of crosstalk. One
common method is to measure all hostile crosstalk. This term
means that the crosstalk to the selected channel is measured
while all other system channels are driven in parallel. In general,
this will yield the worst crosstalk number, but this is not always
the case due to the vector nature of the crosstalk signal.
Other useful crosstalk measurements are those created by one
nearest neighbor or by the two nearest neighbors on either side.
These crosstalk measurements will generally be higher than
those of more distant channels, so they can serve as a worst-case
measure for any other 1-channel or 2-channel crosstalk
measurements.
From a circuit standpoint, the input crosstalk mechanism looks
like a capacitor coupling to a resistive load. For low frequencies,
the magnitude of the crosstalk will be given by
XT = 20 log
R C
× s
10
S
M
Input and Output Crosstalk
where RS is the source resistance, CM is the mutual capacitance
between the test signal circuit and the selected circuit, and s is
the Laplace transform variable.
The flexible programming capability of the AD8108/AD8109
can be used to diagnose whether crosstalk is occurring more on
the input side or the output side. Some examples are illustrative.
A given input channel (IN03 in the middle for this example)
can be programmed to drive OUT03. The input to IN03 is just
terminated to ground (via 50 Ω or 75 Ω) and no signal is
applied.
From the equation, it can be observed that this crosstalk
mechanism has a high-pass nature; it can be minimized by
reducing the coupling capacitance of the input circuits and
lowering the output impedance of the drivers. If the input is
driven from a 75 Ω terminated cable, the input crosstalk can be
reduced by buffering this signal with a low output impedance
buffer.
All the other inputs are driven in parallel with the same test
signal (practically this is provided by a distribution amplifier),
with all other outputs except OUT03 disabled. Since grounded
IN03 is programmed to drive OUT03, there should be no signal
present. Any signal that is present can be attributed to the other
seven hostile input signals because no other outputs are driven.
(They are all disabled.) Thus, this method measures the all-
hostile input contribution to crosstalk into IN03. Of course, the
method can be used for other input channels and combinations
of hostile inputs.
On the output side, the crosstalk can be reduced by driving a
lighter load. Although the AD8108/AD8109 is specified with
excellent differential gain and phase when driving a standard
150 Ω video load, the crosstalk will be higher than the
minimum obtainable due to the high output currents. These
currents will induce crosstalk via the mutual inductance of the
output pins and bond wires of the AD8108/AD8109.
From a circuit standpoint, this output crosstalk mechanism
looks like a transformer, with a mutual inductance between the
windings, that drives a load resistor. For low frequencies, the
magnitude of the crosstalk is given by
For output crosstalk measurement, a single input channel is
driven (IN00, for example) and all outputs other than a given
output (IN03 in the middle) are programmed to connect to
IN00. OUT03 is programmed to connect to IN07 (far away
from IN00), which is terminated to ground. Thus OUT03
should not have a signal present since it is listening to a quiet
input. Any signal measured at the OUT03 can be attributed to
the output crosstalk of the other seven hostile outputs. Again,
this method can be modified to measure other channels and
other crosspoint matrix combinations.
XT = 20 log10
Mxy × s RL
where Mxy is the mutual inductance of Output x to Output y,
and RL is the load resistance on the measured output. This
crosstalk mechanism can be minimized by keeping the mutual
inductance low and increasing RL. The mutual inductance can
be kept low by increasing the spacing of the conductors and
minimizing their parallel length.
Rev. B | Page 23 of 32
AD8108/AD8109
PCB LAYOUT
Extreme care must be exercised to minimize additional
crosstalk generated by the system circuit board(s). The areas
that must be carefully detailed are grounding, shielding, signal
routing, and supply bypassing.
Optimized for video applications, all signal inputs and outputs
are terminated with 75 Ω resistors. Stripline techniques are used
to achieve a characteristic impedance of 75 Ω on the signal
input and output lines. Figure 52 shows a cross section of one of
the input or output tracks along with the arrangement of the
PCB layers. It should be noted that unused regions of the four
layers are filled up with ground planes. As a result, the input
and output traces, in addition to having controlled impedances,
are well shielded.
The packaging of the AD8108/AD8109 is designed to help keep
the crosstalk to a minimum. Each input is separated from each
other input by an analog ground pin. All of these AGNDs
should be directly connected to the ground plane of the circuit
board. These ground pins provide shielding, low impedance
return paths, and physical separation for the inputs. All of these
help to reduce crosstalk.
w = 0.008"
(0.2mm)
TOP LAYER
t = 0.00135" (0.0343mm)
b = 0.024"
(0.6mm)
a = 0.008"
(0.2mm)
Each output is separated from its two neighboring outputs by an
analog ground pin in addition to an analog supply pin of one
polarity or the other. Each of these analog supply pins provides
power to the output stages of only the two nearest outputs.
These supply pins and analog grounds provide shielding,
physical separation, and a low impedance supply for the
outputs. Individual bypassing of each of these supply pins with a
0.01 µF chip capacitor directly to the ground plane minimizes
high frequency output crosstalk via the mechanism of sharing
common impedances.
SIGNAL LAYER
POWER LAYER
BOTTOM LAYER
h = 0.011325"
(0.288mm)
Figure 52. Cross Section of Input and Output Traces
The board has 16 BNC type connectors: eight inputs and eight
outputs. The connectors are arranged in two crescents around
the device. As can be seen from Figure 53, this results in all
eight input signal traces and all eight signal output traces having
the same length. This is useful in tests such as all-hostile
crosstalk where the phase relationship and delay between
signals needs to be maintained from input to output.
Each output also has an on-chip compensation capacitor
that is individually tied to the nearby analog ground pins
AGND00 through AGND07. This technique reduces crosstalk by
preventing the currents that flow in these paths from sharing a
common impedance on the IC and in the package pins. These
AGNDxx signals should all be directly connected to the ground
plane.
The three power supply pins AVCC, DVCC, and AVEE should
be connected to good quality, low noise, 5 V supplies. Where
the same 5 V power supplies are used for analog and digital,
separate cables should be run for the power supply to the
evaluation board’s analog and digital power supply pins.
The input and output signals will have minimum crosstalk if
they are located between ground planes on layers above and
below, and separated by ground in between. Vias should be
located as close to the IC as possible to carry the inputs and
outputs to the inner layer. The only place the input and output
signals surface is at the input termination resistors and the
output series back-termination resistors. These signals should
also be separated, to the extent possible, as soon as they emerge
from the IC package.
As a general rule, each power supply pin (or group of adjacent
power supply pins) should be locally decoupled with a 0.01 µF
capacitor. If there is a space constraint, it is more important to
decouple analog power supply pins before digital power supply
pins. A 0.1 µF capacitor, located reasonably close to the pins,
can be used to decouple a number of power supply pins. Finally
a 10 µF capacitor should be used to decouple power supplies as
they come onto the board.
Rev. B | Page 24 of 32
AD8108/AD8109
Figure 53. Component Side Silkscreen
Figure 54. Board Layout (Component Side)
Rev. B | Page 25 of 32
AD8108/AD8109
Figure 55. Board Layout (Signal Layer)
Figure 56. Board Layout (Power Plane)
Rev. B | Page 26 of 32
AD8108/AD8109
Figure 57. Board Layout (Bottom Layer)
Rev. B | Page 27 of 32
AD8108/AD8109
EVALUATION BOARD
A 4-layer evaluation board for the AD8108/AD8109 is available.
The exact same board and external components are used for each
device. The only difference is the device itself, which offers a
selection of a gain of unity or gain of 2 through the analog
channels. This board has been carefully laid out and tested to
demonstrate the specified high speed performance of the device.
Figure 60 shows the schematic of the evaluation board. Figure 53
shows the component side silk-screen. The layouts of the board’s
four layers are given in Figure 54, Figure 55, Figure 56, and
Figure 57.
When you launch the crosspoint control software, you will be
asked to select the printer port. Most modern PCs have only
one printer port, usually called LPT1. However, some laptop
computers use the PRN port.
Figure 59 shows the main screen of the control software in its
initial reset state (all outputs off). Using the mouse, any input
can be connected with one or more outputs by simply clicking
on the appropriate radio buttons in the 8 × 8 on-screen array.
Each time a button is clicked on, the software automatically
sends and latches the required 32-bit data stream to the
evaluation board. An output can be turned off by clicking the
appropriate button in the off column. To turn off all outputs,
The evaluation board package includes the following:
•
•
Fully populated board with BNC-type connectors.
click on
.
RESET
Windows®-based software for controlling the board from a
PC via the printer port.
The software offers volatile and nonvolatile storage of
configurations. For volatile storage, up to two configurations
can be stored and recalled using the Memory 1 and Memory 2
buffers. These function in an identical fashion to the memory
on a pocket calculator. For nonvolatile storage of a
•
•
Custom cable to connect evaluation board to PC.
Disk containing Gerber files of board layout.
configuration, the save setup and load setup functions can be
used. This stores the configuration as a data file on disk.
CONTROL THE EVALUATION BOARD FROM A PC
The evaluation board includes Windows-based control software
and a custom cable that connects the board’s digital interface to
the printer port of the PC. The wiring of this cable is shown in
Figure 58. The software requires Windows 3.1 or later to
operate. To install the software, insert the disk labeled Disk 1 of
2 into the PC and run the file called SETUP.EXE. Additional
installation instructions will be given on-screen. Before
beginning installation, it is important to terminate any other
Windows applications that are running.
OVERSHOOT OF PC PRINTER PORTS’ DATA LINES
The data lines on some printer ports have excessive overshoot.
Overshoot on the pin that is used as the serial clock (Pin 6 on
the D-Sub-25 connector) can cause communication problems.
This overshoot can be eliminated by connecting a capacitor
from the CLK line on the evaluation board to ground. A pad
has been provided on the solder side of the evaluation board to
allow this capacitor to be soldered into place. Depending on the
overshoot from the printer port, this capacitor may need to be
as large as 0.01µF
MOLEX 0.100" CENTER
CRIMP TERMINAL HOUSING
D-SUB 25 PIN (MALE)
RESET
1
1
14
CLK
CE
UPDATE
DATA IN
DGND
6
MOLEX
TERMINAL HOUSING
D-SUB-25
SIGNAL
2
3
3
1
CE
RESET
25
13
4
5
6
25
4
5
2
6
UPDATE
DATA IN
CLK
DGND
EVALUATION BOARD
PC
Figure 58. Evaluation Board-PC Connection Cable
Figure 59. Evaluation Board Control Panel
Rev. B | Page 28 of 32
AD8108/AD8109
DVCC DGND NC
AVEE AGND AVCC
P1-5
P1-6
NC
P1-7
P1-1 P1-2
P1-3 P1-4
+
+
CR1
CR2
1N4148
DVCC
0.01µF
DVCC
0.01µF
AVCC
0.01µF
AVCC
0.01µF
AVEE
0.01µF
+
0.1µF 10µF
0.1µF 10µF
80
DGND DVCC
43
44
45
46
79
63
0.1µF 10µF
DVCC
AVCC
AVCC
AVEE
AGND
42
41
AGND
1
2
INPUT 00
INPUT 00
AGND
75Ω
OUTPUT 00
75Ω
75Ω
75Ω
75Ω
75Ω
75Ω
75Ω
75Ω
40
39
AVEE
AGND
AVEE
0.01µF
3
4
75Ω
INPUT 01
INPUT 02
INPUT 03
INPUT 04
INPUT 05
INPUT 06
INPUT 07
INPUT 01
AGND
38
OUTPUT 01
37
36
AVCC
AGND
AVCC
0.01µF
75Ω
5
6
35
INPUT 02
AGND
OUTPUT 02
34
33
AVEE
AGND
AVEE
0.01µF
75Ω
32
7
8
OUTPUT 03
INPUT 03
AGND
31
30
AD8108/AD8109
AVCC
AGND
AVCC
0.01µF
75Ω
29
OUTPUT 04
9
INPUT 04
AGND
10
28
27
AVEE
AGND
AVEE
0.01µF
75Ω
26
OUTPUT 05
11
12
INPUT 05
AGND
25
24
AVCC
AGND
AVCC
0.01µF
75Ω
23
OUTPUT 06
13
14
22
21
INPUT 06
AGND
AVEE
AGND
AVEE
0.01µF
75Ω
20
19
OUTPUT 07
AVCC
15
16
INPUT 07
AGND
AVCC
0.01µF
18
17
59
57
AVCC
AVEE
DATA OUT
DATA IN
AVCC
0.01µF
AVEE
P2-5
P2-4
P2-2
P2-3
P2-1
P2-6
0.01µF
62 61 60 58 56 55 54 53 52 51 50 49 48
R25
20kΩ
DVCC
NC
SERIAL MODE
JUMP
NC = NO CONNECT
Figure 60. Evaluation Board Schematic
Rev. B | Page 29 of 32
AD8108/AD8109
OUTLINE DIMENSIONS
14.00
BSC SQ
0.75
0.60
0.45
1.60
MAX
80
61
60
1
PIN
1
12.00
BSC SQ
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.20
0.09
7°
3.5°
0°
20
41
0.15
0.05
21
40
SEATING
PLANE
0.08 MAX
COPLANARITY
VIEW A
0.50
BSC
0.27
0.22
0.17
LEAD PITCH
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BDD
Figure 61. 80-Lead Low Profile Quad Flat Package [LQFP]
(ST-80-1)
Dimensions shown in millimeters
ORDERING GUIDE1
Model
Temperature Range
Package Description
Package Option
ST-80-1
ST-80-1
ST-80-1
ST-80-1
AD8108AST
AD8108ASTZ2
AD8109AST
AD8109ASTZ2
AD8108-EB
AD8109-EB
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
80-Lead Low Profile Quad Flat Package [LQFP]
80-Lead Low Profile Quad Flat Package [LQFP]
80-Lead Low Profile Quad Flat Package [LQFP]
80-Lead Low Profile Quad Flat Package [LQFP]
Evaluation Board
Evaluation Board
1 Details of the lead finish composition can be found on the ADI website at www.analog.com by reviewing the Material Description of each relevant package.
2 Z = Pb-free part.
Rev. B | Page 30 of 32
AD8108/AD8109
NOTES
Rev. B | Page 31 of 32
AD8108/AD8109
NOTES
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C01068–0–9/05(B)
Rev. B | Page 32 of 32
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