AD8112 [ADI]
Audio/Video, 60 MHz, 16 】 8, Gain of +2 Crosspoint Switch; 音频/视频， 60兆赫， 16 】 8日， 2交叉点开关增益
| 型号： | AD8112 |
| 厂家： | 
ADI |
| 描述： | Audio/Video, 60 MHz, 16 】 8, Gain of +2 Crosspoint Switch |
| 文件： | 总28页 (文件大小：536K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Audio/Video, 60 MHz, 16 × 8,
Gain of +2 Crosspoint Switch
AD8112
FEATURES
FUNCTIONAL BLOCK DIAGRAM
SER/PAR D0 D1 D2 D3 D4
Low cost, 16 × 8, high speed, nonblocking switch array
Pin-compatible 16 × 16 version available (AD8113)
Serial or parallel programming of switch array
Serial data out allows daisy chaining control of multiple
16 × 8 arrays to create larger switch arrays
Output disable allows connection of multiple devices
without loading the output bus
A0
A1
A2
CLK
80-BIT SHIFT REGISTER
DATA
OUT
WITH 5-BIT
DATA IN
UPDATE
PARALLEL LOADING
40
40
Complete solution
Buffered inputs
8 output amplifiers
Operates on ±± V or ±12 V supplies
Low supply current of ±4 mA
CE
PARALLEL LATCH
NO
CONNECT
RESET
40
8
DECODE
8 × 5:16 DECODERS
OUTPUT
BUFFER
G = +2
Excellent audio performance VS = ±12 V
±10 V output swing
AD8112
128
0.002% THD at 20 kHz maximum 20 V p-p (RL = 600 Ω)
Excellent video performance VS = ±± V
0.1 dB gain flatness of 10 MHz
0.1% differential gain error (RL = 1 kΩ)
0.1° differential phase error (RL = 1 kΩ)
Excellent ac performance
SWITCH
MATRIX
−3 dB bandwidth 60 MHz
Low all-hostile crosstalk of −83 dB at 20 kHz
Reset pin allows disabling of all outputs (connected to a
capacitor to ground provides power-on reset capability)
100-lead LQFP (14 mm × 14 mm)
Figure 1.
APPLICATIONS
CCTV surveillance/DVR
Analog/digital audio routers
Video routers (NTSC, PAL, S-Video, SECAM)
Multimedia systems
Video conferencing
GENERAL DESCRIPTION
The AD8112 includes eight independent output buffers that can
be placed into a disabled state for paralleling crosspoint outputs
so that off channel loading is minimized. The AD8112 has a gain
of +2. It operates on voltage supplies of 5 V or 12 V while
consuming only 34 mA or 31 mA of current, respectively. The
channel switching is performed via a serial digital control (which
can accommodate the daisy chaining of several devices) or via
a parallel control, allowing updating of an individual output
without reprogramming the entire array.
The AD8112 is a low cost, fully buffered crosspoint switch matrix
that operates on 12 V for audio applications and 5 V for
video applications. It offers a −3 dB signal bandwidth greater
than 60 MHz and channel switch times of less than 60 ns with
0.1% settling for use in both analog and digital audio. The
AD8112 operated at 20 kHz has a crosstalk performance of
−83 dB and isolation of 90 dB. In addition, ground/power pins
surround all inputs and outputs to provide extra shielding for
operation in the most demanding audio routing applications.
With a differential gain and differential phase better than 0.1%
and 0.1°, respectively, and a 0.1 dB flatness output of up to 10 MHz,
the AD8112 is suitable for many video applications.
The AD8112 is packaged in a 100-lead LQFP and is available
over the commercial temperature range of 0°C to 70°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2007 Analog Devices, Inc. All rights reserved.
AD8112
TABLE OF CONTENTS
Features .............................................................................................. 1
Calculation of Power Dissipation............................................. 17
Short-Circuit Output Conditions............................................. 18
Application Notes........................................................................... 19
Serial Programming................................................................... 19
Parallel Programming................................................................ 19
Power-On Reset.......................................................................... 20
Specifying Audio Levels ............................................................ 20
Creating Unity-Gain Channels................................................. 20
Video Signals............................................................................... 20
Creating Larger Crosspoint Arrays.......................................... 21
Multichannel Video and Audio................................................ 23
Crosstalk...................................................................................... 23
PCB Layout...................................................................................... 26
Outline Dimensions....................................................................... 28
Ordering Guide .......................................................................... 28
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics (Serial) .................................................. 5
Timing Characteristics (Parallel) ............................................... 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Power Dissipation......................................................................... 7
Pin Configuration and Function Descriptions............................. 9
I/O Schematics............................................................................ 11
Typical Performance Characteristics ........................................... 12
Theory of Operation ...................................................................... 17
REVISION HISTORY
2/07—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
AD8112
SPECIFICATIONS
TA = 25°C, VS = 12 V, RL = 600 Ω, unless otherwise noted.
Table 1.
Parameter
Conditions
Min
Typ
Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth
VOUT = 200 mV p-p, RL = 600 Ω, VS = ±±2 V
VOUT = 200 mV p-p, RL = ±50 Ω, VS = ±5 V
VOUT = 8 V p-p, RL = 600 Ω, VS = ±±2 V
VOUT = 2 V p-p, RL = ±50 Ω, VS = ±5 V
0.± dB, VOUT = 200 mV p-p, RL = ±50 Ω, VS = ±5 V
VOUT = 2 V p-p, RL = ±50 Ω
0.±%, 2 V Step, RL = ±50 Ω, VS = ±5 V
2 V step, RL = ±50 Ω, VS = ±5 V
20 V step, RL = 600 Ω, VS = ±±2 V
46
4±
60
60
±0
25
±0
20
23
±00
±20
MHz
MHz
MHz
MHz
MHz
ns
ns
V/μs
V/μs
Gain Flatness
Propagation Delay
Settling Time
Slew Rate
NOISE/DISTORTION PERFORMANCE
Differential Gain Error
Differential Phase Error
Total Harmonic Distortion
Crosstalk, All Hostile
NTSC, RL = ± kΩ, VS = ±5 V
NTSC, RL = ± kΩ, VS = ±5 V
20 kHz, RL = 600 Ω, 20 V p-p
f = 5 MHz, RL = ±50 Ω, VS = ±5 V
f = 20 kHz
f = 5 MHz, RL = ±50 Ω, VS = ±5 V, one channel
f = 20 kHz, one channel
20 kHz
0.±
0.±
%
Degrees
%
dB
dB
dB
dB
nV/√Hz
nV/√Hz
0.002
−67
−83
−±00
−83
±4
Off Isolation
Input Voltage Noise
0.± MHz to ±0 MHz
±2
DC PERFORMANCE
Gain Error
No load, VS = ±±2 V, VOUT = ±8 V
RL = 600 Ω, VS = ±±2 V
RL = ±50 Ω, VS = ±5 V
No load, channel-to-channel
RL = 600 Ω, channel-to-channel
RL = ±50 Ω, channel-to-channel
0.3
0.5
0.5
0.7
0.7
0.7
20
2.5
3.5
%
%
%
%
%
%
Gain Matching
Gain Temperature Coefficient
OUTPUT CHARACTERISTICS
Output Resistance
ppm/°C
Enabled
Disabled
Disabled
VS = ±5 V, no load
VS = ±±2 V, no load
IOUT = 20 mA, VS = ±5 V
IOUT = 20 mA, VS = ±±2 V
RL = 0 Ω
0.3
4
5
±3.5
±±0.5
±3
±±0
55
Ω
3.4
kΩ
pF
V
V
V
Output Capacitance
Output Voltage Swing
±3.2
±±0.3
±2.7
±ꢀ.8
V
mA
Short-Circuit Current
INPUT CHARACTERISTICS
Input Offset Voltage
All configurations
Temperature coefficient
No load, VS = ±5 V
VS = ±±2 V
±4.5
±0
±±.5
±5.0
4
±8.5 mV
μV/°C
Input Voltage Range
V
V
pF
MΩ
μA
Input Capacitance
Input Resistance
Input Bias Current
Any switch configuration
50
±±.6
Any number of enabled inputs
+±
Rev. 0 | Page 3 of 28
AD8112
Parameter
Conditions
Min
Typ
Max Unit
SWITCHING CHARACTERISTICS
Enable On Time
Switching Time, 2 V Step
Switching Transient (Glitch)
POWER SUPPLIES
80
50
20
ns
ns
mV p-p
50% update to ±% settling
Supply Current
AVCC outputs enabled, no load, VS = ±±2 V
AVCC outputs disabled, VS = ±±2 V
AVCC outputs enabled, no load, VS = ±5 V
AVCC outputs disabled, VS = ±5 V
AVEE outputs enabled, no load, VS = ±±2 V
AVEE outputs disabled, VS = ±±2 V
AVEE outputs enabled, no load, VS = ±5 V
AVEE outputs disabled, VS = ±5 V
50
34
45
3±
50
34
45
3±
8
54
38
50
35
54
38
50
35
±3
mA
mA
mA
mA
mA
mA
mA
mA
mA
DVCC outputs enabled, no load
DYNAMIC PERFORMANCE
Supply Voltage Range
AVCC
AVEE
DVCC
4.5
−±2.6
4.5
±2.6
−4.5
5.5
V
V
V
PSRR
DC
f = ±00 kHz
f = ± MHz
75
80
60
40
dB
dB
dB
OPERATING TEMPERATURE RANGE
Temperature Range
θJA
Operating (still air)
Operating (still air)
0 to 70
40
°C
°C/W
Rev. 0 | Page 4 of 28
AD8112
TIMING CHARACTERISTICS (SERIAL)
Table 2.
Limit
Typ
Parameter
Symbol
Min
20
±00
20
±00
0
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
μs
ns
ns
Serial Data Setup Time
CLK Pulse Width
Serial Data Hold Time
CLK Pulse Separation, Serial Mode
CLK to UPDATE Delay
t±
t2
t3
t4
t5
t6
t7
UPDATE Pulse Width
50
CLK to DATA OUT Valid, Serial Mode
Propagation Delay, UPDATE to Switch On or Off
Data Load Time, CLK = 5 MHz, Serial Mode
CLK, UPDATE Rise and Fall Times
RESET Time
200
50
±6
±00
200
t2
t4
1
CLK
0
LOAD DATA INTO
SERIAL REGISTER
ON FALLING EDGE
t1
t3
1
OUT07 (D4)
OUT07 (D3)
OUT00 (D0)
DATA IN
0
t5
t6
1 = LATCHED
TRANSFER DATA FROM SERIAL
REGISTER TO PARALLEL
LATCHES DURING LOW LEVEL
UPDATE
0 = TRANSPARENT
t7
DATA OUT
Figure 2. Timing Diagram, Serial Mode
Table 3. Logic Levels
Pins
VIH
VIL
0.8 V max
VOH
VOL
IIH
IIL
IOH
IOL
RESET, SER/PAR,
CLK, DATA IN, CE,
UPDATE
2.0 V min
20 μA max
−400 μA min
DATA OUT
2.7 V min
0.5 V max
−400 μA max
3.0 mA min
Rev. 0 | Page 5 of 28
AD8112
TIMING CHARACTERISTICS (PARALLEL)
Table 4.
Limit
Max
Parameter
Symbol
Min
20
±00
20
±00
0
Unit
ns
ns
ns
ns
Data Setup Time
CLK Pulse Width
Data Hold Time
CLK Pulse Separation
CLK to UPDATE Delay
UPDATE Pulse Width
Propagation Delay, UPDATE to Switch On or Off
CLK, UPDATE Rise and Fall Times
RESET Time
t±
t2
t3
t4
t5
t6
ns
50
ns
50
ns
±00
200
ns
ns
t2
t4
1
CLK
0
t1
t3
1
0
D0 TO D4
A0 TO A2
t5
t6
1 = LATCHED
UPDATE
0 = TRANSPARENT
Figure 3. Timing Diagram, Parallel Mode
Table 5. Logic Levels
Pins
VIH
2.0 V min
VIL
VOH
VOL
IIH
IIL
IOH
IOL
RESET, SER/PAR,
CLK, D0, D±, D2,
D3, D4, A0, A±, A2,
CE, UPDATE
0.8 V max
20 μA max
−400 μA min
DATA OUT
2.7 V min
0.5 V max
−400 μA max
3.0 mA min
Rev. 0 | Page 6 of 28
AD8112
ABSOLUTE MAXIMUM RATINGS
Table 6.
POWER DISSIPATION
The AD8112 is operated with ±5 V to ±12 V supplies and can
drive loads down to 150 Ω (±5 V) or 600 Ω (±12 V), resulting
in a large range of possible power dissipations. For this reason,
extra care must be taken when derating the operating conditions
based on ambient temperature.
Parameter
Rating
Analog Supply Voltage (AVCC to AVEE)
Digital Supply Voltage (DVCC to DGND)
Ground Potential Difference (AGND to DGND) ±0.5 V
Internal Power Dissipation±
Analog Input Voltage2
26.0 V
6 V
3.± W
Maintain linear output
DVCC
(AVCC − ±.5 V) to
(AVEE + ±.5 V)
Momentary
−65°C to +±25°C
300°C
Packaged in a 100-lead LQFP, the AD8112 junction-to-ambient
thermal impedance (θJA) is 40°C/W. For long-term reliability,
the maximum allowed junction temperature of the plastic encap-
sulated die should not exceed 150°C. Temporarily exceeding
this limit may cause a shift in parametric performance due
to a change in the stresses exerted on the die by the package.
Exceeding a junction temperature of 175°C for an extended
period can result in device failure. The curve in Figure 4 shows
the range of allowed power dissipations that meet these conditions
over the commercial range of ambient temperatures.
Digital Input Voltage
Output Voltage (Disabled Output)
Output Short-Circuit Duration
Storage Temperature Range
Lead Temperature (Soldering ±0 sec)
± Specification is for device in free air (TA = 25°C):
±00-lead plastic LQFP (ST): θJA = 40°C/W.
2
To avoid differential input breakdown, ensure that one-half the output
voltage (±/2 VOUT) and any input voltage is less than ±0 V of the potential
differential. See Output Voltage Swing specification for linear output range.
4.0
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
T
= 150°C
J
3.5
3.0
2.5
2.0
ESD CAUTION
0
10
20
30
40
50
60
70
AMBIENT TEMPERATURE (°C)
Figure 4. Maximum Power Dissipation vs. Ambient Temperature
Rev. 0 | Page 7 of 28
AD8112
Table 7. Operation Truth Table
CE UPDATE
RESET SER/PAR
CLK DATA IN
DATA OUT
X
Data i-80
Operation/Comment
±
0
X
±
X
X
X
±
X
0
No change in logic.
Data i
The data on the serial DATA IN line is loaded into serial register.
The first bit clocked into the serial register appears at DATA OUT
80 clocks later.
0
±
D0 ... D4,
A0 ... A2
N/A in
Parallel
Mode
±
±
The data on the parallel data lines, D0 to D4, is loaded into the
80-bit serial shift register location addressed by A0 to A2.
0
0
X
X
X
X
X
±
0
X
X
Data in the 80-bit shift register transfers into the parallel
latches that control the switch array. Latches are transparent.
Asynchronous operation. All outputs are disabled. Remainder
of logic is unchanged.
X
X
X
D0
D1
D2
D3
D4
PARALLEL
DATA
(OUTPUT
ENABLE)
SER/PAR
S
S
S
S
S
S
S
S
S
S
S
S
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D Q
CLK
D
Q
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D Q
DATA OUT
Q
Q
Q
Q
D0
Q
D0
Q
Q
D0
Q
D0
Q
D0
Q
D0
Q
D0
DATA IN
(SERIAL)
D0
D0
D0
D0
D0
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CE
UPDATE
OUT00 EN
OUT01 EN
OUT02 EN
OUT03 EN
OUT04 EN
OUT05 EN
OUT06 EN
OUT07 EN
A0
A1
A2
LE
D
LE
D
LE
D
LE
D
LE
D
LE
D
LE
D
LE
D
LE
D
LE
D
LE
D
LE D
OUT00
B0
OUT00
B1
OUT00
B2
OUT00
B3
OUT00
EN
OUT01
B0
OUT06
EN
OUT07
B0
OUT07
B1
OUT07
B2
OUT07
B3
OUT07
EN
Q
Q
Q
Q
CLR
Q
Q
CLR
Q
Q
Q
Q
Q
CLR Q
RESET
(OUTPUT ENABLE)
DECODE
8
128
SWITCH MATRIX
OUTPUT ENABLE
Figure 5. Logic Diagram
Rev. 0 | Page 8 of 28
AD8112
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DV
DV
CC
CC
PIN 1
2
3
DGND
AGND
IN08
DGND
AGND
IN07
4
5
AGND
IN09
AGND
IN06
6
7
AGND
IN10
AGND
IN05
8
9
AGND
IN04
AGND
IN11
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
AGND
IN12
AGND
IN03
AD8112
TOP VIEW
AGND
IN13
AGND
IN02
(Not to Scale)
AGND
IN14
AGND
IN01
AGND
IN15
AGND
IN00
AGND
AGND
AV
AV
AV
EE
CC
CC
EE
CC
AV
AV
AV 00
CC
NC
OUT00
AV
AV 00/01
EE
EE
NC
OUT01
NC = NO CONNECT
Figure 6. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
Mnemonic
IN00 to IN±5±
Description
58, 60, 62, 64, 66, 68, 70, 72, 4, 6, 8, ±0,
±2, ±4, ±6, ±8
Analog Inputs for Channel Numbers 00 through ±5.
ꢀ6
ꢀ7
ꢀ8
ꢀ5
DATA IN
CLK
DATA OUT
UPDATE
Serial Data Input, TTL-compatible.
Clock, TTL-compatible. Falling edge triggered.
Serial Data Output, TTL-compatible.
Enable (Transparent) Low. Allows serial register to connect directly to switch
matrix. Data latched when high.
±00
ꢀꢀ
RESET
CE
Disable Outputs, Active Low.
Chip Enable, Enable Low. Must be low to clock in and latch data.
ꢀ4
SER/PAR
Serial Data/Parallel Data. When low, this pin selects serial data mode; when
high, this pin selects parallel data mode, high. Must be connected.
53, 5±, 4ꢀ, 47, 45, 43, 4±, 3ꢀ
OUT00 to
OUT07±
Analog Outputs for Channel Numbers 00 Through 07.
3, 5, 7, ꢀ, ±±, ±3, ±5, ±7, ±ꢀ, 57, 5ꢀ, 6±, 63, AGND
65, 67, 6ꢀ, 7±, 73
Analog Ground for Inputs and Switch Matrix. Must be connected.
±, 75
2, 74, 8±
20, 24, 28, 32, 36, 56
DVCC
DGND
AVEE
5 V for Digital Circuitry.
Ground for Digital Circuitry.
−5 V for Inputs and Switch Matrix.
Rev. 0 | Page ꢀ of 28
AD8112
Pin No.
Mnemonic
AVCC
AVCCxx
Description
21, 22, 26, 30, 34, 38, 55
54
5 V for Inputs and Switch Matrix.
5 V for Output Amplifier. This pin is shared by Channel Numbers xx and yy.
Must be connected.
50, 46, 42
AVCCxx/yy1
AVEExx/yy1
5 V for Output Amplifier. This pin is shared by Channel Numbers xx and yy.
Must be connected.
−5 V for Output Amplifier. This pin is shared by Channel Numbers xx and yy.
Must be connected.
52, 48, 44, 40
84
83
82
80
79
78
77
76
A0
A1
A2
D0
D1
D2
D3
D4
NC
Parallel Data Input, TTL-compatible (Output Select LSB).
Parallel Data Input, TTL-compatible (Output Select).
Parallel Data Input, TTL-compatible (Output Select).
Parallel Data Input, TTL-compatible (Input Select LSB).
Parallel Data Input, TTL-compatible (Input Select).
Parallel Data Input, TTL-compatible (Input Select).
Parallel Data Input, TTL-compatible (Input Select MSB).
Parallel Data Input, TTL-compatible (Output Enable).
No Connect.
23, 25, 27, 29, 31, 33, 35, 37, 85 to 93
1 xx = Chanel numbers 00 through 15 for analog inputs; yy = channel numbers 00 through 07 for analog outputs.
Rev. 0 | Page 10 of 28
AD8112
I/O SCHEMATICS
V
CC
V
CC
ESD
ESD
ESD
INPUT
INPUT
ESD
DGND
AV
EE
Figure 7. Analog Input
Figure 10. Logic Input
V
CC
V
CC
2kΩ
ESD
ESD
ESD
ESD
OUTPUT
OUTPUT
DGND
AV
EE
Figure 8. Analog Output
Figure 11. Logic Output
V
CC
ESD
20kΩ
RESET
ESD
DGND
Figure 9. Reset Input
Rev. 0 | Page ±± of 28
AD8112
TYPICAL PERFORMANCE CHARACTERISTICS
3
3
0
0
–3
–6
–3
–6
0.01
0.1
1
10
100
0.1
1
10
FREQUENCY (MHz)
100
FREQUENCY (MHz)
Figure 12. Small-Signal Bandwidth, VS = 5 V, RL = 150 Ω, VOUT = 200 mV p-p
Figure 15. Small-Signal Bandwidth, VS = ±12 V, RL = 600 Ω, VOUT = 200 mV p-p
0.3
0.3
0.2
0.2
0.1
0
0.1
0
–0.1
–0.1
–0.2
–0.3
–0.2
–0.3
0.1
1
10
FREQUENCY (MHz)
100
0.1
1
10
FREQUENCY (MHz)
100
Figure 13. Small-Signal Gain Flatness, VS = 5 V, RL = 150 Ω, VOUT = 200 mV p-p
Figure 16. Small-Signal Gain Flatness, VS = 12 V, RL = 600 Ω, VOUT = 200 mV p-p
3
0
3
0
–3
–6
–3
–6
0.1
1
10
FREQUENCY (MHz)
100
0.1
1
10
FREQUENCY (MHz)
100
Figure 14. Large-Signal Bandwidth, VS = ±5 V, RL = 150 Ω, VOUT = 2 V p-p
Figure 17. Large-Signal Bandwidth, VS = 12 V, RL = 600 Ω, VOUT = 8 V p-p
Rev. 0 | Page ±2 of 28
AD8112
0.3
0.2
0.3
0.2
0.1
0.1
0
0
–0.1
–0.2
–0.3
–0.1
–0.2
–0.3
0.1
1
10
0.1
1
10
FREQUENCY (MHz)
100
FREQUENCY (MHz)
Figure 18. Large-Signal Gain Flatness, VS = 5 V, RL = 150 Ω, VOUT = 2 V p-p
Figure 21. Large-Signal Gain Flatness, VS = ±12 V, RL = 600 Ω, VOUT = 8 V p-p
–30
–40
ALL HOSTILE
–40
–50
ALL HOSTILE
–60
–50
ADJACENT
–60
–70
–80
ADJACENT
–70
–80
–90
–90
–100
0.1
1
10
FREQUENCY (MHz)
100
0.01
0.1
1
10
100
FREQUENCY (MHz)
Figure 19. Crosstalk vs. Frequency, VS = 5 V, RL = 150 Ω, VOUT = 2 V p-p
Figure 22. Crosstalk vs. Frequency, VS = 12 V, RL = 600 Ω, VOUT = 20 V p-p
–70
–75
–80
–85
–50
–60
–70
SECOND HARMONIC
–80
SECOND HARMONIC
–90
–95
–90
–100
–100
THIRD HARMONIC
THIRD HARMONIC
–110
0.001
–105
0.001
0.01
0.1
1
10
100
0.01
0.1
1
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 23. Distortion vs. Frequency, VS = 12 V, RL = 600 Ω, VOUT = 20 V p-p
Figure 20. Distortion vs. Frequency, VS = ±5 V, RL = 150 Ω, VOUT = 2 V p-p
Rev. 0 | Page ±3 of 28
AD8112
300
250
200
150
100
50
INPUT
V
R
= ±12V
= 600Ω
S
OUTPUT
2
L
– INPUT
V
R
= ±5V
= 150Ω
S
L
OUTPUT
0
0
0
5
10
15
20
25
5ns/DIV
30
35
40
45
50
5
10
15
20
25
30
35
SERIES RESISTANCE (Ω)
Figure 24. Capacitive Load vs. Series Resistance for Less than 30% Overshoot
Figure 27. Settling Time to 0.1%, 2 V Step, VS = 5 V, RL = 150 Ω
10k
10k
1k
100
10
1k
100
10
1
0.1
1
0.1
1
10
100
1k
1
10
100
1k
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 25. Disabled Output Impedance vs. Frequency, VS = 5 V
Figure 28. Disabled Output Impedance vs. Frequency, VS = 12 V
1k
1k
100
10
1
100
10
1
0.1
0.1
0.1
0.1
1
10
100
1k
1
10
100
1k
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 26. Enabled Output Impedance vs. Frequency, VS = 5 V
Figure 29. Enabled Output Impedance vs. Frequency, VS = 12 V
Rev. 0 | Page ±4 of 28
AD8112
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
–20
–40
+PSRR
+PSRR
–PSRR
–60
–PSRR
–80
–100
0.01
0.1
1
10
0.01
0.1
FREQUENCY (MHz)
1
10
FREQUENCY (MHz)
Figure 30. PSRR vs. Frequency, VS = 5 V
Figure 33. PSRR vs. Frequency, VS = 12 V
160
140
120
100
80
0
–20
–40
V
R
= ±12V
= 600Ω
S
–60
L
V
= 8V p-p
OUT
60
–80
40
V
R
= ±5V
= 150Ω
S
–100
20
L
V
= 2V p-p
OUT
–120
0
0.1
1
10
100
10
100
1k
10k
100k
1M
10M
FREQUENCY (MHz)
FREQUENCY (Hz)
Figure 31. Noise vs. Frequency
Figure 34. Off Isolation vs. Frequency
50mV/DIV
50mV/DIV
100ns/DIV
50ns/DIV
Figure 32. Small-Signal Pulse Response, VS = 5 V, RL = 150 Ω
Figure 35. Small-Signal Pulse Response, VS = 12 V, RL = 600 Ω
Rev. 0 | Page ±5 of 28
AD8112
500mV/DIV
5V/DIV
100ns/DIV
100ns/DIV
Figure 36. Large-Signal Pulse Response, VS = 5 V, RL = 150 Ω
Figure 39. Large-Signal Pulse Response, VS = 12 V, RL = 600 Ω
UPDATE
UPDATE
2V/DIV
2V/DIV
V
OUT
V
OUT
INPUT 0
INPUT 1
INPUT 1
10V/DIV
INPUT 0
100ns/DIV
100ns/DIV
Figure 37. Switching Time, VS = 5 V, RL = 150 Ω
Figure 40. Switching Time, VS = 12 V, RL = 600 Ω
UPDATE
UPDATE
1V/DIV
1V/DIV
OUTPUT
OUTPUT
20mV/DIV
20mV/DIV
100ns/DIV
100ns/DIV
Figure 38. Switching Transient, VS = 5 V, RL = 150 Ω
Figure 41. Switching Transient, VS = 12 V, RL = 600 Ω
Rev. 0 | Page ±6 of 28
AD8112
THEORY OF OPERATION
these clamps, increasing power dissipation. The valid input
The AD8112 has a gain of +2 and is a crosspoint array with
eight outputs, each of which can be connected to any one of 16
inputs. Organized by output row, 16 switchable transconductance
stages are connected to each output buffer in the form of a 16-to-1
multiplexer. Each of the 16 rows of transconductance stages are
wired in parallel to the 16 input pins, for a total array of 256 trans-
conductance stages. Decoding logic for each output selects one
(or none) of the transconductance stages to drive the output
stage. The transconductance stages are NPN input differential
pairs, sourcing current into the folded cascode output stage.
The compensation networks and emitter follower output buffers
are in the output stage. Voltage feedback sets the gain at +2.
range for 12 V supplies is 5 V. The valid input range for 5 V
supplies is 1.5 V. When outputs are disabled and being driven
externally, the voltage applied to them should not exceed the
valid output swing range for the AD8112. Exceeding 10.5 V on
the outputs of the AD8112 may apply a large differential voltage
on the unused transconductance stages and should be avoided.
A flexible TTL-compatible logic interface simplifies the pro-
gramming of the matrix. Either parallel or serial loading into
a first rank of latches programs each output. A global latch
simultaneously updates all outputs. In serial mode, a serial
output pin allows devices to be daisy-chained together for
single pin programming of multiple ICs. A power-on reset
pin is available to avoid bus conflicts by disabling all outputs.
When operated with 12 V supplies, this architecture provides
10 V drive for 600 Ω audio loads with extremely low distortion
(<0.002%) at audio frequencies. Provided the supplies are low-
ered to 5 V (to limit power consumption), the AD8112 can
drive reverse-terminated video loads, swinging 3.0 V into
150 Ω. Disabling unused outputs and transconductance
stages minimizes on-chip power consumption.
Regardless of the supply voltage applied to the AVCC and AVEE
pins, the digital logic requires 5 V on the DVCC pin with respect
to DGND. In order for the digital-to-analog interface to work
properly, DVCC must be at least 7 V above AVEE. Finally, internal
ESD protection diodes require that the DGND and AGND pins
be at the same potential.
Features of the AD8112 facilitate the construction of larger
switch matrices. The unused outputs can be disabled, leaving
only a feedback network resistance of 4 kΩ on the output. This
allows multiple ICs to be bused together, provided the output
load impedance is greater than the minimum allowed values.
Because no additional input buffering is necessary, high input
resistance and low input capacitance are easily achieved without
additional signal degradation.
CALCULATION OF POWER DISSIPATION
4.0
T
= 150°C
J
3.5
3.0
2.5
2.0
The AD8112 inputs have a unique bias current compensation
scheme that overcomes a problem common to transconductance
input array architectures. Typically, an input bias current increases
as more transconductance stages connected to the same input
are turned on. Anywhere from zero to 16 transconductance
stages can share one input pin, so there is a varying amount of
bias current supplied through the source impedance driving
the input. For audio systems with larger source impedances,
this has the potential of creating large offset voltages, audible
as pops when switching between channels. The AD8112 samples
and cancels the input bias current contributions from each
transconductance stage so that the residual bias current is
nominally zero regardless of the number of enabled inputs.
0
10
20
30
40
50
60
70
AMBIENT TEMPERATURE (°C)
Figure 42. Maximum Power Dissipation vs. Ambient Temperature
The curve in Figure 42 was calculated from
TJUNCTION , MAX − TAMBIENT
PD, MAX
=
θJA
As an example, if the AD8112 is enclosed in an environment
at 50°C (TA), the total on-chip dissipation under all load and
supply conditions must not be allowed to exceed 2.5 W.
Due to the flexibility in allowed supply voltages, internal cross-
talk isolation clamps have variable bias levels. These levels were
chosen to allow for the necessary input range to accommodate
the full output swing with a gain of +2. Overdriving the inputs
beyond the device’s linear range will eventually forward bias
Rev. 0 | Page ±7 of 28
AD8112
2. Calculate the power dissipation from the loads.
When calculating on-chip power dissipation, it is necessary to
include the rms current being delivered to the load multiplied
by the rms voltage drop on the AD8112 output devices. The
dissipation of the on-chip, 4 kΩ feedback resistor network
must also be included. For a sinusoidal output, the on-chip
power dissipation due to the load and feedback network can
be approximated by
PD, OUTPUT = (AVCC − VOUTPUT, RMS) × IOUTPUT, RMS
+
VOUTPUT2/4 kΩ
PD, OUTPUT = (12 V − 6 V) × 6 V/600 Ω + (6 V)2/4 kΩ =
69 mW
There are eight outputs, thus
2
nPD, OUTPUT = 8 × 69 mW = 0.55 W
⎛
⎜
⎞
⎟
VOUTPUT, RMS
PD
=
(
AVCC −VOUTPUT, RMS
)
× IOUTPUT, RMS
+
, MAX
⎜
⎜
⎟
⎟
3. Subtract quiescent output current for number of loads
(assumes output voltage >> 0.5 V).
4 kΩ
⎝
⎠
PDQ, OUTPUT = (AVCC − AVEE) × IO, QUIESCENT
For nonsinusoidal output, the power dissipation is calculated
by integrating the on-chip voltage drop multiplied by the load
current over one period.
PDQ, OUTPUT = (12 V − (−12 V)) × 0.67 mA = 16 mW
There are eight outputs, thus
nPDQ, OUTPUT = 8 × 16 mW = 0.13 W
The user can subtract the quiescent current for the Class AB
output stage when calculating the loaded power dissipation.
For each output stage driving a load, subtract a quiescent power
4. Verify that power dissipation does not exceed the maxi-
mum allowed value.
according to
PD, ON-CHIP = PD, QUIESCENT + nPD, OUTPUT − nPDQ, OUTPUT
PD, OUTPUT = (AVCC − AVEE) × IO, QUIESCENT
PD, ON-CHIP = 1.3 W + 0.55 W − 0.13 W = 1.7 W
where:
IO, QUIESCENT = 0.67 mA.
This power dissipation is below the maximum allowed
dissipation for all ambient temperatures approaching 70°C.
For each disabled output, the quiescent power supply current
in AVCC and AVEE drops by approximately 1.25 mA, although
there is a power dissipation in the on-chip feedback resistors if
the disabled output is being driven from an external source.
It can be shown that for a dual supply of a, a Class AB output
stage dissipates maximum power into a grounded load when
the output voltage is a/2. Therefore, for a 12 V supply, the
previous example demonstrates the worst-case power dissi-
pation into 600 Ω. It can be seen from this example that the
minimum load resistance for 12 V operation is 600 Ω for
full rated operating temperature range. For larger safety margins
when the output signal is unknown, loads of 1 kΩ and greater
are recommended. When operating with 5 V supplies, this
load resistance can be lowered to 150 Ω.
AV
CC
I
O, QUIESCENT
QNPN
QPNP
V
I
OUTPUT
RF
4kΩ
OUTPUT
AGND
SHORT-CIRCUIT OUTPUT CONDITIONS
I
O, QUIESCENT
Although there is short-circuit current protection on the AD8112
outputs, the output current can reach values of 55 mA into a
grounded output. Sustained operation with even one shorted
output will exceed the maximum die temperature and may
result in device failure (see the Absolute Maximum Ratings
section).
AV
EE
Figure 43. Simplified Output Stage
Example
The power supplies of the AD8112 with an ambient temperature
of 70°C and all eight outputs driving 6 V rms into 600 Ω loads
are 12 V.
1. Calculate the power dissipation of the AD8112 using
quiescent currents (see the Specifications section).
P
D, QUIESCENT = (AVCC + IAVCC) + (AVEE × IAVEE) +
(DVCC × IDVCC
)
PD, QUIESCENT = (12 V × 54 mA) + (−12 V × −54 mA) +
(5 V × 13 mA) = 1.3 W
Rev. 0 | Page ±8 of 28
AD8112
APPLICATION NOTES
The AD8112 has two options for changing the programming
of the crosspoint matrix. In the first option, a serial word of 80
bits is provided to update the entire matrix. The serial data needs
to be prefixed with 40 zeros because there are 40 unconnected
bits. The second option allows for changing a single output’s
programming via a parallel interface. The serial option requires
fewer signals but more time (clock cycles) for changing the pro-
gramming, whereas the parallel programming technique
requires more signals but can change outputs individually
and requires fewer clock cycles to complete programming.
PARALLEL PROGRAMMING
When using the parallel programming mode, it is not necessary
to reprogram the entire device when making changes to the
matrix. In fact, parallel programming allows the modification
UPDATE
of a single output. Because this requires only one CLK/
cycle, significant time is saved by using parallel programming.
One important consideration when using parallel programming
RESET
When taken low, the
is that the
signal does not reset all registers in the AD8112.
RESET
signal only sets each output to the
disabled state. This is helpful during power-up to ensure that
two parallel outputs will not be active at the same time.
SERIAL PROGRAMMING
CE
The serial programming mode uses the device pins: , CLK,
After initial power-up, the internal registers in the device gener-
UPDATE
SER
, and /PAR. The first step is to assert
DATA IN,
a low on
RESET
ally have random data, even though the
signal has been
SER
/PAR to enable the serial programming mode. The
asserted. If parallel programming is used to program one output,
then that output is properly programmed, but the rest of the
device has a random program state depending on the internal
register content at power-up. Therefore, when using parallel
programming, it is essential that all outputs be programmed to
a desired state after power-up to ensure that the programming
matrix is always in a known state. Then, parallel programming
can be used to modify a single output or multiple outputs.
CE
pin for the chip must be low to allow data to be clocked into
CE
the device. The
device when devices are connected in parallel.
signal can be used to address an individual
UPDATE
The
shifted into the device’s serial port. Although the data shifts in
UPDATE
signal should be high during the time that data is
when
is low, the transparent asynchronous latches allow
the shifting data to reach the matrix. This causes the matrix to
try to update to every intermediate state as defined by the
shifting data.
CE
UPDATE
are taken low after initial
Similarly, if both
and
power-up, the random power-up data in the shift register is
programmed into the matrix. Therefore, to prevent the crosspoint
from being programmed into an unknown state, do not apply
The data at DATA IN is clocked in upon each falling edge of
CLK. A total of 80 bits must be shifted in to complete the pro-
gramming because there are 40 unconnected bits. For each of
the eight outputs, there are four bits (D0 to D3) that determine
the source of the input followed by one bit (D4) that determines
the enabled state of the output. If D4 is low (output disabled),
the four associated bits (D0 to D3) do not matter, because no
input will be switched to that output.
CE
UPDATE
low logic levels to both
and
after power is initially
applied. Programming the full shift register one time to a desired
state, by either serial or parallel programming after initial
power-up, eliminates the possibility of programming the matrix
to an unknown state.
To change an output programming via parallel programming,
SER
UPDATE
CE
/PAR and
should be taken high and should be
The most significant output address data is shifted in first, and
then followed in sequence until the least significant output address
taken low. The CLK signal should be in the high state. The 3-bit
address of the output to be programmed should be put on A0 to
A2. The first four data bits (D0 to D3) should contain the infor-
mation identifying the input that is programmed to the addressed
output. The fifth data bit (D4) determines the enabled state of
the output. If D4 is low (output disabled), the data on D0 to D3
does not matter.
UPDATE
data is shifted in. At this point
can be taken low, which
programs the device with the data that was just shifted in. The
UPDATE
UPDATE
is low
registers are asynchronous, and when
is low), they are transparent.
CE
(and
If more than one AD8112 device is to be serially programmed
in a system, the DATA OUT signal from one device can be con-
nected to the DATA IN of the next device to form a serial chain.
After the desired address and data signals have been established,
the data can be latched into the shift register by a high to low
transition of the CLK signal. The matrix will not be programmed,
CE UPDATE SER
All of the CLK,
,
, and /PAR pins should be
connected in parallel and operated as described previously. The
serial data is input into the DATA IN pin of the first device
of the chain, and it ripples through to the last device. There-
fore, the data for the last device in the chain should come at the
beginning of the programming sequence. The length of the
programming sequence is 80 bits times the number of devices
in the chain.
UPDATE
however, until the
possible to latch in new data for several or all outputs via suc-
UPDATE
signal is taken low. It is therefore
cessive negative transitions of CLK while
and then for the new data to take effect when
is held high,
UPDATE
goes
Rev. 0 | Page ±ꢀ of 28
AD8112
low. This technique should be used when programming the
device for the first time after power-up when using parallel
programming.
Because P = V2/R, the voltage required to create 1 mW into
600 Ω is 0.775 V rms. This is the voltage reference (0 dB) used
for dBu measurements without regard to the impedance.
The AD8112 operates as a voltage-in/voltage-out device.
Therefore, all parameters are specified in volts, but users
can convert the values to other power units or decibel-type
measurements as required by a particular application.
POWER-ON RESET
When powering up the AD8112, it is usually desirable to have
RESET
the outputs in the disabled state. The
low, causes all outputs to be in the disabled state. However, the
RESET
pin, when taken
signal does not reset all registers in the AD8112. This is
CREATING UNITY-GAIN CHANNELS
important when operating in the parallel programming mode.
(Please refer to the Parallel Programming section for information
about programming internal registers after power-up.) Serial
programming updates the entire matrix, therefore no special
considerations apply.
The channels in the AD8112 each have a gain of +2. This gain is
necessary, as opposed to a gain of unity, to restrict the voltage
on internal nodes to less than the breakdown voltage. If it is
desired to create channels with an overall gain of unity, a resistive
divider can be used at the input to divide the signals by 2. After
passing through any input/output channel combination of the
AD8112, the overall gain of unity is achieved.
Because the data in the shift register is random after power-up,
it should not be used to program the matrix; otherwise the matrix
can enter an unknown state. To prevent this, do not apply logic
+12V
CE
UPDATE
AUDIO
SOURCE
low signals to both
and
immediately after power-
1kΩ
UNITY GAIN
AUDIO OUT
up. The shift register should first be loaded with the desired
UPDATE
AD8112
G = +2
TYPICAL
OUTPUT
TYPICAL
INPUT
data, and then
can be taken low to program the device.
1kΩ
–12V
RESET
The
pin has a 20 kΩ pull-up resistor to DVCC that can be
Figure 44. Input Divide Circuit
used to create a simple power-up reset circuit. A capacitor from
RESET RESET
to ground holds
low until the device stabilizes.
Figure 44 shows a typical input with a divide-by-2 input divider
that creates a unity gain channel. The circuit uses 1 kΩ resistors
to form the divider. These resistors need to be high enough so
they do not overload the drive circuit. But if they are too high,
they generate an offset voltage due to the input bias current that
flows through them. Larger resistors also increase the thermal
noise of the channel.
The low condition causes all the outputs to be disabled. The
capacitor then charges through the pull-up resistor to the high
state, thus allowing full programming capability of the device.
SPECIFYING AUDIO LEVELS
Several methods are used to specify audio levels. A level is actually
a power measurement, which requires not just a voltage meas-
urement, but also a reference impedance. Traditionally both
150 Ω and 600 Ω have been used as references for audio level
measurements.
The circuit shown in Figure 44 can handle inputs that swing
up to 10 V when the AD8112 operates on analog supplies of
12 V. After passing through the divider, the maximum voltage
is 5 V at the input. This maximum input amplitude is 10 V at
the output after the gain of +2 of the channels.
The typical reference power level is 1 mW. Power levels that are
measured relative to this reference level are given the designation
dBm. However, it is necessary to be sure of the reference imped-
ance used for such measurements. This can be either explicit
(for example, 0 dBm (600 Ω)) or implicit (if there is an agree-
ment on what the reference impedance is).
VIDEO SIGNALS
Unlike audio signals, which have lower bandwidths and longer
wavelengths, video signals often use controlled-impedance
transmission lines that are terminated in their characteristic
impedance. Although this is not always the case, there are some
considerations when using the AD8112 to route video signals
with controlled-impedance transmission lines. Figure 45 shows
a schematic of an input and output treatment of a typical video
channel.
Because modern voltmeters have high input impedances, meas-
urements can be made that do not terminate the signal. Therefore,
it is not proper to consider this type of measurement a dBm, or
power measurement. However, a measurement scale that is
designated dBu is used to measure unterminated voltages. This
scale has a voltage reference for 0 dBu that is the same as the
voltage required to produce 0 dBm (600 Ω).
+5V
OR +12V
75Ω
TRANSMISSION
TYPICAL
INPUT
TYPICAL
OUTPUT
LINE
AD8112
G = +2
75Ω
75Ω
75Ω
75Ω
VIDEO
SOURCE
–5V
OR –12V
Figure 45. Video Signal Circuit
Rev. 0 | Page 20 of 28
AD8112
Video signals usually use 75 Ω transmission lines that need to
be terminated with this value of resistance at each end. When
such a source is delivered to one of the AD8112 inputs, the high
input impedance does not properly terminate these signals.
Therefore, the line should be terminated with a 75 Ω shunt
resistor to ground. Because video signals are limited in their
peak-to-peak amplitude, there is no need to attenuate video
signals before they pass through the AD8112.
The basic concept in constructing larger crosspoint arrays is
to connect inputs in parallel in a horizontal direction and to
wire-OR the outputs together in the vertical direction. The
meaning of horizontal and vertical can best be understood by
looking at Figure 46, which illustrates this concept for a 32 × 16
crosspoint array that uses four AD8112s.
16
1kΩ
16
IN00 TO IN15
AD8112
AD8112
The AD8112 outputs are very low impedance and do not prop-
erly terminate the source end of a 75 Ω transmission line. In
these cases, a series 75 Ω resistor should be inserted at an output
that drives a video signal. Then the transmission line should be
terminated with 75 Ω at its far end. This overall termination
scheme divides the amplitude of the AD8112 output by 2. An
overall unity gain channel is produced as a result of the
AD8112’s channel gain of +2.
1kΩ
8
8
16 1kΩ
16
IN16 TO IN31
AD8112
AD8112
1kΩ
8
8
8
8
CREATING LARGER CROSSPOINT ARRAYS
Figure 46. 32 x 16 Audio Crosspoint Array Using Four AD8112s
The AD8112 is a high density building block for creating
crosspoint arrays of dimensions larger than 16 × 8. Various
features, such as output disable and chip enable, are useful
for creating larger arrays.
The inputs are individually assigned to each of the 32 inputs of
the two devices and a divider is used to normalize the channel
gain. The outputs are wire-OR’ed together in pairs. The output
from only one wire-OR’ed pair should be enabled at any given
time. The device programming software must be properly
written to for this to happen.
The first consideration in constructing a larger crosspoint is
to determine the minimum number of devices required. The
16 × 8 architecture of the AD8112 contains 128 points, which
is a factor of 32 greater than a 4 × 1 crosspoint (or multiplexer).
The PC board area, power consumption, and design effort
savings are readily apparent when compared with using these
smaller devices.
Using additional crosspoint devices in the design can lower the
number of outputs that must be wire-OR’ed together. Figure 47
shows a block diagram of a system using ten AD8112s to create
a nonblocking, gain of +2, 128 × 8 crosspoint that restricts the
wire-OR’ing at the output to only four outputs.
For a nonblocking crosspoint, the number of points required is
the product of the number of inputs multiplied by the number
of outputs. Nonblocking requires that the programming of a
given input to one or more outputs does not restrict the avail-
ability of that input to be a source for any other outputs.
Additionally, by using the lower eight outputs from each of the
two Rank 2 AD8112s, a blocking 128 × 16 crosspoint array can
be realized. There are, however, some drawbacks to this technique.
The offset voltages of the various cascaded devices accumulate,
and the bandwidth limitations of the devices compound. In
addition, the extra devices consume more current and take up
more board space. Consider the overall system design speci-
fications when using the various trade-offs.
Some nonblocking crosspoint architectures require more than
this minimum as previously calculated. Also, there are blocking
architectures that can be constructed with fewer devices than
this minimum. These systems have connectivity available on a
statistical basis that is determined when designing the overall
system.
Rev. 0 | Page 2± of 28
AD8112
RANK 1
(8 × AD8112)
128:16
1kΩ
4
4
IN00 TO IN15
1kΩ
AD8112
AD8112
AD8112
AD8112
AD8112
AD8112
AD8112
AD8112
1kΩ
1kΩ
1kΩ
1kΩ
16
R
R
R
R
TERM
TERM
TERM
TERM
1kΩ
1kΩ
1kΩ
1kΩ
1kΩ
1kΩ
1kΩ
4
4
IN16 TO IN31
1kΩ
16
4
4
IN32 TO IN47
1kΩ
16
RANK 2
16:8 NONBLOCKING
(16:16 BLOCKING)
4
4
4
4
IN48 TO IN63
1kΩ
4
1kΩ
OUT00 TO OUT07
NONBLOCKING
16
AD8112
AD8112
4
4
4
1kΩ
IN64 TO IN79
1kΩ
1kΩ
16
R
R
R
R
TERM
TERM
TERM
TERM
4
1kΩ
4
ADDITIONAL
EIGHT OUTPUTS
(SUBJECT
4
4
IN80 TO IN95
1kΩ
1kΩ
1kΩ
1kΩ
4
TO BLOCKING)
16
4
1kΩ
4
4
IN96 TO IN111
1kΩ
16
4
4
IN112 TO IN127
1kΩ
16
Figure 47. Nonblocking 128 × 8 Audio Array (128 × 16 Blocking)
Rev. 0 | Page 22 of 28
AD8112
format, other aspects of these two systems are the same. Stereo
audio can also be routed in a paired-channel arrangement
similar to a two-channel video system.
MULTICHANNEL VIDEO AND AUDIO
The video specifications of the AD8112 make it an ideal
candidate for creating composite video crosspoint switches.
These can be made quite dense by taking advantage of the
AD8112’s high level of integration and the fact that composite
video requires only one crosspoint channel per system video
channel. There are, however, other video formats that can be
routed with the AD8112, requiring more than one crosspoint
channel per video channel.
There are yet other video formats using three channels to carry
the video information. Video cameras produce RGB (red, green,
blue) directly from the image sensors. RGB is also the usual for-
mat used internally by computers for graphics. RGB can also be
converted to Y, R–Y, B–Y format, sometimes called YUV format.
These three-circuit video standards are referred to as compo-
nent analog video.
Some systems use twisted pair cables to carry video or audio
signals. These systems utilize differential signals and can lower
costs because they use lower cost cables, connectors, and termi-
nation methods. They also have the ability to lower crosstalk
and reject common-mode signals, which can be important
for equipment that operates in noisy environments, or where
common-mode voltages are present between transmitting and
receiving equipment.
The component video standards require three crosspoint channels
per video channel to handle the switching function. Similar to
the two-circuit video formats, the inputs and outputs are assigned
in groups of three, and the appropriate logic programming is
performed to route the video signals.
CROSSTALK
Many systems, such as studio audio or broadcast video, that
handle numerous analog signal channels have strict require-
ments for keeping the various signals from influencing other
signals in the system. Crosstalk is the term used to describe the
coupling of the signals of other nearby channels to a given
channel.
In such systems, the audio or video signals are differential;
there are positive and negative (or inverted) versions of the
signals. These complementary signals are transmitted through
each of the two cables of the twisted pair, yielding a first-order
zero common-mode voltage. At the receive end, the signals are
differentially received and converted back into a single-ended
signal.
When there are many signals in close proximity in a system,
as undoubtedly is the case in a system that uses the AD8112, the
crosstalk issues can be quite complex. A good understanding of
the nature of crosstalk and some definition of terms is required
in order to specify a system that uses one or more AD8112s.
When switching these differential signals, two channels are
required in the switching element to handle the two differential
signals that compose the video or audio channel. Thus, one dif-
ferential video or audio channel is assigned to a pair of crosspoint
channels, both input and output. For a single AD8112, eight
differential video or audio channels can be assigned to the 16
inputs, and four differential video or audio channels can be
assigned to the eight outputs. This effectively forms an 8 × 4
differential crosspoint switch.
Types of Crosstalk
Crosstalk can be propagated by one of three methods. These fall
into the categories of electric field, magnetic field, and sharing
of common impedances. This section explains these effects.
Every conductor can be both a radiator of electric fields and a
receiver of electric fields. The electric field crosstalk mechanism
occurs when the electric field created by the transmitter propagates
across a stray capacitance (for example, free space) and then
couples with the receiver and induces a voltage. This voltage is
an unwanted crosstalk signal in any channel that receives it.
Programming such a device requires that inputs and outputs be
programmed in pairs. This information can be deduced through
inspection of the programming format of the AD8112 and the
requirements of the system.
There are other analog video formats requiring more than one
analog circuit per video channel. One two-circuit format that is
commonly being used in systems such as satellite TV, digital
cable boxes, and higher quality VCRs is called S-video or
Y/C video. This format carries the brightness (luminance or
Y) portion of the video signal on one channel and the color
(chrominance, chroma, or C) portion on a second channel.
Currents flowing in conductors create magnetic fields that
circulate around the currents. These magnetic fields then
generate voltages in any other conductor whose paths is linked.
The undesired induced voltages in these other channels are
crosstalk signals. The channels with crosstalk have a mutual
inductance that couples signals from one channel to another.
Because S-video also uses two separate circuits for one video
channel, creating a crosspoint system requires assigning one
video channel to two crosspoint channels, as in the case of a
differential video system. Aside from the nature of the video
The power supplies, grounds, and other signal return paths
of a multichannel system are generally shared by the various
channels. When a current from one channel flows into one of
these paths, a voltage that is developed across the impedance
becomes an input crosstalk signal for other channels that share
the common impedance.
Rev. 0 | Page 23 of 28
AD8112
All these sources of crosstalk are vector quantities; therefore the
magnitudes cannot simply be added together to obtain the total
crosstalk. In fact, there are conditions where driving additional
circuits in parallel in a given configuration can reduce the
crosstalk.
To measure this crosstalk, use one of the following two methods.
In the first method, the crosstalk terms associated with driving
a test signal into each of the other 15 inputs is measured one at
a time, while applying no signal to IN00. In the second method,
the crosstalk terms associated with driving a parallel test signal
into all 15 other inputs is measured two at a time in all possible
combinations, then three at a time, and so on, until, finally, there
is only one way to drive a test signal into all 15 other inputs in
parallel.
Areas of Crosstalk
A practical AD8112 circuit must be mounted to some sort of
circuit board to connect it to power supplies and measurement
equipment. Great care has been taken to create a characteriza-
tion board (also available as an evaluation board) that adds
minimum crosstalk to the intrinsic device. This, however, raises
the issue that the crosstalk of a system is a combination of the
intrinsic crosstalk of both the devices and the circuit board to
which they are mounted. It is important to try to separate these
two areas when attempting to minimize the effect of crosstalk.
Each combination is legitimately different from the others and
might yield a unique value, depending on the resolution of the
measurement system. It is not practical to measure and then
specify all these terms. Furthermore, this describes the crosstalk
matrix for just one input channel. A similar crosstalk matrix can
be proposed for every other input. In addition, if the possible
combinations and permutations for connecting inputs to the
other outputs (not used for measurement) are taken into
consideration, the numbers of possibilities quickly grows to
astronomical proportions. If a larger crosspoint array of multiple
AD8112s is constructed, the numbers grow larger still.
In addition, crosstalk can occur among the inputs as well as the
outputs of a cross-point. It can also occur from input to output.
The following sections describe techniques for measuring and
identifying the source of crosstalk.
Measuring Crosstalk
Obviously, a subset of all these cases must be selected to be
used as a guide for a practical measure of crosstalk. One common
method is to measure all hostile crosstalk; this means that the
crosstalk to the selected channel is measured while all other
system channels are driven in parallel. In general, this yields the
worst crosstalk number, but this is not always the case, due to
the vector nature of the crosstalk signal.
Crosstalk is measured by applying a signal to one or more channels
and measuring the relative strength of that signal on a desired
selected channel. The measurement is usually expressed as
decibels down from the magnitude of the test signal. The
crosstalk is expressed by
| XT |= 20 log10
(Asel s / Atest s )
( ) ( )
Other useful crosstalk measurements are those created by the
nearest neighbor or by the two nearest neighbors on either side.
These crosstalk measurements are generally higher than those
of more distant channels, and therefore can serve as a worst-
case measure for any other 1-channel or 2-channel crosstalk
measurements.
where:
s = jw is the Laplace transform variable.
Asel(s) = the amplitude of the crosstalk induced signal in the
selected channel.
Atest(s) = the amplitude of the test signal.
It can be seen that crosstalk is a function of frequency, but not
a function of the magnitude of the test signal (to first order). In
addition, the crosstalk signal has a phase relative to the test
signal associated with it.
Input and Output Crosstalk
The flexible programming capability of the AD8112 can be used
to diagnose whether crosstalk is greater on the input side or the
output side. For example, to identify the source of crosstalk, the
IN07 input channel can be programmed to drive OUT07, with
the input to IN07 terminated to ground (via 50 Ω or 75 Ω) and
no signal applied.
A network analyzer is most commonly used to measure crosstalk
over a frequency range of interest. It can provide both magni-
tude and phase information about the crosstalk signal.
As a crosspoint system or device grows larger, the number of
theoretical crosstalk combinations and permutations can become
extremely large. For example, in the case of the 16 × 8 matrix of
the AD8112, consider the number of possible sources of crosstalk
terms for a single channel, for example the IN00 input. IN00 is
programmed to connect to one of the AD8112 outputs where
crosstalk can be measured.
All the other inputs are driven in parallel with the same test
signal (practically provided by a distribution amplifier), with all
other outputs except OUT07 disabled. Because grounded IN07
is programmed to drive OUT07, no signal should be present.
Any signal that is present can be attributed to the other 15 hostile
input signals, because no other outputs are driven (they are all
disabled). Therefore, this method measures the all-hostile input
contribution to crosstalk into IN07. This method can be used
for other input channels and combinations of hostile inputs.
Rev. 0 | Page 24 of 28
AD8112
For output crosstalk measurement, a single input channel is
driven (IN00, for example) and all outputs other than a given
output (IN07 in the middle) are programmed to connect to
IN00. OUT07 is programmed to connect to IN15 (not in close
proximity to IN00), which is terminated to ground. Therefore,
OUT07 should not have a signal present because it is listening
to a quiet input. Any signal measured at the OUT07 can be
attributed to the output crosstalk of the other seven hostile
outputs. Again, this method can be modified to measure other
channels and other crosspoint matrix combinations.
From the equation, it can be observed that this crosstalk
mechanism has a high-pass nature. It can also be minimized
by reducing the coupling capacitance of the input circuits and
lowering the output impedance of the drivers. If the input is
driven from a 75 Ω terminated cable, the input crosstalk can
be reduced by buffering this signal with a low output imped-
ance buffer.
On the output side, the crosstalk can be reduced by driving a
lighter load. Although the AD8112 is specified with excellent
differential gain and phase when driving a standard 150 Ω video
load, the crosstalk is higher than the minimum obtainable
crosstalk due to the high output currents. These currents induce
crosstalk via the mutual inductance of the output pins and bond
wires of the AD8112.
Effect of Impedances on Crosstalk
The input side crosstalk can be influenced by the output
impedance of the sources that drive the inputs. The lower
the impedance of the drive source, the lower the magnitude
of the crosstalk. The dominant crosstalk mechanism on the
input side is capacitive coupling. The high impedance inputs do
not have significant current flow to create magnetically induced
crosstalk. However, significant current can flow through the
input termination resistors and the loops that drive them.
Therefore, the PC board on the input side can contribute to
magnetically coupled crosstalk.
From a circuit standpoint, this output crosstalk mechanism
looks like a transformer with a mutual inductance between
the windings that drive a load resistor. For low frequencies,
the magnitude of the crosstalk is given by
| XT |= 20 log10
Mxy × s / RL
where:
From a circuit standpoint, the input crosstalk mechanism looks
like a capacitor coupling to a resistive load. For low frequencies
the magnitude of the crosstalk is given by
Mxy is the mutual inductance of output x to output y.
RL is the load resistance on the measured output.
This crosstalk mechanism can be minimized by keeping the
mutual inductance low and increasing RL. The mutual induc-
tance can be kept low by increasing the spacing of the conductors
and minimizing their parallel length.
|XT| = 20 log10[(RSCM) × s]
where:
RS is the source resistance.
CM is the mutual capacitance between the test signal circuit and
the selected circuit.
s is the Laplace transform variable.
Rev. 0 | Page 25 of 28
AD8112
PCB LAYOUT
Extreme care must be exercised to minimize additional cross-
talk generated by the system circuit board(s). The areas that
must be carefully designed are grounding, shielding, signal
routing, and supply bypassing.
In addition, each output has an on-chip compensation capaci-
tor that is individually tied to the nearby analog ground pins
(AGND00 through AGND07). This technique reduces crosstalk
by preventing the currents that flow in these paths from sharing
a common impedance on the IC and in the package pins. These
AGNDxx signals should all be connected directly to the
ground plane.
The packaging of the AD8112 is designed to help minimize
crosstalk. Each input is separated from each other input by
an analog ground pin. All of these AGNDs should be directly
connected to the ground plane of the circuit board. These
ground pins provide shielding, low impedance return paths,
and physical separation for the inputs. All of these help to
reduce crosstalk.
The input and output signals have minimum crosstalk if they
are located between ground planes on layers above and below,
and separated by ground in between. Vias should be located as
close to the IC as possible to carry the inputs and outputs to the
inner layer. The input and output signals surface at the input
termination resistors and at the output series back-termination
resistors. To the extent possible, these signals should also be
separated as soon as they emerge from the IC package.
Each output is separated from its two neighboring outputs by
an analog supply pin of one polarity or the other. Each of these
analog supply pins provides power to the output stages of only
the two nearest outputs. These supply pins provide shielding,
physical separation, and a low impedance supply for the outputs.
Individual bypassing of each of these supply pins with a 0.01 μF
chip capacitor connected directly to the ground plane minimizes
high frequency output crosstalk via the mechanism of sharing
common impedances.
Rev. 0 | Page 26 of 28
AD8112
DV
DGND NC AV
AGND AV
NC
CC
EE
CC
P1-1 P1-2 P1-3 P1-4 P1-5 P1-6 P1-7
+
+
DV
AV
AV
CC
0.01µF
CC
0.01µF
EE
0.01µF
JUMPER
+
0.1µF 10µF
0.1µF 10µF
1, 75
DV
21, 55
AV
20, 56
AV
EE
85 TO 93
NC
CC
CC
58
INPUT 00
INPUT 01
INPUT 02
INPUT 03
INPUT 04
INPUT 05
INPUT 06
INPUT 07
INPUT 08
INPUT 09
INPUT 10
INPUT 11
INPUT 12
INPUT 13
INPUT 14
INPUT 15
IN00
57, 59
75ꢀ
75ꢀ
75ꢀ
75ꢀ
75ꢀ
75ꢀ
75ꢀ
75ꢀ
75ꢀ
75ꢀ
75ꢀ
75ꢀ
75ꢀ
75ꢀ
75ꢀ
75ꢀ
AV
AGND
CC
EE
CC
EE
CC
EE
CC
EE
54
53
60
61
AV
CC
IN01
OUTPUT 00
0.01µF
AV
75ꢀ
75ꢀ
75ꢀ
75ꢀ
75ꢀ
75ꢀ
75ꢀ
75ꢀ
AGND
OUT00
62
63
IN02
52
51
AV 00/01
EE
AGND
OUTPUT 01
OUTPUT 02
OUTPUT 02
OUTPUT 04
OUTPUT 05
OUTPUT 06
OUTPUT 07
0.01µF
AV
64
65
IN03
OUT01
AGND
50
49
AV 01/02
CC
66
67
IN04
0.01µF
AV
AGND
OUT02
68
69
IN05
48
47
AV 02/03
EE
AGND
0.01µF
AV
70
71
OUT03
IN06
AGND
46
45
AV 03/04
CC
72
IN07
0.01µF
AV
3, 73
OUT04
AGND
4
5
44
43
IN08
AV 04/05
EE
AD8112
AGND
0.01µF
AV
OUT05
6
7
IN09
42
41
AGND
AV 05/06
CC
8
9
0.01µF
AV
IN10
OUT06
AGND
40
39
AV 06/07
EE
10
11
IN11
0.01µF
AGND
OUT07
12
13
IN12
AGND
14
15
IN13
AGND
16
17
IN14
AGND
18
19
IN15
AGND
AV
22
CC
98
96
DATA OUT
DATA IN
R
R
2, 74
100
99
97
R
95
84
R
83
R
82
R
81
R
80
79
R
78
R
77
R
76
R
94
R33
20kꢀ
P2-5
P2-4
P2-2
P2-3
P2-1
P2-6
DV
CC
R
R
SERIAL MODE
JUMP
C
R
R
NOTES
1. R = OPTIONAL 50ꢀ TERMINATOR RESISTORS.
2. C = OPTIONAL SMOOTHING CAPACITOR.
3. NC = NO CONNECT.
Figure 48. Evaluation Board Schematic
Rev. 0 | Page 27 of 28
AD8112
OUTLINE DIMENSIONS
16.20
16.00 SQ
15.80
1.60 MAX
0.75
0.60
0.45
100
1
76
75
PIN 1
14.20
14.00 SQ
13.80
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.20
0.09
7°
3.5°
0°
0.08
COPLANARITY
25
51
50
0.15
0.05
26
SEATING
PLANE
0.27
0.22
0.17
VIEW A
0.50
BSC
LEAD PITCH
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BED
Figure 49. 100-Lead Low Profile Quad Flat Package [LQFP]
(ST-100)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
Package Description
±00-Lead Plastic LQFP
Evaluation Board
Package Option
AD8±±2JSTZ±
AD8±±2-EVALZ±
0°C to 70°C
ST-±00
± Z = Pb-free part.
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06±23-0-2/07(0)
Rev. 0 | Page 28 of 28
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