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AD8115-EB [ADI]

Low Cost 225 MHz 16 X 16 Crosspoint Switches; 低成本的225 MHz的16× 16交叉点开关
AD8115-EB
型号： AD8115-EB
厂家： ADI    ADI
描述：

Low Cost 225 MHz 16 X 16 Crosspoint Switches
低成本的225 MHz的16× 16交叉点开关

开关
文件： 总26页 (文件大小：356K)
中文：  中文翻译
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Low Cost 225 MHz  
16 
؋
16 Crosspoint Switches  
a
AD8114/AD8115*  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
16 
؋
 16 High Speed Nonblocking Switch Arrays  
AD8114; G = +1  
SER/PAR D0 D1 D2 D3  
D4  
AD8115; G = +2  
A0  
A1  
A2  
A3  
Serial or Parallel Programming of Switch Array  
Serial Data Out Allows “Daisy Chaining” of Multiple  
16 
؋
 16s to Create Larger Switch Arrays  
High Impedance Output Disable Allows Connection of  
Multiple Devices Without Loading the Output Bus  
For Smaller Arrays See Our AD8108/AD8109 (8 
؋
 8) or  
AD8110/AD8111 (16 
؋
 8) Switch Arrays  
Complete Solution  
CLK  
80-BIT SHIFT REGISTER  
WITH 5-BIT  
PARALLEL LOADING  
DATA  
OUT  
DATA IN  
UPDATE  
80  
PARALLEL LATCH  
CE  
RESET  
80  
Buffered Inputs  
16  
DECODE  
16 
؋
 5:16 DECODERS  
Programmable High Impedance Outputs  
16 Output Amplifiers, AD8114 (G = +1), AD8115 (G = +2)  
Drives 150 ⍀ Loads  
Excellent Video Performance  
25 MHz, 0.1 dB Gain Flatness  
OUTPUT  
AD8114/AD8115  
BUFFER  
G = +1,  
G = +2  
256  
0.05%/0.05؇ Differential Gain/Differential Phase Error  
(RL = 150 ⍀)  
Excellent AC Performance  
–3 dB Bandwidth: 225 MHz  
Slew Rate: 375 V/␮s  
Low Power of 700 mW (2.75 mW per Point)  
Low All Hostile Crosstalk of –70 dB @ 5 MHz  
Reset Pin Allows Disabling of All Outputs (Connected  
Through a Capacitor to Ground Provides “Power-On”  
Reset Capability)  
SWITCH  
MATRIX  
16  
16 INPUTS  
OUTPUTS  
100-Lead LQFP Package (14 mm 
؋
 14 mm)  
APPLICATIONS  
Routing of High Speed Signals Including:  
Video (NTSC, PAL, S, SECAM, YUV, RGB)  
Compressed Video (MPEG, Wavelet)  
3-Level Digital Video (HDB3)  
Datacomms  
The AD8114 /AD8115 include 16 independent output buffers  
that can be placed into a high impedance state for paralleling  
crosspoint outputs so that off channels do not load the output  
bus. The AD8114 has a gain of +1, while the AD8115 offers  
a gain of +2. They operate on voltage supplies of ±5 V while  
consuming only 70 mA of idle current. The channel switching  
is performed via a serial digital control (which can accommo-  
date “daisy chaining” of several devices) or via a parallel control  
allowing updating of an individual output without reprogram-  
ming the entire array.  
Telecomms  
PRODUCT DESCRIPTION  
The AD8114/AD8115 are high speed 16 × 16 video crosspoint  
switch matrices. They offer a –3 dB signal bandwidth greater  
than 200 MHz and channel switch times of less than 50 ns with  
1% settling. With –70 dB of crosstalk and –90 dB isolation (@  
5 MHz), the AD8114/AD8115 are useful in many high speed  
applications. The differential gain and differential phase of  
better than 0.05% and 0.05° respectively, along with 0.1 dB  
flatness out to 25 MHz while driving a 75 Ω back-terminated  
load, make the AD8114/AD8115 ideal for all types of signal  
switching.  
The AD8114/AD8115 is packaged in 100-lead LQFP package  
and is available over the extended industrial temperature range  
of –40°C to +85°C.  
*Patent Pending.  
REV. 0  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, nor for any infringements of patents or other rights of third parties  
which may result from its use. No license is granted by implication or  
otherwise under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781/329-4700  
Fax: 781/326-8703  
World Wide Web Site: http://www.analog.com  
© Analog Devices, Inc., 1998  
(V = ؎5 V, T = +25؇C, R = 1 k⍀ unless otherwise noted)  
AD8114/AD8115–SPECIFICATIONS  
S
A
L
AD8114/AD8115  
Typ  
Parameter  
Conditions  
Min  
Max  
Units  
DYNAMIC PERFORMANCE  
–3 dB Bandwidth  
200 mV p-p, RL = 150 Ω  
2 V p-p, RL = 150 Ω  
0.1 dB, 200 mV p-p, RL = 150 Ω  
0.1 dB, 2 V p-p, RL = 150 Ω  
2 V p-p, RL = 150 Ω  
150/125  
225/200  
100/125  
25/40  
20/40  
5
MHz  
MHz  
MHz  
MHz  
ns  
Gain Flatness  
Propagation Delay  
Settling Time  
Slew Rate  
0.1%, 2 V Step, RL = 150 Ω  
2 V Step, RL = 150 Ω  
40  
375/450  
ns  
V/µs  
NOISE/DISTORTION PERFORMANCE  
Differential Gain Error  
NTSC or PAL, RL = 1 kΩ  
NTSC or PAL, RL = 150 Ω  
NTSC or PAL, RL = 1 kΩ  
NTSC or PAL, RL = 150 Ω  
f = 5 MHz  
f = 10 MHz  
f = 10 MHz, RL = 150 Ω, One Channel  
0.01 MHz to 50 MHz  
0.05  
0.05  
0.05  
0.05  
–70/–64  
–60/–52  
–90  
%
%
Degrees  
Degrees  
dB  
dB  
dB  
nV/√Hz  
Differential Phase Error  
Crosstalk, All Hostile  
Off Isolation, Input-Output  
Input Voltage Noise  
16/18  
DC PERFORMANCE  
Gain Error  
No Load  
RL = 1 kΩ  
RL = 150 Ω  
No Load, Channel-Channel  
RL = 1 kΩ, Channel-Channel  
0.05/0.2  
0.05/0.2  
0.2/0.35  
0.01/0.5  
0.01/0.5  
0.75/1.5  
0.08/0.6  
0.04/1  
%
%
%
%
%
ppm/°C  
Gain Matching  
Gain Temperature Coefficient  
OUTPUT CHARACTERISTICS  
Output Impedance  
DC, Enabled  
Disabled  
Disabled  
Disabled  
No Load  
0.2  
10  
5
Ω
MΩ  
pF  
µA  
V
V
mA  
Output Disable Capacitance  
Output Leakage Current  
Output Voltage Range  
Voltage Range  
1
±3.0  
±2.5  
±3.3  
±3  
65  
IOUT = 20 mA  
Short Circuit Current  
INPUT CHARACTERISTICS  
Input Offset Voltage  
Worst Case (All Configurations)  
Temperature Coefficient  
No Load  
3
15  
5
mV  
µV/°C  
V
pF  
MΩ  
µA  
10  
±3.5  
5
10  
2
Input Voltage Range  
Input Capacitance  
Input Resistance  
±3/±1.5  
Any Switch Configuration  
1
Input Bias Current  
Per Output Selected  
SWITCHING CHARACTERISTICS  
Enable On Time  
60  
ns  
Switching Time, 2 V Step  
Switching Transient (Glitch)  
50% UPDATE to 1% Settling  
50  
20/30  
ns  
mV p-p  
POWER SUPPLIES  
Supply Current  
AVCC, Outputs Enabled, No Load  
AVCC, Outputs Disabled  
AVEE, Outputs Enabled, No Load  
AVEE, Outputs Disabled  
70/80  
27/30  
70/80  
27/30  
16  
±4.5 to ±5.5  
80  
66  
mA  
mA  
mA  
mA  
mA  
V
dB  
dB  
dB  
DVCC, Outputs Enabled, No Load  
Supply Voltage Range  
PSRR  
DC  
f = 100 kHz  
f = 1 MHz  
64  
46  
OPERATING TEMPERATURE RANGE  
Temperature Range  
θJA  
Operating (Still Air)  
Operating (Still Air)  
–40 to +85  
40  
°C  
°C/W  
Specifications subject to change without notice.  
–2–  
REV. 0  
AD8114/AD8115  
TIMING CHARACTERISTICS (Serial)  
Limit  
Typ  
Parameter  
Symbol  
Min  
Max  
Units  
Serial Data Setup Time  
CLK Pulsewidth  
Serial Data Hold Time  
CLK Pulse Separation, Serial Mode  
CLK to UPDATE Delay  
t1  
t2  
t3  
t4  
t5  
t6  
t7  
–
20  
100  
20  
100  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
µs  
ns  
ns  
UPDATE Pulsewidth  
50  
CLK to DATA OUT Valid, Serial Mode  
Propagation Delay, UPDATE to Switch On or Off  
Data Load Time, CLK = 5 MHz, Serial Mode  
CLK, UPDATE Rise and Fall Times  
RESET Time  
200  
50  
–
–
–
16  
100  
200  
t2  
t4  
1
CLK  
0
LOAD DATA INTO  
SERIAL REGISTER  
ON FALLING EDGE  
t1  
t3  
1
OUT7 (D4)  
OUT7 (D3)  
OUT00 (D0)  
DATA IN  
0
t5  
t6  
1 = LATCHED  
TRANSFER DATA FROM SERIAL  
REGISTER TO PARALLEL  
LATCHES DURING LOW LEVEL  
UPDATE  
0 = TRANSPARENT  
t7  
DATA OUT  
Figure 1. Timing Diagram, Serial Mode  
Table I. Logic Levels  
VIH  
VIL  
VOH  
VOL  
IIH  
IIL  
IOH  
IOL  
RESET, SER/PAR  
CLK, DATA IN,  
CE, UPDATE  
RESET, SER/PAR  
CLK, DATA IN,  
CE, UPDATE  
RESET, SER/PAR  
CLK, DATA IN,  
CE, UPDATE  
RESET, SER/PAR  
CLK, DATA IN,  
CE, UPDATE  
DATA OUT DATA OUT  
2.7 V min 0.5 V max  
DATA OUT  
DATA OUT  
3.0 mA min  
2.0 V min  
0.8 V max  
20 µA max  
–400 µA min  
–400 µA max  
REV. 0  
–3–  
AD8114/AD8115  
TIMING CHARACTERISTICS (Parallel)  
Limit  
Parameter  
Symbol  
Min  
Max  
Units  
Data Setup Time  
CLK Pulsewidth  
Data Hold Time  
CLK Pulse Separation  
CLK to UPDATE Delay  
UPDATE Pulsewidth  
Propagation Delay, UPDATE to Switch On or Off  
CLK, UPDATE Rise and Fall Times  
RESET Time  
t1  
t2  
t3  
t4  
t5  
t6  
–
20  
100  
20  
100  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
50  
50  
100  
200  
–
–
t2  
t4  
1
CLK  
0
t1  
t3  
1
0
D0–D4  
A0–A2  
t5  
t6  
1 = LATCHED  
UPDATE  
0 = TRANSPARENT  
Figure 2. Timing Diagram, Parallel Mode  
Table II. Logic Levels  
VIH  
RESET, SER/PAR  
CLK, D0, D1, D2, D3, CLK, D0, D1, D2, D3,  
VIL  
VOH  
VOL  
IIH  
IIL  
RESET, SER/PAR  
IOH  
IOL  
RESET, SER/PAR  
RESET, SER/PAR  
CLK, D0, D1, D2, D3, CLK, D0, D1, D2, D3,  
D4, A0, A1, A2, A3  
D4, A0, A1, A2, A3  
D4, A0, A1, A2, A3  
DATA OUT DATA OUT CE, UPDATE  
D4, A0, A1, A2, A3  
CE, UPDATE  
CE, UPDATE  
CE, UPDATE  
DATA OUT DATA OUT  
2.0 V min  
0.8 V max  
2.7 V min  
0.5 V max  
20 µA max  
–400 µA min  
–400 µA max 3.0 mA min  
–4–  
REV. 0  
AD8114/AD8115  
MAXIMUM POWER DISSIPATION  
ABSOLUTE MAXIMUM RATINGS1  
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12.0 V  
The maximum power that can be safely dissipated by the  
AD8114/AD8115 is limited by the associated rise in junction  
temperature. The maximum safe junction temperature for plas-  
tic encapsulated devices is determined by the glass transition  
temperature of the plastic, approximately +150°C. Temporarily  
exceeding this limit may cause a shift in parametric performance  
due to a change in the stresses exerted on the die by the pack-  
age. Exceeding a junction temperature of +175°C for an ex-  
tended period can result in device failure.  
Internal Power Dissipation2  
AD8114/AD8115 100-Lead Plastic LQFP (ST) . . . . 2.6 W  
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±VS  
Output Short Circuit Duration  
. . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves  
Storage Temperature Range . . . . . . . . . . . . –65°C to +125°C  
Lead Temperature Range (Soldering 10 sec) . . . . . . . .+300°C  
NOTES  
1Stresses above those listed under Absolute Maximum Ratings may cause perma-  
nent damage to the device. This is a stress rating only; functional operation of the  
device at these or any other conditions above those indicated in the operational  
section of this specification is not implied. Exposure to absolute maximum rating  
conditions for extended periods may affect device reliability.  
2Specification is for device in free air (TA = +25°C):  
While the AD8114/AD8115 is internally short circuit protected,  
this may not be sufficient to guarantee that the maximum junc-  
tion temperature (+150°C) is not exceeded under all conditions.  
To ensure proper operation, it is necessary to observe the maxi-  
mum power derating curves shown in Figure 3.  
100-lead plastic LQFP (ST): θJA = 40°C/W.  
5.0  
T
= +150؇C  
J
4.0  
3.0  
2.0  
1.0  
0
–50 –40 –30 –20 –10  
0
10 20 30 40 50 60 70 80 90  
AMBIENT TEMPERATURE –  
؇
C
Figure 3. Maximum Power Dissipation vs. Temperature  
ORDERING GUIDE  
Package  
Temperature  
Range  
Package  
Option  
Model  
Description  
AD8114AST  
AD8115AST  
AD8114-EB  
AD8115-EB  
–40°C to +85°C  
–40°C to +85°C  
100-Lead Plastic LQFP (14 mm × 14 mm)  
100-Lead Plastic LQFP (14 mm × 14 mm)  
Evaluation Board  
ST-100  
ST-100  
Evaluation Board  
CAUTION  
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily  
accumulate on the human body and test equipment and can discharge without detection.  
Although the AD8114/AD8115 features proprietary ESD protection circuitry, permanent dam-  
age may occur on devices subjected to high energy electrostatic discharges. Therefore, proper  
ESD precautions are recommended to avoid performance degradation or loss of functionality.  
WARNING!  
ESD SENSITIVE DEVICE  
REV. 0  
–5–  
AD8114/AD8115  
Table III. Operation Truth Table  
SER/  
CE  
UPDATE CLK  
DATA IN  
DATA OUT  
RESET  
PAR Operation/Comment  
1
0
X
1
X
f
X
Data i  
X
X
1
X
0
No change in logic.  
Data i-80  
The data on the serial DATA IN line is loaded  
into serial register. The first bit clocked into  
the serial register appears at DATA OUT 80  
clocks later.  
0
1
f
D0 . . . D4,  
A0 . . . A3  
NA in Parallel  
Mode  
1
1
0
1
The data on the parallel data lines, D0–D4, are  
loaded into the 80-bit serial shift register loca-  
tion addressed by A0–A3.  
Data in the 80-bit shift register transfers into the  
parallel latches that control the switch array.  
Latches are transparent.  
0
0
X
X
X
X
X
X
X
X
X
X
Asynchronous operation. All outputs are disabled.  
Remainder of logic is unchanged.  
D0  
D1  
D2  
D3  
D4  
PARALLEL  
DATA  
(OUTPUT  
ENABLE)  
SER/PAR  
S
S
S
S
S
S
S
S
S
S
S
S
D1  
D1  
D1  
D1  
D1  
D1  
D1  
D1  
D1  
D1  
D1  
D1  
DATA  
OUT  
D Q  
CLK  
D
Q
Q
D
D Q  
CLK  
D
Q
D
Q
D
Q
D
Q
D Q  
CLK  
D
Q
D
Q
D
Q
Q
D0  
Q
D0  
Q
D0  
Q
D0  
Q
D0  
Q
D0  
Q
D0  
Q
D0  
Q
D0  
Q
D0  
Q
D0  
Q
D0  
DATA IN  
(SERIAL)  
CLK  
CLK  
CLK  
CLK  
CLK  
CLK  
CLK  
CLK  
CLK  
CLK  
CE  
UPDATE  
OUT0 EN  
OUT1 EN  
OUT2 EN  
OUT3 EN  
OUT4 EN  
OUT5 EN  
OUT6 EN  
OUT7 EN  
OUT8 EN  
OUT9 EN  
OUT10 EN  
OUT11 EN  
OUT12 EN  
OUT13 EN  
OUT14 EN  
OUT15 EN  
A0  
A1  
A2  
A3  
LE  
D
LE  
D
LE  
D
LE  
D
LE  
D
LE  
D
LE  
D
LE  
D
LE  
D
LE  
D
LE  
D
LE D  
OUT0  
B0  
OUT0  
B1  
OUT0  
B2  
OUT0  
B3  
OUT0  
EN  
OUT1  
B0  
OUT14  
EN  
OUT15  
B0  
OUT15  
B1  
OUT15  
B2  
OUT15  
B3  
OUT15  
EN  
Q
Q
Q
Q
CLR  
Q
Q
CLR  
Q
Q
Q
Q
Q
CLR Q  
RESET  
(OUTPUT ENABLE)  
DECODE  
16  
OUTPUT ENABLE  
256  
SWITCH MATRIX  
Figure 4. Logic Diagram  
–6–  
REV. 0  
AD8114/AD8115  
PIN FUNCTION DESCRIPTIONS  
Pin Name  
Pin Numbers  
Pin Description  
INxx  
58, 60, 62, 64, 66, 68, 70, 72,  
4, 6, 8, 10, 12, 14, 16, 18  
Analog Inputs; xx = Channel Numbers 00 Through 15.  
DATA IN  
CLK  
96  
97  
Serial Data Input, TTL Compatible.  
Clock, TTL Compatible. Falling Edge Triggered.  
Serial Data Out, TTL Compatible.  
DATA OUT 98  
UPDATE  
95  
Enable (Transparent) “Low.” Allows serial register to connect directly to switch matrix.  
Data latched when “High.”  
RESET  
CE  
100  
99  
Disable Outputs, Active “Low.”  
Chip Enable, Enable “Low.” Must be “low” to clock in and latch data.  
Selects Serial Data Mode, “Low” or Parallel Data Mode, “High.” Must be connected.  
Analog Outputs yy = Channel Numbers 00 Through 15.  
SER/PAR  
OUTyy  
94  
53, 51, 49, 47, 45, 43, 41, 39,  
37, 35, 33, 31, 29, 27, 25, 23  
AGND  
3, 5, 7, 9, 11, 13, 15, 17, 19, 57,  
59, 61, 63, 65, 67, 69, 71, 73  
Analog Ground for Inputs and Switch Matrix. Must be connected.  
DVCC  
DGND  
AVEE  
AVCC  
AVCCxx/yy  
AVEExx/yy  
A0  
1, 75  
+5 V for Digital Circuitry.  
2, 74  
Ground for Digital Circuitry.  
20, 56  
–5 V for Inputs and Switch Matrix.  
21, 55  
+5 V for Inputs and Switch Matrix.  
54, 50, 46, 42, 38, 34, 30, 26, 22  
+5 V for Output Amplifier that is shared by Channel Numbers xx and yy. Must be connected.  
–5 V for Output Amplifier that is shared by Channel Numbers xx and yy. Must be connected.  
Parallel Data Input, TTL Compatible (Output Select LSB).  
Parallel Data Input, TTL Compatible (Output Select).  
Parallel Data Input, TTL Compatible (Output Select).  
Parallel Data Input, TTL Compatible (Output Select MSB).  
Parallel Data Input, TTL Compatible (Input Select LSB).  
Parallel Data Input, TTL Compatible (Input Select).  
Parallel Data Input, TTL Compatible (Input Select).  
Parallel Data Input, TTL Compatible (Input Select MSB).  
52, 48, 44, 40, 36, 32, 28, 24  
84  
83  
82  
81  
80  
79  
78  
77  
A1  
A2  
A3  
D0  
D1  
D2  
D3  
D4  
NC  
76  
85–93  
Parallel Data Input, TTL Compatible (Output Enable).  
No Connect.  
V
V
CC  
CC  
V
CC  
ESD  
20k⍀  
ESD  
ESD  
ESD  
INPUT  
OUTPUT  
RESET  
ESD  
ESD  
AV  
EE  
AV  
DGND  
EE  
b. Analog Output  
a. Analog Input  
c. Reset Input  
V
V
CC  
CC  
ESD  
ESD  
2k⍀  
ESD  
INPUT  
OUTPUT  
ESD  
DGND  
DGND  
d. Logic Input  
e. Logic Output  
Figure 5. I/O Schematics  
REV. 0  
–7–  
AD8114/AD8115  
PIN CONFIGURATION  
DVCC  
1
2
3
75  
74  
73  
DVCC  
DGND  
AGND  
PIN 1  
IDENTIFIER  
DGND  
AGND  
4
5
72  
71  
IN08  
IN07  
AGND  
AGND  
6
70  
IN09  
IN06  
7
8
69  
68  
AGND  
IN10  
AGND  
IN05  
9
67  
66  
AGND  
IN11  
AGND  
IN04  
10  
11  
65  
AGND  
AGND  
12  
13  
64  
63  
IN12  
IN03  
AD8114/AD8115  
AGND  
AGND  
TOP VIEW  
(Not to Scale)  
14  
15  
62  
61  
IN13  
IN02  
AGND  
AGND  
16  
60  
IN14  
IN01  
17  
18  
59  
58  
AGND  
IN15  
AGND  
IN00  
19  
20  
57  
56  
AGND  
AVEE  
AGND  
AVEE  
21  
55  
AVCC  
AVCC  
22  
23  
54  
53  
AVCC15  
OUT15  
AVCC00  
OUT00  
24  
25  
52  
51  
AVEE14/15  
OUT14  
AVEE00/01  
OUT01  
NC = NO CONNECT  
–8–  
REV. 0  
Typical Performance Characteristics–  
AD8114/AD8115  
0.5  
2
1
0
0.2  
GAIN  
1
0.4  
0.1  
GAIN  
200mV p-p  
0
0.3  
200mV p-p  
0.2  
FLATNESS  
–1  
–2  
–3  
0
–1  
–2  
–0.1  
–0.2  
–0.3  
–0.4  
–0.5  
0.1  
0
FLATNESS  
–3  
–4  
2V p-p  
–0.1  
V
AS SHOWN  
V
AS SHOWN  
O
O
–4  
–5  
–6  
–7  
200mV p-p  
2V p-p  
R
= 150⍀  
R
= 150⍀  
L
L
–0.2  
–0.3  
–0.4  
–0.5  
–5  
–6  
–7  
–8  
2V p-p  
–0.6  
1000  
0.1  
1
10  
FREQUENCY – MHz  
100  
1000  
0.1  
1
10  
100  
FREQUENCY – MHz  
Figure 6. AD8114 Frequency Response; RL = 150 Ω  
Figure 9. AD8115 Frequency Response; RL = 150 Ω  
3
2
0.5  
3
2
1
0.4  
0.3  
0.4  
0.3  
1
0
0.2  
0.1  
0
200mV p-p  
200mV p-p  
GAIN  
GAIN  
0
–1  
–2  
0.2  
0.1  
0
FLATNESS  
–1  
–2  
–3  
–4  
–5  
–6  
–7  
FLATNESS  
–0.1  
–0.2  
–0.3  
V
AS SHOWN  
O
2V p-p  
R
= 1k⍀  
L
–0.1  
–0.2  
–0.3  
–3  
–4  
–5  
–6  
–7  
V
AS SHOWN  
O
200mV p-p  
2V p-p  
R
= 1k⍀  
L
–0.4  
–0.5  
–0.6  
2V p-p  
–0.4  
–0.5  
0.1  
1
10  
FREQUENCY – MHz  
100  
1000  
0.1  
1
10  
100  
1000  
FREQUENCY – MHz  
Figure 7. AD8114 Frequency Response; RL = 1 kΩ  
Figure 10. AD8115 Frequency Response; RL = 1 kΩ  
10  
4
V
= 200mV p-p  
AS SHOWN  
= 18pF  
V
= 200mV p-p  
AS SHOWN  
= 18pF  
8
6
3
2
1
O
O
R
C
R
C
R
= 1k⍀  
L
L
L
R
= 1k⍀  
L
L
L
4
2
0
–1  
–2  
0
R
= 150⍀  
L
R
= 150⍀  
–2  
L
–3  
–4  
–5  
–6  
–4  
–6  
–8  
–10  
0.1  
0.1  
1
10  
FREQUENCY – MHz  
100  
1000  
1
10  
FREQUENCY – MHz  
100  
1000  
Figure8. AD8114FrequencyResponsevs.LoadImpedance  
Figure 11. AD8115 Frequency Response vs. Load Impedance  
REV. 0  
–9–  
AD8114/AD8115  
0
0
–10  
–20  
–30  
–40  
–50  
–60  
R
R
= 1k⍀  
R
R
= 1k⍀  
L
T
L
T
–10  
–20  
–30  
–40  
–50  
–60  
= 37.5⍀  
= 37.5⍀  
ALL HOSTILE  
ALL HOSTILE  
ADJACENT  
–70  
–80  
–70  
–80  
ADJACENT  
–90  
–90  
–100  
–100  
0.1  
1
10  
FREQUENCY – MHz  
100  
1000  
0.1  
1
10  
FREQUENCY – MHz  
100  
1000  
Figure 12. AD8114 Crosstalk vs. Frequency  
Figure 15. AD8115 Crosstalk vs. Frequency  
0
0
V
= 2V p-p  
V
= 2V p-p  
–10  
O
–10  
O
R
= 150⍀  
R
= 150⍀  
L
L
–20  
–30  
–40  
–50  
–60  
–70  
–20  
–30  
–40  
–50  
–60  
–70  
2ND HARMONIC  
2ND HARMONIC  
3RD HARMONIC  
–80  
3RD HARMONIC  
–80  
–90  
–90  
–100  
–100  
1
10  
FUNDAMENTAL FREQUENCY – MHz  
50  
1
10  
FUNDAMENTAL FREQUENCY – MHz  
50  
Figure 13. AD8114 Distortion vs. Frequency  
Figure 16. AD8115 Distortion vs. Frequency  
V
= 2V STEP  
V
= 2V STEP  
O
O
R
= 150⍀  
R
= 150⍀  
L
L
0
5
10 15 20 25 30 35 40 45  
5ns/DIV  
0
5
10 15 20 25 30 35 40 45  
5ns/DIV  
Figure 14. AD8114 Settling Time  
Figure 17. AD8115 Settling Time  
–10–  
REV. 0  
AD8114/AD8115  
1M  
1M  
100k  
100k  
10k  
1k  
10k  
1k  
100  
0.1  
100  
0.1  
1
10  
100  
500  
1
10  
100  
500  
FREQUENCY – MHz  
FREQUENCY – MHz  
Figure 18. AD8114 Input Impedance vs. Frequency  
Figure 21. AD8115 Input Impedance vs. Frequency  
1000  
100  
1000  
100  
10  
10  
1
1
0.1  
0.1  
0.1  
0.1  
1
10  
100  
1000  
1
10  
100  
1000  
FREQUENCY – MHz  
FREQUENCY – MHz  
Figure 22. AD8115 Output Impedance Enabled  
vs. Frequency  
Figure 19. AD8114 Output Impedance, Enabled  
vs. Frequency  
1M  
100k  
10k  
1k  
1M  
100k  
10k  
1k  
100  
10  
100  
10  
0.1  
0.1  
1
10  
100  
1000  
1
10  
100  
1000  
FREQUENCY – MHz  
FREQUENCY – MHz  
Figure 23. AD8115 Output Impedance, Disabled  
vs. Frequency  
Figure 20. AD8114 Output Impedance, Disabled  
vs. Frequency  
REV. 0  
–11–  
AD8114/AD8115  
–40  
–50  
–60  
–70  
–40  
–50  
–60  
–70  
–80  
–90  
–80  
–90  
–100  
–110  
–100  
–110  
–120  
–130  
–140  
–120  
–130  
–140  
0.1  
1
10  
100  
500  
0.1  
1
10  
100  
500  
FREQUENCY – MHz  
FREQUENCY – MHz  
Figure 24. AD8114 Off Isolation, Input-Output  
Figure 27. AD8115 Off Isolation, Input-Output  
–20  
–30  
–40  
–20  
–30  
–40  
+PSRR  
–50  
–50  
–PSRR  
–PSRR  
–60  
–60  
+PSRR  
–70  
–70  
–80  
–80  
–90  
–90  
–100  
0.03  
–100  
0.03  
1
0.1  
10  
1
0.1  
10  
FREQUENCY – MHz  
FREQUENCY – MHz  
Figure 25. AD8114 PSRR vs. Frequency  
Figure 28. AD8115 PSRR vs. Frequency  
170  
150  
170  
150  
130  
110  
90  
130  
110  
90  
70  
70  
50  
50  
30  
10  
30  
18nV/ Hz  
16nV/ Hz  
10  
10  
100  
1k  
10k  
100k  
1M  
10M  
10  
100  
1k  
10k  
100k  
1M  
10M  
FREQUENCY – Hz  
FREQUENCY – Hz  
Figure 26. AD8114 Voltage Noise vs. Frequency  
Figure 29. AD8115 Voltage Noise vs. Frequency  
–12–  
REV. 0  
AD8114/AD8115  
V
= 200mV STEP  
V
= 200mV STEP  
O
O
0.15V  
0.10V  
0.15V  
0.10V  
0.05V  
0V  
R
= 150⍀  
R
= 150⍀  
L
L
0.05V  
0V  
–0.05V  
–0.10V  
–0.15V  
–0.05V  
–0.10V  
–0.15V  
25ns  
50mV  
50mV  
25ns  
Figure 33. AD8115 Pulse Response, Small Signal  
Figure 30. AD8114 Pulse Response, Small Signal  
V
= 2V STEP  
V
= 2V STEP  
O
O
1.5V  
1.0V  
0.5V  
0V  
1.5V  
1.0V  
0.5V  
0V  
R
= 150⍀  
R
= 150⍀  
L
L
–0.5V  
–1.0V  
–1.5V  
–0.5V  
–1.0V  
–1.5V  
500mV  
20ns  
500mV  
25ns  
Figure 34. AD8115 Pulse Response, Large Signal  
Figure 31. AD8114 Pulse Response, Large Signal  
+5V  
+5V  
UPDATE  
UPDATE  
0V  
0V  
+2V  
INPUT 1  
AT +1V  
–0V  
+1V  
INPUT 1  
AT +1V  
–2V  
–0V  
V
INPUT 0  
AT –1V  
V
OUT  
OUT  
INPUT 0  
AT –1V  
–1V  
10ns  
10ns  
Figure 35. AD8115 Switching Time  
Figure 32. AD8114 Switching Time  
REV. 0  
–13–  
AD8114/AD8115  
5V  
5V  
0V  
UPDATE  
UPDATE  
0V  
0.05V  
0V  
0.05V  
0V  
–0.05V  
–0.05V  
50ns  
50ns  
Figure 36. AD8114 Switching Transient (Glitch)  
Figure 39. AD8115 Switching Transient (Glitch)  
260  
240  
220  
200  
180  
160  
240  
220  
200  
180  
160  
140  
120  
100  
80  
140  
120  
100  
80  
60  
60  
40  
40  
20  
0
20  
0
–12  
–8  
–4  
0
4
8
–10  
–6  
–2  
2
6
10  
–14  
–10  
–6  
–2  
2
6
10  
14  
18  
16  
–12  
–8  
–4  
0
4
8
12  
OFFSET VOLTAGE – mV  
OFFSET VOLTAGE – mV  
Figure 37. AD8114 Offset Voltage Distribution  
Figure 40. AD8115 Offset Voltage Distribution  
44  
40  
36  
32  
28  
24  
20  
16  
12  
8
44  
40  
36  
32  
28  
24  
20  
16  
12  
8
4
0
4
0
–12  
–8  
–4  
0
4
8
12  
16  
20  
–20 –16 –12  
–8  
–4  
0
4
8
12  
16  
20  
OFFSET VOLTAGE DRIFT – ␮V/؇C  
OFFSET VOLTAGE DRIFT – ␮V/؇C  
Figure 41. AD8115 Offset Voltage Drift Distribution  
(–40°C to +85°C)  
Figure 38. AD8114 Offset Voltage Drift Distribution  
(–40°C to +85°C)  
–14–  
REV. 0  
AD8114/AD8115  
shift in when UPDATE is LOW, the transparent, asynchronous  
latches will allow the shifting data to reach the matrix. This will  
cause the matrix to try to update to every intermediate state as  
defined by the shifting data.  
THEORY OF OPERATION  
The AD8114 (G = +1) and AD8115 (G = +2) are crosspoint  
arrays with 16 outputs, each of which can be connected to any  
one of 16 inputs. Organized by output row, 16 switchable trans-  
conductance stages are connected to each output buffer, in the  
form of a 16-to-1 multiplexer. Each of the 16 rows of transconduc-  
tance stages are wired in parallel to the 16 input pins, for a total  
array of 256 transconductance stages. Decoding logic for each  
output selects one (or none) of the transconductance stages to  
drive the output stage. The transconductance stages are NPN-  
input differential pairs, sourcing current into the folded cascode  
output stage. The compensation network and emitter follower  
output buffer are in the output stage. Voltage feedback sets the  
gain, with the AD8114 being configured as a unity gain follower,  
and the AD8115 as a gain-of-two amplifier with a feedback  
network.  
The data at DATA IN is clocked in at every down edge of CLK.  
A total of 80 bits must be shifted in to complete the program-  
ming. For each of the 16 outputs, there are four bits (D0–D3)  
that determine the source of its input followed by one bit (D4)  
that determines the enabled state of the output. If D4 is LOW  
(output disabled), the four associated bits (D0–D3) do not  
matter, because no input will be switched to that output.  
The most-significant-output-address data is shifted in first, then  
following in sequence until the least-significant-output-address  
data is shifted in. At this point UPDATE can be taken LOW,  
which will cause the programming of the device according to the  
data that was just shifted in. The UPDATE registers are asyn-  
chronous and when UPDATE is LOW (and CE is LOW), they  
are transparent.  
This architecture provides drive for a reverse-terminated video  
load (150 Ω), with low differential gain and phase error for  
relatively low power consumption. Power consumption is fur-  
ther reduced by disabling outputs and transconductance stages  
that are not in use. The user will notice a small increase in input  
bias current as each transconductance stage is enabled.  
If more than one AD8114/AD8115 device is to be serially pro-  
grammed in a system, the DATA OUT signal from one device  
can be connected to the DATA IN of the next device to form a  
serial chain. All of the CLK, CE, UPDATE and SER/PAR pins  
should be connected in parallel and operated as described above.  
The serial data is input to the DATA IN pin of the first device  
of the chain, and it will ripple on through to the last. Therefore,  
the data for the last device in the chain should come at the be-  
ginning of the programming sequence. The length of the pro-  
gramming sequence will be 80 bits times the number of devices  
in the chain.  
Features of the AD8114 and AD8115 simplify the construction  
of larger switch matrices. The unused outputs of both devices  
can be disabled to a high impedance state, allowing the outputs  
of multiple ICs to be bused together. In the case of the AD8115, a  
feedback isolation scheme is used so that the impedance of the  
gain-of-two feedback network does not load the output. Because  
no additional input buffering is necessary, high input resistance  
and low input capacitance are easily achieved without additional  
signal degradation. To control enable glitches, it is recommended  
that the disabled output voltage be maintained within its normal  
enabled voltage range (±3.3 V). If necessary, the disabled out-  
put can be kept from drifting out of range by applying an output  
load resistor to ground.  
Parallel Programming  
When using the parallel programming mode, it is not necessary  
to reprogram the entire device when making changes to the  
matrix. In fact, parallel programming allows the modification  
of a single output at a time. Since this takes only one CLK/  
UPDATE cycle, significant time savings can be realized by  
using parallel programming.  
A flexible TTL-compatible logic interface simplifies the pro-  
gramming of the matrix. Both parallel and serial loading into a  
first rank of latches programs each output. A global latch simul-  
taneously updates all outputs. A power-on reset pin is available  
to avoid bus conflicts by disabling all outputs.  
One important consideration in using parallel programming is  
that the RESET signal DOES NOT RESET ALL REGISTERS  
in the AD8114/AD8115. When taken low, the RESET signal  
will only set each output to the disabled state. This is helpful  
during power-up to ensure that two parallel outputs will not be  
active at the same time.  
APPLICATIONS  
The AD8114/AD8115 have two options for changing the pro-  
gramming of the crosspoint matrix. In the first option a serial  
word of 80 bits can be provided that will update the entire ma-  
trix each time. The second option allows for changing a single  
output’s programming via a parallel interface. The serial option  
requires fewer signals, but more time (clock cycles) for changing  
the programming, while the parallel programming technique re-  
quires more signals, but can change a single output at a time  
and requires fewer clock cycles to complete programming.  
After initial power-up, the internal registers in the device will  
generally have random data, even though the RESET signal has  
been asserted. If parallel programming is used to program one  
output, then that output will be properly programmed, but the  
rest of the device will have a random program state depending  
on the internal register content at power-up. Therefore, when  
using parallel programming, it is essential that ALL OUTPUTS  
BE PROGRAMMED TO A DESIRED STATE AFTER  
POWER-UP. This will ensure that the programming matrix is  
always in a known state. From then on, parallel programming  
can be used to modify a single output or more at a time.  
Serial Programming  
The serial programming mode uses the device pins CE, CLK,  
DATA IN, UPDATE and SER/PAR. The first step is to assert a  
LOW on SER/PAR in order to enable the serial programming  
mode. CE for the chip must be LOW to allow data to be clocked  
into the device. The CE signal can be used to address an indi-  
vidual device when devices are connected in parallel.  
In similar fashion, if both CE and UPDATE are taken LOW  
after initial power-up, the random power-up data in the shift  
register will be programmed into the matrix. Therefore, in order  
to prevent the crosspoint from being programmed into an un-  
known state DO NOT APPLY LOW LOGIC LEVELS TO  
BOTH CE AND UPDATE AFTER POWER IS INITIALLY  
The UPDATE signal should be HIGH during the time that data  
is shifted into the device’s serial port. Although the data will still  
REV. 0  
–15–  
AD8114/AD8115  
APPLIED. Programming the full shift register one time to a  
desired state, either by serial or parallel programming after  
initial power-up, will eliminate the possibility of programming  
the matrix to an unknown state.  
drive a video line. Its high output disabled impedance minimizes  
signal degradation when paralleling additional outputs.  
CREATING LARGER CROSSPOINT ARRAYS  
The AD8114/AD8115 are high density building blocks for cre-  
ating crosspoint arrays of dimensions larger than 16 × 16. Vari-  
ous features, such as output disable, chip enable, and gain-  
of-one and gain-of-two options, are useful for creating larger  
arrays. When required for customizing a crosspoint array size,  
they can be used with the AD8108 and AD8109, a pair (unity  
gain and gain-of-two) of 8 × 8 video crosspoint switches, or the  
AD8110 and AD8111, a pair (unity gain and gain-of-two)  
16 × 8 video crosspoint switches.  
To change an output’s programming via parallel programming,  
SER/PAR and UPDATE should be taken HIGH and CE should  
be taken LOW. The CLK signal should be in the HIGH state.  
The 4-bit address of the output to be programmed should be put  
on A0–A3. The first four data bits (D0–D3) should contain the  
information that identifies the input that gets programmed to the  
output that is addressed. The fourth data bit (D4) will deter-  
mine the enabled state of the output. If D4 is LOW (output  
disabled) then the data on D0–D3 does not matter.  
The first consideration in constructing a larger crosspoint is to  
determine the minimum number of devices are required. The  
16 × 16 architecture of the AD8114/AD8115 contains 256  
“points,” which is a factor of 64 greater than a 4 × 1 crosspoint  
(or multiplexer). The PC board area, power consumption and  
design effort savings are readily apparent when compared to  
using these smaller devices.  
After the desired address and data signals have been established,  
they can be latched into the shift register by a HIGH to LOW  
transition of the CLK signal. The matrix will not be programmed,  
however, until the UPDATE signal is taken low. It is thus pos-  
sible to latch in new data for several or all of the outputs first via  
successive negative transitions of CLK while UPDATE is held  
high, and then have all the new data take effect when UPDATE  
goes LOW. This is the technique that should be used when  
programming the device for the first time after power-up when  
using parallel programming.  
For a nonblocking crosspoint, the number of points required is  
the product of the number of inputs multiplied by the number  
of outputs. Nonblocking requires that the programming of a  
given input to one or more outputs does not restrict the avail-  
ability of that input to be a source for any other outputs.  
POWER-ON RESET  
When powering up the AD8114/AD8115 it is usually desirable  
to have the outputs come up in the disabled state. The RESET  
pin, when taken LOW will cause all outputs to be in the dis-  
abled state. However, the RESET signal DOES NOT RESET  
ALL REGISTERS in the AD8114/AD8115 This is important  
when operating in the parallel programming mode. Please refer  
to that section for information about programming internal  
registers after power-up. Serial programming will program the  
entire matrix each time, so no special considerations apply.  
Some nonblocking crosspoint architectures will require more  
than this minimum as calculated above. Also, there are blocking  
architectures that can be constructed with fewer devices than  
this minimum. These systems have connectivity available on a  
statistical basis that is determined when designing the overall  
system.  
The basic concept in constructing larger crosspoint arrays is  
to connect inputs in parallel in a horizontal direction and to  
“wire-OR” the outputs together in the vertical direction. The  
meaning of horizontal and vertical can best be understood by  
looking at a diagram. Figure 42 illustrates this concept for a  
32 × 32 crosspoint array that uses four AD8114s or AD8115s.  
Since the data in the shift register is random after power-up,  
they should not be used to program the matrix or else the matrix  
can enter unknown states. To prevent this, DO NOT APPLY  
LOGIC LOW SIGNALS TO BOTH CE AND UPDATE  
INITIALLY AFTER POWER-UP. The shift register should  
first be loaded with the desired data, and then UPDATE can be  
taken LOW to program the device.  
AD8114  
OR  
AD8115  
AD8114  
OR  
AD8115  
16  
16  
IN 00–15  
16  
R
TERM  
The RESET pin has a 20 kΩ pull-up resistor to DVDD that can  
be used to create a simple power-up reset circuit. A capacitor  
from RESET to ground will hold RESET LOW for some time  
while the rest of the device stabilizes. The LOW condition will  
cause all the outputs to be disabled. The capacitor will then  
charge through the pull-up resistor to the HIGH state, thus  
allowing full programming capability of the device.  
16  
16  
AD8114  
OR  
AD8115  
AD8114  
OR  
AD8115  
16  
16  
IN 16–31  
16  
R
TERM  
16  
16  
GAIN SELECTION  
Figure 42. 32 × 32 Crosspoint Array Using Four AD8114s  
or Four AD8115s  
The 16 × 16 crosspoints come in two versions, depending on the  
gain of the analog circuit paths that is desired. The AD8114  
device is unity gain and can be used for analog logic switching  
and other applications where unity gain is desired. The AD8114  
can also be used for the input and interior sections of larger  
crosspoint arrays where termination of output signals is not  
usually used. The AD8114 outputs have a very high impedance  
when their outputs are disabled.  
The inputs are each uniquely assigned to each of the 32 inputs  
of the two devices and terminated appropriately. The outputs  
are wired-ORed together in pairs. The output from only one of  
a wire-ORed pair should be enabled at any given time. The  
device programming software must be properly written to cause  
this to happen.  
The AD8115 can be used for devices that will be used to drive  
a terminated cable with its outputs. This device has a built-in  
gain-of-two that eliminates the need for a gain-of-two buffer to  
Using additional crosspoint devices in the design can lower the  
number of outputs that have to be wire-ORed together. Figure  
43 shows a block diagram of a system using eight AD8114s and  
–16–  
REV. 0  
AD8114/AD8115  
RANK 1  
(8 
؋
 AD8114)  
128:32  
8
8
IN 00–15  
IN 16–31  
IN 32–47  
IN 48–63  
IN 64–79  
IN 80–95  
IN 96–111  
AD8114  
AD8114  
AD8114  
AD8114  
AD8114  
AD8114  
AD8114  
AD8114  
16  
16  
16  
16  
16  
16  
16  
R
R
R
R
R
R
R
TERM  
TERM  
TERM  
TERM  
TERM  
TERM  
TERM  
8
8
8
8
RANK 2  
32:16 NONBLOCKING  
(32:32 BLOCKING)  
8
8
8
8
8
1k⍀  
OUT 00–15  
NONBLOCKING  
AD8115  
AD8115  
8
8
8
1k⍀  
8
1k⍀  
8
ADDITIONAL  
16 OUTPUTS  
(SUBJECT  
8
8
8
TO BLOCKING)  
8
1k⍀  
8
8
8
8
IN 112–127  
16  
R
TERM  
Figure 43. Nonblocking 128 × 16 Array (128 × 32 Blocking)  
that operates in noisy environments or where common-mode  
voltages are present between transmitting and receiving equipment.  
two AD8115s to create a nonblocking, gain-of-two, 128 × 16  
crosspoint that restricts the wire-ORing at the output to only  
four outputs.  
In such systems, the video signals are differential; there is a  
positive and negative (or inverted) version of the signals. These  
complementary signals are transmitted onto each of the two  
wires of the twisted pair, yielding a first order zero common-  
mode voltage. At the receive end, the signals are differentially  
received and converted back into a single-ended signal.  
Additionally, by using the lower eight outputs from each of the  
two Rank 2 AD8115s, a blocking 128 × 32 crosspoint array can  
be realized. There are, however, some drawbacks to this tech-  
nique. The offset voltages of the various cascaded devices will  
accumulate and the bandwidth limitations of the devices will  
compound. In addition, the extra devices will consume more  
current and take up more board space. Once again, the overall  
system design specifications will determine how to make the  
various tradeoffs.  
When switching these differential signals, two channels are  
required in the switching element to handle the two differential  
signals that make up the video channel. Thus, one differential  
video channel is assigned to a pair of crosspoint channels, both  
input and output. For a single AD8114/AD8115, eight differential  
video channels can be assigned to the 16 inputs and 16 outputs.  
This will effectively form an 8 × 8 differential crosspoint switch.  
Multichannel Video  
The excellent video specifications of the AD8114/AD8115 make  
them ideal candidates for creating composite video crosspoint  
switches. These can be made quite dense by taking advantage of  
the AD8114/AD8115’s high level of integration and the fact that  
composite video requires only one crosspoint channel per sys-  
tem video channel. There are, however, other video formats that  
can be routed with the AD8114/AD8115 requiring more than  
one crosspoint channel per video channel.  
Programming such a device will require that inputs and outputs  
be programmed in pairs. This information can be deduced by  
inspection of the programming format of the AD8114/AD8115  
and the requirements of the system.  
There are other analog video formats requiring more than one  
analog circuit per video channel. One two-circuit format that is  
commonly being used in systems such as satellite TV, digital  
cable boxes and higher quality VCRs, is called S-video or Y/C  
video. This format carries the brightness (luminance or Y)  
portion of the video signal on one channel and the color (chromi-  
nance, chroma or C) on a second channel.  
Some systems use twisted-pair wiring to carry video signals.  
These systems utilize differential signals and can lower costs  
because they use lower cost cables, connectors and termination  
methods. They also have the ability to lower crosstalk and reject  
common-mode signals, which can be important for equipment  
REV. 0  
–17–  
AD8114/AD8115  
Since S-video also uses two separate circuits for one video chan-  
nel, creating a crosspoint system requires assigning one video  
channel to two crosspoint channels as in the case of a differen-  
tial video system. Aside from the nature of the video format,  
other aspects of these two systems will be the same.  
Areas of Crosstalk  
For a practical AD8114/AD8115 circuit, it is required that it be  
mounted to some sort of circuit board in order to connect it to  
power supplies and measurement equipment. Great care has  
been taken to create a characterization board (also available as  
an evaluation board) that adds minimum crosstalk to the intrin-  
sic device. This, however, raises the issue that a system’s crosstalk  
is a combination of the intrinsic crosstalk of the devices in addi-  
tion to the circuit board to which they are mounted. It is impor-  
tant to try to separate these two areas of crosstalk when attempting  
to minimize its effect.  
There are yet other video formats using three channels to carry  
the video information. Video cameras produce RGB (red, green,  
blue) directly from the image sensors. RGB is also the usual  
format used by computers internally for graphics. RGB can also  
be converted to Y, R-Y, B-Y format, sometimes called YUV  
format. These three-circuit, video standards are referred to as  
component analog video.  
In addition, crosstalk can occur among the inputs to a cross-  
point and among the output. It can also occur from input to  
output. Techniques will be discussed for diagnosing which part  
of a system is contributing to crosstalk.  
The component video standards require three crosspoint chan-  
nels per video channel to handle the switching function. In a  
fashion similar to the two-circuit video formats, the inputs and  
outputs are assigned in groups of three and the appropriate logic  
programming is performed to route the video signals.  
Measuring Crosstalk  
Crosstalk is measured by applying a signal to one or more chan-  
nels and measuring the relative strength of that signal on a de-  
sired selected channel. The measurement is usually expressed as  
dB down from the magnitude of the test signal. The crosstalk is  
expressed by:  
CROSSTALK  
Many systems, such as broadcast video, that handle numerous  
analog signal channels have strict requirements for keeping the  
various signals from influencing any of the others in the system.  
Crosstalk is the term used to describe the coupling of the signals  
of other nearby channels to a given channel.  
|XT| = 20 log10 (Asel(s)/Atest(s))  
where s = jw is the Laplace transform variable, Asel(s) is the  
amplitude of the crosstalk-induced signal in the selected channel  
and Atest(s) is the amplitude of the test signal. It can be seen  
that crosstalk is a function of frequency, but not a function of  
the magnitude of the test signal (to first order). In addition, the  
crosstalk signal will have a phase relative to the test signal asso-  
ciated with it.  
When there are many signals in close proximity in a system, as  
will undoubtedly be the case in a system that uses the AD8114/  
AD8115, the crosstalk issues can be quite complex. A good  
understanding of the nature of crosstalk and some definition of  
terms is required in order to specify a system that uses one or  
more AD8114/AD8115s.  
A network analyzer is most commonly used to measure crosstalk  
over a frequency range of interest. It can provide both magni-  
tude and phase information about the crosstalk signal.  
Types of Crosstalk  
Crosstalk can be propagated by means of any of three methods.  
These fall into the categories of electric field, magnetic field and  
sharing of common impedances. This section will explain these  
effects.  
As a crosspoint system or device grows larger, the number of  
theoretical crosstalk combinations and permutations can be-  
come extremely large. For example, in the case of the 16 × 16  
matrix of the AD8114/AD8115, we can examine the number of  
crosstalk terms that can be considered for a single channel, say  
IN00 input. IN00 is programmed to connect to one of the  
AD8114/AD8115 outputs where the measurement can be made.  
Every conductor can be both a radiator of electric fields and a  
receiver of electric fields. The electric field crosstalk mechanism  
occurs when the electric field created by the transmitter propa-  
gates across a stray capacitance (e.g., free space) and couples  
with the receiver and induces a voltage. This voltage is an un-  
wanted crosstalk signal in any channel that receives it.  
First, we can measure the crosstalk terms associated with driv-  
ing a test signal into each of the other 15 inputs one at a time,  
while applying no signal to IN00. We can then measure the  
crosstalk terms associated with driving a parallel test signal into  
all 15 other inputs taken two at a time in all possible combina-  
tions; and then three at a time, etc., until, finally, there is only  
one way to drive a test signal into all 15 other inputs in parallel.  
Currents flowing in conductors create magnetic fields that circu-  
late around the currents. These magnetic fields will then gener-  
ate voltages in any other conductors whose paths they link. The  
undesired induced voltages in these other channels are crosstalk  
signals. The channels that crosstalk can be said to have a mutual  
inductance that couples signals from one channel to another.  
Each of these cases is legitimately different from the others and  
might yield a unique value depending on the resolution of the  
measurement system, but it is hardly practical to measure all  
these terms and then to specify them. In addition, this describes  
the crosstalk matrix for just one input channel. A similar cross-  
talk matrix can be proposed for every other input. In addition, if  
the possible combinations and permutations for connecting  
inputs to the other (not used for measurement) outputs are  
taken into consideration, the numbers rather quickly grow to  
astronomical proportions. If a larger crosspoint array of multiple  
AD8114/AD8115s is constructed, the numbers grow larger still.  
The power supplies, grounds and other signal return paths of a  
multichannel system are generally shared by the various chan-  
nels. When a current from one channel flows in one of these  
paths, a voltage that is developed across the impedance becomes  
an input crosstalk signal for other channels that share the com-  
mon impedance.  
All these sources of crosstalk are vector quantities, so the  
magnitudes cannot simply be added together to obtain the total  
crosstalk. In fact, there are conditions where driving additional  
circuits in parallel in a given configuration can actually reduce  
the crosstalk.  
Obviously, some subset of all these cases must be selected to  
be used as a guide for a practical measure of crosstalk. One  
–18–  
REV. 0  
AD8114/AD8115  
common method is to measure “all hostile” crosstalk. This term  
means that the crosstalk to the selected channel is measured  
while all other system channels are driven in parallel. In general,  
this will yield the worst crosstalk number, but this is not always  
the case due to the vector nature of the crosstalk signal.  
reducing the coupling capacitance of the input circuits and  
lowering the output impedance of the drivers. If the input is  
driven from a 75 Ω terminated cable, the input crosstalk can be  
reduced by buffering this signal with a low output impedance  
buffer.  
Other useful crosstalk measurements are those created by one  
nearest neighbor or by the two nearest neighbors on either side.  
These crosstalk measurements will generally be higher than  
those of more distant channels, so they can serve as a worst case  
measure for any other one-channel or two-channel crosstalk  
measurements.  
On the output side, the crosstalk can be reduced by driving a  
lighter load. Although the AD8114/AD8115 is specified with  
excellent differential gain and phase when driving a standard  
150 Ω video load, the crosstalk will be higher than the minimum  
obtainable due to the high output currents. These currents will  
induce crosstalk via the mutual inductance of the output pins  
and bond wires of the AD8114/AD8115.  
Input and Output Crosstalk  
The flexible programming capability of the AD8114/AD8115  
can be used to diagnose whether crosstalk is occurring more on  
the input side or the output side. Some examples are illustrative.  
A given input channel (IN07 in the middle for this example) can  
be programmed to drive OUT07 (also in the middle). The input  
to IN07 is just terminated to ground (via 50 Ω or 75 Ω) and no  
signal is applied.  
From a circuit standpoint, this output crosstalk mechanism  
looks like a transformer with a mutual inductance between the  
windings that drives a load resistor. For low frequencies, the  
magnitude of the crosstalk is given by:  
|XT| = 20 log10 (Mxy × s/RL)  
where Mxy is the mutual inductance of output X to output Y  
and RL is the load resistance on the measured output. This  
crosstalk mechanism can be minimized by keeping the mutual  
inductance low and increasing RL. The mutual inductance can  
be kept low by increasing the spacing of the conductors and  
minimizing their parallel length.  
All the other inputs are driven in parallel with the same test  
signal (practically provided by a distribution amplifier), with all  
other outputs except OUT07 disabled. Since grounded IN07 is  
programmed to drive OUT07, no signal should be present. Any  
signal that is present can be attributed to the other 15 hostile  
input signals, because no other outputs are driven (they are all  
disabled). Thus, this method measures the all-hostile input  
contribution to crosstalk into IN07. Of course, the method can  
be used for other input channels and combinations of hostile  
inputs.  
PCB Layout  
Extreme care must be exercised to minimize additional crosstalk  
generated by the system circuit board(s). The areas that must be  
carefully detailed are grounding, shielding, signal routing and  
supply bypassing.  
The packaging of the AD8114/AD8115 is designed to help keep  
the crosstalk to a minimum. Each input is separated from each  
other input by an analog ground pin. All of these AGNDs should  
be directly connected to the ground plane of the circuit board.  
These ground pins provide shielding, low impedance return  
paths and physical separation for the inputs. All of these help to  
reduce crosstalk.  
For output crosstalk measurement, a single input channel is  
driven (IN00 for example) and all outputs other than a given  
output (IN07 in the middle) are programmed to connect to  
IN00. OUT07 is programmed to connect to IN15 (far away  
from IN00), which is terminated to ground. Thus OUT07  
should not have a signal present since it is listening to a quiet  
input. Any signal measured at the OUT07 can be attributed to  
the output crosstalk of the other 16 hostile outputs. Again, this  
method can be modified to measure other channels and other  
crosspoint matrix combinations.  
Each output is separated from its two neighboring outputs by an  
analog supply pin of one polarity or the other. Each of these  
analog supply pins provides power to the output stages of only  
the two nearest outputs. These supply pins provide shielding,  
physical separation and a low impedance supply for the outputs.  
Individual bypassing of each of these supply pins with a 0.01 µF  
chip capacitor directly to the ground plane minimizes high fre-  
quency output crosstalk via the mechanism of sharing common  
impedances.  
Effect of Impedances on Crosstalk  
The input side crosstalk can be influenced by the output imped-  
ance of the sources that drive the inputs. The lower the imped-  
ance of the drive source, the lower the magnitude of the crosstalk.  
The dominant crosstalk mechanism on the input side is capaci-  
tive coupling. The high impedance inputs do not have signifi-  
cant current flow to create magnetically induced crosstalk.  
However, significant current can flow through the input termi-  
nation resistors and the loops that drive them. Thus, the PC  
board on the input side can contribute to magnetically coupled  
crosstalk.  
Each output also has an on-chip compensation capacitor that  
is individually tied to the nearby analog ground pins AGND00  
through AGND07. This technique reduces crosstalk by prevent-  
ing the currents that flow in these paths from sharing a common  
impedance on the IC and in the package pins. These AGNDxx  
signals should all be connected directly to the ground plane.  
From a circuit standpoint, the input crosstalk mechanism looks  
like a capacitor coupling to a resistive load. For low frequencies  
the magnitude of the crosstalk will be given by:  
The input and output signals will have minimum crosstalk if  
they are located between ground planes on layers above and  
below, and separated by ground in between. Vias should be  
located as close to the IC as possible to carry the inputs and  
outputs to the inner layer. The only place the input and output  
signals surface is at the input termination resistors and the out-  
put series back-termination resistors. To the extent possible,  
these signals should also be separated as soon as they emerge  
from the IC package.  
|XT| = 20 log10 [(RS CM) × s]  
where RS is the source resistance, CM is the mutual capacitance  
between the test signal circuit and the selected circuit, and s is  
the Laplace transform variable.  
From the equation it can be observed that this crosstalk mecha-  
nism has a high-pass nature; it can be also minimized by  
REV. 0  
–19–  
AD8114/AD8115  
DVCC DGND NC AVEE AGND AVCC NC  
P1-1 P1-2  
+
P1-4  
P1-5  
P1-7  
P1-3  
P1-6  
+
DVCC  
0.01␮F  
AVCC  
0.01␮F  
AVEE  
0.01␮F  
JUMPER  
+
0.1␮F 10␮F  
0.1␮F 10␮F  
1, 75  
DVCC  
21, 55  
AVCC  
20, 56  
AVEE  
0.1␮F 10␮F  
NO CONNECT:  
85-93  
AVCC  
58  
54  
53  
INPUT 00  
INPUT 00  
AVCC  
OUTPUT 00  
OUTPUT 01  
OUTPUT 02  
OUTPUT 03  
OUTPUT 04  
OUTPUT 05  
OUTPUT 06  
OUTPUT 07  
OUTPUT 08  
OUTPUT 09  
OUTPUT 10  
OUTPUT 11  
OUTPUT 12  
OUTPUT 13  
OUTPUT 14  
OUTPUT 15  
57,59  
0.01␮F  
0.01␮F  
0.01␮F  
0.01␮F  
0.01␮F  
0.01␮F  
0.01␮F  
0.01␮F  
0.01␮F  
0.01␮F  
0.01␮F  
0.01␮F  
0.01␮F  
0.01␮F  
0.01␮F  
0.01␮F  
75⍀  
AGND  
75⍀  
75⍀  
75⍀  
75⍀  
75⍀  
75⍀  
75⍀  
75⍀  
75⍀  
75⍀  
75⍀  
75⍀  
75⍀  
75⍀  
75⍀  
75⍀  
OUTPUT 00  
60  
61  
AV  
EE  
INPUT 01  
INPUT 02  
INPUT 03  
INPUT 04  
INPUT 05  
INPUT 06  
INPUT 07  
INPUT 08  
INPUT 09  
INPUT 10  
INPUT 11  
INPUT 12  
INPUT 13  
INPUT 14  
INPUT 15  
INPUT 01  
AGND  
52  
51  
AVEE  
75⍀  
OUTPUT 01  
62  
63  
AVCC  
75⍀  
INPUT 02  
AGND  
50  
49  
AVCC  
OUTPUT 02  
64  
65  
INPUT 03  
AGND  
AV  
EE  
48  
47  
AVEE  
75⍀  
OUTPUT 03  
66  
67  
INPUT 04  
AGND  
AVCC  
75⍀  
46  
45  
AVCC  
68  
69  
OUTPUT 04  
INPUT 05  
AGND  
AV  
EE  
44  
43  
AVEE  
70  
71  
75⍀  
INPUT 06  
AGND  
OUTPUT 05  
AVCC  
75⍀  
42  
41  
AVCC  
72  
INPUT 07  
AGND  
OUTPUT 06  
3,73  
AV  
EE  
40  
39  
AVEE  
4
5
INPUT 08  
AGND  
AD8114/  
AD8115  
75⍀  
OUTPUT 07  
AVCC  
75⍀  
38  
37  
6
7
AVCC  
INPUT 09  
AGND  
OUTPUT 08  
AV  
EE  
8
9
36  
35  
INPUT 10  
AGND  
AVEE  
75⍀  
OUTPUT 09  
10  
11  
AVCC  
75⍀  
INPUT 11  
AGND  
34  
33  
AVCC  
OUTPUT 10  
12  
13  
INPUT 12  
AGND  
AV  
EE  
32  
31  
AVEE  
75⍀  
OUTPUT 11  
14  
15  
INPUT 13  
AGND  
AVCC  
75⍀  
30  
29  
AVCC  
16  
17  
OUTPUT 12  
INPUT 14  
AGND  
AV  
EE  
28  
27  
AVEE  
75⍀  
18  
19  
OUTPUT 13  
INPUT 15  
AGND  
AVCC  
75⍀  
26  
25  
AVCC  
98  
96  
DATA OUT  
DATA IN  
OUTPUT 14  
R
AV  
EE  
24  
23  
AVEE  
OUTPUT 15  
AVCC  
75⍀  
R
22  
P2-5  
P2-4  
P2-2  
P2-3  
P2-1  
P2-6  
2,74 100 99 97  
95 84 83 82 81 80 79 78 77 76 94  
R
R33  
20k⍀  
R
C
DVCC  
R
R
R
R
R
R
R
R
R
R
R
R
SERIAL MODE  
JUMP  
NOTE  
R = OPTIONAL 50⍀ TERMINATOR RESISTORS  
C = OPTIONAL SMOOTHING CAPACITOR  
Figure 44. Evaluation Board Schematic  
–20–  
REV. 0  
AD8114/AD8115  
Figure 45. Component Side Silkscreen  
Figure 46. Board Layout (Component Side)  
–21–  
REV. 0  
AD8114/AD8115  
Figure 47. Board Layout (Signal Layer)  
Figure 48. Board Layout (Ground Plane)  
–22–  
REV. 0  
AD8114/AD8115  
Figure 49. Board Layout (Circuit Side)  
Figure 50. Circuit Side Silkscreen  
REV. 0  
–23–  
AD8114/AD8115  
Optimized for video applications, all signal inputs and outputs  
are terminated with 75 Ω resistors. Stripline techniques are used  
to achieve a characteristic impedance on the signal input and  
output lines, also of 75 Ω. Figure 51 shows a cross-section of one  
of the input or output tracks along with the arrangement of the  
PCB layers. It should be noted that unused regions of the four  
layers are filled up with ground planes. As a result, the input and  
output traces, in addition to having controlled impedances, are  
well shielded.  
The board has 32 BNC type connectors: 16 inputs and 16  
outputs. The connectors are arranged in a crescent around the  
device. As can be seen from Figure 47, this results in all 16  
input signal traces and all 16 signal output traces having the  
same length. This is useful in tests such as All-Hostile  
Crosstalk where the phase relationship and delay between  
signals needs to be maintained from input to output.  
The three power supply pins AVCC, DVCC and AVEE should  
be connected to good quality, low noise, ±5 V supplies. Where  
the same ±5 V power supplies are used for analog and digital,  
separate cables should be run for the power supply to the  
evaluation board’s analog and digital power supply pins.  
w = 0.008"  
(0.2mm)  
TOP LAYER  
As a general rule, each power supply pin (or group of adjacent  
power supply pins) should be locally decoupled with a 0.01 µF  
capacitor. If there is a space constraint, it is more important to  
decouple analog power supply pins before digital power supply  
pins. A 0.1 µF capacitor, located reasonably close to the pins,  
can be used to decouple a number of power supply pins. Fi-  
nally a 10 µF capacitor should be used to decouple power sup-  
plies as they come onto the board.  
t = 0.00135" (0.0343mm)  
b = 0.0514"  
(1.3mm)  
a = 0.008"  
(0.2mm)  
SIGNAL LAYER  
POWER LAYER  
BOTTOM LAYER  
h = 0.025"  
(0.63mm)  
Figure 51. Cross Section of Input and Output Traces  
MOLEX 0.100" CENTER  
CRIMP TERMINAL HOUSING  
RESET  
D-SUB 25 PIN (MALE)  
1
1
14  
CLK  
CE  
UPDATE  
DATA IN  
6
DGND  
MOLEX  
TERMINAL HOUSING  
D-SUB-25  
SIGNAL  
2
3
4
5
6
25  
3
1
4
5
2
6
CE  
RESET  
UPDATE  
25  
13  
DATA IN  
CLK  
DGND  
EVALUATION BOARD  
PC  
Figure 52. Evaluation Board-PC Connection Cable  
–24–  
REV. 0  
AD8114/AD8115  
While the computer software only supports serial programming  
via a PC’s parallel port and the provided cable, the evaluation  
board has a connector that can be used for parallel program-  
ming. The SER/PAR signal should be at a logic high to use  
parallel programming. There is no cable nor software provided  
with the evaluation board for parallel programming. These are  
left to the user to provide.  
Controlling the Evaluation Board from a PC  
The evaluation board includes Windows®-based control soft-  
ware and a custom cable that connects the board’s digital inter-  
face to the printer port of the PC. The wiring of this cable is  
shown in Figure 52. The software requires Windows 3.1 or later  
to operate. To install the software, insert the disk labeled “Disk  
#1 of 2” in the PC and run the file called SETUP.EXE. Addi-  
tional installation instructions will be given on-screen. Before  
beginning installation, it is important to terminate any other  
Windows applications that are running.  
The software offers volatile and nonvolatile storage of configura-  
tions. For volatile storage, up to two configurations can be stored  
and recalled using the Memory 1 and Memory 2 Buffers. These  
function in a fashion identical to the memory on a pocket calcu-  
lator. For nonvolatile storage of a configuration, the Save Setup  
and Load Setup functions can be used. This stores the configu-  
ration as a data file on disk.  
When you launch the crosspoint control software, you will be  
asked to select the printer port you are using. Most modern PCs  
have only one printer port, usually called LPT1. However some  
laptop computers use the PRN port.  
Overshoot on PC Printer Ports’ Data Lines  
Figure 53 shows the main screen of the control software in its  
initial reset state (all outputs off). Using the mouse, any input  
can be connected with one or more outputs by simply clicking  
on the appropriate radio buttons in the 16 × 16 on-screen array.  
Each time a button is clicked on, the software automatically  
sends and latches the required 80-bit data stream to the evalua-  
tion board. An output can be turned off by clicking the appro-  
priate button in the Off column. To turn off all outputs, click on  
RESET.  
The data lines on some printer ports have excessive overshoot.  
Overshoot on the pin that is used as the serial clock (Pin 6 on  
the D-Sub-25 connector) can cause communication problems.  
This overshoot can be eliminated by connecting a capacitor  
from the CLK line on the evaluation board to ground. A pad  
has been provided on the circuit-side (C33) of the evaluation  
board to allow this capacitor to be soldered into place. Depend-  
ing upon the overshoot from the printer port, this capacitor may  
need to be as large as 0.01 µF.  
AD8114/AD8115  
Parallel Port Selection  
Figure 53. Screen Display and Control Software  
Windows is a registered trademark of Microsoft Corporation.  
REV. 0  
–25–  
AD8114/AD8115  
OUTLINE DIMENSIONS  
Dimensions shown in inches and (mm).  
100-Lead Plastic Thin Quad Flatpack (LQFP)  
(ST-100)  
0.063 (1.60)  
MAX  
0.630 (16.00) SQ  
0.030 (0.75)  
0.551 (14.00) SQ  
0.024 (0.60)  
0.018 (0.45)  
100  
76  
75  
1
SEATING  
PLANE  
TOP VIEW  
(PINS DOWN)  
STANDOFF  
0.003 (0.08)  
MAX  
25  
51  
26  
50  
0.057 (1.45)  
0.055 (1.40)  
0.053 (1.35)  
0.006 (0.15)  
0.002 (0.05)  
7؇  
3.5؇  
0؇  
0.008 (0.20)  
0.004 (0.09)  
0.020 (0.50)  
BSC  
0.011 (0.27)  
0.009 (0.22)  
0.007 (0.17)  
CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED  
–26–  
REV. 0  

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