AD8118_15 [ADI]
Analog Crosspoint Switch;型号: | AD8118_15 |
厂家: | ADI |
描述: | Analog Crosspoint Switch |
文件: | 总36页 (文件大小:1022K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
600 MHz, 32 × 32 Buffered
Analog Crosspoint Switch
AD8117/AD8118
FEATURES
FUNCTIONAL BLOCK DIAGRAM
D0 D1 D2 D3 D4 D5
VDD
DGND
High channel count, 32 × 32 high speed, non-blocking
switch array
Differential or single-ended operation
Differential G = +1 (AD8117) or G = +2 (AD8118)
Flexible power supplies
Single +5 V supply, or dual 2.5 V supplies
Serial or parallel programming of switch array
High impedance output disable allows connection of
multiple devices with minimal loading on output bus
Excellent video performance
>50 MHz 0.1 dB gain flatness
0.05%/0.05° differential gain/phase error (RL = 150 Ω)
Excellent ac performance
Bandwidth: 600 MHz
Slew rate: 1800 V/μs
A0
A1
A2
A3
A4
AD8117/
AD8118
SER/PAR
WE
1
0
192-BIT SHIFT REGISTER
WITH 6-BIT
PARALLEL LOADING
DATA
OUT
CLK
DATA IN
192
UPDATE
RESET
PARALLEL LATCH
192
DECODE
32 × 6:32 DECODERS
32
INPUT
1024
OUTPUT
BUFFER
G = +1
RECEIVER
G = +1*
G = +2**
2
2
Settling time: 2.5 ns to 1%
Low power of 2.5 W
Low all hostile crosstalk
< −70 dB @ 5 MHz
SWITCH
MATRIX
< −43 dB @ 600 MHz
Reset pin allows disabling of all outputs (connected through
a capacitor to ground provides power-on reset capability)
304-ball BGA package (31 mm × 31 mm)
APPLICATIONS
Routing of high speed signals including
RGB and component video routing
KVM
*AD8117 ONLY
**AD8118 ONLY
VPOS VNEG
VOCM
Figure 1.
Compressed video (MPEG, wavelet)
Data communications
GENERAL DESCRIPTION
The AD8117/AD8118 are high speed, 32 × 32 analog crosspoint
switch matrices. They offer 600 MHz bandwidth and slew rate of
1800 V/μs for high resolution computer graphics (RGB) signal
switching. With less than −70 dB of crosstalk and −90 dB
isolation (@ 5 MHz), the AD8117/AD8118 are useful in many
high speed applications. The 0.1 dB flatness greater than
50 MHz makes the AD8117/AD8118 ideal for composite video
switching.
back-terminated load applications. They operate as fully
differential devices or can be configured for single-ended
operation. Either a single +5 V supply or dual 2.5 V supplies
can be used, while consuming only 500 mA of idle current with
all outputs enabled. The channel switching is performed via a
double-buffered, serial digital control (which can accommodate
daisy chaining of several devices), or via a parallel control,
allowing updating of an individual output without reprogram-
ming the entire array.
The AD8117/AD8118 include 32 independent output buffers
that can be placed into a high impedance state for paralleling
crosspoint outputs so that off-channels present minimal loading
to an output bus. The AD8117 has a differential gain of +1,
while the AD8118 has a differential gain of +2 for ease of use in
The AD8117/AD8118 are packaged in a 304-ball BGA package
and are available over the extended industrial temperature
range of −40°C to +85°C.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2007 Analog Devices, Inc. All rights reserved.
AD8117/AD8118
TABLE OF CONTENTS
Features .............................................................................................. 1
ESD Caution...................................................................................7
Pin Configuration and Function Descriptions..............................8
Truth Table and Logic Diagram ............................................... 13
I/O Schematics................................................................................ 15
Typical Performance Characteristics ........................................... 17
Theory of Operation ...................................................................... 25
Applications..................................................................................... 26
Programming.............................................................................. 26
Operating Modes........................................................................ 27
Outline Dimensions....................................................................... 36
Ordering Guide .......................................................................... 36
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics (Serial Mode) ....................................... 5
Timing Characteristics (Parallel Mode) .................................... 6
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
Power Dissipation......................................................................... 7
REVISION HISTORY
5/07—Rev. 0 to Rev. A
Added AD8118 ...................................................................Universal
Changes to Data Sheet Title ........................................................... 1
Changes to Table 1............................................................................ 3
2/07—Revision 0: Initial Version
Rev. A | Page 2 of 36
AD8117/AD8118
SPECIFICATIONS
VS = 2.5 V at TA = 25°C, RL, diff = 200 Ω, VOCM = 0 V, differential I/O mode, unless otherwise noted.
Table 1.
AD8117/AD8118
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth
200 mV p-p, typical channel
2 V p-p, typical channel
0.1 dB, 200 mV p-p
0.1 dB, 2 V p-p
2 V p-p
1%, 2 V step
600
MHz
MHz
MHz
MHz
ns
ns
V/μs
V/μs
420/525
100/50
70/50
1.3
2.5
1800
1500
Gain Flatness
Propagation Delay
Settling Time
Slew Rate
2 V step, peak
2 V step, 10% to 90%
NOISE/DISTORTION PERFORMANCE
Differential Gain Error
Differential Phase Error
Crosstalk, All Hostile
NTSC or PAL, RL = 150 Ω
NTSC or PAL, RL = 150 Ω
f = 5 MHz
f = 10 MHz
f = 100 MHz
f = 600 MHz
f = 10 MHz, one channel
0.1 MHz to 50 MHz
0.05
0.05
%
Degrees
dB
dB
dB
dB
−70/−75
−65/−70
−45/−50
−43/−50
−90
Off Isolation, Input-Output
Input Voltage Noise
DC PERFORMANCE
Voltage Gain
dB
nV/√Hz
45/53
Differential
+1/+2
1
V/V
%
Gain Error
No load
1
3
%
Gain Matching
Channel-to-channel
1
%
Differential Offset
5
25
25
90
mV
mV
Common-Mode Offset
OUTPUT CHARACTERISTICS
Output Impedance
DC, enabled
Disabled, differential
Disabled
Disabled
No load
VOUT, diff = 2 V p-p
VOUT, diff = 2.8 V p-p
Single-ended output
Maximum operating signal
0.1
30
4
Ω
kΩ
pF
μA
V p-p
V
V
V
mA
Output Disable Capacitance
Output Leakage Current
Output Voltage Range
VOCM Input Range
1
2.8
3.8
−0.5
−0.25
−1.3
0.8
0.6
1.3
Output Swing Limit
Output Current
30
INPUT CHARACTERISTICS
Input Voltage Range
Common mode, VIN, diff = 2 V p-p
Differential
f = 10 MHz
Any switch configuration
Differential
−2
2
V
V
2/1
48
2
5
1
Common-Mode Rejection Ratio
Input Capacitance
Input Resistance
Input Offset Current
VOCM Input Bias Current
VOCM Input Impedance
dB
pF
kΩ
ꢀA
μA
kΩ
64
4
Rev. A | Page 3 of 36
AD8117/AD8118
AD8117/AD8118
Parameter
Conditions
Min
Typ
Max
Unit
SWITCHING CHARACTERISTICS
Enable On Time
Switching Time, 2 V Step
Switching Transient (Glitch)
POWER SUPPLIES
50% update to 1% settling
50% update to 1% settling
Differential
100
100
40
ns
ns
mV p-p
Supply Current
VPOS, outputs enabled, no load
Outputs disabled
VNEG, outputs enabled, no load
Outputs disabled
500
200
500
200
580
240
580
240
1.2
mA
mA
mA
mA
mA
V
VDD, outputs enabled, no load
Supply Voltage Range
PSRR
4.5 to 5.5
85
75
VNEG, VPOS, f = 1 MHz
VOCM, f = 1 MHz
dB
dB
OPERATING TEMPERATURE RANGE
Temperature Range
θJA
θJC
Operating (still air)
Operating (still air)
Operating (still air)
−40 to +85
14
1
°C
°C/W
°C/W
Rev. A | Page 4 of 36
AD8117/AD8118
TIMING CHARACTERISTICS (SERIAL MODE)
Specifications subject to change without notice.
Table 2.
Limit
Typ
Parameter
Symbol
Min
40
50
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Serial Data Setup Time
CLK Pulse Width
t1
t2
t3
t4
t5
t6
t7
Serial Data Hold Time
CLK Pulse Separation
CLK to UPDATE Delay
UPDATE Pulse Width
CLK to DATA OUT Valid
Propagation Delay, UPDATE to Switch On or Off
RESET Pulse Width
50
150
10
90
120
100
200
60
RESET Time
1
WE
0
t2
t4
1
CLK
0
LOAD DATA INTO
SERIAL REGISTER
ON FALLING EDGE
t1
t3
1
DATA IN
0
OUT31 (D5)
OUT30 (D4)
OUT00 (D0)
t5
t6
1 = LATCHED
TRANSFER DATA FROM SERIAL
REGISTER TO PARALLEL
LATCHES DURING LOW LEVEL
UPDATE
0 = TRANSPARENT
t7
DATA OUT
Figure 2. Timing Diagram, Serial Mode
Table 3. Logic Levels
VIH
VIL
VOH
VOL
IIH
RESET1,
IIL
RESET1,
IOH
IOL
RESET,
RESET,
DATA OUT
DATA OUT
DATA OUT
DATA OUT
SER/PAR, CLK,
DATA IN,
UPDATE
SER/PAR, CLK,
DATA IN,
UPDATE
SER/PAR, CLK,
DATA IN,
UPDATE
SER/PAR, CLK,
DATA IN,
UPDATE
2.0 V min
0.6 V max
VDD − 0.3 V min DGND + 0.5 V max
1 ꢀA max
–1 ꢀA min
−1 mA max
1 mA min
1 See Figure 15.
Rev. A | Page 5 of 36
AD8117/AD8118
TIMING CHARACTERISTICS (PARALLEL MODE)
Specifications subject to change without notice.
Table 4.
Limit
Typ
Parameter
Symbol
Min
80
110
150
90
Max
Unit
ns
ns
Parallel Data Setup Time
WE Pulse Width
t1
t2
t3
t4
t5
t6
Parallel Data Hold Time
WE Pulse Separation
WE to UPDATE Delay
UPDATE Pulse Width
Propagation Delay, UPDATE to Switch On or Off
RESET Pulse Width
ns
ns
10
ns
90
ns
100
200
ns
60
ns
RESET Time
ns
t2
t4
1
WE
0
t1
t3
1
D0 TO D5
A0 TO A4
0
t5
t6
1 = LATCHED
UPDATE
0 = TRANSPARENT
Figure 3. Timing Diagram, Parallel Mode
Table 5. Logic Levels
VIH
VIL
VOH
VOL
IIH
RESET1,
IIL
RESET1,
IOH
IOL
RESET,
RESET,
DATA OUT
DATA OUT
DATA OUT
DATA OUT
SER/PAR, WE,
SER/PAR, WE,
SER/PAR, WE,
SER/PAR, WE,
D0, D1, D2, D3, D0, D1, D2, D3,
D4, D5, A0, A1, D4, D5, A0, A1,
D0, D1, D2, D3, D0, D1, D2, D3,
D4, D5, A0, A1, D4, D5, A0, A1,
A2, A3, A4,
UPDATE
A2, A3, A4,
UPDATE
A2, A3, A4,
UPDATE
A2, A3, A4,
UPDATE
2.0 V min
0.6 V max
Disabled
Disabled
1 μA max
–1 μA min
Disabled
Disabled
1 See Figure 15.
Rev. A | Page 6 of 36
AD8117/AD8118
ABSOLUTE MAXIMUM RATINGS
Table 6.
POWER DISSIPATION
Parameter
Rating
The AD8117/AD8118 are operated with 2.5 V or +5 V
supplies and can drive loads down to 100 ꢀ, resulting in a large
range of possible power dissipations. For this reason, extra care
must be taken derating the operating conditions based on
ambient temperature.
Analog Supply Voltage (VPOS – VNEG
Digital Supply Voltage (VDD – DGND
Ground Potential Difference
)
)
6 V
6 V
+0.5 V to −2.5 V
(VNEG – DGND
Maximum Potential Difference
(VDD – VNEG
Common-Mode Analog Input
Voltage
Differential Analog Input Voltage
Digital Input Voltage
Output Voltage
)
8 V
Packaged in a 304-ball BGA, the AD8117/AD8118 junction-to-
ambient thermal impedance (θJA) is 14°C/W. For long-term
reliability, the maximum allowed junction temperature of the
die should not exceed 150°C. Temporarily exceeding this limit
may cause a shift in parametric performance due to a change in
stresses exerted on the die by the package. Exceeding a junction
temperature of 175°C for an extended period can result in
device failure. The following curve shows the range of allowed
internal die power dissipations that meet these conditions over
the −40°C to +85°C ambient temperature range. When using
the table, do not include external load power in the maximum
power calculation, but do include load current dropped on the
die output transistors.
)
VNEG to VPOS
2 V
VDD
(VPOS − 1 V) to (VNEG + 1 V)
(Disabled Analog Output)
Output Short-Circuit Duration
Output Short-Circuit Current
Storage Temperature
Operating Temperature Range
Lead Temperature
(Soldering 10 sec)
Momentary
80 mA
−65°C to +125°C
−40°C to +85°C
300°C
Junction Temperature
150°C
8
T
= 150°C
J
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
7
6
5
4
THERMAL RESISTANCE
15
25
35
45
55
65
75
85
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
AMBIENT TEMPERATURE (°C)
Figure 4. Maximum Die Power Dissipation vs. Ambient Temperature
Table 7. Thermal Resistance
Package Type
θJA
θJC
θJB
ψJT
ψJB
Unit
ESD CAUTION
304-Ball BGA
14
1
6.5
0.6
5.7
°C/W
Rev. A | Page 7 of 36
AD8117/AD8118
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
VPOS OP17
OP16 ON16
ON17
OP19
ON19
OP21
ON21
OP23
ON23
OP25
ON25
OP27
ON27
OP29
ON29
OP31
ON31 VPOS
VPOS VPOS
VPOS VPOS
VPOS VPOS
VPOS VPOS
VPOS VPOS VPOS
VPOS VPOS VPOS
VPOS VPOS VPOS
A
B
A
B
OP18
ON18
OP20
ON20
OP22
ON22
OP24
ON24
OP26
ON26
OP28
ON28
OP30
ON30
VPOS VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS
VNEG VOCM VNEG VNEG VNEG VNEG VNEG VPOS VPOS VPOS VNEG VNEG VNEG VNEG VNEG VOCM VNEG VPOS
C
C
VPOS VPOS
IN17
IP0
IN0
VPOS
IP1
IN16
IP16
IN18
IP18
IN20
IP20
IN22
IP22
IN24
IP24
IN26
IP26
IN28
IP28
IN30
IP30
VPOS
D
D
VNEG VOCM
VOCM VNEG
E
E
VNEG
VDD
VDD
VNEG
IP2
IN1
IP17
IN19
IP19
IN21
IP21
IN23
IP23
IN25
IP25
IN27
IP27
IN29
IP29
IN31
IP31
F
F
VNEG DGND
VNEG RESET
VNEG
DGND VNEG
IN2
IP3
G
H
G
H
DATA
VNEG
OUT
IP4
IN3
CLK
VNEG
VNEG
VPOS
VPOS
VPOS
VNEG
VNEG
VNEG
VNEG
IN4
IP5
J
J
DATA
IN
VNEG
VPOS
VPOS
VPOS
VNEG
VNEG
VNEG
VNEG
WE
D5
IP6
IN5
K
K
SER/
PAR
IN6
IP7
L
L
AD8117/AD8118
A4
A3
IP8
IN7
D4
M
N
M
N
BOTTOM VIEW
(Not to Scale)
IN8
IP9
D3
A2
IP10
IN10
IP12
IN12
IP14
IN14
VPOS
IN9
D2
P
P
A1
IP11
IN11
IP13
IN13
IP15
IN15
D1
R
R
D0
A0
T
T
VDD
VDD
U
U
VNEG DGND
VNEG VOCM
DGND VNEG
VOCM VNEG
V
V
W
Y
W
Y
VPOS
VNEG VOCM VNEG VNEG VNEG VNEG VNEG VPOS VPOS VPOS VNEG VNEG VNEG VNEG VNEG VOCM VNEG VPOS
VPOS VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS
VPOS VPOS
VPOS VPOS
VPOS VPOS
VPOS VPOS VPOS
VPOS VPOS VPOS
VPOS VPOS VPOS
AA
AB
AC
AA
AB
AC
VPOS ON14
ON15 OP15
OP14
ON13
ON12
OP13
OP12
ON11
ON10
OP11
OP10
ON9
ON8
OP9
OP8
ON7
ON6
OP7
OP6
ON5
ON4
OP5
OP4
ON3
ON2
OP3
OP2
ON1
ON0
OP1
OP0
VPOS
VPOS VPOS
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Figure 5. Package Bottom View
Rev. A | Page 8 of 36
AD8117/AD8118
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
23
22
21
VPOS VPOS
VPOS VPOS
VPOS VPOS
VPOS ON31
VPOS VPOS
OP31
OP21
VPOS VPOS VPOS
VPOS VPOS VPOS
VPOS VPOS VPOS
ON29
OP29
ON27
OP27
ON25
OP25
ON23
OP23
ON21
ON19
OP19
ON17
OP17 VPOS
ON16 OP16
A
B
A
ON30
OP30
ON28
OP28
ON26
OP26
ON24
OP24
ON22
OP22
ON20
OP20
ON18
OP18
B
VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VPOS
VPOS VNEG VOCM VNEG VNEG VNEG VNEG VNEG VPOS VPOS VPOS VNEG VNEG VNEG VNEG VNEG VOCM VNEG
C
C
VPOS
IP1
IP0
IN0
VPOS VPOS
VOCM VNEG
IN17
IN16
IP16
IN18
IP18
IN20
IP20
IN22
IP22
IN24
IP24
IN26
IP26
IN28
IP28
IN30
IP30
VPOS
D
D
VNEG VOCM
E
E
IN1
IP2
VNEG
VDD
VDD
VNEG
IP17
IN19
IP19
IN21
IP21
IN23
IP23
IN25
IP25
IN27
IP27
IN29
IP29
IN31
IP31
F
F
IP3
IN2
VNEG DGND
DGND VNEG
RESET VNEG
VNEG
G
H
G
H
DATA
VNEG
IN3
IP4
OUT
IP5
IN4
VNEG
VNEG
VPOS
VPOS
VPOS
VNEG
VNEG
VNEG
VNEG
CLK
J
J
DATA
IN
IN5
IP6
VNEG
VPOS
VPOS
VPOS
VNEG
VNEG
VNEG
VNEG
WE
D5
K
K
SER/
PAR
IP7
IN6
L
L
AD8117/AD8118
IN7
IP8
A4
A3
D4
M
N
M
N
TOP VIEW
(Not to Scale)
IP9
IN8
D3
IN9
IP10
IN10
IP12
IN12
IP14
IN14
VPOS
A2
D2
P
P
IP11
IN11
IP13
IN13
IP15
IN15
A1
D1
R
R
A0
D0
T
T
VDD
VDD
U
U
VNEG DGND
VNEG VOCM
DGND VNEG
VOCM VNEG
V
V
W
Y
W
Y
VPOS VNEG VOCM VNEG VNEG VNEG VNEG VNEG VPOS VPOS VPOS VNEG VNEG VNEG VNEG VNEG VOCM VNEG
VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VPOS
VPOS
VPOS VPOS
VPOS VPOS
VPOS VPOS
VPOS VPOS VPOS
VPOS VPOS VPOS
VPOS VPOS VPOS
AA
AB
AC
AA
AB
AC
VPOS
OP0
ON0
OP1
ON10
OP11
OP12
ON11
ON12
OP13
OP14
ON13
ON14 VPOS
OP15 ON15
OP2
ON1
ON2
OP3
OP4
ON3
ON4
OP5
OP6
ON5
ON6
OP7
OP8
ON7
ON8
OP9
OP10
ON9
VPOS VPOS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Figure 6. Package Top View
Table 8. Ball Grid Description
Ball No. Mnemonic Description
Ball No. Mnemonic Description
A1
A2
A3
A4
A5
A6
A7
A8
VPOS
VPOS
VPOS
ON31
OP31
ON29
OP29
ON27
OP27
ON25
OP25
ON23
OP23
ON21
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
A15
A16
A17
A18
A19
A20
A21
A22
A23
B1
OP21
ON19
OP19
ON17
OP17
VPOS
VPOS
VPOS
VPOS
VPOS
VPOS
VPOS
VPOS
ON30
Output Number 21, Positive Phase.
Output Number 19, Negative Phase.
Output Number 19, Positive Phase.
Output Number 17, Negative Phase.
Output Number 17, Positive Phase.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Output Number 30, Negative Phase.
Output Number 31, Negative Phase.
Output Number 31, Positive Phase.
Output Number 29, Negative Phase.
Output Number 29, Positive Phase.
Output Number 27, Negative Phase.
Output Number 27, Positive Phase.
Output Number 25, Negative Phase.
Output Number 25, Positive Phase.
Output Number 23, Negative Phase.
Output Number 23, Positive Phase.
Output Number 21, Negative Phase.
A9
A10
A11
A12
A13
A14
B2
B3
B4
B5
Rev. A | Page 9 of 36
AD8117/AD8118
Ball No. Mnemonic Description
Ball No. Mnemonic Description
B6
B7
B8
B9
OP30
ON28
OP28
ON26
OP26
ON24
OP24
ON22
OP22
ON20
OP20
ON18
OP18
ON16
OP16
VPOS
VPOS
VPOS
VPOS
VPOS
VPOS
VPOS
VNEG
VNEG
VNEG
VNEG
VNEG
VNEG
VPOS
VPOS
VPOS
VNEG
VNEG
VNEG
VNEG
VNEG
VNEG
VPOS
VPOS
VPOS
VPOS
VPOS
IP0
Output Number 30, Positive Phase.
Output Number 28, Negative Phase.
Output Number 28, Positive Phase.
Output Number 26, Negative Phase.
Output Number 26, Positive Phase.
Output Number 24, Negative Phase.
Output Number 24, Positive Phase.
Output Number 22, Negative Phase.
Output Number 22, Positive Phase.
Output Number 20, Negative Phase.
Output Number 20, Positive Phase.
Output Number 18, Negative Phase.
Output Number 18, Positive Phase.
Output Number 16, Negative Phase.
Output Number 16, Positive Phase.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Input Number 0, Positive Phase.
Analog Positive Power Supply.
Analog Negative Power Supply.
D12
D13
D14
D15
D16
D17
D18
D19
VPOS
VPOS
VNEG
VNEG
VNEG
VNEG
VNEG
VOCM
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Output Common-Mode Reference
Supply.
Analog Negative Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
D1
D20
D21
D22
VNEG
VPOS
VPOS
D23
E1
E2
E3
E4
IN16
IP1
IN0
VNEG
VOCM
Input Number 16, Negative Phase.
Input Number 1, Positive Phase.
Input Number 0, Negative Phase.
Analog Negative Power Supply.
Output Common-Mode Reference
Supply.
E20
VOCM
Output Common-Mode Reference
Supply.
E21
E22
E23
F1
F2
F3
VNEG
IN17
IP16
IN1
IP2
VNEG
VDD
VDD
VNEG
IP17
IN18
IP3
IN2
VNEG
DGND
DGND
VNEG
IN19
IP18
Analog Negative Power Supply.
Input Number 17, Negative Phase.
Input Number 16, Positive Phase.
Input Number 1, Negative Phase.
Input Number 2, Positive Phase.
Analog Negative Power Supply.
Logic Positive Power Supply.
F4
F20
F21
F22
F23
G1
G2
G3
G4
G20
G21
G22
G23
H1
H2
H3
H4
H20
H21
H22
H23
J1
J2
J3
J4
Logic Positive Power Supply.
Analog Negative Power Supply.
Input Number 17, Positive Phase.
Input Number 18, Negative Phase.
Input Number 3, Positive Phase.
Input Number 2, Negative Phase.
Analog Negative Power Supply.
Logic Negative Power Supply.
Logic Negative Power Supply.
Analog Negative Power Supply.
Input Number 19, Negative Phase.
Input Number 18, Positive Phase.
Input Number 3, Negative Phase.
Input Number 4, Positive Phase.
Analog Negative Power Supply.
Control Pin: Serial Data Out.
Control Pin: Second Rank Data Reset.
Analog Negative Power Supply.
Input Number 19, Positive Phase.
Input Number 20, Negative Phase.
Input Number 5, Positive Phase.
Input Number 4, Negative Phase.
Analog Negative Power Supply.
Control Pin: Serial Data Clock.
Control Pin: Second Rank Write Strobe.
IN3
IP4
VNEG
DATA OUT
RESET
VNEG
IP19
IN20
IP5
IN4
D2
D3
D4
D5
VPOS
VNEG
VOCM
Output Common-Mode Reference
Supply.
D6
D7
D8
D9
D10
D11
VNEG
VNEG
VNEG
VNEG
VNEG
VPOS
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Positive Power Supply.
VNEG
CLK
J20
UPDATE
Rev. A | Page 10 of 36
AD8117/AD8118
Ball No. Mnemonic Description
Ball No. Mnemonic Description
J21
J22
J23
K1
K2
K3
VNEG
IN21
IP20
IN5
Analog Negative Power Supply.
Input Number 21, Negative Phase.
Input Number 20, Positive Phase.
Input Number 5, Negative Phase.
Input Number 6, Positive Phase.
Analog Negative Power Supply.
Control Pin: Serial Data In.
T2
T3
T4
T20
T21
T22
T23
IP12
VNEG
A0
Input Number 12, Positive Phase.
Analog Negative Power Supply.
Control Pin: Output Address Bit 0.
Control Pin: Input Address Bit 0.
Analog Negative Power Supply.
Input Number 27, Positive Phase.
Input Number 28, Negative Phase.
D0
IP6
VNEG
IP27
IN28
VNEG
DATA IN
WE
K4
K20
K21
K22
K23
L1
L2
L3
L4
Control Pin: First Rank Write Strobe.
Analog Negative Power Supply.
Input Number 21, Positive Phase.
Input Number 22, Negative Phase.
Input Number 7, Positive Phase.
Input Number 6, Negative Phase.
Analog Positive Power Supply.
Control Pin: Serial/Parallel Mode Select.
Control Pin: Input Address Bit 5.
Analog Positive Power Supply.
Input Number 23, Negative Phase.
Input Number 22, Positive Phase.
Input Number 7, Negative Phase.
Input Number 8, Positive Phase.
Analog Positive Power Supply.
Control Pin: Output Address Bit 4.
Control Pin: Input Address Bit 4.
Analog Positive Power Supply.
Input Number 23, Positive Phase.
Input Number 24, Negative Phase.
Input Number 9, Positive Phase.
Input Number 8, Negative Phase.
Analog Positive Power Supply.
Control Pin: Output Address Bit 3.
Control Pin: Input Address Bit 3.
Analog Positive Power Supply.
Input Number 25, Negative Phase.
Input Number 24, Positive Phase.
Input Number 9, Negative Phase.
Input Number 10, Positive Phase.
Analog Negative Power Supply.
Control Pin: Output Address Bit 2.
Control Pin: Input Address Bit 2.
Analog Negative Power Supply.
Input Number 25, Positive Phase.
Input Number 26, Negative Phase.
Input Number 11, Positive Phase.
Input Number 10, Negative Phase.
Analog Negative Power Supply.
Control Pin: Output Address Bit 1.
Control Pin: Input Address Bit 1.
Analog Negative Power Supply.
Input Number 27, Negative Phase.
Input Number 26, Positive Phase.
Input Number 11, Negative Phase.
U1
IP13
Input Number 13, Positive Phase.
Input Number 12, Negative Phase.
Analog Negative Power Supply.
Logic Positive Power Supply.
VNEG
IP21
IN22
IP7
U2
U3
U4
U20
U21
U22
U23
IN12
VNEG
VDD
VDD
VNEG
IN29
IP28
Logic Positive Power Supply.
IN6
Analog Negative Power Supply.
Input Number 29, Negative Phase.
Input Number 28, Positive Phase.
VPOS
SER/PAR
D5
VPOS
IN23
IP22
IN7
IP8
VPOS
A4
L20
L21
L22
L23
M1
M2
M3
M4
M20
M21
M22
M23
N1
N2
N3
N4
N20
N21
N22
N23
P1
P2
P3
P4
P20
P21
P22
P23
R1
R2
R3
R4
R20
R21
R22
R23
T1
V1
V2
V3
V4
V20
V21
V22
V23
W1
W2
W3
W4
IN13
IP14
Input Number 13, Negative Phase.
Input Number 14, Positive Phase.
Analog Negative Power Supply.
Logic Negative Power Supply.
Logic Negative Power Supply.
Analog Negative Power Supply.
Input Number 29, Positive Phase.
Input Number 30, Negative Phase.
Input Number 15, Positive Phase.
Input Number 14, Negative Phase.
Analog Negative Power Supply.
Output Common-Mode Reference
Supply.
Output Common-Mode Reference
Supply.
Analog Negative Power Supply.
Input Number 31, Negative Phase.
Input Number 30, Positive Phase.
Input Number 15, Negative Phase.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Negative Power Supply.
VNEG
DGND
DGND
VNEG
IP29
IN30
IP15
IN14
VNEG
VOCM
D4
VPOS
IP23
IN24
IP9
IN8
VPOS
A3
W20
VOCM
W21
W22
W23
Y1
Y2
Y3
VNEG
IN31
IP30
D3
VPOS
IN25
IP24
IN9
IP10
VNEG
A2
IN15
VPOS
VPOS
VNEG
VOCM
Y4
Y5
Output Common-Mode Reference
Supply.
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
VNEG
VNEG
VNEG
VNEG
VNEG
VPOS
VPOS
VPOS
VNEG
VNEG
VNEG
VNEG
VNEG
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
D2
VNEG
IP25
IN26
IP11
IN10
VNEG
A1
D1
VNEG
IN27
IP26
IN11
Rev. A | Page 11 of 36
AD8117/AD8118
Ball No. Mnemonic Description
Ball No. Mnemonic Description
Y19
VOCM
Output Common-Mode Reference
Supply.
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AC1
OP6
ON6
OP8
ON8
Output Number 6, Positive Phase.
Output Number 6, Negative Phase.
Output Number 8, Positive Phase.
Output Number 8, Negative Phase.
Output Number 10, Positive Phase.
Output Number 10, Negative Phase.
Output Number 12, Positive Phase.
Output Number 12, Negative Phase.
Output Number 14, Positive Phase.
Output Number 14, Negative Phase.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Output Number 1, Positive Phase.
Output Number 1, Negative Phase.
Output Number 3, Positive Phase.
Output Number 3, Negative Phase.
Output Number 5, Positive Phase.
Output Number 5, Negative Phase.
Output Number 7, Positive Phase.
Output Number 7, Negative Phase.
Output Number 9, Positive Phase.
Output Number 9, Negative Phase.
Output Number 11, Positive Phase.
Output Number 11, Negative Phase.
Output Number 13, Positive Phase.
Output Number 13, Negative Phase.
Output Number 15, Positive Phase.
Output Number 15, Negative Phase.
Analog Positive Power Supply.
Y20
Y21
Y22
Y23
VNEG
VPOS
IP31
Analog Negative Power Supply.
Analog Positive Power Supply.
Input Number 31, Positive Phase.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Negative Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Analog Positive Power Supply.
Output Number 0, Positive Phase.
Output Number 0, Negative Phase.
Output Number 2, Positive Phase.
Output Number 2, Negative Phase.
Output Number 4, Positive Phase.
Output Number 4, Negative Phase.
OP10
ON10
OP12
ON12
OP14
ON14
VPOS
VPOS
VPOS
VPOS
VPOS
VPOS
VPOS
VPOS
OP1
VPOS
VPOS
VPOS
VPOS
VPOS
VNEG
VNEG
VNEG
VNEG
VNEG
VNEG
VPOS
VPOS
VPOS
VNEG
VNEG
VNEG
VNEG
VNEG
VNEG
VPOS
VPOS
VPOS
VPOS
VPOS
VPOS
VPOS
OP0
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9
AA10
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AB1
AC2
AC3
AC4
AC5
AC6
ON1
AC7
AC8
AC9
OP3
ON3
OP5
ON5
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
OP7
ON7
OP9
ON9
OP11
ON11
OP13
ON13
OP15
ON15
VPOS
VPOS
VPOS
AB2
AB3
AB4
AB5
AB6
AB7
AB8
AB9
ON0
OP2
ON2
OP4
Analog Positive Power Supply.
Analog Positive Power Supply.
ON4
Rev. A | Page 12 of 36
AD8117/AD8118
TRUTH TABLE AND LOGIC DIAGRAM
Table 9. Operation Truth Table
DATA
INPUT
DATA
OUTPUT
WE
UPDATE
CLK
RESET
SER/PAR
Operation/Comment
X
X
X
X
X
0
X
Asynchronous reset. All outputs are
disabled. Remainder of logic in 192-bit shift
register is unchanged.
0
1
X
X
X
D0…D51
Datai2
NA in
parallel
mode
1
1
0
0
Broadcast. The data on parallel lines D0 to
D5 are loaded into all 32 output address
locations of the 192-bit shift register.
Serial mode. The data on the serial DATA IN
line is loaded into the serial register. The first
bit clocked into the serial register appears
at DATA OUT 192 clock cycles later.
Datai-192
0
1
1
X
0
X
X
X
X
D0…D51
A0…A43
NA in
parallel
mode
NA in
parallel
mode
1
1
1
1
X
1
Parallel programming mode. The data on
parallel lines D0 to D5 are loaded into the
shift register location addressed by A0 to A4.
Switch matrix update. Data in the 192-bit
shift register transfers into the parallel
latches that control the switch array.
X
X
X
No change in logic.
1 D0…D5: data bits.
2 Datai: serial data.
3 A0…A4: address bits.
Rev. A | Page 13 of 36
AD8117/AD8118
0 0 7 6 5 6 - 0 3
R E D O C E
E S D R A D
D 3 2 T O 5
S
T U P T O U
Figure 7. Logic Diagram
Rev. A | Page 14 of 36
AD8117/AD8118
I/O SCHEMATICS
IPn
INn
1.3pF
1.3pF
2500Ω
2500Ω
OPn, ONn
0.3pF
Figure 8. AD8117/AD8118 Enabled Output
(see also ESD Protection Map, Figure 18)
Figure 12. AD8117/AD8118 Receiver Simplified Equivalent Circuit When
Driving Differentially
OPn
IPn
3.4pF
3.33kΩ AD8117 G = +1
3.76kΩ AD8118 G = +2
1.6pF
0.4pF
30kΩ
INn
3.4pF
ONn
Figure 13. AD8117/AD8118 Receiver Simplified Equivalent Circuit When
Driving Single-Ended
Figure 9. AD8117/AD8118 Disabled Output
(see also ESD Protection Map, Figure 18)
2500Ω
1.3pF
2538Ω
IPn
INn
VOCM
0.3pF
1.3pF
2500Ω
VNEG
2538Ω
Figure 14. VOCM Input (see also ESD Protection Map, Figure 18)
Figure 10. AD8117 Receiver (see also ESD Protection Map, Figure 18)
2500Ω
5075Ω
5075Ω
IPn
INn
VDD
1.3pF
25kΩ
1kΩ
0.3pF
RESET
1.3pF
2500Ω
DGND
Figure 11. AD8118 Receiver (see also ESD Protection Map, Figure 18)
Figure 15. Reset Input (see also ESD Protection Map, Figure 18)
Rev. A | Page 15 of 36
AD8117/AD8118
VPOS
VDD
CLK, RESET,
SER/PAR, WE,
UPDATE,
DATA IN,
DATA OUT,
A[4:0], D[5:0]
IPn, INn,
OPn, ONn,
VOCM
CLK, SER/PAR, WE,
UPDATE, DATA IN,
A[4:0], D[5:0]
1kΩ
DGND
VNEG
DGND
Figure 16. Logic Input (see also ESD Protection Map, Figure 18)
Figure 18. ESD Protection Map
VDD
DATA OUT
DGND
Figure 17. Logic Output (see also ESD Protection Map, Figure 18)
Rev. A | Page 16 of 36
AD8117/AD8118
TYPICAL PERFORMANCE CHARACTERISTICS
VS = 2.5 V at TA = 25°C, RL, diff = 200 Ω, VOCM = 0 V, differential I/O mode, unless otherwise noted.
10
8
400
350
300
250
200
150
100
50
AD8118
6
4
2
AD8117
0
–2
–4
–6
–8
–10
0
540
560
580
600
620
640
660
680
700
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 19. AD8117, AD8118 Small Signal Frequency Response, 200 mV p-p
Figure 22. AD8117 −3 dB Bandwidth Histogram,
One Device, All 1024 Channels
10
0
–1
–2
–3
8
AD8118
6
4
2
AD8117
0
–2
–4
–6
–8
–10
1
10
100
1000
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
FREQUENCY (MHz)
NUMBER OF ENABLED CHANNELS
Figure 20. AD8117, AD8118 Large Signal Frequency Response, 2 V p-p
Figure 23. AD8117 Bandwidth Error vs. Enabled Channels
10
8
0
DIFFERENTIAL OUT
–10
6
10pF
5pF
–20
–30
–40
–50
–60
–70
4
2
2pF
0
–2
0pF
–4
–6
–8
–10
0
10
100
1000
300k
1M
10M
100M
1G 2G
FREQUENCY (MHz)
FREQUENCY (Hz)
Figure 21. AD8117 Small Signal Frequency Response with Capacitive Loads,
200 mV p-p
Figure 24. AD8117, AD8118 Common-Mode Rejection
Rev. A | Page 17 of 36
AD8117/AD8118
–15
0
–20
DIFFERENTIAL IN/OUT
DIFFERENTIAL OUT
–25
V
AGGRESSOR
NEG
–35
V
AGGRESSOR
POS
–45
–55
–65
–75
–85
–95
–40
V
AGGRESSOR
OCM
–60
–80
–100
0.1
1
10
FREQUENCY (MHz)
100
1000
300k
1M
10M
FREQUENCY (Hz)
100M
1G
Figure 25. AD8117 Power Supply Rejection
Figure 28. AD8117 Crosstalk, One Adjacent Channel
10
5
0
–20
SINGLE-ENDED OUT
DIFFERENTIAL IN/OUT
0
–5
V
AGGRESSOR
OCM
–10
–15
–20
–25
–30
–35
–40
–45
–50
–40
V
AGGRESSOR
NEG
–60
V
AGGRESSOR
POS
10
–80
–100
300k
0.1
1
100
1000
1M
10M
100M
1G
FREQUENCY (MHz)
FREQUENCY (Hz)
Figure 29. AD8118 Crosstalk, One Adjacent Channel
Figure 26. AD8117 Power Supply Rejection, Single-Ended
0
–20
180
SINGLE-ENDED IN/OUT
DIFFERENTIAL OUT
160
140
120
100
80
–40
AD8118
AD8117
–60
60
40
–80
20
–100
300k
0
1k
1M
10M
100M
1G
10k
100k
FREQUENCY (Hz)
1M
FREQUENCY (Hz)
Figure 30. AD8117 Crosstalk, One Adjacent Channel, Single-Ended
Figure 27. AD8117, AD8118 Noise Spectral Density, RTO
Rev. A | Page 18 of 36
AD8117/AD8118
0
–20
0
–20
SINGLE-ENDED IN/OUT
SINGLE-ENDED IN/OUT
–40
–40
–60
–60
–80
–80
–100
–100
300k
1M
10M
100M
1G
300k
1M
10M
FREQUENCY (Hz)
100M
1G
FREQUENCY (Hz)
Figure 31. AD8118 Crosstalk, One Adjacent Channel, Single-Ended
Figure 34. AD8117 Crosstalk, All Hostile, Single-Ended
0
0
–20
SINGLE-ENDED IN/OUT
DIFFERENTIAL IN/OUT
–20
–40
–40
–60
–60
–80
–80
–100
300k
–100
300k
1M
10M
100M
1G
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 35. AD8118 Crosstalk, All Hostile, Single-Ended
Figure 32. AD8117 Crosstalk, All Hostile
0
–20
0
DIFFERENTIAL IN/OUT
DIFFERENTIAL IN/OUT
–20
–40
–40
–60
–60
–80
–80
–100
–100
300k
1M
10M
100M
1G 2G
300k
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 33. AD8118 Crosstalk, All Hostile
Figure 36. AD8117 Crosstalk, Off Isolation
Rev. A | Page 19 of 36
AD8117/AD8118
0
30k
25k
20k
15k
10k
5k
SINGLE-ENDED IN/OUT
DIFFERENTIAL OUT
–20
–40
–60
–80
–100
0
300k
1M
10M
100M
1G 2G
100k
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 37. AD8117 Crosstalk, Off Isolation, Single-Ended
Figure 40. AD8117, AD8118 Output Impedance, Disabled
6k
1000
DIFFERENTIAL IN
AD8118
AD8117
5k
4k
3k
2k
1k
0
100
10
1
0.1
300k
1M
10M
100M
1G
100k
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 38. AD8117, AD8118 Input Impedance
Figure 41. AD8117, AD8118 Output Impedance, Enabled
4500
4000
3500
3000
2500
2000
1500
1000
500
0.4
SINGLE-ENDED IN
AD8118
AD8117
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
300k
1M
10M
100M
1G
FREQUENCY (Hz)
TIME (ns)
Figure 39. AD8117, AD8118 Input Impedance, Single-Ended
Figure 42. AD8117 Small Signal Pulse Response, 200 mV p-p
Rev. A | Page 20 of 36
AD8117/AD8118
1.5
1.0
3
0.20
0.15
0.10
0.05
0
UPDATE
2
N-CHANNEL
P-CHANNEL
0.5
1
0
0
–0.05
–0.10
–0.15
–0.20
–0.5
–1.0
–1.5
–1
–2
–3
V
OUT
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
–40
–20
0
20
40
60
80
100
120
TIME (ns)
TIME (ns)
Figure 46. AD8117 Switching Time
Figure 43. AD8117 Small Signal Pulse Response, Single-Ended, 200 mV p-p
2
1
5000
4000
3000
2000
1000
0
2.0
1.5
1.0
0
0.5
V
OUT
–1
–2
–3
–4
0
–0.5
–1.0
–1.5
–2.0
SLEW RATE
1
–1000
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
0
2
3
4
5
TIME (ns)
TIME (ns)
Figure 47. AD8117 Large Signal Rising Edge and Slew Rate
Figure 44. AD8117 Large Signal Pulse Response, 2 V p-p
2
1
3500
1.0
V
0.8
0.6
OUT
2500
1500
500
0.4
N-CHANNEL
P-CHANNEL
0
0.2
–1
–2
–3
–4
0
SLEW RATE
–0.2
–0.4
–0.6
–0.8
–1.0
–500
–1500
–2500
0
1
2
3
4
5
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
1ns/DIV
TIME (ns)
Figure 48. AD8117 Large Signal Falling Edge and Slew Rate
Figure 45. AD8117 Large Signal Pulse Response, Single-Ended, 2 V p-p
Rev. A | Page 21 of 36
AD8117/AD8118
0.014
0.012
0.010
0.008
0.006
0.004
0.002
0
5
4
3
2
1
0
–0.002
–0.004
–700
–500
–300
–100
100
300
500
700
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90 100
TEMPERATURE (ºC)
V
, DIFF (mV)
IN
Figure 49. AD8117 VOS vs. Temperature in Broadcast Mode
Figure 52. AD8117 Phase vs. DC Voltage, Carrier Frequency = 3.58 MHz,
Subcarrier Amplitude = 600 mV p-p, Differential
50
2.0
10pF
1.5
40
30
5pF
1.0
2pF
0.5
20
0pF
0
10
–0.5
–1.0
–1.5
–2.0
0
–10
–20
–0.10 –0.08 –0.06 –0.04 –0.02
0
0.02 0.04 0.06 0.08 0.10
0
2
4
6
8
10
12
14
16
18
TIME (µs)
TIME (ns)
Figure 50. AD8117 Switching Transient (Glitch)
Figure 53. AD8117 Large Signal Pulse Response with Capacitive Loads
0.020
0.015
0.010
0.005
0
0.4
10pF
0.3
5pF
0.2
2pF
0.1
0pF
0
–0.1
–0.2
–0.3
–0.4
–0.005
–0.010
–700
–500
–300
–100
100
300
500
700
0
2
4
6
8
10
12
14
16
18
V
, DIFF (mV)
IN
TIME (ns)
Figure 51. AD8117 Gain vs. DC Voltage, Carrier Frequency = 3.58 MHz,
Subcarrier Amplitude = 600 mV p-p, Differential
Figure 54. AD8117 Small Signal Pulse Response with Capacitive Loads
Rev. A | Page 22 of 36
AD8117/AD8118
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0
600
500
400
300
200
100
900
I
AND I
(BROADCAST)
NEG
POS
UPDATE
800
I
(SERIAL MODE)
DD
700
600
500
400
I
(PARALLEL MODE)
DD
V
OUT
I
AND I
NEG
POS
(ALL OUTPUTS DISABLED)
–0.2
–50 –30 –10
–0.4
110 130 150
–35 –25 –15 –5
5
15 25 35 45 55 65 75 85 95
10
30
50
70
90
TEMPERATURE (°C)
TIME (ns)
Figure 58. AD8117, AD8118 Quiescent Supply Currents vs. Temperature
Figure 55. AD8117 Enable Time
500
450
400
350
300
250
200
950
900
850
800
750
700
650
600
550
500
450
1.4
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0
I
, I
POS NEG
UPDATE
1.2
1.0
0.8
0.6
0.4
0.2
0
V
OUT
I
I
SERIAL
DD
PARALLEL
DD
–0.2
–50 –30 –10
–0.4
110 130 150
4
8
12
16
20
24
28
32
10
30
50
70
90
CHANNELS
TIME (ns)
Figure 59. AD8117, AD8118 Quiescent Supply Currents vs. Enabled Outputs
Figure 56. AD8117 Disable Time
65
60
55
50
45
40
35
30
25
20
15
10
5
3.25
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
0
(V
– V )/V
IN OUT
OUT
–0.01
V
IN
–0.02
–0.03
–0.04
–0.05
V
OUT
0
–5
–0.25
0
1
2
3
4
5
6
7
–50
–25
0
25
50
75
100
TIME (ns)
TEMPERATURE (ºC)
Figure 60. AD8117 Settling Time
Figure 57. AD8117 DC Gain vs. Temperature
Rev. A | Page 23 of 36
AD8117/AD8118
5
2.0
1.5
4
V
OUTP
3
1.0
2
0.5
1
V
INP
0
0
–1
–2
–3
–4
–5
–0.5
–1.0
–1.5
–2.0
V
OUTN
V
INN
0
1
2
3
4
5
6
7
0
100
200
300
400
500
600
700
TIME (ns)
TIME (ns)
Figure 61. AD8117 Settling Time (Zoom)
Figure 63. AD8118 Overdrive Recovery, Single-Ended
2.5
2.0
–30
–40
–50
–60
–70
–80
–90
–100
V
= 2V p-p, DIFF
OUT
V
INP
V
OUTP
1.5
1.0
THIRD
HARMONIC
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
SECOND
HARMONIC
V
OUTN
V
INN
0
100
200
300
400
500
600
700
0.1
1
10
FREQUENCY (MHz)
100
1000
TIME (ns)
Figure 62. AD8117 Overdrive Recovery, Single-Ended
Figure 64. AD8117 Harmonic Distortion
Rev. A | Page 24 of 36
AD8117/AD8118
THEORY OF OPERATION
The AD8117/AD8118 are fully differential crosspoint arrays
with 32 outputs, each of which can be connected to any one of
32 inputs. Organized by output row, 32 switchable input trans-
conductance stages are connected to each output buffer to form
32-to-1 multiplexers. There are 32 of these multiplexers, each
with its inputs wired in parallel, for a total array of 1024
transconductance stages forming a multicast-capable
crosspoint switch.
The outputs of the AD8117/AD8118 can be disabled to
minimize on-chip power dissipation. When disabled, there is a
feedback network of 25 kꢀ between the differential outputs.
This high impedance allows multiple ICs to be bussed together
without additional buffering. Care must be taken to reduce
output capacitance, which results in more overshoot and
frequency domain peaking. A series of internal amplifiers drive
internal nodes such that a wideband high impedance is
presented at the disabled output, even while the output bus is
under large signal swings. When the outputs are disabled and
driven externally, the voltage applied to them should not exceed
the valid output swing range for the AD8117/AD8118 in order
to keep these internal amplifiers in their linear range of
operation. Applying excess differential voltages to the disabled
outputs can cause damage to the AD8117/AD8118 and should
be avoided (see the Absolute Maximum Ratings section for
guidelines).
Decoding logic for each output selects one (or none) of the
transconductance stages to drive the output stage. The enabled
transconductance stage drives the output stage, and feedback
forms a closed-loop amplifier with a differential gain of one (the
difference between the output voltages is equal to the difference
between the input voltages). A second feedback loop controls
the common-mode output level, forcing the average of the
differential output voltages to match the voltage on the VOCM
reference pin. Although each output has an independent
common-mode control loop, the VOCM reference is common
for the entire chip, and as such needs to be driven with a low
impedance to avoid crosstalk.
The connection of the AD8117/AD8118 is controlled by a
flexible TTL-compatible logic interface. Either parallel or serial
loading into a first rank of latches preprograms each output. A
global update signal moves the programming data into the
second rank of latches, simultaneously updating all outputs. In
serial mode, a serial-out pin allows devices to be daisy-chained
together for single-pin programming of multiple ICs. A power-
on reset pin is available to avoid bus conflicts by disabling all
outputs. This power-on reset clears the second rank of latches,
but does not clear the first rank of latches. In parallel mode, to
quickly clear the first rank, a broadcast parallel programming
feature is available. In serial mode, preprogramming individual
inputs is not possible and the entire shift register needs to
be flushed.
Each differential input to the AD8117/AD8118 is buffered by a
receiver. The purpose of this receiver is to provide an extended
input common-mode range, and to remove this common mode
from the signal chain. Like the output multiplexers, the input
receiver has both a differential loop and a common-mode
control loop. A mask-programmable feedback network sets the
closed-loop differential gain. For the AD8117, this differential
gain is one, and for the AD8118, this differential gain is two.
The receiver has an input stage that does not respond to the
common mode of the signal. This architecture, along with the
attenuating feedback network, allows the user to apply input
voltages that extend from rail-to-rail. Excess differential loop
gain bandwidth product reduces the effect of the closed-loop
gain on the bandwidth of the device.
The AD8117/AD8118 can operate on a single +5 V supply,
powering both the signal path (with the VPOS/VNEG supply
pins), and the control logic interface (with the VDD/DGND
supply pins). However, to easily interface to ground-referenced
video signals, split supply operation is possible with 2.5 V
supplies. In this case, a flexible logic interface allows the control
logic supplies (VDD/DGND) to be run off +2 V/0 V to
+5 V/0 V while the core remains on split supplies. Additional
flexibility in the analog output common-mode level facilitates
unequal split supplies. If +3 V/–2 V supplies to +2 V/–3 V
supplies are desired, the VOCM pin can still be set to 0 V for
ground-referenced video signals.
The output stage of the AD8117/AD8118 is designed for low
differential gain and phase error when driving composite video
signals. It also provides slew current for fast pulse response
when driving component video signals. Unlike many multi-
plexer designs, these requirements are balanced such that large
signal bandwidth is very similar to small signal bandwidth. The
design load is 150 ꢀ, but provisions are made to drive loads
as low as 75 ꢀ so long as on-chip power dissipation limits are
not exceeded.
Rev. A | Page 25 of 36
AD8117/AD8118
APPLICATIONS
the programming sequence is 192 bits times the number of
devices in the chain.
PROGRAMMING
The AD8117/AD8118 have two options for changing the
programming of the crosspoint matrix. In the first option, a
serial word of 192 bits can be provided that updates the entire
matrix each time. The second option allows for changing the
programming of a single output via a parallel interface. The
serial option requires fewer signals, but more time (clock cycles)
for changing the programming, while the parallel programming
technique requires more signals, but can change a single output
at a time and requires fewer clock cycles to complete
programming.
Parallel Programming Description
When using the parallel programming mode, it is not necessary
to reprogram the entire device when making changes to the matrix.
In fact, parallel programming allows the modification of a
WE UPDATE
single output at a time. Because this takes only one
/
cycle, significant time savings can be realized by using parallel
programming.
One important consideration in using parallel programming is
RESET
that the
signal does not reset all registers in the AD8117/
RESET
Serial Programming Description
AD8118. When taken low, the
signal only sets each
CLK
The serial programming mode uses the
UPDATE SER
, DATA IN,
output to the disabled state. This is helpful during power-up to
ensure that two parallel outputs are not active at the same time.
, and
/PAR device pins. The first step is to assert a
/PAR in order to enable the serial programming
SER
low on
After initial power-up, the internal registers in the device
WE
mode. The parallel clock
entire serial programming operation.
should be held high during the
RESET
generally have random data, even though the
signal has
been asserted. If parallel programming is used to program one
output, then that output will be properly programmed, but the
rest of the device will have a random program state depending
on the internal register content at power-up. Therefore, when
using parallel programming, it is essential that all outputs be
programmed to a desired state after power-up. This ensures that
the programming matrix is always in a known state. From then
on, parallel programming can be used to modify a single output
or more at a time.
UPDATE
The
shifted into the serial port of the device. Although the data still
UPDATE
signal should be high during the time that data is
shifts in when
is low, the transparent, asynchronous
latches allow the shifting data to reach the matrix. This causes
the matrix to try to update to every intermediate state as
defined by the shifting data.
CLK
The data at DATA IN is clocked in at every falling edge of
.
A total of 192 bits must be shifted in to complete the program-
ming. For each of the 32 outputs, there are five bits (D0 to D4)
that determine the source of its input followed by one bit (D5)
that determines the enabled state of the output. If D5 is low
(output disabled), the five associated bits (D0 to D4) do not
matter, because no input is switched to that output.
UPDATE
In similar fashion, if
is taken low after initial power-
up, the random power-up data in the shift register will be
programmed into the matrix. Therefore, in order to prevent the
crosspoint from being programmed into an unknown state, do
UPDATE
not apply a low logic level to
after power is initially
applied. Programming the full shift register one time to a
desired state, by either serial or parallel programming after
initial power-up, eliminates the possibility of programming the
matrix to an unknown state.
The most significant output address data is shifted in first, with
the enable bit (D5) shifted in first, followed by the input address
(D4 to D0) entered sequentially with D4 first and D0 last. Each
remaining output is programmed sequentially, until the least
significant output address data is shifted in. At this point,
To change the programming of an output via parallel program-
SER
UPDATE
CLK
ming,
programming clock,
/PAR and
should be taken high. The serial
, should be left high during parallel
UPDATE
can be taken low, which causes the programming of
the device according to the data that was just shifted in. The
UPDATE UPDATE
WE
programming. The parallel clock,
, should start in the high
latches are asynchronous and when
they are transparent.
is low,
state. The 5-bit address of the output to be programmed should
be put on A0 to A4. The first five data bits (D0 to D4) should
contain the information that identifies the input that is pro-
grammed to the output that is addressed. The sixth data bit
(D5) determines the enabled state of the output. If D5 is low
(output disabled), then the data on D0 to D4 does not matter.
If more than one AD8117/AD8118 device is to be serially
programmed in a system, the DATA OUT signal from one
device can be connected to the DATA IN of the next device to
CLK UPDATE SER
form a serial chain. All of the
,
, and /PAR
pins should be connected in parallel and operated as described
previously. The serial data is input to the DATA IN pin of the
first device of the chain, and it ripples through to the last.
Therefore, the data for the last device in the chain should come
at the beginning of the programming sequence. The length of
After the desired address and data signals have been established,
they can be latched into the shift register by a high to low
WE
transition of the
signal. The matrix is not programmed,
UPDATE
however, until the
signal is taken low. It is thus possible
to latch in new data for several or all of the outputs first via
Rev. A | Page 26 of 36
AD8117/AD8118
WE
UPDATE
The receivers respond only to the difference in input voltages,
and will restore a common-mode voltage suitable for the
internal signal path. Noise or crosstalk that is present in both
inputs is rejected by the input stage, as specified by its common-
mode rejection ratio (CMRR). Differential operation offers a
great noise benefit for signals that are propagated over distance
in a noisy environment.
successive negative transitions of
while
is held
UPDATE
high, and then have all the new data take effect when
goes low. This technique should be used when programming
the device for the first time after power-up when using parallel
programming.
Reset
When powering up the AD8117/AD8118, it is usually desirable
R
F
RESET
to have the outputs come up in the disabled state. The
pin, when taken low, causes all outputs to be in the disabled state.
UPDATE
AD8117/AD8118. This is important when operating in the
parallel programming mode. Refer to the Parallel Programming
Description section for information about programming internal
registers after power-up. Serial programming programs the entire
matrix each time; therefore, no special considerations apply.
R
R
G
G
IN+
VOCM
IN–
OUT–
However, the
signal does not reset all registers in the
RCVR
TO SWITCH MATRIX
OUT+
R
F
Figure 65. Input Receiver Equivalent Circuit
The circuit configuration used by the differential input receivers
is similar to that of several Analog Devices, Inc. general-
purpose differential amplifiers, such as the AD8131. It is a
voltage feedback amplifier with internal gain setting resistors.
The arrangement of feedback makes the differential input
impedance appear to be 5 kꢀ across the inputs.
Since the data in the shift register is random after power-up, it
should not be used to program the matrix, or the matrix can
enter unknown states. To prevent this, do not apply a logic low
UPDATE
signal to
initially after power-up. The shift register
UPDATE
should first be loaded with the desired data, and then
can be taken low to program the device.
RIN,dm = 2 × RG = 5 kꢀ
RESET
The
pin has a 20 kꢀ pull-up resistor to VDD that can be
This impedance creates a small differential termination error if
the user does not account for the 5 kꢀ parallel element, although
this error is less than 1% in most cases. Additionally, the source
impedance driving the AD8117/AD8118 appears in parallel
with the internal gain-setting resistors, such that there may be a
gain error for some values of source resistance. The AD8117/
AD8118 are adjusted such that its gains are correct when driven
by a back-terminated 75 ꢀ source impedance at each input
phase (37.5 ꢀ effective impedance to ground at each input pin,
or 75 ꢀ differential source impedance across pairs of input
pins). If a different source impedance is presented, the differential
gain of the AD8117/AD8118 can be calculated by
used to create a simple power-up reset circuit. A capacitor from
RESET RESET
of the device stabilizes. The low condition causes all the outputs
to be disabled. The capacitor then charges through the pull-up
resistor to the high state, thus allowing full programming
capability of the device.
to ground holds
low for some time while the rest
Broadcast
The AD8117/AD8118 logic interface has a broadcast mode, in
which all first rank latches can be simultaneously parallel-
programmed to the same data in one write cycle. This is especially
useful in clearing random first rank data after power-up. To
access the broadcast mode, the part is parallel programmed
VOUT,dm
RF
Gdm
=
=
WE
UPDATE
/PAR pin is held low, as if
using the
The only difference is that the
serial programming. By holding
, A0 to A4, D0 to D5, and
device pins.
VIN,dm
RG + RS
SER
CLK
where:
RG = 2.5 kꢀ.
high, no serial clocking
WE
occurs, and instead,
can be used to clock all first rank
RS is the user single-ended source resistance (such as 37.5 ꢀ for
a back-terminated 75 ꢀ source).
RF = 2.538 kꢀ for the AD8117 and 5.075 kꢀ for the AD8118.
latches in the chip at once.
OPERATING MODES
The AD8117/AD8118 has fully differential inputs and outputs.
The inputs and outputs can also be operated in a single-ended
fashion. This presents several options for circuit configurations
that require different gains and treatment of terminations, if
they are used.
In the case of the AD8117,
2.538 kꢀ
Gdm
=
2.5 kꢀ+ RS
In the case of the AD8118,
5.075 kꢀ
Differential Input
Gdm
=
Each differential input to the AD8117/AD8118 is applied to a
differential receiver. These receivers allow the user to drive the
inputs with a differential signal with an uncertain common-
mode voltage, such as from a remote source over twisted pair.
2.5 kꢀ+ RS
When operating with a differential input, care must be taken to
keep the common mode, or average, of the input voltages within
Rev. A | Page 27 of 36
AD8117/AD8118
RG + RS
the linear operating range of the AD8117/AD8118 receiver. This
common-mode range can extend rail-to-rail, provided the
differential signal swing is small enough to avoid forward
biasing the ESD diodes (it is safest to keep the common mode
plus differential signal excursions within the supply voltages of
the part). See the Specifications section for guaranteed input
range.
RIN
=
RF
1 −
2 × (RG + RS + RF )
where:
RG = 2.5 kꢀ.
RS is the user single-ended source resistance (such as 37.5 ꢀ for
a back-terminated 75 ꢀ source).
The differential output of the AD8117/AD8118 receiver is
linear for a peak of 1.4 V of output voltage difference (1.4 V
peak input difference for the AD8117, and 0.7 V peak input
difference for the AD8118). Taking the output differentially,
using the two output phases, this allows 2.8 V p-p of linear
output signal swing. Beyond this level, the signal path can
saturate and will limit the signal swing. This is not a desired
operation, as the supply current increases and the signal path
will be slow to recover from clipping. The absolute maximum
allowed differential input signal is limited by the long-term
reliability of the input stage. The limits in the Absolute
Maximum Ratings section should be observed in order to avoid
degrading device performance permanently.
RF = 2.538 kꢀ for the AD8117 and 5.075 kꢀ for the AD8118.
In most cases, a single-ended input signal is referred to
midsupply, typically ground. In this case, the undriven
differential input can be connected to ground. For best dynamic
performance and lowest offset voltage, this unused input should
be terminated with an impedance matching the driven input,
instead of being directly shorted to ground. Due to the
differential feedback of the receiver, there is high frequency
signal current in the undriven input and it should
be treated as a signal line in the board design.
AD8117
IPn
INn
OPn
ONn
RCVR
AD8117
IPn
INn
OPn
ONn
75Ω
(OR 37.5Ω)
75Ω
RCVR
50Ω
50Ω
Figure 67. Example of Input Driven Single-Ended
AC Coupling of Inputs
Figure 66. Example of Input Driven Differentially
It is possible to ac couple the inputs of the AD8117/AD8118
receiver. This is simplified because the bias current does not
need to be supplied externally. A capacitor in series with the
inputs to the AD8117/AD8118 creates a high-pass filter with
the input impedance of the device. This capacitor needs to be
sized such that the corner frequency is low enough for
frequencies of interest.
Single-Ended Input
The AD8117/AD8118 input receivers can be driven single-
endedly (unbalanced). From the standpoint of the receiver,
there is very little difference between signals applied positive
and negative in two phases to the input pair, vs. a signal applied
to one input only with the other input held at a constant
potential. One small difference is that the common mode
between the input pins is changing if only one input is moving,
and there is a very small common-mode to differential
conversion gain in the receiver that adds an additional gain
error to the output (see the common-mode rejection ratio for
the input stage in the Specifications section). For low
Differential Output
Benefits of Differential Operation
The AD8117/AD8118 have a fully differential switch core, with
differential outputs. The two output voltages move in opposite
polarity, with a differential feedback loop maintaining a fixed
output stage differential gain of +1 (the different overall signal
path gains between the AD8117 and AD8118 are set in the
input stage for best signal-to-noise ratio). This differential
output stage provides a benefit of crosstalk-canceling due to
parasitic coupling from one output to another, being equal and
out of phase. Additionally, if the output of the device is utilized
in a differential design, noise, crosstalk, and offset voltages
generated on-chip that are coupled equally into both outputs are
cancelled by the common-mode rejection ratio of the next
device in the signal chain. By utilizing the AD8117/AD8118
outputs in a differential application, the best possible noise and
offset specifications can be realized.
frequencies, this gain error is negligible. The common-mode
rejection ratio degrades with increasing frequency.
When operating the AD8117/AD8118 receivers single-endedly,
the observed input resistance at each input pin is lower than in
the differential input case, due to a fraction of the receiver
internal output voltage appearing as a common-mode signal on
its input terminals, bootstrapping the voltage on the input
resistance. This single-ended input resistance can be calculated
by the equation
Rev. A | Page 28 of 36
AD8117/AD8118
and termination of the output trace or cable. This is known as
back-termination, and helps shorten settling time by terminating
reflected signals when driving a load that is not accurately
terminated at the load end. A side effect of back-termination is
an attenuation of the output signal by a factor of two. In this
case, a gain of two is usually necessary somewhere in the signal
path to restore the signal.
Differential Gain
The specified signal path gain of the AD8117/AD8118 refers to
its differential gain. For the AD8117, the gain of +1 means that
the difference in voltage between the two output terminals is
equal to the difference applied between the two input terminals.
For the AD8118, the ratio of output difference voltage to
applied input difference voltage is +2.
The common mode, or average voltage of the pair of output
signals is set by the voltage on the VOCM pin. This voltage is
typically set to midsupply (often ground), but can be moved
approximately 0.5 V in order to accommodate cases where the
desired output common-mode voltage may not be midsupply
(as in the case of unequal split supplies). Adjusting VOCM can
limit differential swing internally below the specifications on
the data sheet.
AD8117/
AD8118
50Ω
50Ω
OPn
ONn
+
100Ω
–
Figure 68. Example of Back-Terminated Differential Load
Regardless of the differential gain of the device, the common-
mode gain for the AD8117 and AD8118 is +1 to the output.
This means that the common mode of the output voltages
directly follows the reference voltage applied to the VOCM
input.
Single-Ended Output
Usage
The AD8117/AD8118 output pairs can be used single-endedly,
taking only one output and not using the second. This is often
desired to reduce the routing complexity in the design, or
because a single-ended load is being driven directly. This mode
of operation produces good results, but has some shortcomings
when compared to taking the output differentially. When
observing the single-ended output, noise that is common to
both outputs appears in the output signal. This includes thermal
noise in the chip biasing, as well as crosstalk that is coupled into
the signal path. This component noise and crosstalk is equal in
both outputs, and as such can be ignored by a differential
receiver with a high common-mode rejection ratio. However,
when taking the output single-ended, this noise is present with
respect to the ground (or VOCM) reference and is not rejected.
The VOCM reference is a high speed signal input, common to
all output stages on the device. It requires only small amounts of
bias current, but noise appearing on this pin is buffered to the
outputs of all the output stages. As such, the VOCM node should
be connected to a low noise, low impedance voltage to avoid
being a source of noise, offset, and crosstalk in the signal path.
Termination
The AD8117/AD8118 are designed to drive 150 ꢀ on each
output (or an effective 300 ꢀ differential), but the output stage
is capable of supplying the current to drive 100 ꢀ loads (200 ꢀ
differential) over the specified operating temperature range. If
care is taken to observe the maximum power derating curves,
the output stage can drive 75 ꢀ loads with slightly reduced slew
rate and bandwidth (an effective 150 ꢀ differential load).
When observing the output single-ended, the distribution of
offset voltages appears greater. In the differential case, the
difference between the outputs when the difference between the
inputs is zero is a small differential offset. This offset is created
from mismatches in components of the signal path, which must
be corrected by the finite differential loop gain of the device. In
the single-ended case, this differential offset is still observed,
but an additional offset component is also relevant. This
additional component is the common-mode offset, which is a
difference between the average of the outputs and the VOCM
reference. This offset is created by mismatches that affect the
signal path in a common-mode manner, and is corrected by the
finite common-mode loop gain of the device. A differential
receiver would reject this common-mode offset voltage, but in
the single-ended case, this offset is observed with respect to the
signal ground. The single-ended output sums half the
Termination at the load end is recommended for best signal
integrity. This load termination is often a resistor to a ground
reference on each individual output. By terminating to the
same voltage level that drives the VOCM reference, the power
dissipation due to dc termination current is reduced. In
differential signal paths, it is often desirable to terminate
differentially, with a single resistor across the differential
outputs at the load end. This is acceptable for the AD8117/
AD8118, but when the device outputs are placed in a disabled
state, a small amount of dc bias current is required if the output
is to present as a high impedance over an excursion of output
bus voltages. If the AD8117/AD8118 disabled outputs are
floated (or simply tied together by a resistor), internal nodes
saturate and an increase in disabled output current may
be observed.
differential offset voltage and all of the common-mode offset
voltage for a net increase in observed offset.
For best pulse response, it is often desirable to place a series
resistor in each output to match the characteristic impedance
Rev. A | Page 29 of 36
AD8117/AD8118
output draws current from the positive supply, the other output
draws current from the negative supply. When the phase
alternates, the first output draws current from the negative
supply and the second from the positive supply. The effect is
that a more constant current is drawn from each supply, such
that the crosstalk-inducing supply fluctuation is minimized.
Single-Ended Gain
The AD8117/AD8118 operate as a closed-loop differential
amplifier. The primary control loop forces the difference
between the output terminals to be a ratio of the difference
between the input terminals. One output increases in voltage,
while the other decreases an equal amount to make the total
difference correct. The average of these output voltages is forced
to be equal to the voltage on the VOCM terminal by a second
control loop. If only one output terminal is observed with
respect to the VOCM terminal, only half of the difference
voltage is observed. This implies that when using only one
output of the device, half of the differential gain is observed. An
AD8117 taken with single-ended output appears to have a gain
of +0.5. An AD8118 has a single-ended gain of +1.
A third benefit of driving balanced loads can be seen if one
considers that the output pulse response changes as load
changes. The differential signal control loop in the
AD8117/AD8118 forces the difference of the outputs to be a
fixed ratio to the difference of the inputs. If the two output
responses are different due to loading, this creates a difference
that the control loop sees as signal response error, and it will
attempt to correct this error. This distorts the output signal
from the ideal response if the two outputs were balanced.
This factor of one half in the gain increases the noise of the
device when referred to the input, contributing to higher noise
specifications for single-ended output designs.
AD8117/
AD8118
75Ω
OPn
ONn
Termination
75Ω
When operating the AD8117/AD8118 with a single-ended
output, the preferred output termination scheme is a resistor at
the load end to the VOCM voltage. A back-termination can be
used, at an additional cost of one half the signal gain.
150Ω
Figure 69. Example of Back-Terminated Single-Ended Load
In single-ended output operation, the complementary phase of
the output is not used, and may or may not be terminated
locally. Although the unused output can be floated to reduce
power dissipation, there are several reasons for terminating the
unused output with a load resistance matched to the load on the
signal output.
Decoupling
The signal path of the AD8117/AD8118 is based on high open-
loop gain amplifiers with negative feedback. Dominant-pole
compensation is used on-chip to stabilize these amplifiers over
the range of expected applied swing and load conditions. To
guarantee this designed stability, proper supply decoupling is
necessary with respect to both the differential control loops and
the common-mode control loops of the signal path. Signal-
generated currents must return to their sources through low
impedance paths at all frequencies in which there is still loop
gain (up to 700 MHz at a minimum). A wideband parallel
capacitor arrangement is necessary to properly decouple the
AD8117/AD8118.
One component of crosstalk is magnetic, coupling by mutual
inductance between output package traces and bond wires that
carry load current. In a differential design, there is coupling
from one pair of outputs to other adjacent pairs of outputs. The
differential nature of the output signal simultaneously drives the
coupling field in one direction for one phase of the output, and
in an opposite direction for the other phase of the output. These
magnetic fields do not couple exactly equal into adjacent output
pairs due to different proximities, but they do destructively
cancel the crosstalk to some extent. If the load current in each
output is equal, this cancellation is greater, and less adjacent
crosstalk is observed (regardless if the second output is actually
being used).
The signal path compensation capacitors in the AD8117/
AD8118 are connected to the VNEG supply. At high frequencies,
this limits the power supply rejection ratio (PSRR) from the
VNEG supply to a lower value than that from the VPOS supply.
If given a choice, an application board should be designed such
that the VNEG power is supplied from a low inductance plane,
subject to a least amount of noise.
A second benefit of balancing the output loads in a differential
pair is to reduce fluctuations in current requirements from the
power supply. In single-ended loads, the load currents alternate
from the positive supply to the negative supply. This creates a
parasitic signal voltage in the supply pins due to the finite
resistance and inductance of the supplies. This supply fluctuation
appears as crosstalk in all outputs, attenuated by the power
supply rejection ratio (PSRR) of the device. At low frequencies,
this is a negligible component of crosstalk, but PSRR falls off as
frequency increases. With differential, balanced loads, as one
The VOCM should be considered a reference pin and not a
power supply. It is an input to the high speed, high gain
common-mode control loop of all receivers and output drivers.
In the single-ended output sense, there is no rejection from
noise on the VOCM net to the output. For this reason, care
must be taken to produce a low noise VOCM source over the
entire range of frequencies of interest. This is not only
important to single-ended operation, but to differential
Rev. A | Page 30 of 36
AD8117/AD8118
V
POS
operation, as there is a common-mode to differential gain
conversion that becomes greater at higher frequencies.
I
OUTPUT, QUIESCENT
During operation of the AD8117/AD8118, transient currents
flow into the VOCM net from the amplifier control loops.
Although the magnitude of these currents are small (10 μA to
20 μA per output), they can contribute to crosstalk if they flow
through significant impedances. Driving VOCM with a low
impedance, low noise source is desirable.
QNPN
QPNP
V
OUTPUT
I
OUTPUT
I
OUTPUT, QUIESCENT
V
NEG
Power Dissipation
Figure 71. Simplified Output Stage
Calculation of Power Dissipation
8
Example
T
= 150°C
J
For the AD8117/AD8118, in an ambient temperature of 85°C,
with all 32 outputs driving 1 V rms into 100 ꢀ loads and power
supplies at 2.5 V, follow these steps:
7
6
5
4
1. Calculate power dissipation of AD8117/AD8118 using data
sheet quiescent currents. Disregard VDD current, as it is
insignificant.
PD,QUIESCENT
PD,QUIESCENT
=
=
VPOS × IVPOS
+
VNEG × IVNEG
(
2.5 V× 500 mA
)
+
(
2.5 V× 500 mA = 2.5 W
)
2. Calculate power dissipation from loads. For a differential
output and ground-referenced load, the output power is
symmetrical in each output phase.
15
25
35
45
55
65
75
85
AMBIENT TEMPERATURE (°C)
Figure 70. Maximum Die Power Dissipation vs. Ambient Temperature
The curve in Figure 70 was calculated from
TJUNCTION, MAX − TAMBIENT
PD,OUTPUT
PD,OUTPUT
=
=
VPOS − VOUTPUT,RMS
× IOUTPUT,RMS
= 15 mW
(2.5 V− 1V
)
×
(
1V/100 ꢀ
)
PD, MAX
=
(1)
There are 32 output pairs, or 64 output currents.
θJA
nPD,OUTPUT = 64 × 15mW = 0.96 W
As an example, if the AD8117/AD8118 is enclosed in an envi-
ronment at 45°C (TA), the total on-chip dissipation under all
load and supply conditions must not be allowed to exceed 7.0 W.
3. Subtract the quiescent output stage current for number of
loads (64 in this example). The output stage is either
standing, or driving a load, but the current only needs to
be counted once (valid for output voltages > 0.5 V).
When calculating on-chip power dissipation, it is necessary to
include the rms current being delivered to the load, multiplied
by the rms voltage drop on the AD8117/AD8118 output
devices. For a sinusoidal output, the on-chip power dissipation
due to the load can be approximated by
PDQ,OUTPUT
PDQ,OUTPUT
=
=
VPOS − VNEG
× IOUTPUT,QUIESCENT
× 1.65 mA = 8.25 mW
2.5 V− (−2.5 V)
)
There are 32 output pairs, or 64 output currents.
PD,OUTPUT
=
VPOS − VO
× IOUTPUT, RMS
UTPUT, RMS
nPDQ,OUTPUT = 64 × 8.25 mW = 0.53 W
For nonsinusoidal output, the power dissipation should be
calculated by integrating the on-chip voltage drop multiplied by
the load current over one period.
4. Verify that the power dissipation does not exceed
maximum allowed value.
PD,ON −CHIP = PD,QUIESCENT + nPD,OUTPUT − nPDQ,OUTPUT
PD,ON−CHIP = 2.5 W+ 0.96 W− 0.53 W = 2.9 W
The user can subtract the quiescent current for the Class AB
output stage when calculating the loaded power dissipation. For
each output stage driving a load, subtract a quiescent power
according to
From Figure 70 or Equation 1, this power dissipation is below
the maximum allowed dissipation for all ambient temperatures
up to and including 85°C.
PDQ,OUTPUT
=
VPOS − VNEG × IOUTPUT,QUIESCENT
where IOUTPUT, QUIESCENT = 1.65 mA for each single-ended output pin.
For each disabled output, the quiescent power supply current in
VPOS and VNEG drops by approximately 9 mA.
Rev. A | Page 31 of 36
AD8117/AD8118
are common mode to the signal and can be rejected by a
differential receiver.
Short-Circuit Output Conditions
Although there is short-circuit current protection on the
AD8117/AD8118 outputs, the output current can reach values
of 80 mA into a grounded output. Any sustained operation with
too many shorted outputs can exceed the maximum die
temperature and can result in device failure (see the Absolute
Maximum Ratings section).
Areas of Crosstalk
A practical AD8117/AD8118 circuit must be mounted to some
sort of circuit board in order to connect it to power supplies and
measurement equipment. Great care has been taken to create an
evaluation board that adds minimum crosstalk to the intrinsic
device. This, however, raises the issue that a system’s crosstalk is
a combination of the intrinsic crosstalk of the devices in
addition to the circuit board to which they are mounted. It is
important to try to separate these two areas when attempting to
minimize the effect of crosstalk.
Crosstalk
Many systems, such as broadcast video and KVM switches, that
handle numerous analog signal channels, have strict require-
ments for keeping the various signals from influencing any of
the others in the system. Crosstalk is the term used to describe
the coupling of the signals of other nearby channels to a given
channel.
In addition, crosstalk can occur among the inputs to a
crosspoint and among the outputs. It can also occur from input
to output. Techniques are discussed in the following sections for
diagnosing which part of a system is contributing to crosstalk.
When there are many signals in close proximity in a system, as
is undoubtedly the case in a system that uses the AD8117/AD8118,
the crosstalk issues can be quite complex. A good understanding
of the nature of crosstalk and some definition of terms is
required in order to specify a system that uses one or more
crosspoint devices.
Measuring Crosstalk
Crosstalk is measured by applying a signal to one or more
channels and measuring the relative strength of that signal on a
desired selected channel. The measurement is usually expressed
as dB down from the magnitude of the test signal. The crosstalk
is expressed by
Types of Crosstalk
Crosstalk can be propagated by means of any of three methods.
These fall into the categories of electric field, magnetic field,
and sharing of common impedances. This section explains
these effects.
⎛
⎜
⎞
⎟
A
SEL (s)
XT = 20 log10
⎜
⎝
⎟
⎠
ATEST (s)
where:
s = jω, the Laplace transform variable.
SEL(s) is the amplitude of the crosstalk induced signal in the
selected channel.
TEST(s) is the amplitude of the test signal.
Every conductor can be both a radiator of electric fields and a
receiver of electric fields. The electric field crosstalk mechanism
occurs when the electric field created by the transmitter
propagates across a stray capacitance (for example free space),
couples with the receiver, and induces a voltage. This voltage is
an unwanted crosstalk signal in any channel that receives it.
A
A
It can be seen that crosstalk is a function of frequency, but not a
function of the magnitude of the test signal (to first order). In
addition, the crosstalk signal will have a phase relative to the
test signal associated with it.
Currents flowing in conductors create magnetic fields that
circulate around the currents. These magnetic fields then
generate voltages in any other conductors whose paths they
link. The undesired induced voltages in these other channels
are crosstalk signals. The channels that crosstalk can be said to
have a mutual inductance that couples signals from one channel
to another.
A network analyzer is most commonly used to measure
crosstalk over a frequency range of interest. It can provide both
magnitude and phase information about the crosstalk signal.
As a crosspoint system or device grows larger, the number of
theoretical crosstalk combinations and permutations can
become extremely large. For example, in the case of the 32 × 32
matrix of the AD8117/AD8118, look at the number of crosstalk
terms that can be considered for a single channel, for example,
the input IN00. IN00 is programmed to connect to one of the
AD8117/AD8118 outputs where the measurement can be made.
The power supplies, grounds, and other signal return paths of a
multichannel system are generally shared by the various
channels. When a current from one channel flows in one of
these paths, a voltage that is developed across the impedance
becomes an input crosstalk signal for other channels that share
the common impedance.
All these sources of crosstalk are vector quantities; therefore, the
magnitudes cannot simply be added together to obtain the total
crosstalk. In fact, there are conditions where driving additional
circuits in parallel in a given configuration can actually reduce
the crosstalk. Because the AD8117/AD8118 are fully differential
designs, many sources of crosstalk either destructively cancel, or
First, the crosstalk terms associated with driving a test signal
into each of the other 31 inputs can be measured one at a time,
while applying no signal to IN00. Then the crosstalk terms
associated with driving a parallel test signal into all 31 other
inputs can be measured two at a time in all possible
combinations, then three at a time, and so on, until, finally,
Rev. A | Page 32 of 36
AD8117/AD8118
there is only one way to drive a test signal into all 31 other
inputs in parallel.
All the other inputs are driven in parallel with the same test
signal (practically provided by a distribution amplifier), with all
other outputs except OUT07 disabled. Since grounded IN07
is programmed to drive OUT07, no signal should be present.
Any signal that is present can be attributed to the other 15
hostile input signals, because no other outputs are driven
(they are all disabled). Thus, this method measures the all
hostile input contribution to crosstalk into IN07. Of course, the
method can be used for other input channels and combinations
of hostile inputs.
Each of these cases is legitimately different from the others and
might yield a unique value, depending on the resolution of the
measurement system, but it is hardly practical to measure all
these terms and then specify them. In addition, this describes
the crosstalk matrix for just one input channel. A similar
crosstalk matrix can be proposed for every other input. In
addition, if the possible combinations and permutations for
connecting inputs to the other outputs (not used for measure-
ment) are taken into consideration, the numbers rather quickly
grow to astronomical proportions. If a larger crosspoint array of
multiple AD8117/AD8118s is constructed, the numbers grow
larger still.
For output crosstalk measurement, a single input channel is
driven (IN00, for example) and all outputs other than a given
output (IN07 in the middle) are programmed to connect to
IN00. OUT07 is programmed to connect to IN15 (far away
from IN00), which is terminated to ground. Thus OUT07
should not have a signal present since it is listening to a quiet
input. Any signal measured at the OUT07 can be attributed to
the output crosstalk of the other 16 hostile outputs. Again, this
method can be modified to measure other channels and other
crosspoint matrix combinations.
Obviously, some subset of all these cases must be selected to be
used as a guide for a practical measure of crosstalk. One
common method is to measure all hostile crosstalk; this means
that the crosstalk to the selected channel is measured while all
other system channels are driven in parallel. In general, this
yields the worst crosstalk number, but this is not always the
case, due to the vector nature of the crosstalk signal.
Effect of Impedances on Crosstalk
Other useful crosstalk measurements are those created by one
nearest neighbor or by the two nearest neighbors on either side.
These crosstalk measurements are generally higher than those
of more distant channels, so they can serve as a worst-case
measure for any other one-channel or two-channel crosstalk
measurements.
The input side crosstalk can be influenced by the output
impedance of the sources that drive the inputs. The lower the
impedance of the drive source, the lower the magnitude of the
crosstalk. The dominant crosstalk mechanism on the input side
is capacitive coupling. The high impedance inputs do not have
significant current flow to create magnetically induced crosstalk.
However, significant current can flow through the input termi-
nation resistors and the loops that drive them. Thus, the PC
board on the input side can contribute to magnetically coupled
crosstalk.
Input and Output Crosstalk
Capacitive coupling is voltage-driven (dV/dt), but is generally a
constant ratio. Capacitive crosstalk is proportional to input or
output voltage, but this ratio is not reduced by simply reducing
signal swings. Attenuation factors must be changed by changing
impedances (lowering mutual capacitance), or destructive
canceling must be utilized by summing equal and out of phase
components. For high input impedance devices such as the
AD8117/AD8118, capacitances generally dominate input-
generated crosstalk.
From a circuit standpoint, the input crosstalk mechanism looks
like a capacitor coupling to a resistive load. For low frequencies,
the magnitude of the crosstalk is given by
XT = 20 log10
where:
RS is the source resistance.
(RSCM ) × s
]
Inductive coupling is proportional to current (dI/dt), and often
scales as a constant ratio with signal voltage, but also shows a
dependence on impedances (load current). Inductive coupling
can also be reduced by constructive canceling of equal and out
of phase fields. In the case of driving low impedance video
loads, output inductances contribute highly to output crosstalk.
CM is the mutual capacitance between the test signal circuit and
the selected circuit.
s is the Laplace transform variable.
From the preceding equation, it can be observed that this
crosstalk mechanism has a high-pass nature; it can also be
minimized by reducing the coupling capacitance of the input
circuits and lowering the output impedance of the drivers. If the
input is driven from a 75 ꢀ terminated cable, the input crosstalk
can be reduced by buffering this signal with a low output
impedance buffer.
The flexible programming capability of the AD8117/AD8118
can be used to diagnose whether crosstalk is occurring more on
the input side or the output side. Some examples are illustrative.
A given input pair (IN07 in the middle for this example) can be
programmed to drive OUT07 (also in the middle). The inputs
to IN07 are just terminated to ground (via 50 ꢀ or 75 ꢀ) and no
signal is applied.
Rev. A | Page 33 of 36
AD8117/AD8118
On the output side, the crosstalk can be reduced by driving a
lighter load. Although the AD8117/AD8118 are specified with
excellent differential gain and phase when driving a standard
150 ꢀ video load, the crosstalk will be higher than the
minimum obtainable due to the high output currents. These
currents will induce crosstalk via the mutual inductance of the
output pins and bond wires of the AD8117/AD8118.
applications are generally 50 ꢀ single-ended (and board
manufacturers have the most experience with this application).
CAT-5 cabling is usually driven as differential pairs of 100 ꢀ
differential impedance.
For flexibility, the AD8117/AD8118 do not contain on-chip
termination resistors. This flexibility in application comes with
some board layout challenges. The distance between the termi-
nation of the input transmission line and the AD8117/AD8118
die is a high impedance stub, and causes reflections of the input
signal. With some simplification, it can be shown that these
reflections cause peaking of the input at regular intervals in
frequency, dependent on the propagation speed (VP) of the
signal in the chosen board material and the distance (d)
between the termination resistor and the AD8117/AD8118. If
the distance is great enough, these peaks can occur in-band. In
fact, practical experience shows that these peaks are not high-Q,
and should be pushed out to three or four times the desired
bandwidth in order to not have an effect on the signal. For a
board designer using FR4 (VP = 144 × 106 m/s), this means the
AD8117/AD8118 input should be placed no farther than 1.5 cm
after the termination resistors, and preferably should be placed
even closer. The BGA substrate routing inside the AD8117/
AD8118 is approximately 1 cm in length and adds to the stub
length, so 1.5 cm PCB routing equates to d = 2.5 × 10−2 m in the
calculations.
From a circuit standpoint, this output crosstalk mechanism
looks like a transformer with a mutual inductance between the
windings that drive a load resistor. For low frequencies, the
magnitude of the crosstalk is given by
⎛
⎜
⎝
⎞
⎟
⎟
⎠
s
⎜
XT = 20 log10 MXY
×
RL
where:
XY is the mutual inductance of Output X to Output Y.
M
RL is the load resistance on the measured output.
This crosstalk mechanism can be minimized by keeping the
mutual inductance low and increasing RL. The mutual
inductance can be kept low by increasing the spacing of the
conductors and minimizing their parallel length.
PCB Layout
Extreme care must be exercised to minimize additional
crosstalk generated by the system circuit board(s). The areas
that must be carefully detailed are grounding, shielding, signal
routing, and supply bypassing.
(
2n + 1 × VP
)
fPEAK
=
4d
The packaging of the AD8117/AD8118 is designed to help keep
the crosstalk to a minimum. On the BGA substrate, each pair is
carefully routed to predominately couple to each other, with
shielding traces separating adjacent signal pairs. The ball grid
array is arranged such that similar board routing can be achieved.
Only the outer two rows are used for signals, such that vias can
be used to take the input rows to a lower signal plane if desired.
where n = {0, 1, 2, 3, …}.
In some cases, it is difficult to place the termination close to the
AD8117/AD8118 due to space constraints, differential routing,
and large resistor footprints. A preferable solution in this case is
to maintain a controlled transmission line past the AD8117/
AD8118 inputs and terminate the end of the line. This is known
as fly-by termination. The input impedance of the AD8117/
AD8118 is large enough and stub length inside the package is
small enough that this works well in practice. Implementation
of fly-by input termination often includes bringing the signal in
on one routing layer, then passing through a filled via under the
AD8117/AD8118 input ball, then back out to termination on
another signal layer. In this case, care must be taken to tie the
reference ground planes together near the signal via if the signal
layers are referenced to different ground planes.
The input and output signals have minimum crosstalk if they
are located between ground planes on layers above and below,
and separated by ground in between. Vias should be located as
close to the IC as possible to carry the inputs and outputs to the
inner layer. The input and output signals surface at the input
termination resistors and the output series back-termination
resistors. To the extent possible, these signals should also be
separated as soon as they emerge from the IC package.
PCB Termination Layout
AD8117/
AD8118
As frequencies of operation increase, the importance of proper
transmission line signal routing becomes more important. The
bandwidth of the AD8117/AD8118 is large enough that using
high impedance routing does not provide a flat in-band
frequency response for practical signal trace lengths. It is
necessary for the user to choose a characteristic impedance
suitable for the application and properly terminate the input
and output signals of the AD8117/AD8118. Traditionally, video
applications have used 75 ꢀ single-ended environments. RF
OPn
ONn
IPn
INn
75Ω
Figure 72. Fly-By Input Termination, Grounds for the Two Transmission Lines
Shown Must be Tied Together Close to the INn Pin.
Rev. A | Page 34 of 36
AD8117/AD8118
If multiple AD8117/AD8118s are to be driven in parallel, a fly-
by input termination scheme is very useful, but the distance
from each AD8117/AD8118 input to the driven input
transmission line is a stub that should be minimized in length
and parasitics using the discussed guidelines.
as trace widths become large. In most cases, the best practical
solution is to place the half-characteristic impedance resistor as
close as possible (preferably less than 1.5 cm away) and to
reduce the parasitics of the stub (by removing the ground plane
under the stub, for example). In either case, the designer must
decide if the layout complexity created by a balanced,
terminated solution is preferable to simply grounding the
undriven input at the ball with no trace.
When driving the AD8117/AD8118 single-endedly, the
undriven input is often terminated with a resistance in order to
balance the input stage. It can be seen that by terminating the
undriven input with a resistor of one half the characteristic
impedance, the input stage is perfectly balanced (37.5 ꢀ, for
example, to balance the two parallel 75 ꢀ terminations on the
driven input). However, due to the feedback in the input
receiver, there is high speed signal current leaving the undriven
input. In order to terminate this high speed signal, proper
transmission line techniques should be used. One solution is to
adjust the trace width to create a transmission line of half the
characteristic impedance and terminate the far end with this
resistance (37.5 ꢀ in a 75 ꢀ system). This is not often practical
Although the examples discussed so far are for input
termination, the theory is similar for output back-termination.
Taking the AD8117/AD8118 as an ideal voltage source, any
distance of routing between the AD8117/AD8118 and a back-
termination resistor will be an impedance mismatch that
potentially creates reflections. For this reason, back-termination
resistors should also be placed close to the AD8117/AD8118. In
practice, because back-termination resistors are series elements,
they can be placed close to the AD8117/AD8118 outputs.
VPOS
VDD
J3
PC_VDD
PLD_VDD
VDD
VPOS
ANALOG
SMA
SMA
50Ω
IN[31:0],
IP[31:0]
ON[31:0],
OP[31:0]
IN[31:0], IP[31:0]
ON[31:0], OP[31:0]
50Ω
AD8117/
AD8118
CLK
RESET
WE
UPDATE
DATA IN
DATA OUT
VOCM
PC
PARALLEL
PORT
LOGIC
ISOLATORS
CPLD
LOGIC
DGND
VNEG
J8,
W3 TO W7
PC_GND
VNEG
GND
Figure 73. Evaluation Board Simplified Schematic
Rev. A | Page 35 of 36
AD8117/AD8118
OUTLINE DIMENSIONS
A1 CORNER
INDEX AREA
31.00
BSC SQ
6
4
2
22 20 18 16 14 12 10
23 21 19 17 15 13 11
8
9
7
5
3
1
A
B
C
D
E
F
BALL A1
INDICATOR
G
H
J
K
L
27.94
TOP VIEW
BOTTOM
VIEW
BSC SQ
M
N
P
R
T
U
V
W
1.27
BSC
Y
AA
AB
AC
DETAIL A
1.07
0.99
0.92
DETAIL A
*
1.765 MAX
0.10 MIN
0.70
0.63
0.56
0.90
0.75
0.60
COPLANARITY
0.20
0.25 MIN
(4
SEATING
PLANE
BALL DIAMETER
)
*
COMPLIANT TO JEDEC STANDARDS MO-192-BAN-2
WITH THE EXCEPTION TO PACKAGE HEIGHT.
Figure 74. 304-Ball Ball Grid Array, Thermally Enhanced [BGA_ED]
(BP-304)
Dimensions shown in millimeters
ORDERING GUIDE
Temperature
Range
Model
Package Description
Package Option
BP-304
BP-304
AD8117ABPZ1
AD8118ABPZ1
AD8117-EVAL
AD8118-EVAL
−40°C to +85°C
−40°C to +85°C
304-Ball Ball Grid Array Package, Thermally Enhanced [BGA_ED]
304-Ball Ball Grid Array Package, Thermally Enhanced [BGA_ED]
Evaluation Board
Evaluation Board
1 Z = RoHS Compliant Part.
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06365-0-5/07(A)
Rev. A | Page 36 of 36
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