AD812ARZ [ADI]
Dual, Current Feedback Low Power Op Amp; 双通道，电流反馈型低功耗运算放大器
| 型号： | AD812ARZ |
| 厂家： | 
ADI |
| 描述： | Dual, Current Feedback Low Power Op Amp |
| 文件： | 总16页 (文件大小：358K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual, Current Feedback
Low Power Op Amp
a
AD812
PIN CONFIGURATION
8-Lead Plastic
FEATURES
Two Video Amplifiers in One 8-Lead SOIC Package
Optimized for Driving Cables in Video Systems
Excellent Video Specifications (RL = 150 ⍀):
Gain Flatness 0.1 dB to 40 MHz
0.02% Differential Gain Error
0.02؇ Differential Phase Error
Low Power
Operates on Single +3 V Supply
5.5 mA/Amplifier Max Power Supply Current
High Speed
Mini-DIP and SOIC
OUT1
–IN1
+IN1
V–
1
2
3
4
8
7
6
5
V+
+
OUT2
–IN2
+IN2
+
AD812
145 MHz Unity Gain Bandwidth (3 dB)
1600 V/s Slew Rate
Easy to Use
50 mA Output Current
Output Swing to 1 V of Rails (150 ⍀ Load)
APPLICATIONS
The AD812 offers low power of 4.0 mA per amplifier max (VS =
+5 V) and can run on a single +3 V power supply. The outputs
of each amplifier swing to within one volt of either supply rail to
easily accommodate video signals of 1 V p-p. Also, at gains of
+2 the AD812 can swing 3 V p-p on a single +5 V power sup-
ply. All this is offered in a small 8-lead plastic DIP or 8-lead
SOIC package. These features make this dual amplifier ideal
for portable and battery powered applications where size and
power is critical.
Video Line Driver
Professional Cameras
Video Switchers
Special Effects
PRODUCT DESCRIPTION
The AD812 is a low power, single supply, dual video amplifier.
Each of the amplifiers have 50 mA of output current and are
optimized for driving one back-terminated video load (150 Ω)
each. Each amplifier is a current feedback amplifier and fea-
tures gain flatness of 0.1 dB to 40 MHz while offering differen-
tial gain and phase error of 0.02% and 0.02°. This makes the
AD812 ideal for professional video electronics such as cameras
and video switchers.
The outstanding bandwidth of 145 MHz along with 1600 V/µs
of slew rate make the AD812 useful in many general purpose
high speed applications where a single +5 V or dual power sup-
plies up to ±15 V are available. The AD812 is available in the
industrial temperature range of –40°C to +85°C.
0.4
0.06
G = +2
= 150⍀
0.3
R
L
0.04
0.2
0.1
DIFFERENTIAL GAIN
0.08
0.06
0.04
0.02
0
–0.1
–0.2
DIFFERENTIAL PHASE
V
= ؎15V
S
–0.3
–0.4
؎5V
5V
0.02
0
–0.5
–0.6
3V
100k
1M
10M
100M
5
6
7
8
9
10
11
12
13
14
15
SUPPLY VOLTAGE – ؎Volts
FREQUENCY – Hz
Figure 1. Fine-Scale Gain Flatness vs. Frequency, Gain
Figure 2. Differential Gain and Phase vs. Supply Voltage,
= +2, RL = 150 Ω
Gain = +2, RL = 150 Ω
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1998
AD812–SPECIFICATIONS
Dual Supply(@ TA = +25؇C, RL = 150 ⍀, unless otherwise noted)
Model
AD812A
Typ
Conditions
VS
Min
Max
Units
DYNAMIC PERFORMANCE
–3 dB Bandwidth
G = +2, No Peaking
±5 V
50
75
100
20
25
65
MHz
MHz
MHz
MHz
MHz
V/µs
V/µs
V/µs
V/µs
±15 V
±15 V
±5 V
±15 V
±5 V
±15 V
±5 V
±15 V
100
145
30
Gain = +1
G = +2
Bandwidth for 0.1 dB Flatness
Slew Rate1
40
G = +2, RL = 1 kΩ
20 V Step
G = –1, RL = 1 kΩ
275
1400
425
1600
250
600
Settling Time to 0.1%
G = –1, RL = 1 kΩ
VO = 3 V Step
±5 V
±15 V
50
40
ns
ns
VO = 10 V Step
NOISE/HARMONIC PERFORMANCE
Total Harmonic Distortion
Input Voltage Noise
fC = 1 MHz, RL = 1 kΩ
f = 10 kHz
f = 10 kHz, +In
f = 10 kHz, –In
±15 V
–90
3.5
1.5
dBc
±5 V, ±15 V
±5 V, ±15 V
±5 V, ±15 V
nV/√Hz
pA/√Hz
pA/√Hz
%
%
Degrees
Degrees
Input Current Noise
18
Differential Gain Error
Differential Phase Error
NTSC, G = +2, RL = 150 Ω ±5 V
0.05
0.02
0.07
0.02
0.1
±15 V
±5 V
±15 V
0.06
0.15
0.06
DC PERFORMANCE
Input Offset Voltage
±5 V, ±15 V
2
5
12
mV
mV
µV/°C
µA
T
MIN –TMAX
Offset Drift
–Input Bias Current
±5 V, ±15 V
±5 V, ±15 V
15
7
25
TMIN –TMAX
38
µA
+Input Bias Current
±5 V, ±15 V
±5 V
0.3
76
1.5
2.0
µA
µA
dB
dB
TMIN –TMAX
VO = ±2.5 V, RL = 150 Ω
TMIN –TMAX
Open-Loop Voltage Gain
68
69
VO = ±10 V, RL = 1 kΩ
TMIN –TMAX
±15 V
76
75
82
dB
dB
Open-Loop Transresistance
VO = ±2.5 V, RL = 150 Ω
±5 V
350
270
450
370
550
800
kΩ
kΩ
kΩ
kΩ
T
MIN –TMAX
VO = ±10 V, RL = 1 kΩ
TMIN –TMAX
±15 V
INPUT CHARACTERISTICS
Input Resistance
+Input
–Input
+Input
±15 V
15
65
1.7
4.0
13.5
MΩ
Ω
pF
±V
±V
Input Capacitance
Input Common Mode
Voltage Range
±5 V
±15 V
Common-Mode Rejection Ratio
Input Offset Voltage
–Input Current
+Input Current
Input Offset Voltage
–Input Current
VCM = ±2.5 V
VCM = ±12 V
±5 V
51
55
58
2
0.07
60
1.5
0.05
dB
3.0
0.15
µA/V
µA/V
dB
µA/V
µA/V
±15 V
3.3
0.15
+Input Current
REV. B
–2–
AD812
Model
AD812A
Typ
Conditions
VS
Min
Max
Units
OUTPUT CHARACTERISTICS
Output Voltage Swing
RL = 150 Ω, TMIN –TMAX
RL = 1 kΩ, TMIN –TMAX
±5 V
±15 V
±5 V
±15 V
±15 V
3.5
13.6
30
3.8
14.0
40
50
100
±V
±V
mA
mA
mA
Output Current
40
Short Circuit Current
Output Resistance
G = +2, RF = 715 Ω
VIN = 2 V
Open-Loop
±15 V
15
Ω
MATCHING CHARACTERISTICS
Dynamic
Crosstalk
Gain Flatness Match
DC
G = +2, f = 5 MHz
G = +2, f = 40 MHz
±5 V, ±15 V
±15 V
–75
0.1
dB
dB
Input offset Voltage
–Input Bias Current
TMIN –TMAX
TMIN –TMAX
±5 V, ±15 V
±5 V, ±15 V
0.5
2
3.6
25
mV
µA
POWER SUPPLY
Operating Range
Quiescent Current
±1.2
±18
4.0
5.5
6.0
V
Per Amplifier
±5 V
±15 V
±15 V
3.5
4.5
mA
mA
mA
TMIN –TMAX
Power Supply Rejection Ratio
Input Offset Voltage
–Input Current
VS = ±1.5 V to ±15 V
70
80
0.3
0.005
dB
µA/V
µA/V
0.6
0.05
+Input Current
NOTES
1Slew rate measurement is based on 10% to 90% rise time in the specified closed-loop gain.
Specifications subject to change without notice.
Single Supply
(@ TA = +25؇C, RL = 150 ⍀, unless otherwise noted)
Model
AD812A
Conditions
VS
Min
Typ
Max
Units
DYNAMIC PERFORMANCE
–3 dB Bandwidth
G = +2, No Peaking
+5 V
+3 V
35
30
50
40
MHz
MHz
Bandwidth for 0.1 dB
Flatness
G = +2
+5 V
+3 V
+5 V
+3 V
13
10
20
18
125
60
MHz
MHz
V/µs
Slew Rate1
G = +2, RL = 1 kΩ
V/µs
NOISE/HARMONIC PERFORMANCE
Input Voltage Noise
f = 10 kHz
f = 10 kHz, +In
f = 10 kHz, –In
+5 V, +3 V
+5 V, +3 V
+5 V, +3 V
3.5
1.5
18
0.07
0.15
0.06
0.15
nV/√Hz
pA/√Hz
pA/√Hz
%
%
Degrees
Degrees
Input Current Noise
Differential Gain Error2
Differential Phase Error2
NTSC, G = +2, RL = 150 Ω +5 V
G = +1
G = +2
G = +1
+3 V
+5 V
+3 V
REV. B
–3–
AD812–SPECIFICATIONS
Single Supply (Continued)
AD812A
Typ
Model
Conditions
VS
Min
Max
Units
DC PERFORMANCE
Input Offset Voltage
+5 V, +3 V
1.5
4.5
7.0
mV
mV
µV/°C
µA
TMIN –TMAX
Offset Drift
–Input Bias Current
+5 V, +3 V
+5 V, +3 V
7
2
20
TMIN –TMAX
MIN –TMAX
30
1.5
2.0
µA
µA
µA
+Input Bias Current
+5 V, +3 V
0.2
T
Open-Loop Voltage Gain
Open-Loop Transresistance
VO = +2.5 V p-p
VO = +0.7 V p-p
VO = +2.5 V p-p
VO = +0.7 V p-p
+5 V
+3 V
+5 V
+3 V
67
73
70
400
300
dB
dB
kΩ
kΩ
250
INPUT CHARACTERISTICS
Input Resistance
+Input
–Input
+Input
+5 V
+5 V
15
90
2
MΩ
Ω
pF
V
Input Capacitance
Input Common Mode
Voltage Range
+5 V
+3 V
1.0
1.0
4.0
2.0
V
Common-Mode Rejection Ratio
Input Offset Voltage
–Input Current
+Input Current
Input Offset Voltage
–Input Current
VCM = 1.25 V to 3.75 V
VCM = 1 V to 2 V
+5 V
+3 V
52
55
3
0.1
52
3.5
0.1
dB
5.5
0.2
µA/V
µA/V
dB
µA/V
µA/V
+Input Current
OUTPUT CHARACTERISTICS
Output Voltage Swing p-p
RL = 1 kΩ, TMIN –TMAX
RL = 150 Ω, TMIN –TMAX
+5 V
+5 V
+3 V
+5 V
+3 V
+5 V
3.0
2.8
1.0
20
3.2
3.1
1.3
30
25
40
V p-p
V p-p
V p-p
mA
mA
mA
Output Current
15
Short Circuit Current
G = +2, RF = 715 Ω
VIN = 1 V
MATCHING CHARACTERISTICS
Dynamic
Crosstalk
Gain Flatness Match
DC
G = +2, f = 5 MHz
G = +2, f = 20 MHz
+5 V, +3 V
+5 V, +3 V
–72
0.1
dB
dB
Input offset Voltage
–Input Bias Current
TMIN –TMAX
TMIN –TMAX
+5 V, +3 V
+5 V, +3 V
0.5
2
3.5
25
mV
µA
POWER SUPPLY
Operating Range
Quiescent Current
2.4
70
36
V
Per Amplifier
+5 V
+3 V
+5 V
3.2
3.0
4.0
3.5
4.5
mA
mA
mA
TMIN –TMAX
Power Supply Rejection Ratio
Input Offset Voltage
–Input Current
VS = +3 V to +30 V
80
0.3
0.005
dB
µA/V
µA/V
0.6
0.05
+Input Current
TRANSISTOR COUNT
NOTES
56
1Slew rate measurement is based on 10% to 90% rise time in the specified closed-loop gain.
2Single supply differential gain and phase are measured with the ac coupled circuit of Figure 53.
Specifications subject to change without notice.
–4–
REV. B
AD812
ABSOLUTE MAXIMUM RATINGS1
MAXIMUM POWER DISSIPATION
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±18 V
The maximum power that can be safely dissipated by the
AD812 is limited by the associated rise in junction temperature.
The maximum safe junction temperature for the plastic encap-
sulated parts is determined by the glass transition temperature
of the plastic, about 150°C. Exceeding this limit temporarily
may cause a shift in parametric performance due to a change in
the stresses exerted on the die by the package. Exceeding a
junction temperature of 175°C for an extended period can result
in device failure.
Internal Power Dissipation2
Plastic (N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Watts
Small Outline (R) . . . . . . . . . . . . . . . . . . . . . . . . . . 0.9 Watts
Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ±VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ±1.2 V
Output Short Circuit Duration
. . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves
Storage Temperature Range N, R . . . . . . . . . –65°C to +125°C
Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C
Lead Temperature Range (Soldering, 10 sec) . . . . . . . +300°C
While the AD812 is internally short circuit protected, this may
not be sufficient to guarantee that the maximum junction tem-
perature (150 degrees) is not exceeded under all conditions. To
ensure proper operation, it is important to observe the derating
curves.
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2Specification is for device in free air: 8-lead plastic package: θJA = 90°C/Watt;
8-lead SOIC package: θJA = 150°C/Watt.
It must also be noted that in high (noninverting) gain configura-
tions (with low values of gain resistor), a high level of input
overdrive can result in a large input error current, which may
result in a significant power dissipation in the input stage. This
power must be included when computing the junction tempera-
ture rise due to total internal power.
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Option
Model
2.0
T
= +150؇C
J
AD812AN
AD812AR
–40°C to +85°C 8-Lead Plastic DIP N-8
–40°C to +85°C 8-Lead Plastic SOIC SO-8
8-LEAD MINI-DIP PACKAGE
AD812AR-REEL
AD812AR-REEL7
13" Reel
7" Reel
1.5
1.0
0.5
0
METALIZATION PHOTO
Dimensions shown in inches and (mm).
8-LEAD SOIC PACKAGE
0.0783
(1.99)
V+
8
OUT2
7
–IN2
6
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
5 +IN2
AMBIENT TEMPERATURE – ؇C
Figure 3. Plot of Maximum Power Dissipation vs.
Temperature
0.0539
(1.37)
4 V–
1
2
–IN1
3
+IN1
4
V–
OUT1
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD812 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
–5–
AD812–Typical Performance Characteristics
16
20
14
12
15
10
V
= ؎15V
S
10
V
= ؎5V
S
8
6
4
5
0
–60 –40 –20
0
20
40
60
80
100 120 140
0
5
10
15
20
SUPPLY VOLTAGE – ؎Volts
JUNCTION TEMPERATURE – ؇C
Figure 4. Input Common-Mode Voltage Range vs. Supply
Voltage
Figure 7. Total Supply Current vs. Junction Temperature
10
20
T
= +25 C
A
NO LOAD
9
8
7
6
5
15
10
R
= 150⍀
L
5
0
10
SUPPLY VOLTAGE – ؎Volts
12
14
16
0
2
4
6
8
0
5
10
15
20
SUPPLY VOLTAGE – ؎Volts
Figure 5. Output Voltage Swing vs. Supply Voltage
Figure 8. Total Supply Current vs. Supply Voltage
30
25
20
؎15V SUPPLY
25
15
–I , V = ؎5V
10
5
B
S
20
15
10
0
–5
+I , V = ؎5V, ؎15V
B S
–10
–15
–20
–25
–I , V = ؎15V
؎5V SUPPLY
B
S
5
0
10
100
1k
10k
–40 –20
0
20
40
60
80 100 120 140
–60
LOAD RESISTANCE – ⍀
JUNCTION TEMPERATURE – ؇C
Figure 6. Output Voltage Swing vs. Load Resistance
Figure 9. Input Bias Current vs. Junction Temperature
REV. B
–6–
AD812
70
4
2
V
= ؎5V
S
60
50
0
–2
–4
V
= ؎15V
S
–6
40
30
–8
–10
–12
–14
–16
20
10
15
20
0
5
–60 –40 –20
0
20
40
60
80 100 120 140
SUPPLY VOLTAGE – ؎Volts
JUNCTION TEMPERATURE – ؇C
Figure 10. Input Offset Voltage vs. Junction Temperature
Figure 13. Linear Output Current vs. Supply Voltage
1k
160
140
G = +2
100
SINK
V
= ؎15V
S
120
10
1
100
80
SOURCE
؎5V
S
0.1
60
؎15V
S
0.01
40
10k
100k
1M
FREQUENCY – Hz
10M
100M
–60 –40 –20
0
20
40
60
80 100 120 140
JUNCTION TEMPERATURE – ؇C
Figure 11. Short Circuit Current vs. Junction Temperature
Figure 14. Closed-Loop Output Resistance vs. Frequency
30
80
70
60
50
V
= ؎15V
S
25
20
15
10
5
R
= 1k⍀
L
V
= ؎5V
S
40
30
20
V
= ؎5V
S
V
= ؎15V
S
0
–60 –40 –20
0
20
40
60
80 100 120 140
100k
1M
10M
FREQUENCY – Hz
100M
JUNCTION TEMPERATURE – ؇C
Figure 12. Linear Output Current vs. Junction Temperature
Figure 15. Large Signal Frequency Response
REV. B
–7–
AD812
100
100
0
–45
120
100
80
V
V
= ؎15V
PHASE
S
INVERTING INPUT
CURRENT NOISE
–90
–135
–180
GAIN
= 3V
S
10
10
VOLTAGE NOISE
V
= 3V
V
= ؎15V
S
S
NONINVERTING INPUT
CURRENT NOISE
60
1
100k
1
10
40
10k
100
1k
FREQUENCY – Hz
10k
100k
1M
FREQUENCY – Hz
10M
100M
Figure 16. Input Current and Voltage Noise vs. Frequency
Figure 19. Open-Loop Transimpedance vs. Frequency
(Relative to 1 Ω)
–30
90
681⍀
G = +2
V
V
V
= 2V p-p
80
70
60
50
40
30
20
10
681⍀
681⍀
S
S
S
V
V
IN
OUT
= ؎15V ; R = 1k⍀
L
–50
–70
–90
= ؎5V ; R = 150⍀
L
681⍀
V
= ؎5V
S
V
S
= ؎15V
V
= ؎15V
ND
S
2
HARMONIC
HARMONIC
V
= 3V
S
RD
3
–110
–130
ND
2
RD
3
10k
100k
1M
FREQUENCY – Hz
10M
100M
1k
10k
100k
FREQUENCY – Hz
1M
10M
100M
Figure 17. Common-Mode Rejection vs. Frequency
Figure 20. Harmonic Distortion vs. Frequency
80
10
GAIN = –1
؎15V
8
70
V
=
S
؎15V
6
4
2
60
50
؎1.5V
40
0.025%
0
1%
0.1%
–2
–4
30
20
10
–6
–8
0
10k
–10
20
100k
1M
10M
100M
30
40
SETTLING TIME – ns
50
60
FREQUENCY – Hz
Figure 18. Power Supply Rejection vs. Frequency
Figure 21. Output Swing and Error vs. Settling Time
REV. B
–8–
AD812
1400
1200
1000
800
600
400
200
0
1400
1200
1000
800
600
400
200
0
G = +1
G = +1
V
= ؎15V
= 500⍀
S
R
L
G = +2
G = +2
G = +10
G = +10
G = –1
G = –1
0
1.5
3.0
4.5
6.0
7.5
9.0 10.5 12.0 13.5 15.0
0
1
2
3
4
5
6
7
8
9
10
SUPPLY VOLTAGE – ؎Volts
OUTPUT STEP SIZE – Vp-p
Figure 22. Slew Rate vs. Output Step Size
Figure 25. Maximum Slew Rate vs. Supply Voltage
500mV
20ns
50ns
2V
100
90
100
90
V
V
IN
IN
V
V
OUT
10
10
OUT
0%
0%
500mV
2V
Figure 26. Small Signal Pulse Response, Gain = +1,
(RF = 750 Ω, RL = 150 Ω, VS = ±5 V)
Figure 23. Large Signal Pulse Response, Gain = +1,
(RF = 750 Ω, RL = 150 Ω, VS = ±5 V)
200
G = +1
= 150⍀
PHASE
GAIN
G = +1
180
R
0
L
R
= 150⍀
L
V
= ؎15V
؎5V
S
160
140
120
100
80
–90
R
= 750⍀
= 866⍀
F
1
–180
–270
R
F
5V
3V
0
PEAKING 1dB
–1
–2
–3
–4
V
= ؎15V
PEAKING 0.2dB
S
؎5V
60
5V
3V
40
20
–5
–6
0
0
2
4
6
8
10
12
14
16
18
20
1
10
100
1000
FREQUENCY – MHz
SUPPLY VOLTAGE – ؎Volts
Figure 24. Closed-Loop Gain and Phase vs. Frequency,
G = +1
Figure 27. –3 dB Bandwidth vs. Supply Voltage, G = +1
REV. B
–9–
AD812
20ns
50mV
50ns
500mV
100
90
100
V
V
IN
IN
90
V
10
V
OUT
10
OUT
0%
0%
500mV
5V
Figure 28. Large Signal Pulse Response, Gain = +10,
(RF = 357 Ω, RL = 500 Ω, VS = ±15 V)
Figure 31. Small Signal Pulse Response, Gain = +10,
(RF = 357 Ω, RL = 150 Ω, VS = ±5 V)
PHASE
GAIN
G = +10
= 150⍀
PHASE
GAIN
G = +10
= 1k⍀
0
V
= ؎15V
V
= ؎15V
؎5V
S
0
S
R
R
L
L
–90
؎5V
–90
3V
5V
5V
–180
–270
1
0
1
0
–180
–270
–360
3V
V
= ؎15V
S
–1
–1
5V
3V
5V
3V
–2
–3
–4
–2
–3
–4
V
= ؎15V
S
؎5V
؎5V
–5
–6
–5
–6
1
10
100
1000
1
10
100
1000
FREQUENCY – MHz
FREQUENCY – MHz
Figure 29. Closed-Loop Gain and Phase vs. Frequency,
Gain = +10, RL = 150 Ω
Figure 32. Closed-Loop Gain and Phase vs. Frequency,
Gain = +10, RL = 1 kΩ
100
110
G = +10
90
G = +10
100
R = 150⍀
L
R
= 1k⍀
L
80
70
60
90
80
70
R
= 357⍀
= 649⍀
F
R
= 357⍀
= 649⍀
PEAKING 1dB
F
R
= 154⍀
F
R
= 154⍀
F
50
40
30
60
R
F
R
F
50
40
30
20
10
0
20
10
0
2
4
6
8
10
12
14
16
18
20
0
2
4
6
8
10
12
14
16
18
20
SUPPLY VOLTAGE – ؎Volts
SUPPLY VOLTAGE – ؎Volts
Figure 30. –3 dB Bandwidth vs. Supply Voltage,
Gain = +10, RL = 150 Ω
Figure 33. –3 dB Bandwidth vs. Supply Voltage,
Gain = +10, RL = 1 kΩ
REV. B
–10–
AD812
50ns
500mV
20ns
2V
100
90
100
90
V
V
IN
IN
V
10
10
V
OUT
OUT
0%
0%
500mV
2V
Figure 34. Large Signal Pulse Response, Gain = –1,
Figure 37. Small Signal Pulse Response, Gain = –1,
(RF = 750 Ω, RL = 150 Ω, VS = ±5 V)
(RF = 750 Ω, RL = 150 Ω, VS = ±5 V)
PHASE
GAIN
V
= ؎15V
G = –1
= 150⍀
S
V
= ؎15V
PHASE
GAIN
G = –10
= 1k⍀
S
R
0
L
0
R
؎5V
L
؎5V
5V
–90
–90
3V
1
0
–180
–270
–180
–270
5V
1
0
3V
–1
–2
–3
–4
–1
V
= ؎15V
S
–2
–3
–4
V
= ؎15V
S
؎5V
؎5V
5V
3V
5V
–5
–6
3V
–5
–6
1
10
100
1000
1
10
100
1000
FREQUENCY – MHz
FREQUENCY – MHz
Figure 35. Closed-Loop Gain and Phase vs. Frequency,
Gain = –1, RL = 150 Ω
Figure 38. Closed-Loop Gain and Phase vs. Frequency,
Gain = –10, RL = 1 kΩ
130
100
G = –1
120
G = –10
90
R
= 150⍀
L
R
= 1k⍀
L
R
= 681⍀
F
110
100
90
80
70
60
50
40
30
20
10
0
PEAKING Յ 1.0dB
R
= 357⍀
= 649⍀
F
R
= 715⍀
F
R
= 154⍀
R
F
F
80
70
60
PEAKING Յ 0.2dB
50
40
30
0
2
4
6
8
10
12
14
16
18
20
0
2
4
6
8
10
12
14
16
18
20
SUPPLY VOLTAGE – ؎Volts
SUPPLY VOLTAGE – ؎Volts
Figure 36. –3 dB Bandwidth vs. Supply Voltage,
Gain = –1, RL = 150 Ω
Figure 39. –3 dB Bandwidth vs. Supply Voltage,
Gain = –10, RL = 1 kΩ
REV. B
–11–
AD812
General Considerations
To estimate the –3 dB bandwidth for closed-loop gains or feed-
back resistors not listed in the above table, the following two
pole model for the AD812 many be used:
The AD812 is a wide bandwidth, dual video amplifier which
offers a high level of performance on less than 5.5 mA per am-
plifier of quiescent supply current. It is designed to offer out-
standing performance at closed-loop inverting or noninverting
gains of one or greater.
G
ACL
=
RF +GrIN CT
(
)
Built on a low cost, complementary bipolar process, and achiev-
ing bandwidth in excess of 100 MHz, differential gain and phase
errors of better than 0.1% and 0.1° (into 150 Ω), and output
current greater than 40 mA, the AD812 is an exceptionally
efficient video amplifier. Using a conventional current feedback
architecture, its high performance is achieved through careful
attention to design details.
S2
+S RF +GrIN CT +1
(
)
2πf2
where: ACL = closed-loop gain
= 1 + RF/RG
G
rIN = input resistance of the inverting input
CT = “transcapacitance,” which forms the open-loop
dominant pole with the tranresistance
RF = feedback resistor
Choice of Feedback and Gain Resistors
Because it is a current feedback amplifier, the closed-loop band-
width of the AD812 depends on the value of the feedback resis-
tor. The bandwidth also depends on the supply voltage. In
addition, attenuation of the open-loop response when driving
load resistors less than about 250 Ω will affect the bandwidth.
Table I contains data showing typical bandwidths at different
supply voltages for some useful closed-loop gains when driving a
load of 150 Ω. (Bandwidths will be about 20% greater for load
resistances above a few hundred ohms.)
RG = gain resistor
f2 = frequency of second (nondominant) pole
S
= 2 πj f
Appropriate values for the model parameters at different supply
voltages are listed in Table II. Reasonable approximations for
these values at supply voltages not found in the table can be
obtained by a simple linear interpolation between those tabu-
lated values which “bracket” the desired condition.
Table II. Two-Pole Model Parameters at Various
Supply Voltages
The choice of feedback resistor is not critical unless it is impor-
tant to maintain the widest, flattest frequency response. The
resistors recommended in the table are those (metal film values)
that will result in the widest 0.1 dB bandwidth. In those appli-
cations where the best control of the bandwidth is desired, 1%
metal film resistors are adequate. Wider bandwidths can be
attained by reducing the magnitude of the feedback resistor (at
the expense of increased peaking), while peaking can be reduced
by increasing the magnitude of the feedback resistor.
VS
rIN (⍀)
CT (pF)
f2 (MHz)
±15
±5
+5
85
90
105
115
2.5
3.8
4.8
5.5
150
125
105
95
+3
As discussed in many amplifier and electronics textbooks (such
as Roberge’s Operational Amplifiers: Theory and Practice), the
–3 dB bandwidth for the 2-pole model can be obtained as:
1/2
Table I. –3 dB Bandwidth vs. Closed-Loop Gain and
Feedback Resistor (RL = 150 Ω)
f3 = fN [1 – 2d2 + (2 – 4d2 + 4d4)1/2
]
VS (V)
Gain
RF (⍀)
BW (MHz)
where:
±15
+1
+2
+10
–1
–10
866
715
357
715
357
145
100
65
100
60
1/2
f2
fN =
R + GrIN C
F T
(
)
±5
+5
+3
+1
+2
+10
–1
–10
750
681
154
715
154
90
65
45
70
45
and:
d = (1/2) [f2 (RF + GrIN) CT]1/2
This model will predict –3 dB bandwidth within about 10 to
15% of the correct value when the load is 150 Ω. However, it is
not an accurate enough to predict either the phase behavior or
the frequency response peaking of the AD812.
+1
+2
+10
–1
–10
750
681
154
715
154
60
50
35
50
35
Printed Circuit Board Layout Guidelines
As with all wideband amplifiers, printed circuit board parasitics
can affect the overall closed-loop performance. Most important
for controlling the 0.1 dB bandwidth are stray capacitances at
the output and inverting input nodes. Increasing the space between
signal lines and ground plane will minimize the coupling. Also,
signal lines connecting the feedback and gain resistors should be
kept short enough that their associated inductance does not
cause high frequency gain errors.
+1
+2
+10
–1
–10
750
681
154
715
154
50
40
30
40
25
REV. B
–12–
AD812
Power Supply Bypassing
The input and output signal return paths must also be kept from
overlapping. Since ground connections are not of perfectly zero
impedance, current in one ground return path can produce a
voltage drop in another ground return path if they are allowed
to overlap.
Adequate power supply bypassing can be very important when
optimizing the performance of high speed circuits. Inductance
in the supply leads can (for example) contribute to resonant
circuits that produce peaking in the amplifier’s response. In
addition, if large current transients must be delivered to a load,
then large (greater than 1 µF) bypass capacitors are required to
produce the best settling time and lowest distortion. Although
0.1 µF capacitors may be adequate in some applications, more
elaborate bypassing is required in other cases.
Electric field coupling external to (and across) the package can
be reduced by arranging for a narrow strip of ground plane to be
run between the pins (parallel to the pin rows). Doing this on
both sides of the board can reduce the high frequency crosstalk
by about 5 dB or 6 dB.
When multiple bypass capacitors are connected in parallel, it is
important to be sure that the capacitors themselves do not form
resonant circuits. A small (say 5 Ω) resistor may be required in
series with one of the capacitors to minimize this possibility.
Driving Capacitive Loads
When used with the appropriate output series resistor, any load
capacitance can be driven without peaking or oscillation. In
most cases, less than 50 Ω is all that is needed to achieve an
extremely flat frequency response. As illustrated in Figure 44,
the AD812 can be very attractive for driving largely capacitive
loads. In this case, the AD812’s high output short circuit
current allows for a 150 V/µs slew rate when driving a 510 pF
capacitor.
As discussed below, power supply bypassing can have a signifi-
cant impact on crosstalk performance.
Achieving Low Crosstalk
Measured crosstalk from the output of amplifier 2 to the input
of amplifier 1 of the AD812 is shown in Figure 40. The crosstalk
from the output of amplifier 1 to the input of amplifier 2 is a few
dB better than this due to the additional distance between criti-
cal signal nodes.
R
F
+V
0.1F
1.0F
S
A carefully laid-out PC board should be able to achieve the level
of crosstalk shown in the figure. The most significant contribu-
tors to difficulty in achieving low crosstalk are inadequate power
supply bypassing, overlapped input and/or output signal paths,
and capacitive coupling between critical nodes.
R
G
8
R
S
V
AD812
O
The bypass capacitors must be connected to the ground plane at
a point close to and between the ground reference points for the
two loads. (The bypass of the negative power supply is particu-
larly important in this regard.) There are two amplifiers in the
package, and low impedance signal return paths must be pro-
vided for each load. (Using a parallel combination of 1 µF,
0.1 µF, and 0.01 µF bypass capacitors will help to achieve opti-
mal crosstalk.)
V
C
R
IN
L
4
L
1.0F
0.1F
R
T
–V
S
Figure 41. Circuit for Driving a Capacitive Load
–10
–20
V
= ؎5V
S
G = +2
R
= 150⍀
R
R
C
= 750⍀
L
F
L
L
–30
–40
= 1k⍀
= 10pF
12
9
6
–50
R
= 0
S
–60
R
= 30⍀
S
3
0
–70
R
= 50⍀
S
–80
–3
–6
–90
–100
–110
1
10
100
1000
100k
1M
10M
100M
FREQUENCY – MHz
FREQUENCY – Hz
Figure 42. Response to a Small Load Capacitor at ±5 V
Figure 40. Crosstalk vs. Frequency
REV. B
–13–
AD812
V
= ؎15V
S
50ns
1V
G = +2
R
R
= 750⍀
= 1k⍀
F
L
100
90
V
IN
12
9
6
C
= 150pF, R = 30⍀
S
L
3
0
V
10
OUT
0%
–3
–6
C
= 510pF, R = 15⍀
L
S
2V
–9
1
10
100
1000
Figure 45. 6 dB Overload Recovery; G = 10, RL = 500 Ω,
VS = ±5 V
FREQUENCY – MHz
Figure 43. Response to Large Load Capacitor, VS = ±15 V
In the case of high gains with very high levels of input overdrive,
a longer recovery time may occur. For example, if the input
common-mode voltage range is exceeded in a gain of +10, the
recovery time will be on the order of 100 ns. This is primarily
due to current overloading of the input stage.
5V
100ns
V
100
90
IN
As noted in the warning under “Maximum Power Dissipation,”
a high level of input overdrive in a high noninverting gain circuit
can result in a large current flow in the input stage. For differ-
ential input voltages of less than about 1.25 V, this will be inter-
nally limited to less than 20 mA (decreasing with supply voltage).
For input overdrives which result in higher differential input
voltages, power dissipation in the input stage must be consid-
ered. It is recommended that external diode clamps be used in
cases where the differential input voltage is expected to exceed
1.25 V.
V
10
OUT
0%
5V
Figure 44. Pulse Response of Circuit of Figure 41 with
CL = 510 pF, RL = 1 kΩ, RF = RG = 715 Ω, RS = 15 Ω
High Performance Video Line Driver
At a gain of +2, the AD812 makes an excellent driver for a back-
terminated 75 Ω video line. Low differential gain and phase
errors and wide 0.1 dB bandwidth can be realized over a wide
range of power supply voltage. Outstanding gain and group
delay matching are also attainable over the full operating supply
voltage range.
Overload Recovery
There are three important overload conditions to consider.
They are due to input common mode voltage overdrive, input
current overdrive, and output voltage overdrive. When the
amplifier is configured for low closed-loop gains, and its input
common-mode voltage range is exceeded, the recovery time will
be very fast, typically under 10 ns. When configured for a higher
gain, and overloaded at the output, the recovery time will also
be short. For example, in a gain of +10, with 6 dB of input
overdrive, the recovery time of the AD812 is about 10 ns.
R
R
F
G
+V
S
0.1F
75⍀
CABLE
8
75⍀
75⍀
CABLE
V
AD812
OUT
V
75⍀
4
IN
75⍀
0.1F
–V
S
Figure 46. Gain of +2 Video Line Driver (RF = RG from
Table I)
REV. B
–14–
AD812
90
0.4
PHASE
GAIN
G = +2
G = +2
= 150⍀
0
0.3
0.2
0.1
R
= 150⍀
L
R
L
–90
3V
V
= ؎15V
؎5V
S
5V
–180
–270
1
0
0
5V
3V
–1
–0.1
–2
–3
–4
V
= ؎15V
–0.2
S
V
= ؎15V
S
–0.3
–0.4
؎5V
؎5V
5V
–5
–6
–0.5
–0.6
3V
1
10
100
1000
100k
1M
10M
100M
FREQUENCY – Hz
FREQUENCY –MHz
Figure 47. Closed-Loop Gain and Phase vs. Frequency for
the Line Driver
Figure 50. Fine-Scale Gain Flatness vs. Frequency,
Gain = +2, RL = 150 Ω
120
1.0
R
R
R
= 590⍀
= 715⍀
= 750⍀
F
F
F
G = +2
= 150⍀
G = +2
= 150⍀
110
100
90
80
70
60
50
40
30
20
0.8
R
L
R
L
V
= 3V
S
0.6
0.4
PEAKING Յ 1dB
R
= 681⍀
F
0.2
NO PEAKING
0
V
= ؎15V
= 715⍀
S
–0.2
–0.4
–0.6
–0.8
–1.0
R
F
0
2
4
6
8
10
12
14
16
18
20
1
10
100
1000
SUPPLY VOLTAGE – ؎Volts
FREQUENCY – MHz
Figure 48. –3 dB Bandwidth vs. Supply Voltage,
Gain = +2, RL = 150 Ω
Figure 51. Closed-Loop Gain Matching vs. Frequency,
Gain = +2, RL = 150 Ω
DELAY
0.06
0.04
0.02
8
3V
6
5V
؎5V
4
DIFFERENTIAL GAIN
؎15V
2
0.08
0
0.06
DELAY MATCHING
0.4
DIFFERENTIAL PHASE
0.2
0.04
V
= 3V TO ؎15V
S
0
–0.2
–0.4
0.02
0
100k
1M
10M
100M
5
6
7
8
9
10
11
12
13
14
15
FREQUENCY – Hz
SUPPLY VOLTAGE – ؎Volts
Figure 52. Group Delay and Group Delay Matching vs.
Frequency, G = +2, RL = 150 Ω
Figure 49. Differential Gain and Phase vs. Supply Voltage,
Gain = +2, RL = 150 Ω
REV. B
–15–
AD812
Operation Using a Single Supply
90
PHASE
GAIN
The AD812 will operate with total supply voltages from 36 V
down to 2.4 V. With proper biasing (see Figure 53), it can be an
outstanding single supply video amplifier. Since the input and
output voltage ranges extend to within 1 volt of the supply rails,
it will handle a 1.3 V p-p signal on a single 3.3 V supply, or a
3 V p-p signal on a single 5 V supply. The small signal, 0.1 dB
bandwidths will exceed 10 MHz in either case, and the large
signal bandwidths will exceed 6 MHz.
0
V
= 5V
S
0.5
0
–90
–180
–270
–0.5
–1.0
–1.5
–2.0
–2.5
The capacitively coupled cable driver in Figure 53 will achieve
outstanding differential gain and phase errors of 0.07% and 0.06
degrees respectively on a single 5 V supply. Resistor R2, in this
circuit, is selected to optimize the differential gain and phase by
operating the amplifier in its most linear region. To optimize the
circuit for a 3 V supply, a value of 8 kΩ is recommended for R2.
–3.0
–3.5
1
10
100
1000
FREQUENCY – MHz
Figure 54. Closed-Loop Gain and Phase vs. Frequency,
Circuit of Figure 53
649⍀
649⍀
C3
30F
R3
1k⍀
+V
S
C2
1V
50ns
1F
R1
9k⍀
C
OUT
75⍀
CABLE
100
90
8
47F
75⍀
V
IN
C1
2F
V
OUT
AD812
V
IN
75⍀
4
R2
11.8k⍀
V
OUT
Figure 53. Biasing for Single Supply Operation
10
0%
500mV
Figure 55. Pulse Response of the Circuit of Figure 53 with
VS = 5 V
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Plastic DIP
(N-8)
8-Lead Plastic SOIC
(SO-8)
0.39 (9.91)
0.1968 (5.00)
0.1890 (4.80)
8
5
4
0.25
(6.35)
8
1
5
4
0.1574 (4.00)
0.1497 (3.80)
0.2440 (6.20)
0.2284 (5.80)
1
0.325 (8.25)
0.300 (7.62)
0.060 (1.52)
0.015 (0.38)
PIN 1
0.10
0.195 (4.95)
0.115 (2.93)
0.165 ؎0.01
(4.19 ؎0.25)
PIN 1
0.0688 (1.75)
0.0532 (1.35)
0.0196 (0.50)
0.0099 (0.25)
؋
45؇ 0.0098 (0.25)
0.0040 (0.10)
0.125 (3.18)
MIN
0.015 (0.381)
0.008 (0.204)
SEATING
PLANE
0.018 ؎0.003
0.033 (0.84)
NOM
8؇
0؇
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
(0.46 +0.08) (2.54)
BSC
SEATING
PLANE
0.0098 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
REV. B
–16–
相关型号：
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