AD8132ARM-REEL [ADI]
Low-Cost, High-Speed Differential Amplifier; 低成本，高速差分放大器
| 型号： | AD8132ARM-REEL |
| 厂家： | 
ADI |
| 描述： | Low-Cost, High-Speed Differential Amplifier |
| 文件： | 总20页 (文件大小：390K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low-Cost, High-Speed
Differential Amplifier
a
AD8132
FUNCTIONAL BLOCK DIAGRAM
AD8132
FEATURES
High Speed
350 MHz –3 dB Bandwidth
1200 V/ꢀs Slew rate
1
2
3
4
8
7
6
5
–IN
+IN
NC
Resistor-Settable Gain
V
OCM
+
Internal Common-Mode Feedback to Improve Gain
and Phase Balance –68 dB @ 10 MHz
Separate Input to Set the Common-Mode Output
Voltage
V+
V–
–OUT
+OUT
NC = NO CONNECT
Low Distortion –99 dBc SFDR @ 5 MHz 800 ꢁ Load
Low Power 10.7 mA @ 5 V
Power Supply Range +2.7 V to ꢂ5.5 V
APPLICATIONS
Low Power Differential ADC Driver
Differential Gain and Differential Filtering
Video Line Driver
Differential In/Out Level-Shifting
Single-Ended Input to Differential Output Driver
Active Transformer
GENERAL DESCRIPTION
Differential signal processing reduces the effects of ground noise
which plagues ground referenced systems. The AD8132 can be
used for differential signal processing (gain and filtering) through-
out a signal chain, easily simplifying the conversion between
differential and single-ended components.
The AD8132 is a low-cost differential or single-ended input to
differential output amplifier with resistor-settable gain. The
AD8132 is a major advancement over op amps for driving differ-
ential input ADCs or for driving signals over long lines. The
AD8132 has a unique internal feedback feature that provides
output gain and phase matching balanced to –68 dB at 10 MHz,
suppressing harmonics, and reducing radiated EMI.
The AD8132 is available in both SOIC and µSOIC packages for
operation over –40°C to +85°C temperatures.
Manufactured on ADI’s next generation of XFCB bipolar pro-
cess, the AD8132 has a –3 dB bandwidth of 350 MHz and
delivers a differential signal with –99 dBc SFDR at 5 MHz,
despite its low cost. The AD8132 eliminates the need for a
transformer with high-performance ADCs, preserving the low
frequency and dc information. The common-mode level of the
differential output is adjustable by applying a voltage on the VOCM
pin, easily level-shifting the input signals for driving single supply
ADCs. Fast overload recovery preserves sampling accuracy.
6
V
= ꢂ5V
S
G = 1
3
0
V
= 2V p-p
O,dm
R
= 499ꢁ
L,dm
–3
–6
The AD8132 can also be used as a differential driver for the
transmission of high-speed signals over low-cost twisted pair or
coaxial cables. The feedback network can be adjusted to boost
the high-frequency components of the signal. The AD8132 can
be used for either analog or digital video signals or for other high-
speed data transmission. The AD8132 is capable of driving either
cat3 or cat5 twisted pair or coaxial with minimal line attenu-
ation. The AD8132 has considerable cost and performance
improvements over discrete line driver solutions.
–9
–12
1
10
100
1k
FREQUENCY – MHz
Figure 1. Large Signal Frequency Response
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000
(@ 25ꢃC, VS = ꢂ5 V, VOCM = 0 V, G = 1, RL,dm = 499 ꢁ, RF = RG = 348 ꢁ unless
otherwise noted. For G = 2, RL,dm = 200 ꢁ, RF = 1000 ꢁ, RG = 499 ꢁ. Refer to TPC 1 and TPC 10 for test setup and label descriptions. All
specifications refer to single-ended input and differential outputs unless otherwise noted.)
AD8132–SPECIFICATIONS
P
arameter
Conditions
Min
Typ
Max
Unit
ꢂDIN to ꢂOUT Specifications
DYNAMIC PERFORMANCE
–3 dB Large Signal Bandwidth
VOUT = 2 V p-p
VOUT = 2 V p-p, G = 2
VOUT = 0.2 V p-p
VOUT = 0.2 V p-p, G = 2
VOUT = 0.2 V p-p
VOUT = 0.2 V p-p, G = 2
VOUT = 2 V p-p
0.1%, VOUT = 2 V p-p
VIN = 5 V to 0 V Step, G = 2
300
350
190
360
160
90
50
1200
15
5
MHz
MHz
MHz
MHz
MHz
MHz
V/µs
ns
–3 dB Small Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time
Overdrive Recovery Time
1000
ns
NOISE/HARMONIC PERFORMANCE
Second Harmonic
VOUT = 2 V p-p, 1 MHz, RL,dm = 800 Ω
VOUT = 2 V p-p, 5 MHz, RL,dm = 800 Ω
VOUT = 2 V p-p, 20 MHz, RL,dm = 800 Ω
VOUT = 2 V p-p, 1 MHz, RL,dm = 800 Ω
VOUT = 2 V p-p, 5 MHz, RL,dm = 800 Ω
VOUT = 2 V p-p, 20 MHz, RL,dm = 800 Ω
20 MHz, RL,dm = 800 Ω
–96
–83
–73
–102
–98
–67
–76
40
8
1.8
0.01
0.10
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBm
nV/√Hz
pA/√Hz
%
Third Harmonic
IMD
IP3
20 MHz, RL,dm = 800 Ω
Input Voltage Noise (RTI)
Input Current Noise
Differential Gain Error
Differential Phase Error
f = 0.1 MHz to 100 MHz
f = 0.1 MHz to 100 MHz
NTSC, G = 2, RL,dm = 150 Ω
NTSC, G = 2, RL,dm = 150 Ω
Degrees
INPUT CHARACTERISTICS
Offset Voltage (RTI)
VOS,dm = VOUT,dm/2; VDIN+ = VDIN– = VOCM = 0 V
TMIN to TMAX Variation
1.0
10
3
12
3.5
1
3.5
7
mV
µV/°C
µA
MΩ
MΩ
pF
Input Bias Current
Input Resistance
Differential
Common-Mode
Input Capacitance
Input Common-Mode Voltage
CMRR
–7 to +6
–70
V
dB
∆VOUT,dm/∆VIN,cm; ∆VIN,cm
=
1 V;
–60
Resistors Matched to 0.01%
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Current
Maximum ∆VOUT; Single-Ended Output
∆VOUT,cm/∆VOUT,dm; ∆VOUT,dm = 1 V
–3.6 to +3.6
70
–70
V
mA
dB
Output Balance Error
VOCM to ꢂOUT Specifications
DYNAMIC PERFORMANCE
–3 dB Bandwidth
Slew Rate
∆VOCM = 600 mV p-p
∆VOCM = –1 V to +1 V
210
400
MHz
V/µs
DC PERFORMANCE
Input Voltage Range
Input Resistance
Input Offset Voltage
Input Bias Current
VOCM CMRR
3.6
150
1.5
0.5
–68
V
kΩ
mV
µA
dB
VOS,cm = VOUT,cm; VDIN+ = VDIN– = VOCM = 0 V
7
[∆VOUT,dm/∆VOCM]; ∆VOCM
Resistors Matched to 0.01%
∆VOUT,cm/∆VOCM; ∆VOCM
=
1 V;
Gain
=
1 V
0.985
1
1.015
V/V
POWER SUPPLY
Operating Range
Quiescent Current
1.35
11
5.5
13
V
VDIN+ = VDIN– = VOCM = 0 V
TMIN to TMAX Variation
∆VOUT,dm/∆VS; ∆VS = 1 V
12
16
–70
mA
µA/°C
dB
Power Supply Rejection Ratio
–60
OPERATING TEMPERATURE RANGE
–40
+85
°C
Specifications subject to change without notice.
–2–
REV. 0
AD8132
AD8132–SPECIFICATIONS (@ 25ꢃC, VS = 5 V, VOCM = 2.5 V, G = 1, RL,dm = 499 ꢁ, RF = RG = 348 ꢁ unless
otherwise noted. For G = 2, RL,dm = 200 ꢁ, RF = 1000 ꢁ, RG = 499 ꢁ. Refer to TPC 1 and TPC 10 for test setup and label descriptions. All
specifications refer to single-ended input and differential outputs unless otherwise noted.)
P
arameter
Conditions
Min
Typ
Max
Unit
ꢂDIN to ꢂOUT Specifications
DYNAMIC PERFORMANCE
–3 dB Large Signal Bandwidth
VOUT = 2 V p-p
VOUT = 2 V p-p, G = 2
VOUT = 0.2 V p-p
VOUT = 0.2 V p-p, G = 2
VOUT = 0.2 V p-p
VOUT = 0.2 V p-p, G = 2
VOUT = 2 V p-p
0.1%, VOUT = 2 V p-p
250
300
180
360
155
65
50
1000
20
MHz
MHz
MHz
MHz
MHz
MHz
V/µs
ns
–3 dB Small Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time
800
Overdrive Recovery Time
VIN = 2.5 V to 0 V Step, G = 2
5
ns
NOISE/HARMONIC PERFORMANCE
Second Harmonic
VOUT = 2 V p-p, 1 MHz, RL,dm = 800 Ω
VOUT = 2 V p-p, 5 MHz, RL,dm = 800 Ω
VOUT = 2 V p-p, 20 MHz, RL,dm = 800 Ω
VOUT = 2 V p-p, 1 MHz, RL,dm = 800 Ω
VOUT = 2 V p-p, 5 MHz, RL,dm = 800 Ω
VOUT = 2 V p-p, 20 MHz, RL,dm = 800 Ω
20 MHz, RL,dm = 800 Ω
–97
–100
–74
–100
–99
–67
–76
40
8
1.8
0.025
0.15
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBm
nV/√Hz
pA/√Hz
%
Third Harmonic
IMD
IP3
20 MHz, RL,dm = 800 Ω
Input Voltage Noise (RTI)
Input Current Noise
Differential Gain Error
Differential Phase Error
f = 0.1 MHz to 100 MHz
f = 0.1 MHz to 100 MHz
NTSC, G = 2, RL,dm = 150 Ω
NTSC, G = 2, RL,dm = 150 Ω
Degree
INPUT CHARACTERISTICS
Offset Voltage (RTI)
VOS,dm = VOUT,dm/2; VDIN+ = VDIN– = VOCM = 2.5 V
TMIN to TMAX Variation
1.0
3.5
7
mV
µV/°C
µA
MΩ
MΩ
pF
6
3
Input Bias Current
Input Resistance
Differential
Common-Mode
10
3
1
Input Capacitance
Input Common-Mode Voltage
CMRR
–1 to +4
–70
V
dB
∆VOUT,dm/∆VIN,cm; ∆VIN,cm
=
1 V;
–60
Resistors Matched to 0.01%
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Current
Maximum ∆VOUT; Single-Ended Output
∆VOUT,cm/∆VOUT,dm; ∆VOUT,dm = 1 V
1 to 3.7
50
–68
V
mA
dB
Output Balance Error
VOCM to ꢂOUT Specifications
DYNAMIC PERFORMANCE
–3 dB Bandwidth
Slew Rate
∆VOCM = 600 mV p-p
∆VOCM = 1.5 V to 3.5 V
210
340
MHz
V/µs
DC PERFORMANCE
Input Voltage Range
Input Resistance
Input Offset Voltage
Input Bias Current
VOCM CMRR
1 to 3.7
130
5
0.5
–66
V
kΩ
mV
µA
dB
VOS,cm = VOUT,cm; VDIN+ = VDIN– = VOCM = 2.5 V
11
[∆VOUT,dm/∆VOCM]; ∆VOCM = 2.5 1 V;
Resistors Matched to 0.01%
Gain
∆VOUT,cm/∆VOCM; ∆VOCM = 2.5 1 V
0.985
1
1.015
V/V
POWER SUPPLY
Operating Range
Quiescent Current
2.7
9.4
11
12
V
VDIN+ = VDIN– = VOCM = 2.5 V
TMIN to TMAX Variation
∆VOUT,dm/∆VS; ∆VS = 1 V
10.7
10
–70
mA
µA/°C
dB
Power Supply Rejection Ratio
–60
OPERATING TEMPERATURE RANGE
–40
+85
°C
Specifications subject to change without notice.
–3–
REV. 0
AD8132–SPECIFICATIONS
(@ 25ꢃC, VS = 3 V, VOCM = 1.5 V, G = 1, RL,dm = 499 ꢁ, RF = RG = 348 ꢁ unless
otherwise noted. For G = 2, RL,dm = 200 ꢁ, RF = 1000 ꢁ, RG = 499 ꢁ. Refer to TPC 1 and TPC 10 for test setup and label descriptions. All
specifications refer to single-ended input and differential outputs unless otherwise noted.)
P
arameter
Conditions
Min
Typ
Max
Unit
ꢂDIN to ꢂOUT Specifications
DYNAMIC PERFORMANCE
–3 dB Large Signal Bandwidth
VOUT = 1 V p-p
VOUT = 1 V p-p, G = 2
VOUT = 0.2 V p-p
VOUT = 0.2 V p-p, G = 2
VOUT = 0.2 V p-p
350
165
350
150
45
MHz
MHz
MHz
MHz
MHz
MHz
–3 dB Small Signal Bandwidth
Bandwidth for 0.1 dB Flatness
VOUT = 0.2 V p-p, G = 2
50
NOISE/HARMONIC PERFORMANCE
Second Harmonic
VOUT = 1 V p-p, 1 MHz, RL,dm = 800 Ω
VOUT = 1 V p-p, 5 MHz, RL,dm = 800 Ω
VOUT = 1 V p-p, 20 MHz, RL,dm = 800 Ω
VOUT = 1 V p-p, 1 MHz, RL,dm = 800 Ω
VOUT = 1 V p-p, 5 MHz, RL,dm = 800 Ω
VOUT = 1 V p-p, 20 MHz, RL,dm = 800 Ω
–100
–94
–77
–90
–85
–66
dBc
dBc
dBc
dBc
dBc
dBc
Third Harmonic
INPUT CHARACTERISTICS
Offset Voltage (RTI)
Input Bias Current
CMRR
VOS,dm = VOUT,dm/2; VDIN+ = VDIN– = VOCM = 1.5 V
10
3
–60
mV
µA
dB
∆VOUT,dm/∆VIN,cm; ∆VIN,cm
=
0.5 V;
Resistors Matched to 0.01%
VOCM to ꢂOUT Specifications
DC PERFORMANCE
Input Offset Voltage
Gain
VOS,cm = VOUT,cm; VDIN+ = VDIN– = VOCM = 1.5 V
∆VOUT,cm/∆VOCM; ∆VOCM 0.5 V
7
1
mV
V/V
=
POWER SUPPLY
Operating Range
2.7
11
V
Quiescent Current
Power Supply Rejection Ratio
VDIN+ = VDIN– = VOCM = 0 V
∆VOUT,dm/∆VS; ∆VS = 0.5 V
7.25
–70
mA
dB
OPERATING TEMPERATURE RANGE
Specifications subject to change without notice.
–40
+85
°C
–4–
REV. 0
AD8132
ABSOLUTE MAXIMUM RATINGS1, 2
PIN FUNCTION DESCRIPTIONS
Pin No. Name Function
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
VOCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VS
Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . 250 mW
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . 300°C
1
2
–IN
VOCM
Negative Input.
Voltage applied to this pin sets the common-
mode output voltage with a ratio of 1:1. For
example, 1 V dc on VOCM will set the dc bias
level on +OUT and –OUT to 1 V.
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above listed in the operational section of this
specification is not implied. Exposure to Absolute Maximum Ratings for any
extended periods may affect device reliability.
3
4
V+
Positive Supply Voltage.
+OUT Positive Output. Note: the voltage at –DIN is
inverted at +OUT.
–OUT Negative Output. Note: the voltage at +DIN
is inverted at –OUT.
2Thermal resistance measured on SEMI standard 4-layer board.
8-Lead SOIC: θJA = 121°C/W
8-Lead µSOIC: θJA = 142°C/W
5
6
7
8
V–
NC
+IN
Negative Supply Voltage.
No Connect.
Positive Input.
2.0
T
= 150ꢃC
PIN CONFIGURATION
J
8-LEAD SOIC
PACKAGE
1.5
1.0
0.5
0
AD8132
1
2
3
4
8
7
6
5
–IN
+IN
NC
V
OCM
+
V+
V–
8-LEAD
microSOIC
–OUT
+OUT
NC = NO CONNECT
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
AMBIENT TEMPERATURE – ꢃC
Figure 2. Plot of Maximum Power Dissipation vs.
Temperature
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD8132AR
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
8-Lead SOIC
SO-8
AD8132AR-REEL1
AD8132AR-REEL72
AD8132ARM
13" Tape and Reel
7" Tape and Reel
8-Lead µSOIC
13" Tape and Reel
7" Tape and Reel
Evaluation Board
SM-8
AD8132ARM-REEL3
AD8132ARM-REEL72
AD8132-EVAL
NOTES
113" Reels of 2500 each.
27" Reels of 1000 each.
313" Reels of 3000 each.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8132 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–5–
REV. 0
AD8132
–Typical Performance Characteristics
0.5
0.4
2
V
AS SHOWN
V
= 3V
S
S
CF
G = 1
V
= 3V
S
1
0
V
= 5V
V
= 0.2V p-p
S
O,dm
0.3
R
= 499ꢁ
L,dm
348ꢁ
V
= 5V
S
0.2
348ꢁ
0.1ꢀF
0.1
V
= ꢂ5V
S
–1
–2
49.9ꢁ
24.9ꢁ
0.0
499ꢁ
–0.1
–0.2
–0.3
–0.4
–0.5
V
= ꢂ5V
S
348ꢁ
–3
V
AS SHOWN
S
G = 1
348ꢁ
V
= 0.2V p-p
O,dm
–4
–5
R
= 499ꢁ
L,dm
CF
1
10
100
1k
1
10
100
1k
1k
1k
FREQUENCY – MHz
FREQUENCY – MHz
TPC 1. Basic Test Circuit, G = 1
TPC 2. Small Signal Frequency
Response
TPC 3. 0.1 dB Flatness vs. Frequency;
CF = 0 pF
2
1
0.2
3
V
= ꢂ5V
S
V
= 3V
S
V
= 3V
S
0.1
0.0
2
1
V
= 5V
V
= 3V
S
S
V
= 5V
S
V
= 5V
S
0
–1
–2
–3
–4
–5
V
= ꢂ5V
S
0
–1
–2
V
= ꢂ5V
–0.1
–0.2
–0.3
–0.4
–0.5
S
V
= 3V
S
V
= 3V
S
V
G = 1
V
V
R
AS SHOWN
S
V
G = 1
V
V
R
AS SHOWN
S
V
AS SHOWN
–3
S
= 2V p-p FOR V = ꢂ5V, 5V
= 1V p-p FOR V = 3V
O,dm
S
G = 1
= 2V p-p FOR V = ꢂ5V, 5V
= 1V p-p FOR V = 3V
= 499ꢁ
O,dm
O,dm
L,dm
S
O,dm
S
V
= 0.2V p-p
O,dm
S
–4
–5
= 499ꢁ
L,dm
R
= 499ꢁ
L,dm
1
10
100
1k
1
10
100
1k
1
10
100
FREQUENCY – MHz
FREQUENCY – MHz
FREQUENCY – MHz
TPC 4. 0.1 dB Flatness vs. Frequency;
CF = 0.5 pF
TPC 5. Large Signal Frequency
Response; CF = 0 pF
TPC 6. Large Signal Frequency
Response; CF = 0.5 pF
3
3
100
10
1
+85ꢃC
+25ꢃC
R
= 499ꢁ
= 348ꢁ
F
2
2
1
R
F
1
0
0
–1
–2
–40ꢃC
R
= 249ꢁ
F
–1
–2
V
= ꢂ5V
V
= ꢂ5V
S
S
G = 1
–3
–4
–5
G = 1
–3
–4
–5
V
= 2V p-p
V
= 2V p-p
O,dm
O,dm
V
= 5V
S
R
= 499ꢁ
R
R
= 499ꢁ
L,dm
L,dm
V
= ꢂ5V
S
TEMPERATURE AS SHOWN
AS SHOWN
F
0.1
1
10
100
1k
1
10
100
1
10
FREQUENCY – MHz
100
FREQUENCY – MHz
FREQUENCY – MHz
TPC 7. Large Signal Response vs.
Temperature
TPC 8. Large Signal Frequency
Response vs. RF
TPC 9. Closed-Loop Single-Ended
ZOUT vs. Frequency; G = 1
–6–
REV. 0
AD8132
7
6
5
4
3
2
1
6.1
6.0
5.9
5.8
5.7
5.6
5.5
1000ꢁ
V
= ꢂ5V,
+5V
S
499ꢁ
0.1ꢀF
49.9ꢁ
24.9ꢁ
200ꢁ
V
= 3V
S
499ꢁ
V
AS SHOWN
S
V
= 3V, 5V, ꢂ5V
S
G = 2
G = 2
1000ꢁ
V
= 0.2V p-p
V
= 0.2V p-p
O,dm
O,dm
R
= 200ꢁ
R
= 200ꢁ
L,dm
L,dm
1
10
100
1k
1
10
100
1k
FREQUENCY – MHz
FREQUENCY – MHz
TPC 12. 0.1 dB Flatness vs.
Frequency
TPC 10. Basic Test Circuit, G = 2
TPC 11. Small Signal Frequency
Response
7
7
R
= 1.5kꢁ
F
V
= 5V, ꢂ5V
S
6
5
4
3
2
1
6
5
4
3
2
1
R
F
V
= 3V
S
R
= 1.0kꢁ
F
499ꢁ
0.1ꢀF
R
= 499ꢁ
F
49.9ꢁ
24.9ꢁ
200ꢁ
V
G = 2
AS SHOWN
S
V
= 2V p-p FOR
O,dm
O,dm
V
= ꢂ5V
S
499ꢁ
V
= ꢂ5V, 5V
= 1V p-p FOR
= 3V
G = 2
S
V
= 0.2V p-p
V
O,dm
R
F
V
R
= 200ꢁ
S
L,dm
R
= 200ꢁ
R
AS SHOWN
L,dm
F
1
10
100
1k
1
10
100
1k
FREQUENCY – MHz
FREQUENCY – MHz
TPC 13. Large Signal Frequency
Response
TPC 14. Small Signal Frequency
Response vs. RF
TPC 15. Test Circuit for Various
Gains
25
–25
V
= ꢂ5V
S
G = 10, R = 4.99kꢁ
F
R
F
–30
–35
–40
–45
–50
GAIN AS SHOWN
ꢄV
ꢄV
20
15
10
5
= 2V p-p
OUT,dm
OUT,cm
R
R
R
G = 5, R = 2.49kꢁ
/ꢄV
G
L
F
OUT,dm
49.9ꢁ
24.9ꢁ
0.1ꢀF
G = 2, R = 1kꢁ
F
G = 1
L
R
G
G = 1, R = 499ꢁ
F
–55
–60
0
R
F
V
V
= ꢂ5V
–5
–10
–15
G = 2
S
–65
–70
–75
= 2V p-p
G = 1: R = R = 348ꢁ, R = 249ꢁ (R = 498ꢁ)
G = 2: R = 1000ꢁ, R = 499ꢁ, R = 100ꢁ
O, dm
F
G
L
L,dm
R
R
= 200ꢁ
= 499ꢁ
L, dm
F
G
L
(R
= 200ꢁ)
G
L,dm
1
10
100
1k
1
10
100
1k
FREQUENCY – MHz
FREQUENCY – MHz
TPC 18. RTI Output Balance
Error vs. Frequency
TPC 16. Large Signal Response for
Various Gains
TPC 17. Test Circuit for Output
Balance
–7–
REV. 0
AD8132
348ꢁ
2:1 TRANSFORMER
348ꢁ
0.1ꢀF
300ꢁ
HPF
= 50ꢁ
LPF
Z
IN
49.9ꢁ
24.9ꢁ
348ꢁ
300ꢁ
348ꢁ
TPC 19. Harmonic Distortion Test Circuit,
G = 1, RL,dm = 800 Ω
–40
–50
–60
–40
–30
V
R
= 3V
R
V
= 800ꢁ
R
= 800ꢁ
= 1V p-p
S
L,dm
HD3 (V = 5V)
S
L,dm
HD3 (F = 20MHz)
= 2V p-p
= 800ꢁ
V
–40
–50
–60
–70
OUT,dm
L,dm
OUT,dm
–50
–60
HD3 (V = 3V)
S
HD2 (V = ꢂ5V)
HD2 (F = 20MHz)
S
HD2 (V = 3V)
–70
–80
–70
–80
S
HD3 (V = ꢂ5V)
S
HD2 (V = 5V)
S
–80
–90
HD2 (V = 5V)
S
–90
–90
HD3 (F = 5MHz)
–100
–110
–100
–110
–100
–110
HD2 (F = 5MHz)
HD3 (V = 5V)
S
0
10
20
30
40
50
60
70
0.25
0.50
0.75
1.00
1.25
1.50
1.75
0
10
20
30
40
50
60
70
FREQUENCY – MHz
DIFFERENTIAL OUTPUT VOLTAGE – V p-p
FREQUENCY – MHz
TPC 20. Harmonic Distortion vs.
Frequency, G = 1
TPC 21. Harmonic Distortion vs.
Frequency, G = 1
TPC 22. Harmonic Distortion vs.
Differential Output Voltage, G = 1
–40
–40
–50
V
R
= 5V
V
R
= ꢂ5V
V
= 3V
S
S
S
HD3 (F = 20MHz)
= 800ꢁ
V
= 1V p-p
= 800ꢁ
L,dm
L,dm
O,dm
–50
–60
–50
–60
HD3 (F = 20MHz)
HD2 (F = 20MHz)
–60
–70
HD3 (F = 20MHz)
HD2 (F = 20MHz)
–70
–80
–70
–80
–80
HD2 (F = 20MHz)
–90
HD2 (F = 5MHz)
HD3 (F = 5MHz)
HD2 (F = 5MHz)
–90
–90
–100
–100
–110
–100
–110
HD3 (F = 5MHz)
3 4
HD2 (F = 5MHz)
HD3 (F = 5MHz)
–110
0
1
2
3
4
5
6
0
1
2
200 300 400 500 600 700 800 900 1000
– ꢁ
DIFFERENTIAL OUTPUT VOLTAGE – V p-p
DIFFERENTIAL OUTPUT VOLTAGE – V p-p
R
LOAD
TPC 23. Harmonic Distortion vs.
Differential Output Voltage, G = 1
TPC 24. Harmonic Distortion vs.
Differential Output Voltage, G = 1
TPC 25. Harmonic Distortion vs.
LOAD, G = 1
R
–8–
REV. 0
AD8132
–50
–60
–50
–60
V
V
= ꢂ5V
V
V
= 5V
S
S
= 2V p-p
= 2V p-p
OUT,dm
OUT,dm
HD3 (F = 20MHz)
HD2 (F = 20MHz)
HD3 (F = 20MHz)
–70
–80
–70
–80
HD2 (F = 20MHz)
HD2 (F = 5MHz)
HD2 (F = 5MHz)
–90
–90
HD3 (F = 5MHz)
–100
–100
HD3 (F = 5MHz)
–110
–110
200 300 400 500 600 700 800 900 1000
– ꢁ
200 300 400 500 600 700 800 900 1000
– ꢁ
R
R
LOAD
LOAD
TPC 27. Harmonic Distortion vs.
RLOAD, G = 1
TPC 26. Harmonic Distortion vs.
LOAD, G = 1
R
1000ꢁ
2:1 TRANSFORMER
499ꢁ
0.1ꢀF
300ꢁ
HPF
IN
LPF
Z
= 50ꢁ
49.9ꢁ
24.9ꢁ
499ꢁ
300ꢁ
1000ꢁ
TPC 28. Harmonic Distortion Test Circuit, G = 2, RL,dm = 800 Ω
–40
–40
–50
–20
HD3 (V = 5V)
V = 5V
S
R
V
= 800ꢁ
R
V
= 800ꢁ
S
L,dm
L,dm
HD3 (F = 20MHz)
= 1V p-p
R
= 800ꢁ
= 4V p-p
OUT,dm
–50
L,dm
–30
OUT,dm
HD3 (V = 3V)
S
HD2 (V = 5V)
S
–60
–70
–40
–50
–60
–70
HD2 (F = 20MHz)
HD2 (F = 5MHz)
HD3 (V = ꢂ5V)
S
–80
–60
–70
–80
HD2 (V = 5V)
S
–80
–90
–90
–100
–110
–120
HD2 (V = 3V)
S
HD2 (V = ꢂ5V)
S
–100
–110
–90
HD3 (V = 5V)
S
HD3 (F = 5MHz)
–100
0
1
2
3
4
0
10
20
30
40
50
60
70
0
10
20 30
40
50
60 70
80
DIFFERENTIAL OUTPUT VOLTAGE – V p-p
FREQUENCY – MHz
FREQUENCY – MHz
TPC 29. Harmonic Distortion vs.
Frequency, G = 2
TPC 31. Harmonic Distortion vs.
Differential Output Voltage, G = 2
TPC 30. Harmonic Distortion vs.
Frequency, G = 2
–9–
REV. 0
AD8132
–50
–60
–50
–60
–40
V
V
= ꢂ5V
V
V
= 5V
S
V
R
= 5V
S
HD3 (F = 20MHz)
HD2 (F = 20MHz)
HD3 (F = 20MHz)
S
HD3 (F = 20MHz)
HD2 (F = 20MHz)
= 2V p-p
= 2V p-p
OUT,dm
= 800ꢁ
OUT,dm
L,dm
–50
–60
HD2 (F = 20MHz)
–70
–70
–70
–80
–80
HD2 (F = 5MHz)
–80
HD2 (F = 5MHz)
–90
–90
–90
HD3 (F = 5MHz)
–100
–110
–100
–110
–100
–110
HD2 (F = 5MHz)
HD3 (F = 5MHz)
HD3 (F = 5MHz)
200 300 400 500 600 700 800 900 1000
– ꢁ
200 300 400 500 600 700 800 900 1000
– ꢁ
0
1
2
3
4
5
6
R
R
LOAD
DIFFERENTIAL OUTPUT VOLTAGE – V p-p
LOAD
TPC 32. Harmonic Distortion vs.
Differential Output Voltage, G = 2
TPC 33. Harmonic Distortion vs.
RLOAD, G = 2
TPC 34. Harmonic Distortion vs.
R
LOAD, G = 2
45
10
V
R
= ꢂ5V, 5V
S
f
V
= 20MHz
C
V
= ꢂ5V, 5V, 3V
0
S
= 800ꢁ
L,dm
= ꢂ5V
S
40
35
30
25
20
15
R
= 800ꢁ
L,dm
–10
–20
–30
–40
–50
–60
–70
–80
–90
40mV
5ns
0
10
20
30
40
50
60
70
19.5
20
20.5
FREQUENCY – MHz
FREQUENCY – MHz
TPC 37. Small Signal Transient
Response, G = 1
TPC 35. Intermodulation
Distortion, G = 1
TPC 36. Third Order Intercept vs.
Frequency, G = 1
V
V
= 3V
S
V
= 5V
S
C
= 0pF
F
V
= ꢂ5V
S
C
= 0pF
F
= 1.5V p-p
OUT,dm
V
= 2V p-p
OUT,dm
V
= 2V p-p
OUT,dm
C
= 0pF
F
C
= 0.5pF
F
C
= 0.5pF
F
C
= 0.5pF
F
300mV
5ns
400mV
5ns
400mV
5ns
TPC 40. Large Signal Transient
Response, G = 1
TPC 38. Large Signal Transient
Response, G = 1
TPC 39. Large Signal Transient
Response, G = 1
–10–
REV. 0
AD8132
V
= ꢂ5, 5, 3V
V
= 3V
S
S
V
,dm
OUT
V
OUT–
V
OUT+
V
+DIN
40mV
5ns
5ns
300mV
1V
5ns
TPC 41. Large Signal Transient
Response, G = 1
TPC 42. Small Signal Transient
Response, G = 2
TPC 43. Large Signal Transient
Response, G = 2
V
= ꢂ5V
V
= 5, ꢂ5V
V
= ꢂ5V
S
S
S
G = 1
V
= 2V p-p
,dm
O
R
= 499ꢁ
V
,dm
L
,dm
OUT
V
OUT–
V
OUT+
V
+DIN
400mV
5ns
1V
5ns
2mV
5ns
0
5
10 15 20 25 30 35 40
5ns/DIV
TPC 44. Large Signal Transient
Response, G = 2
TPC 45. Large Signal Transient
Response, G = 2
TPC 46. 0.1% Settling Time
0
–10
–20
–30
C
= 0pF
ꢄ V
L
OUT,dm
–PSRR
ꢄ V
S
C
= 5pF
L
348ꢁ
+PSRR (V = ꢂ5V, 5V)
–PSRR (V = ꢂ5V)
S
C
= 20pF
348ꢁ
24.9ꢁ
24.9ꢁ
L
S
+PSRR
–40
–50
49.9ꢁ
C
L
453ꢁ
0.1ꢀF
348ꢁ
24.9ꢁ
–60
–70
–80
–90
348ꢁ
5ns
400mV
0.1
1
10
100
1000
FREQUENCY – MHz
TPC 47. Test Circuit for Cap Load
Drive
TPC 48. Large Signal Transient
Response for Various Capacitor
Loads
TPC 49. PSRR vs. Frequency
–11–
REV. 0
AD8132
–20
–30
–40
6
3
0
V
V
= ꢂ5V
ꢄV
V
= ꢂ5V
S
OUT,cm
ꢄV
S
= 2V p-p
IN,cm
OCM
ꢄV
= 600mV p-p
OCM
348ꢁ
ꢄV
ꢄV
OUT,cm
348ꢁ
249ꢁ
ꢄV
= 2V p-p
OCM
IN,cm
–3
–6
–50
–60
–70
–80
V
OUT,dm
V
OUT, cm
49.9ꢁ
348ꢁ
249ꢁ
–9
ꢄV
ꢄV
OUT,dm
348ꢁ
IN,cm
–12
–15
NOTE: RESISTORS MATCHED TO 0.01%.
1
10
100
1000
1
10
100
1000
FREQUENCY – MHz
FREQUENCY – MHz
TPC 50. CMRR Test Circuit
TPC 51. CMRR vs. Frequency
TPC 52. VOCM Gain Response
1000
–10
ꢄV
ꢄV
= 600mV p-p
OUT,dm
ꢄV
V
V
= ꢂ5V
OCM
S
= –1V TO +1V
OCM
OCM
–20
–30
–40
–50
–60
–70
–80
V
OUT,cm
100
10
1
ꢄV
= 2V p-p
OCM
8nV/ Hz
400mV
5ns
1
10
100
1000
10 100
1k
10k 100k 1M 10M 100M
FREQUENCY – MHz
FREQUENCY – Hz
TPC 53. VOCM Transient Response
TPC 54. VOCM CMRR vs. Frequency
TPC 55. Input Voltage Noise vs.
Frequency
15
13
1000
100
V
(0.5V/DIV)
OUT,dm
V
(1V/DIV)
IN,sm
V
= ꢂ5V
S
11
9
V
= 5V
S
V
= 5V
S
10
V
= 2.5V STEP
IN
G = 2
F
1.8pA/ Hz
7
R
R
= 1kꢁ
= 200ꢁ
L,dm
5ns
V/DIV AS SHOWN
5
1
–50 –30 –10
10
30
50
70
90
10 100
1k
10k 100k 1M 10M 100M
TEMPERATURE – ꢃC
FREQUENCY – Hz
TPC 56. Input Current Noise vs.
Frequency
TPC 57. Overdrive Recovery
TPC 58. Quiescent Current vs.
Temperature
–12–
REV. 0
AD8132
0
–0.5
–1.0
–1.5
–2.0
–2.5
V
= 5V
S
V
= ꢂ5V
S
–40 –20
0
20
40
60
80
100
TEMPERATURE – ꢃC
TPC 59. Differential Offset Voltage vs. Temperature
OPERATIONAL DESCRIPTION
Definition of Terms
Table I indicates the gain from any type of input to either type
of output.
C
F
Table I. Differential and Common-Mode Gains
R
F
Input
VOUT,dm
VOUT,cm
R
G
G
+IN
–OUT
VIN,dm
VIN,cm
VOCM
RF/RG
0
0
0 (By Design)
0 (By Design)
1 (By Design)
+D
IN
R
V
, dm
OUT
V
AD8132
, dm
L
OCM
–D
IN
–IN
+OUT
R
R
F
The differential output (VOUT,dm) is equal to the differential
input voltage (VIN,dm) times RF/RG. In this case, it does not
matter if both differential inputs are driven, or only one output
is driven and the other is tied to a reference voltage, like ground.
As can be seen from the two zero entries in the first column,
neither of the common-mode inputs has any effect on this gain.
C
F
Figure 3. Circuit Definitions
Differential voltage refers to the difference between two node
voltages. For example, the output differential voltage (or
equivalently output differential-mode voltage) is defined as:
The gain from VIN,dm to VOUT,cm is 0 and to first order does not
depend on the ratio matching of the feedback networks. The
common-mode feedback loop within the AD8132 provides a
corrective action to keep this gain term minimized. The term
“balance error” describes the degree to which this gain term
differs from zero.
V
OUT,dm = (V+OUT – V–OUT
)
V
+OUT and V–OUT refer to the voltages at the +OUT and –OUT
terminals with respect to a common reference.
Common-mode voltage refers to the average of two node volt-
ages. The output common-mode voltage is defined as:
The gain from VIN,cm to VOUT,dm does directly depend on the
matching of the feedback networks. The analogous term for this
transfer function, which is used in conventional op amps, is
“common-mode rejection ratio” or CMRR. Thus, if it is desirable
to have a high CMRR, the feedback ratios must be well matched.
V
OUT,cm = (V+OUT + V–OUT)/2
Basic Circuit Operation
One of the more useful and easy to understand ways to use the
AD8132 is to provide two equal-ratio feedback networks. To
match the effect of parasitics, these networks should actually be
comprised of two equal-value feedback resistors, RF and two
equal-value gain resistors, RG. This circuit is diagrammed in
Figure 3.
The gain from VIN,cm to VOUT,cm is also ideally 0, and is first-
order independent of the feedback ratio matching. As in the
case of VIN,dm to VOUT,cm, the common-mode feedback loop
keeps this term minimized.
Like a conventional op amp, the AD8132 has two differential
inputs that can be driven with both a differential-mode input
The gain from VOCM to VOUT,dm is ideally 0 only when the feed-
back ratios are matched. The amount of differential output
signal that will be created by varying VOCM is related to the
degree of mismatch in the feedback networks.
voltage, VIN,dm, and a common-mode input voltage, VIN,cm
.
There is another input, VOCM, which is not present on conven-
tional op amps, but provides another input to consider on the
AD8132. It is totally separate from the above inputs.
VOCM controls the output common-mode voltage VOUT,cm with a
unity-gain transfer function. With equal-ratio feedback networks
(as assumed above), its effect on each output will be the same,
which is another way to say that the gain from VOCM to VOUT,dm
is zero. If not driven, the output common-mode will be at mid-
supplies. It is recommended that a 0.1 µF bypass capacitor be
There are two complementary outputs whose response can be
defined by a differential-mode output, VOUT,dm and a common-
mode output, VOUT,cm
.
connected to VOCM
.
–13–
REV. 0
AD8132
When unequal feedback ratios are used, the two gains associated
with VOUT,dm become nonzero. This significantly complicates
the mathematical analysis along with any intuitive understand-
ing of how the part operates. Some of these configurations will
be in another section.
The feedback factor β1 is for the side that is driven, while the
feedback factor β2 is for the side that is tied to a reference volt-
age, (ground for now). Note also that each feedback factor can
vary anywhere between 0 and 1.
A single-ended-to-differential gain equation can be derived
which is true for all values of β1 and β2:
THEORY OF OPERATION
G = 2 × (1–β1)/(β1 + β2)
The AD8132 differs from conventional op amps by the external
presence of an additional input and output. The additional
input, VOCM, controls the output common-mode voltage. The
additional output is the analog complement of the single output
of a conventional op amp. For its operation, the AD8132 makes
use of two feedback loops as compared to the single loop of
conventional op amps. While this provides significant freedom
to create various novel circuits, basic op amp theory can still be
used to analyze the operation.
This expression is not very intuitive, but some further examples
can provide better understanding of its implications. One obser-
vation that can be made right away is that a tolerance error in β1
does not have the same effect on gain as the same tolerance
error in β2.
Resistorless Differential Amplifier (High Input Impedance
Inverting Amplifier)
The simplest closed-loop circuit that can be made does not require
any resistors and is shown in Figure 7. In this circuit, β1 is equal
to zero, and β2 is equal to one. The gain is equal to two.
One of the feedback loops controls the output common-mode
voltage, VOUT,cm. Its input is VOCM (Pin 2) and the output is the
common-mode, or average voltage, of the two differential outputs
(+OUT and –OUT). The gain of this circuit is internally set to
unity. When the AD8132 is operating in its linear region, this
A more intuitive means to figure the gain is by simple inspec-
tion. +OUT is connected to –IN, whose voltage is equal to the
voltage at +IN under equilibrium conditions. Thus, +VOUT is
equal to VIN, and there is unity gain in this path. Since –OUT
has to swing in the opposite direction from +OUT due to the
common-mode constraint, its effect will double the output
signal and produce a gain of two.
establishes one of the operational constraints: VOUT,cm = VOCM
.
The second feedback loop controls the differential operation.
Similar to an op amp, the gain and gain-shaping of the transfer
function is controllable by adding passive feedback networks. How-
ever, only one feedback network is required to “close the loop” and
fully constrain the operation. But depending on the function
desired, two feedback networks can be used. This is possible as
a result of having two outputs that are each inverted with respect
to the differential inputs.
One useful function that this circuit provides is a high input-
impedance inverter. If +OUT is ignored, there is a unity-gain,
high-input-impedance amplifier formed from +IN to –OUT.
Most traditional op amp inverters have relatively low input
impedances, unless they are buffered with another amplifier.
General Usage of the AD8132
Several assumptions are made here for a first-order analysis, which
are the typical assumptions used for the analysis of op amps:
V
OCM has been assumed to be at midsupply. Since there is
still the constraint from the above discussion that +VOUT must
equal VIN, changing the VOCM voltage will not change +VOUT
(= VIN). Therefore, all of the effect of changing VOCM must
show up at –OUT.
•
The input impedances are arbitrarily large and their loading
effect can be ignored.
•
The input bias currents are sufficiently small so they can be
neglected.
For example, if VOCM is raised by 1 V, then –VOUT must go up
by 2 V. This makes VOUT,cm also go up by 1 V, since it is defined
as the average of the two differential output voltages. This means
that the gain from VOCM to the differential output is two.
•
•
The output impedances are arbitrarily low.
The open-loop gain is arbitrarily large, which drives the
amplifier to a state where the input differential voltage is
effectively zero.
Other ꢅ2 = 1 Circuits
The above simple configuration with β2 = 1 and its gain-of-two
is the highest gain circuit that can be made under this condition.
Since β1 was equal to zero, only higher β1 values are possible.
All of these circuits with higher values of β1 will have gains lower
than two. However, circuits with β1 equal to one are not practical,
because they have no effective input, and result in a gain of 0.
•
Offset voltages are assumed to be zero.
While it is possible to operate the AD8132 with a purely differ-
ential input, many of its applications call for a circuit that has a
single-ended input with a differential output.
For a single-ended-to-differential circuit, the RG of the undriven
input will be tied to a reference voltage. For now this is ground,
and other conditions will be discussed later. Also, the voltage at
VOCM, and hence VOUT,cm will be assumed to be ground for now.
Figure 4 shows a generalized schematic of such a circuit using
an AD8132 with two feedback paths.
To increase β1 from zero, it is necessary to add two resistors in
a feedback network. A generalized circuit that has β1 with a
value higher than zero is shown in Figure 6. A couple of differ-
ent convenient gains that can be created are a gain of 1, when
β1 is equal to 1/3, and a gain of 0.5 when β1 equals 0.6.
In all of these circuits with β2 equal to 1, VOCM serves as the
reference voltage from which to measure the input voltage and
the individual output voltages. In general, when VOCM is varied
in these circuits, a differential output signal will be generated in
addition to VOUT,cm changing the same amount as the voltage
For each feedback network, a feedback factor can be defined,
which is the fraction of the output signal that is fed back to the
opposite-sign input. These terms are:
β1 = RG1/(RG1+ RF1)
β2 = RG2/(RG2 + RF2)
change of VOCM
.
–14–
REV. 0
AD8132
Varying ꢅ2
To compute the total output referred noise for the circuit of
Figure 3, consideration must also be given to the contribution of
the resistors RF and RG. Refer to Table II for estimated output
noise voltage densities at various closed-loop gains.
While the circuit above sets β2 to 1, another class of simple
circuits can be made that set β2 equal to zero. This means that
there is no feedback from +OUT to –IN. This class of circuits is
very similar to a conventional inverting op amp. However, the
AD8132 circuits have an additional output and common-mode
input which can be analyzed separately (see Figure 8).
Table II. Recommended Resistor Values and
Noise Performance for Specific Gains
RG RF
Gain (ꢁ) (ꢁ)
Bandwidth Output Noise Output Noise
With –IN connected to ground, +IN becomes a “virtual ground”
in the same sense that the term is used in conventional op amps.
Both inputs must maintain the same voltage for equilibrium
operation, so if one is set to ground, the other will be driven to
ground. The input impedance can also be seen to be equal to
RG, just as in a conventional op amp.
–3 dB
AD8132 Only AD8132 + RG, RF
1
2
5
10
499 499
360 MHz
16 nV/√Hz 17 nV/√Hz
499 1.0 k 160 MHz
499 2.49 k 65 MHz
499 4.99 k 20 MHz
24.1 nV/√Hz 26.1 nV/√Hz
48.4 nV/√Hz 53.3 nV/√Hz
88.9 nV/√Hz 98.6 nV/√Hz
In this case, however, the positive input and negative output are
used for the feedback network. Since a conventional op amp
does not have a negative output, only its inverting input can be
used for the feedback network. The AD8132 is symmetrical, so the
feedback network on either side can be used to produce the same
results.
Calculating an Application Circuit’s Input Impedance
The effective input impedance of a circuit such as that in Fig-
ure 3, at +DIN and –DIN, will depend on whether the amplifier is
being driven by a single-ended or differential signal source. For
balanced differential input signals, the input impedance (RIN,dm)
between the inputs (+DIN and –DIN) is simply:
Since +IN is a summing junction, by analogy to conventional op
amps, the gain from VIN to –OUT will be –RF/RG. This will hold
true regardless of the voltage on VOCM. And since +OUT will
move the same amount in the opposite direction from –OUT,
the overall gain will be –2 (RF/RG).
R
IN,dm = 2 × RG
In the case of a single-ended input signal (for example if –DIN is
grounded and the input signal is applied to +DIN), the input
impedance becomes:
V
OCM still governs VOUT,cm, so +OUT must be the only output
that moves when VOCM is varied. Since VOUT,cm is the average
of the two outputs, +OUT must move twice as fast and in the
same direction as VOCM to create the proper VOUT,cm. Therefore,
the gain from VOCM to +OUT must be two.
RG
RF
RIN,dm
=
1 −
2 × RG + RF
(
)
In these circuits with β2 equal to zero, the gain can theoretically
be set to any value from close to zero to infinity, just as it can
with a conventional op amp in the inverting mode. However,
practical real-world limitations and parasitics will limit the range
of acceptable gains to more modest values.
The circuit’s input impedance is effectively higher than it would
be for a conventional op amp connected as an inverter because a
fraction of the differential output voltage appears at the inputs
as a common-mode signal, partially bootstrapping the voltage
across the input resistor RG.
ꢅ1 = 0
There is yet another class of circuits where there is no feedback
from –OUT to +IN. This is the case where β1 = 0. The resistorless
differential amplifier described above meets this condition, but
it was presented only with the condition that β2 = 1. Recall that
this circuit had a gain equal to two.
Input Common-Mode Voltage Range in Single Supply
Applications
The AD8132 is optimized for level-shifting “ground” referenced
input signals. For a single-ended input this would imply, for
example, that the voltage at –DIN in Figure 3 would be zero
volts when the amplifier’s negative power supply voltage (at V–)
was also set to zero volts.
If β2 is decreased in this circuit from unity, a smaller part of
+VOUT will be fed back to –IN and the gain will increase. See
Figure 5. This circuit is very similar to a noninverting op amp
configuration, except for the presence of the additional comple-
mentary output. Therefore, the overall gain is twice that of a
noninverting op amp or 2 × (1 + RF2/RG2) or 2 × (1/ β2).
Setting the Output Common-Mode Voltage
The AD8132’s VOCM pin is internally biased at a voltage approxi-
mately equal to the midsupply point (average value of the voltages
on V+ and V–). Relying on this internal bias will result in an
output common-mode voltage that is within about 100 mV of
the expected value.
Once again, varying VOCM will not affect both outputs in the
same way, so in addition to varying VOUT,cm with unity gain,
there will also be an affect on VOUT,dm by changing VOCM
.
In cases where more accurate control of the output common-mode
level is required, it is recommended that an external source,
or resistor divider (with RSOURCE < 10K), be used. The output
common-mode offset specified on pages 2 and 3 assume the
VOCM input is driven by a low impedance voltage source.
Estimating the Output Noise Voltage
Similar to the case of a conventional op amp, the differential
output errors (noise and offset voltages) can be estimated by
multiplying the input referred terms, at +IN and –IN, by the
circuit noise gain. The noise gain is defined as:
RF
RG
GN = 1 +
–15–
REV. 0
AD8132
Driving a Capacitive Load
CIRCUITS
A purely capacitive load can react with the pin and bondwire
inductance of the AD8132 resulting in high frequency ringing in
the pulse response. One way to minimize this effect is to place a
small capacitor across each of the feedback resistors. The added
capacitance should be small to avoid destabilizing the amplifier.
An alternative technique is to place a small resistor in series with
the amplifier’s outputs as shown in TPC 47.
R
+
F1
R
R
G1
G2
R
F2
Figure 4. Typical Four-Resistor Feedback Circuit
LAYOUT, GROUNDING AND BYPASSING
As a high-speed part, the AD8132 is sensitive to the PCB
environment in which it has to operate. Realizing its superior
specifications requires attention to various details of good high-
speed PCB design.
+
V
IN
The first requirement is a good solid ground plane that covers as
much of the board area around the AD8132 as possible. The
only exception to this is that the two input pins (Pins 1 and 8)
should be kept a few mm from the ground plane, and ground
should be removed from inner layers and the opposite side of
the board under the input pins. This will minimize the stray
capacitance on these nodes and help preserve the gain flatness
vs. frequency.
R
F2
R
G2
Figure 5. Typical Circuit with β1 = 0
The power supply pins should be bypassed as close as possible
to the device to the nearby ground plane. Good high-frequency
ceramic chip capacitors should be used. This bypassing should
be done with a capacitance value of 0.01 µF to 0.1 µF for each
supply. Further away, low frequency bypassing should be provided
with 10 µF tantalum capacitors from each supply to ground.
R
+
F1
R
G1
Figure 6. Typical Circuit with β2 = 1
The signal routing should be short and direct in order to avoid
parasitic effects. Wherever there are complementary signals, a
symmetrical layout should be provided to the extent possible to
maximize the balance performance. When running differential
signals over a long distance, the traces on PCB should be close
together or any differential wiring should be twisted together to
minimize the area of the loop that is formed. This will reduce
the radiated energy and make the circuit less susceptible to
interference.
+
V
IN
Figure 7. Resistorless G = 2 Circuit with β1 = 0
R
+
F1
R
G1
V
IN
Figure 8. Typical Circuit with β2 = 0
–16–
REV. 0
AD8132
3V
10kꢁ
3V
3V
+
0.1ꢀF
10ꢀF
348ꢁ
0.1ꢀF
10kꢁ
348ꢁ
0.1ꢀF
1V p-p
60.4ꢁ
60.4ꢁ
AVDD
DRVDD
AINN
AINP
20pF
20pF
49.9ꢁ
DIGITAL
OUTPUTS
AD9203
AD8132
0.1ꢀF
348ꢁ
24.9ꢁ
AVSS
DRVSS
348ꢁ
Figure 9. AD8132 Driving AD9203, a 10-Bit 40 MSPS A/D Converter
APPLICATIONS
A/D Driver
10
FUND
0
f
f
= 40MHz
= 2.5MHz
S
IN
Many of the newer high-speed A/D converters are single-supply
and have differential inputs. Thus, the driver for these devices
should be able to convert from a single-ended to a differential
signal and provide output common-mode level-shifting in
addition to having low distortion and noise. The AD8132 con-
veniently performs these functions when driving the AD9203, a
10-bit, 40 MSPS A/D converter.
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
2ND
5TH
12.5
6TH
8TH
9TH
7TH
In Figure 9 a 1 V p-p signal drives the input of an AD8132
configured for unity gain. Both the AD8132 and the AD9203
are powered from a single 3 V supply. A voltage divider biases
VOCM at midsupply, which in turn drives VOUT,cm to be half the
supply voltage. This is within the common-mode range of the
AD9203.
3RD
4TH
–120
0
2.5
5.0
7.5
10.0
15.0
17.5
20.0
INPUT FREQUENCY – MHz
Between the A/D and the driver is a one-pole, differential filter
that helps to filter some of the noise and assists the switched-
capacitor inputs of the A/D. Each of the A/D inputs will be driven
by a 0.5 V p-p signal that goes from 1.25 V dc to 1.75 V dc.
Figure 10. FFT Response for AD8132 Driving AD9203
Balanced Cable Driver
When driving a twisted pair cable, it is desirable to drive only a
pure differential signal onto the line. If the signal is purely dif-
ferential (i.e., fully balanced), and the transmission line is twisted
and balanced, there will be a minimum radiation of any signal.
Figure 10 is an FFT plot of the performance of the circuit when
running at a clock rate of 40 MSPS and an input frequency of
2.5 MHz.
+5V
+5V
+
10ꢀF
0.1ꢀF
1kꢁ
+
10ꢀF
0.1ꢀF
499ꢁ
49.9ꢁ
1
49.9ꢁ
10ꢀF
100ꢁ
AD8132
50ꢁ
SOURCE
0.1ꢀF
523ꢁ
2
3
AD830
TWISTED
PAIR
7
49.9ꢁ
V
OUT
4
1kꢁ
0.1ꢀF
–5V
5
+
0.1ꢀF
–5V
10ꢀF
+
Figure 11. Balanced Line Driver and Receiver Using AD8132 and AD830
–17–
REV. 0
AD8132
Low-Pass Differential Filter
The complementary electrical fields will mostly be confined to
the space between the two twisted conductors and will not sig-
nificantly radiate out from the cable. The current in the cable will
create magnetic fields that will radiate to some degree. However,
the amount of radiation is mitigated by the twists, because for
each twist, the two adjacent twists will have an opposite polarity
magnetic field. If the twist pitch is tight enough, these small
magnetic field loops will contain most of the magnetic flux,
and the magnetic far-field strength will be negligible.
Similar to an op amp, various types of active filters can be cre-
ated with the AD8132. These can have single-ended inputs and
differential outputs, which can provide an antialias function
when driving a differential A/D converter.
Figure 14 is a schematic of a low-pass, multiple-feedback filter.
The active section contains two poles, and an additional pole is
added at the output. The filter was designed to have a –3 dB
frequency of 1 MHz. The actual –3 dB frequency was measured
to be 1.12 MHz as shown in Figure 15.
Any imbalance in the differential drive signal will appear as a
common-mode signal on the cable. This is the equivalent of a
single wire that is driven with the common-mode signal. In this
case, the wire will act as an antenna and radiate. Thus, in order
to minimize radiation when driving differential twisted pair
cables, the differential drive signal should be very well balanced.
2.15kꢁ
549ꢁ
33pF
2kꢁ
953ꢁ
200pF
200pF
100pF
100pF
V
V
IN
49.9ꢁ
OUT
953ꢁ
2kꢁ
33pF
The common-mode feedback loop in the AD8132 helps to
minimize the amount of common-mode voltage at the output,
and can therefore be used to create a well-balanced differential
line driver. Figure 11 shows an application that uses an AD8132
as a balanced line driver and AD830 as a differential receiver
configured for unity gain. This circuit was operated with 10 m
of Category 5 cable.
24.9ꢁ
549ꢁ
2.15kꢁ
Figure 14. 1 MHz, 3-Pole Differential Output Low-Pass
Multiple Feedback Filter
10
0
Transmit Equalizer
–10
–20
–30
–40
–50
–60
–70
–80
–90
Any length of transmission line will attenuate the signals it carries.
This effect is worse at higher frequencies than at low frequen-
cies. One way to compensate for this is to provide an equalizer
circuit that boosts the higher frequencies in the transmitter
circuit, so that at the receive end of the cable, the attenuation
effects are diminished.
By lowering the impedance of the RG component of the feed-
back network at higher frequency, the gain can be increased at
high frequency. Figure 12 shows a gain-of-two line driver that
has its RGs shunted by 10 pF resistors. The effect of this is shown
in the frequency response plot of Figure 13.
10k
100k
1M
10M
100M
FREQUENCY – Hz
499ꢁ
10pF
Figure 15. Frequency Response of 1 MHz Low-Pass Filter
49.9ꢁ
V
High Common-Mode-Output-Impedance Amplifier
Changing the connection to VOCM (Pin 2) can change the
common-mode from low impedance to high impedance. If
VOCM is actively set to a particular voltage, the AD8132 will try
to force VOUT,cm to the same voltage with a relatively low output
impedance. All the previous analysis assumed that this output
impedance is arbitrarily low enough to drive the load condition
in the circuit.
IN
249ꢁ
249ꢁ
100ꢁ
49.9ꢁ
V
49.9ꢁ
24.9ꢁ
OUT
10pF
499ꢁ
Figure 12. Frequency Boost Circuit
20
10
However, the are some applications that benefit from a high
common-mode output impedance. This can be accomplished
with the circuit shown in Figure 16.
0
–10
–20
–30
–40
–50
–60
–70
R
F
348ꢁ
R
10ꢁ
G
348ꢁ
49.9ꢁ
49.9ꢁ
1kꢁ
1kꢁ
R
G
10ꢁ
348ꢁ
R
F
348ꢁ
–80
10
100
1000
1
FREQUENCY – MHz
Figure 13. Frequency Response for Transmit Boost Circuit
Figure 16. High Common-Mode Output Impedance Differ-
ential Amplifier
–18–
REV. 0
AD8132
VOCM is driven by a resistor divider that “measures” the output
common- mode voltage. Thus, the common-mode output volt-
age takes on the value that is set by the driven circuit. In this
case it comes from the center point of the termination at the
receive end of a 10 m length of Category 5 twisted pair cable.
V
V
DIFF
OCM
Figure 18. Transformer with High Output Impedance
Secondary
If the receive end common-mode voltage is set to “ground,” it
will be well-defined at the receive end. Any common-mode
signal that is picked up over the cable length due to noise, will
appear at the transmit end, and must be “absorbed” by the
transmitter. Thus, it is important that the transmitter have
adequate common-mode output range to absorb the full ampli-
tude of the common-mode signal coupled onto the cable and
thus prevent clipping.
Full-Wave Rectifier
The balanced outputs of the AD8132, along with a couple of
Schottky diodes, can create a very high-speed full-wave rectifier.
Such circuits are useful for measuring ac voltages and other
computational tasks.
Figure 19 shows the configuration of such a circuit. Each of the
AD8132 outputs drives the anode of an HP 2835 Schottky diode.
These Schottky diodes were chosen for their high-speed opera-
tion. At lower frequencies (approximately lower than 10 MHz),
a silicon signal diode, like a 1N4148 can be used. The cathodes
of the two diodes are connected together and this output node is
connected to ground by a 50 Ω resistor.
Another way to look at this is that the circuit performs what is
sometimes called “transformer action.” One main difference is
that the AD8132 passes dc while transformers do not.
A transformer can also be easily configured to have either a high
or low common-mode output impedance. If the transformer’s
center tap is connected to a solid voltage reference, it will set the
common-mode voltage on the secondary side of the transformer.
In this case, if one of the differential outputs is grounded, the
other output will have only half of the differential output signal.
This keeps the common-mode voltage at ground, where it is
required to be due to the center tap connection. This is analo-
gous to the AD8132 operating with a low output impedance
common-mode. See Figure 17.
+5V
R
F1
348ꢁ
R
348ꢁ
G1
V
IN
R
T1
49.9ꢁ
R
R
T2
G2
HP2835
24.9ꢁ
348ꢁ
R
V
F2
OUT
R
348ꢁ
L
5V
100ꢁ
–5V
10kꢁ
CR1
V
V
DIFF
OCM
Figure 19. Full-Wave Rectifier
Figure 17. Transformer Whose Low Output Impedance
Secondary Is Set at VOCM
The diodes should be operated such that they are slightly forward-
biased when the differential output voltage is zero. For the
Schottky diodes, this is about 400 mV. The forward biasing can
be conveniently adjusted by CR1, which, in this circuit, raises
and lowers VOUT,CM without creating a differential output voltage.
If the center tap of the secondary of a transformer is allowed to
float (or there is no center tap), the transformer will have a high
common-mode output impedance. This means that the common-
mode of the secondary will be determined by what it is connected
to, and not by anything to do with the transformer itself.
One advantage of this circuit is that the feedback loop is never
momentarily opened while the diodes reverse their polarity within
the loop. This is the scheme that is sometimes used for full-wave
rectifiers that use conventional op amps. These conventional
circuits do not work well at frequencies above about 1 MHz.
If one of the differential ends of the transformer is grounded, the
other end will swing with the full output voltage. This means
that the common-mode of the output voltage is one-half of the
differential output voltage. But this shows that the common-mode
is not forced via a low impedance to a given voltage. The common-
mode output voltage can easily be changed to any voltage through
its other output terminals.
If there is not enough forward bias (VOUT,cm too low), the lower
sharp cusps of the full-wave rectified output waveform will be
rounded off. Also, as the frequency increases, there tends to be
some rounding of the lower cusps. The forward bias can be
increased to yield sharper cusps at higher frequencies.
The AD8132 can exhibit the same performance when one of the
outputs in Figure 16 is grounded. The other output will swing
at the full differential output voltage. The common-mode signal
is “measured” by the voltage divider across the outputs and input
to VOCM. This then drives VOUT,cm to the same level. At higher
frequencies, it is important to minimize the capacitance on the
VOCM node or else phase shifts can compromise the performance.
The voltage divider resistances can also be lowered for better
frequency response.
There is not a reliable, entirely quantifiable, means to measure
the performance of a full-wave rectifier. Since the ideal wave-
form has periodic sharp discontinuities, it should have (mostly
even) harmonics that have no upper bound on the frequency.
However, for a practical circuit, as the frequency increases, the
higher harmonics become attenuated and the sharp cusps that
are present at low frequencies become significantly rounded.
–19–
REV. 0
AD8132
The circuit was run at a frequency up to 300 MHz and, while
it was still functional, the major harmonic that remained in
the output was the second. This made it look like a sine
wave at 600 MHz. Figure 20 is an oscilloscope plot of the
output when driven by a 100 MHz, 2.5 V p-p input.
1V
Sometimes a second harmonic generator is actually useful, as
for creating a clock to oversample a DAC by a factor of two.
If the output of this circuit is run through a low-pass filter, it
can be used as a second harmonic generator.
100mV
2ns
Figure 20. Full-Wave Rectifier Response with
100 MHz Input
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead SOIC
(SO-8)
0.1968 (5.00)
0.1890 (4.80)
8
1
5
4
0.2440 (6.20)
0.2284 (5.80)
0.1574 (4.00)
0.1497 (3.80)
PIN 1
0.0196 (0.50)
0.0099 (0.25)
0.0500 (1.27)
BSC
ꢆ 45ꢃ
0.0688 (1.75)
0.0532 (1.35)
0.0098 (0.25)
0.0040 (0.10)
8ꢃ
0ꢃ
0.0500 (1.27)
0.0160 (0.41)
0.0192 (0.49)
0.0138 (0.35)
0.0098 (0.25)
0.0075 (0.19)
SEATING
PLANE
8-Lead microSOIC
(SM-8)
0.122 (3.10)
0.114 (2.90)
8
5
4
0.122 (3.10)
0.114 (2.90)
0.199 (5.05)
0.187 (4.75)
1
PIN 1
0.0256 (0.65) BSC
0.120 (3.05)
0.112 (2.84)
0.120 (3.05)
0.112 (2.84)
0.043 (1.09)
0.037 (0.94)
0.006 (0.15)
0.002 (0.05)
33ꢃ
0.018 (0.46)
0.008 (0.20)
27ꢃ
0.028 (0.71)
0.016 (0.41)
0.011 (0.28)
0.003 (0.08)
SEATING
PLANE
–20–
REV. 0
相关型号：
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