AD8133ACP-R2 [ADI]
Triple Differential Driver With Output Pull-Down; 三重差分驱动器，输出下拉
| 型号： | AD8133ACP-R2 |
| 厂家： | 
ADI |
| 描述： | Triple Differential Driver With Output Pull-Down |
| 文件： | 总16页 (文件大小：486K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Triple Differential Driver
With Output Pull-Down
AD8133
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Triple high speed fully differential driver
225 MHz −3 dB large signal bandwidth
24
23
22
21
20
19
Easily drives 1.4 V p-p video signal into source-terminated
100 Ω UTP cable
1600 V/µs slew rate
OPD
1
2
3
4
5
18
17
V
V
C
OCM
S+
AD8133
V
S–
Fixed internal gain of 2
–IN A
+IN A
16 –IN C
15 +IN C
Internal common-mode feedback network
Output balance error −60 dB @ 50 MHz
Differential input and output
B
V
14
V
S–
A
C
S–
Differential-to-differential or single-ended-to-differential
operation
–OUT A
6
13 –OUT C
7
8
9
10
11
12
Adjustable output common-mode voltage
Output pull-down feature for line isolation
Low distortion: 64 dB SFDR @ 10 MHz on 5 V supply,
RL, dm = 200 Ω
Figure 1.
0
Low offset: 4 mV typical output referred on 5 V supply
Low power: 26 mA @ 5 V for three drivers
∆V
= 2V p-p
OUT, dm
OUT, cm
–10 ∆V
/∆V
OUT, dm
Wide supply voltage range: +5 V to 5 V
–20
V
= ±5V
Available in space-saving packaging: 4 mm × 4 mm LFCSP
S
–30
–40
–50
–60
APPLICATIONS
V
= +5V
KVM (keyboard-video-mouse) networking
UTP (unshielded twisted pair) driving
Differential signal multiplexing
S
–70
–80
–90
GENERAL DESCRIPTION
–100
1
10
FREQUENCY (MHz)
100
500
The AD8133 is a major advancement beyond using discrete
op amps for driving differential RGB signals over twisted pair
cable. The AD8133 is a triple, low cost differential or single-
ended input to differential output driver, and each amplifier has
a fixed gain of 2 to compensate for the attenuation of line ter-
mination resistors. The AD8133 is specifically designed for RGB
signals but can be used for any type of analog signals or high speed
data transmission. The AD8133 is capable of driving either Cate-
gory 5 unshielded twisted pair (UTP) cable or differential printed
circuit board transmission lines with minimal signal degradation.
Figure 2. Output Balance vs. Frequency
Manufactured on Analog Devices’ next generation XFCB bipo-
lar process, the AD8133 has a large signal bandwidth of
225 MHz and a slew rate of 1600 V/µs. The AD8133 has an
internal common-mode feedback feature that provides output
amplitude and phase matching that is balanced to −60 dB at
50 MHz, suppressing harmonics and minimizing radiated elec-
tromagnetic interference (EMI).
The outputs of the AD8133 can be set to a low voltage state to
be used with series diodes for line isolation, allowing easy dif-
ferential multiplexing over the same twisted pair cable. The
AD8133 driver can be used in conjunction with the AD8129
and AD8130 differential receivers.
The output common-mode level is easily adjustable by applying
a voltage to the VOCM input pin. The VOCM input can also be used
to transmit signals on the output common-mode voltages.
The AD8133 is available in a 24-lead LFCSP package and can
operate over the temperature range of −40°C to +85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
AD8133
TABLE OF CONTENTS
Specifications..................................................................................... 3
Driving a Capacitive Load......................................................... 13
Output Pull-Down (OPD) ........................................................ 13
Output Common-Mode Control ............................................. 13
Applications..................................................................................... 14
Driving RGB Video Signals Over Category-5 UTP Cable.... 14
Output Pull-Down ..................................................................... 15
KVM Networks........................................................................... 15
Layout and Power Supply Decoupling Considerations .... 15
Amplifier-to-Amplifier Isolation ............................................. 15
Exposed Paddle (EP).................................................................. 15
Outline Dimensions....................................................................... 16
Ordering Guide .......................................................................... 16
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 12
Definition of Terms.................................................................... 12
Analyzing an Application Circuit............................................. 12
Closed-Loop Gain ...................................................................... 12
Calculating an Application Circuit’s Input Impedance ......... 13
Input Common-Mode Voltage Range in Single-Supply
Applications .................................................................................. 13
REVISION HISTORY
7/04—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
AD8133
SPECIFICATIONS
VS = 5V, VOCM = 0 V @ 25°C, RL, dm = 200 Ω, unless otherwise noted. TMIN to TMAX = −40°C to +85°C.
Table 1.
Parameter
Conditions
Min
Typ
Max
Unit
DIFFERENTIAL INPUT PERFORMANCE
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
−3 dB Large Signal Bandwidth
Bandwidth for 0.1 dB Flatness
VO = 0.2 V p-p
VO = 2 V p-p
VO = 0.2 V p-p
VO = 2 V p-p
VO = 2 V p-p, 25% to 75%
VO = 2 V Step
450
225
60
55
1600
15
MHz
MHz
MHz
MHz
V/µs
ns
Slew Rate
Settling Time to 0.1%
Isolation between Amplifiers
DIFFERENTIAL INPUT CHARACTERISTICS
Input Common-Mode Voltage Range
Input Resistance
f = 10 MHz, between Amplifiers A and B
81
dB
−5 to +5
1.5
1.13
1
V
Differential
Single-Ended Input
Differential
kΩ
kΩ
pF
dB
Input Capacitance
DC CMRR
∆VOUT, dm/∆VIN, cm, ∆VIN, cm = 1 V
−50
DIFFERENTIAL OUTPUT CHARACTERISTICS
Differential Signal Gain
Output Voltage Swing
Output Offset Voltage
Output Offset Drift
∆VOUT, dm/∆VIN, dm; ∆VIN, dm = 1 V
Each Single-Ended Output
1.925
VS− + 1.9
−24
1.960
2.000
VS+ – 1.6
+24
V/V
V
mV
µV/°C
dB
dB
nV/√Hz
mA
+4
30
−60
−70
25
TMIN to TMAX
∆VOUT, cm/∆VIN, dm, ∆VOUT, dm = 2 V p-p, f = 50 MHz
DC
f = 1 MHz
Output Balance Error
−58
Output Voltage Noise (RTO)
Output Short-Circuit Current
VOCM to VO, cm PERFORMANCE
VOCM DYNAMIC PERFORMANCE
−3 dB Bandwidth
90
∆VOCM = 100 mV p-p
VOCM = −1 V to +1 V, 25% to 75%
∆VOCM = 1 V
330
1000
0.995
MHz
V/µs
V/V
Slew Rate
DC Gain
0.980
−15
1.005
+15
VOCM INPUT CHARACTERISTICS
Input Voltage Range
Input Resistance
Input Offset Voltage
Input Offset Voltage Drift
DC CMRR
3.1
70
−6
50
−42
V
kΩ
mV
µV/°C
dB
TMIN to TMAX
∆VOUT, dm/∆VOCM, ∆VOCM = 1 V
POWER SUPPLY
Operating Range
+4.5
6
V
Quiescent Current
PSRR
28
−84
29
−76
mA
dB
∆VOUT, dm/∆VS; ∆VS = 1 V
OUTPUT PULL-DOWN PERFORMANCE
OPD Input Low Voltage
OPD Input High Voltage
OPD Input Bias Current
OPD Assert Time
VS− to VS+ − 4.15
VS+ − 3.15 to VS+
67
100
100
V
V
µA
ns
ns
V
90
OPD De-Assert Time
Output Voltage When OPD Asserted
Each Output, OPD Input @ VS+
VS− + 0.86
VS− + 0.90
Rev. 0 | Page 3 of 16
AD8133
VS = 5 V, VOCM = 2.5 V @ 25°C, RL, dm = 200 Ω, unless otherwise noted. TMIN to TMAX = −40°C to +85°C.
Table 2.
Parameter
Conditions
Min
Typ
Max
Unit
DIFFERENTIAL INPUT PERFORMANCE
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
−3 dB Large Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
VO = 0.2 V p-p
VO = 2 V p-p
VO = 0.2 V p-p
VO = 2 V p-p, 25% to 75%
VO = 2 V Step
400
200
50
1400
14
MHz
MHz
MHz
V/µs
ns
Settling Time to 0.1%
Isolation Between Amplifiers
DIFFERENTIAL INPUT CHARACTERISTICS
Input Common-Mode Voltage Range
Input Resistance
f = 10 MHz, between Amplifiers A and B
75
dB
0 to 5
1.5
1.13
1
V
Differential
Single-Ended Input
Differential
kΩ
kΩ
pF
dB
Input Capacitance
DC CMRR
∆VOUT, dm/∆VIN, cm, ∆VIN, cm = 1 V
−50
DIFFERENTIAL OUTPUT CHARACTERISTICS
Differential Signal Gain
Output Voltage Swing
Output Offset Voltage
Output Offset Drift
∆VOUT, dm/∆VIN, dm; ∆VIN, dm = 1 V
Each Single-Ended Output
1.925
VS− + 1.25
−24
1.960
2.000
VS+ − 1.15
+24
V
mV
µV/°C
dB
dB
+4
30
−60
−70
25
TMIN to TMAX
∆VOUT, cm/∆VIN, dm, ∆VOUT, dm = 2 V p-p, f = 50 MHz
DC
f = 1 MHz
Output Balance Error
−58
Output Voltage Noise (RTO)
Output Short-Circuit Current
VOCM PERFORMANCE
VOCM DYNAMIC PERFORMANCE
−3 dB Bandwidth
nV/√Hz
mA
90
∆VOCM = 100 mV p-p
VOCM = −1 V to +1 V, 25% to 75%
∆VOCM = 1 V, TMIN to TMAX
290
700
0.995
MHz
V/µs
V/V
Slew Rate
DC Gain
0.980
−15
1.005
+15
VOCM INPUT CHARACTERISTICS
Input Voltage Range
Input Resistance
Input Offset Voltage
Input Offset Voltage Drift
DC CMRR
1.25 to 3.85
70
+2
50
−42
V
kΩ
mV
µV/°C
dB
TMIN to TMAX
∆VO, dm/∆VOCM; ∆VOCM = 1 V
POWER SUPPLY
Operating Range
+4.5
6
V
Quiescent Current
PSRR
26
−84
27
−76
mA
dB
∆VOUT, dm/∆VS; ∆VS = 1 V
OUTPUT PULL-DOWN PERFORMANCE
OPD Input Low Voltage
OPD Input High Voltage
OPD Input Bias Current
OPD Assert Time
VS− to VS+ − 3.85
VS+ − 2.85 to VS+
63
100
100
V
V
µA
ns
ns
V
80
OPD De-Assert Time
Output Voltage When OPD Asserted
Each Output, OPD Input @ VS+
VS− + 0.79
VS− + 0.82
Rev. 0 | Page 4 of 16
AD8133
ABSOLUTE MAXIMUM RATINGS
The power dissipated in the package (PD) is the sum of the
Table 3.
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). The load current consists of differential
and common-mode currents flowing to the loads, as well as
currents flowing through the internal differential and common-
mode feedback loops. The internal resistor tap used in the
common-mode feedback loop places a 4 kΩ differential load on
the output. RMS output voltages should be considered when
dealing with ac signals.
Parameter
Rating
Supply Voltage
12 V
All VOCM
VS
Power Dissipation
Input Common-Mode Voltage
Storage Temperature
Operating Temperature Range
Lead Temperature Range
(Soldering 10 sec)
See Figure 3
VS
−65°C to +125°C
−40°C to +85°C
300°C
Junction Temperature
150°C
Airflow reduces θJA. Also, more metal directly in contact with
the package leads from metal traces, through holes, ground,
and power planes reduces the θJA. The exposed paddle on the
underside of the package must be soldered to a pad on the PCB
surface that is thermally connected to a copper plane in order to
achieve the specified θJA.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at these or any
other conditions above those indicated in the operational sec-
tion of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Figure 3 shows the maximum safe power dissipation in the
package versus ambient temperature for the 24-lead LFCSP
(70°C/W) package on a JEDEC standard 4-layer board with the
underside paddle soldered to a pad that is thermally connected
to a PCB plane. θJA values are approximations.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, i.e., θJA is specified
for the device soldered in a circuit board in still air.
Table 4. Thermal Resistance with the Underside Pad
Connected to the Plane
4.0
3.5
Package Type/PCB Type
θJA
Unit
24-Lead LFCSP/4-Layer
70
°C/W
3.0
2.5
2.0
Maximum Power Dissipation
The maximum safe power dissipation in the AD8133 package is
limited by the associated rise in junction temperature (TJ) on
the die. At approximately 150°C, which is the glass transition
temperature, the plastic changes its properties. Even temporarily
exceeding this temperature limit may change the stresses that
the package exerts on the die, permanently shifting the para-
metric performance of the AD8133. Exceeding a junction tem-
perature of 175°C for an extended period of time can result in
changes in the silicon devices potentially causing failure.
1.5
LFCSP
1.0
0.5
0
–40
–20
0
20
40
60
80
AMBIENT TEMPERATURE (°C)
Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features proprie-
tary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic
discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of
functionality.
Rev. 0 | Page 5 of 16
AD8133
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
24
23
22
21
20
19
OPD
1
2
3
4
5
18
17
V
V
C
OCM
S+
AD8133
V
S–
–IN A
+IN A
16 –IN C
15 +IN C
B
V
14
V
S–
A
C
S–
–OUT A
6
13 –OUT C
7
8
9
10
11
12
Figure 4. 24-Lead LFCSP
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
OPD
Output Pull-Down
2, 5, 14, 21
3
4
6
VS−
−IN A
+IN A
Negative Power Supply Voltage
Inverting Input, Amplifier A
Noninverting Input, Amplifier A
Negative Output, Amplifier A
Positive Output, Amplifier A
Positive Power Supply Voltage
Positive Output, Amplifier B
Negative Output, Amplifier B
Positive Output, Amplifier C
Negative Output, Amplifier C
Noninverting Input, Amplifier C
Inverting Input, Amplifier C
−OUT A
+OUT A
VS+
+OUT B
−OUT B
+OUT C
−OUT C
+IN C
7
8, 11, 17, 24
9
10
12
13
15
16
18
19
20
22
23
−IN C
VOCM
VOCM
VOCM
+IN B
−IN B
C
B
A
Voltage Applied to This Pin Controls Output Common-Mode Voltage, Amplifier C
Voltage Applied to This Pin Controls Output Common-Mode Voltage, Amplifier B
Voltage Applied to This Pin Controls Output Common-Mode Voltage, Amplifier A
Noninverting Input, Amplifier B
Inverting Input, Amplifier B
+5V
V
S+
0.1µF ON ALL V PINS
S+
AD8133
1.5kΩ
50Ω
50Ω
750Ω
53.6Ω
53.6Ω
–
+
V
R
200Ω V
OUT, dm
V
TEST
L, dm
OCM
–
+
TEST
SIGNAL
SOURCE
750Ω
1.5kΩ
MIDSUPPLY
V
S–
0.1µF ON ALL V PINS
S–
–5V
Figure 5. Basic Test Circuit
Rev. 0 | Page 6 of 16
AD8133
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise noted, RL, dm = 200 Ω, VS = 5 V, TA = 25°C, VOCMA = VOCMB = VOCMC = 0 V. Refer to the basic test circuit in Figure 5 for
the definition of terms.
9
6
3
9
6
3
–40°C
25°C
85°C
25°C
–40°C
85°C
0
0
V
= 2V p-p
OUT, dm
V
= 200mV p-p
10
OUT, dm
–3
–3
1
100
FREQUENCY (MHz)
1000
1
10
100
1000
FREQUENCY (MHz)
Figure 6. Small Signal Frequency Response at Various Temperatures
Figure 9. Large Signal Frequency Response at Various Temperatures
9
6.9
6.8
6.7
V
= ±5V
S
6
3
0
V
= 2V p-p
OUT, dm
6.6
6.5
6.4
6.3
6.2
V
= +5V
S
V
= 200mV p-p
OUT, dm
–3
–6
6.1
6.0
5.9
V
= 2V p-p
OUT, dm
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 7. Large Signal Frequency Response for Various Power Supplies
Figure 10. 0.1 dB Flatness Response
–30
–30
–40
–50
–60
–70
–80
V
= +5V
S
V = +5V
S
V
= 2V p-p
OUT, dm
V
= 2V p-p
OUT, dm
–40
–50
–60
–70
–80
R
= 200Ω
L, dm
R
= 200Ω
L, dm
–90
–100
–110
R
= 1000Ω
L, dm
R
= 1000Ω
L, dm
–90
–120
–130
–100
0.1
1
10
FREQUENCY (MHz)
100
0.1
1
10
FREQUENCY (MHz)
100
Figure 8. Second Harmonic Distortion at VS = 5 V at Various Loads
Figure 11. Third Harmonic Distortion at VS = 5 V at Various Loads
Rev. 0 | Page 7 of 16
AD8133
–30
–40
–50
–30
–40
V
= 2V p-p
V
= 2V p-p
OUT, dm
OUT, dm
–50
–60
R
= 200Ω
L, dm
–60
–70
–80
R
= 200Ω
L, dm
–70
–80
–90
–90
–100
–110
R
= 1000Ω
L, dm
–100
R
= 1000Ω
L, dm
–110
–120
–130
–120
0.1
1
10
FREQUENCY (MHz)
100
0.1
1
10
FREQUENCY (MHz)
100
Figure 12. Second Harmonic Distortion at VS = 5 V at Various Loads
Figure 15. Third Harmonic Distortion at VS = 5 V at Various Loads
200
V
= 2V p-p
OUT, dm
V
= 200mV p-p
V
= +5V
V
= +5V
OUT, dm
S
S
1.0
0.5
100
50
V
= ±5V
S
V
= ±5V
S
0
–0.5
–1.0
0
–50
–100
–200
5ns/DIV
5ns/DIV
Figure 16. Large Signal Transient Response
for Various Power Supply Voltages
Figure 13. Small Signal Transient Response
for Various Power Supply Voltages
10
2 × V
IN, dm
8
6
V
IN, dm
250mV/DIV
V
OUT, dm
4
2
0
+0.1%
–0.1%
SETTLING TIME ERROR
2mV/DIV
–2
–4
–6
–8
10ns/DIV
100ns/DIV
–10
t
= 0
Figure 14. Overdrive Recovery
Figure 17. Settling Time (0.1%)
Rev. 0 | Page 8 of 16
AD8133
–30
–32
–34
–36
–38
–40
–42
–44
2
1
R
= ∞
V
/V
L, dm
OUT, dm IN, dm WITH
OUTPUT PULL-DOWN
SINGLE-ENDED OUTPUT
0
–1
–2
V
2V p-p
I, dm =
OUTPUT
PULL-DOWN
–3
–4
–5
+5
–5
–46
–48
–50
100ns/DIV
V
ON
0.1
1
10
100
1000
t
= 0
FREQUENCY (MHz)
Figure 18. Output Pull-Down Response
Figure 21. Output Pull-Down Isolation vs. Frequency
1000
0
–10
–20
–30
∆
∆
V
= 2V p-p
OUT, dm
V
/∆V
OUT, cm OUT, dm
V
= ±5V
S
–40
–50
–60
100
V
= +5V
S
–70
–80
–90
10
10
–100
100
1k
10k
100k
1M
10M
100M
1
10
FREQUENCY (MHz)
100
500
FREQUENCY (Hz)
Figure 19. Output-Referred Voltage Noise vs. Frequency
Figure 22. Output Balance vs. Frequency
–30
–35
–40
–45
–50
–55
10
∆V
/∆V
OUT, dm S
∆
V
= 200mV p-p
IN, cm
0
–10
–20
–30
–40
–50
–60
–70
–80
PSRR–
PSRR–
∆
V
/∆V
OUT, dm IN, cm
–60
–65
–90
–100
1
10
100
1000
0.1
1
10
FREQUENCY (MHz)
100
1000
FREQUENCY (MHz)
Figure 20. Common-Mode Rejection Ratio vs. Frequency
Figure 23. Power Supply Rejection Ratio vs. Frequency
Rev. 0 | Page 9 of 16
AD8133
–40
30
29
28
27
AMPLIFIER A TO
AMPLIFIER B
V
= 200mV p-p
IN, dm
V
= ±5V
S
∆V
B/
∆V
A
OUT, dm
IN, dm
–50
–60
–70
26
25
V
= 2V p-p
IN, dm
V = +5V
S
–80
–90
24
23
22
–100
–110
21
20
1
10
100
1000
1000
1000
–40 –30
–10
10
30
50
70
85
FREQUENCY (MHz)
TEMPERATURE (
°
C)
Figure 24. Amplifier-to-Amplifier Isolation vs. Frequency
Figure 27. Power Supply Current vs. Temperature
1.5
1.0
0.5
0
–20
V = 2V p-p
OUT, cm
∆
V
= 200mV p-p
OCM
V
= +5V
S
–30
–40
–50
V
= ±5V
S
∆
V
/∆V
OUT, dm OCM
–60
–70
–80
–0.5
–1.0
–1.5
5ns/DIV
1
10
100
FREQUENCY (MHz)
Figure 28. VOCM Large Signal Transient Response
for Various Power Supply Voltages
Figure 25 VOCM CMRR vs. Frequency
1.0
2
1
∆
V
/∆V
OUT, cm OCM
0.8
0.6
0.4
0.2
0
V
= ±5V
S
0
–1
–2
–3
V
= +5V
S
–4
–5
–0.2
–0.4
–6
–7
–0.6
–0.8
–1.0
–8
–9
V
V
= 100mV p-p
TAKEN SINGLE ENDED
OUT, cm
OUT, cm
–10
–5
–4
–3
–2
–1
0
1
2
3
4
5
1
10
100
FREQUENCY (MHz)
V
INPUT VOLTAGE
OCM
Figure 26. VOCM Frequency Response for
Various Power Supply Voltages
Figure 29. VOCM Bias Current vs. VOCM Input Voltage
Rev. 0 | Page 10 of 16
AD8133
4.5
3.5
2.5
100
10
5
1.5
0.5
4
3
2
V
= +5V
V = ±5V
S
S
–0.5
–1.5
–2.5
1
0
1
V
= ±5V
S
–3.5
–4.5
V
= +5V
10
S
0.1
0.01
100
1000
LOAD (Ω)
10000
0.1
1
100
1000
FREQUENCY (MHz)
Figure 32. Single-Ended Output Impedance Magnitude vs. Frequency
Figure 30. Output Saturation Voltage vs. Single-Ended Output Load
–1.0
1.5
4.0
3.5
1.0
–1.5
V
= +5V
S
V
= ±5V
S
3.0
0.5
0
–2.0
–2.5
5.0
4.5
2.5
2.0
V
= +5V
S
V
= ±5V
15
–3.0
–3.5
S
1.5
1.0
4.0
3.5
–40
–25
–5
35
55
75 85
–40
–25
–5
15
35
55
75 85
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 33. Negative Output Saturation Voltage vs. Temperature
Figure 31. Positive Output Saturation Voltage vs. Temperature
Rev. 0 | Page 11 of 16
AD8133
THEORY OF OPERATION
Each differential driver in the AD8133 differs from a conven-
tional op amp in that it has two outputs whose voltages move in
opposite directions. Like an op amp, it relies on high open-loop
gain and negative feedback to force these outputs to the desired
voltages. The AD8133 drivers make it easy to perform single-
ended-to-differential conversion, common-mode level shifting,
and amplification of differential signals.
Common-mode voltage refers to the average of two node volt-
ages with respect to a common reference. The output common-
mode voltage is defined as
(VOP +VON
)
VOUT,cm
=
2
Output Balance
Output balance is a measure of how well the differential output
signals are matched in amplitude and how close they are to
exactly 180° apart in phase. Balance is most easily determined
by placing a well-matched resistor divider between the differen-
tial output voltage nodes and comparing the magnitude of the
signal at the divider’s midpoint with the magnitude of the dif-
ferential signal. By this definition, output balance error is the
magnitude of the change in output common-mode voltage
divided by the magnitude of the change in output differential-
mode voltage in response to a differential input signal.
Previous differential drivers, both discrete and integrated
designs, have been based on using two independent amplifiers
and two independent feedback loops, one to control each of the
outputs. When these circuits are driven from a single-ended
source, the resulting outputs are typically not well balanced.
Achieving a balanced output has typically required exceptional
matching of the amplifiers and feedback networks.
DC common-mode level shifting has also been difficult with
previous differential drivers. Level shifting has required the use
of a third amplifier and feedback loop to control the output
common-mode level. Sometimes, the third amplifier has also
been used to attempt to correct an inherently unbalanced
circuit. Excellent performance over a wide frequency range has
proven difficult with this approach.
∆VOUT,cm
Output Balance Error =
∆VOUT,dm
ANALYZING AN APPLICATION CIRCUIT
The AD8133 uses high open-loop gain and negative feedback to
force its differential and common-mode output voltages to
minimize the differential and common-mode input error
voltages. The differential input error voltage is defined as the
voltage between the differential inputs labeled VAP and VAN in
Figure 34. For most purposes, this voltage can be assumed to be
zero. Similarly, the difference between the actual output
common-mode voltage and the voltage applied to VOCM can also
be assumed to be zero. Starting from these two assumptions, any
application circuit can be analyzed.
Each of the AD8133 drivers uses two feedback loops to
separately control the differential and common-mode output
voltages. The differential feedback, set by the internal resistors,
controls only the differential output voltage. The internal
common-mode feedback loop controls only the common-mode
output voltage. This architecture makes it easy to arbitrarily set
the output common-mode level by simply applying a voltage to
the VOCM input. The output common-mode voltage is forced, by
internal common-mode feedback, to equal the voltage applied to
the VOCM input, without affecting the differential output voltage.
CLOSED-LOOP GAIN
The AD8133 architecture results in outputs that are highly
balanced over a wide frequency range without requiring exter-
nal components or adjustments. The common-mode feedback
loop forces the signal component of the output common-mode
voltage to be zeroed. The result is nearly perfectly balanced dif-
ferential outputs of identical amplitude that are exactly 180°
apart in phase.
The differential mode gain of the circuit in Figure 34 can be
described by the following equation.
VOUT,dm
VIN,dm
RF
RG
=
= 2
where RF = 1.5 kΩ and RG = 750 Ω nominally.
DEFINITION OF TERMS
R
F
Differential Voltage
V
R
AP
AN
G
G
+
V
V
ON
Differential voltage refers to the difference between two node
voltages that are balanced with respect to each other. For exam-
ple, in Figure 34 the output differential voltage (or equivalently
output differential mode voltage) is defined as
IP
OCM
V
R
V
V
L, dm
OUT, dm
IN, dm
–
V
V
OP
IN
V
R
R
F
Figure 34.
VOUT,dm
=
VOP −VON
Rev. 0 | Page 12 of 16
AD8133
CALCULATING AN APPLICATION CIRCUIT’S INPUT
IMPEDANCE
DRIVING A CAPACITIVE LOAD
A purely capacitive load can react with the output
The effective input impedance of a circuit such as that in
Figure 34 at VIP and VIN depends on whether the amplifier is
being driven by a single-ended or differential signal source. For
balanced differential input signals, the differential input imped-
ance, RIN, dm, between the inputs VIP and VIN is simply
impedance of the AD8133 to reduce phase margin, resulting in
high frequency ringing in the pulse response. The best way to
minimize this effect is to place a small resistor in series with
each of the amplifier’s outputs to buffer the load capacitance.
OUTPUT PULL-DOWN (OPD)
RIN,dm = 2× RG = 1.5kΩ
The AD8133 has an OPD pin that when pulled high signifi-
cantly reduces the power consumed while simultaneously
pulling the outputs to within less than 1 V of VS− when used
with series diodes (see the Applications section). The equivalent
schematic of the output pull-down circuit is shown in Figure 35.
(The ESD diodes shown in Figure 35 are for ESD protection and
are distinct from the series diodes used with the output pull-
down feature.) See Figure 18 and Figure 21 for the output
pull-down transient and isolation performance plots. The
threshold levels for the OPD pin are referenced to the positive
power supply voltage and are presented in the Specifications
tables. When the OPD pin is pulled high, the AD8133 enters the
output low disable state.
In the case of a single-ended input signal (for example, if VIN is
grounded and the input signal is applied to VIP), the input
impedance becomes:
⎛
⎜
⎞
⎟
RG
RF
RG + RF
⎜
⎟
RIN,dm
=
=1.125kΩ
⎜
⎜
⎝
⎟
⎟
⎠
1−
2×
(
)
The circuit’s input impedance is effectively higher than it would
be for a conventional op amp connected as an inverter because
a fraction of the differential output voltage appears at the inputs
as a common-mode signal, partially bootstrapping the voltage
across the input resistor RG.
V
S+
V
CC
ESD
DIODE
V
OUT
INPUT COMMON-MODE VOLTAGE RANGE IN SINGLE-
SUPPLY APPLICATIONS
PULLDOWN
The inputs of the AD8133 are designed to facilitate level-
shifting of ground referenced input signals on a single power
supply. For a single-ended input, this would imply, for example,
that the voltage at VIN in Figure 34 would be 0 V when the
amplifier’s negative power supply voltage was also set to 0 V.
(OUTPUT IS
PULLED DOWN
WHEN SWITCH
IS CLOSED)
ESD
DIODE
V
S–
Figure 35. Output Pull-Down Equivalent Circuit
It is important to ensure that the common-mode voltage at the
amplifier inputs, VAP and VAN, stays within its specified range.
Since voltages VAP and VAN are driven to be essentially equal by
negative feedback, the amplifier’s input common-mode voltage
can be expressed as a single term, VACM. VACM can be calculated
as follows
OUTPUT COMMON-MODE CONTROL
The AD8133 allows the user to control each of the three
common-mode output levels independently through the three
OCM input pins. The VOCM pins pass a signal to the common-
mode output level of each of their respective amplifiers with
330 MHz of small signal bandwidth and an internally fixed
gain of one. In this way, additional control and communication
signals can be embedded on the common-mode levels as the
user sees fit.
V
VOCM + 2VICM
VACM
=
3
where VICM is the common-mode voltage of the input signal, i.e.,
VIP + VIN
With no external circuitry, the level at the VOCM input of each
amplifier defaults to approximately midsupply. An internal
resistive divider with an impedance of approximately 100 kΩ
sets this level. To limit common-mode noise in dc common-
mode applications, external bypass capacitors should be
connected from each of the VOCM input pins to ground.
VICM
=
.
2
Rev. 0 | Page 13 of 16
AD8133
APPLICATIONS
DRIVING RGB VIDEO SIGNALS OVER CATEGORY-5
UTP CABLE
The foremost application of the AD8133 is driving RGB video
signals over UTP cable in KVM networks. Single-ended video
signals are easily converted to differential signals for
transmission over the cable, and the internally fixed gain of 2
automatically compensates for the losses incurred by the source
and load terminations. The common topologies used in KVM
networks, such as daisy-chained, star, and point-to-point, are
supported by the AD8133. Figure 36 shows the AD8133 in a
triple single-ended-to-differential application when driven from
a 75 Ω source, which is typical of how RGB video is driven over
an UTP cable. In applications that use the OPD feature, the
Schottky diodes are placed in series with each of the 49.9 Ω
resistors in the outputs.
+5V
0.1µF ON ALL V PINS
S+
V
S+
AD8133
1.5kΩ
75Ω
750Ω
750Ω
49.9Ω
49.9Ω
–
80.6Ω
+2.5V
V
A
OUT A
+
OCM
VIDEO
SOURCE A
38.3Ω
1.5kΩ
1.5k
75Ω
750Ω
750Ω
49.9Ω
49.9Ω
–
80.6Ω
+2.5V
V
B
OUT B
+
OCM
VIDEO
SOURCE B
38.3Ω
1.5kΩ
1.5kΩ
75Ω
750Ω
750Ω
49.9Ω
49.9Ω
–
80.6Ω
+2.5V
V
C
OUT C
+
OCM
VIDEO
SOURCE C
38.3Ω
1.5kΩ
OPD
OUTPUT
PULLDOWN
V
S–
Figure 36. AD8133 in Single-Ended-to-Differential Application
Rev. 0 | Page 14 of 16
AD8133
In the daisy-chained and star networks that use diodes for isola-
tion, return paths are required for the common-mode currents
that flow through the series diodes. A common-mode tap can
be implemented at each receiver by splitting the100 Ω termina-
tion resistor into two 50 Ω resistors in series. The diode currents
are routed from the tap between the 50 Ω resistors back to the
respective transmitters over one of the wires of the fourth
twisted pair in the UTP cable. Series resistors in the common-mode
return path are generally required to set the desired diode current.
OUTPUT PULL-DOWN
The output pull-down feature, when used in conjunction with
series Schottky diodes, offers a convenient means to connect a
number of AD8133 outputs together to form a video network.
The OPD pin is a binary input that controls the state of the
AD8133 outputs. Its binary input level is referenced to the most
positive power supply (see the Specifications tables for the logic
levels). When the OPD input is driven to its low state, the
AD8133 output is enabled and operates in its normal fashion. In
this state, the VOCM input can be used to provide a positive bias
on the series diodes, allowing the AD8133 to transmit signals
over the network. When the OPD input is driven to its high
state, the outputs of the AD8133 are forced to a low voltage,
irrespective of the level on the VOCM input, reverse-biasing the
series diodes and thus presenting high impedance to the net-
work. This feature allows a three-state output to be realized that
maintains its high impedance state even when the AD8133 is
not powered. This condition can occur in KVM networks where
the AD8133s do not all reside in the same module, and some
modules in the network are not powered.
In point-to-point networks, there is one transmitter and one
receiver per cable, and the switching is generally implemented
with a crosspoint switch. In this case, there is no need to use
diodes or the output pull-down feature.
Diode and crosspoint switching are by no means the only type
of switching that can be used with the AD8133. Many other
types of mechanical, electromechanical, and electronic switches
can be used.
LAYOUT AND POWER SUPPLY DECOUPLING
CONSIDERATIONS
It is recommended that the output pull-down feature only be
used in conjunction with series diodes in such a way as to
ensure that the diodes are reverse-biased when the output pull-
down feature is asserted, since some loading conditions can
prevent the output voltage from being pulled all the way down.
Standard high speed PCB layout practices should be adhered to
when designing with the AD8133. A solid ground plane is
recommended and good wideband power supply decoupling
networks should be placed as close as possible to the supply
pins. Small surface-mount ceramic capacitors are recommended
for these networks, and tantalum capacitors are recommended
for bulk supply decoupling.
KVM NETWORKS
In daisy-chained KVM networks, the drivers are distributed
along one cable and a triple receiver is located at one end.
Schottky diodes in series with the driver outputs are biased such
that the one driver that is transmitting video signals has its
diodes forward-biased and the disabled drivers have their
diodes reverse-biased. The output common-mode voltage, set
by the VOCM input, supplies the forward-biased voltage. When
the output pull-down feature is asserted, the differential outputs
are pulled to a low voltage, reverse-biasing the diodes.
AMPLIFIER-TO-AMPLIFIER ISOLATION
The least amount of isolation between the three amplifiers
exists between Amplifier A and Amplifier B. This is therefore
viewed as the worst-case isolation and is what is reflected in the
Specifications tables and Typical Performance Characteristics.
Refer to the Basic Test Circuit shown in Figure 5 for the test
conditions.
EXPOSED PADDLE (EP)
In star networks, all cables radiate out from a central hub,
which contains a triple receiver. The series diodes are all located
at the receiver in the star network. Only one ray of the star is
transmitting at a given time, and all others are isolated by the
reverse-biased diodes. Diode biasing is controlled in the same
way as in the daisy-chained network.
The LFCSP-24 package has an exposed paddle on the underside
of its body. In order to achieve the specified thermal resistance,
it must have a good thermal connection to one of the PCB
planes. The exposed paddle must be soldered to a pad on the
top of the board that is connected to an inner plane with several
thermal vias.
Rev. 0 | Page 15 of 16
AD8133
OUTLINE DIMENSIONS
0.60 MAX
4.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
19
24
1
18
0.50
BSC
2.25
2.10 SQ
1.95
PIN 1
INDICATOR
TOP
VIEW
3.75
BSC SQ
BOTTOM
VIEW
0.50
0.40
0.30
13
12
6
7
0.25 MIN
2.50 REF
0.80 MAX
0.65TYP
1.00
0.85
0.80
12° MAX
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.30
0.23
0.18
0.20 REF
SEATING
PLANE
COMPLIANTTOJEDECSTANDARDSMO-220-VGGD-2
Figure 37. 24-Lead Lead Frame Chip Scale Package [LFCSP],
4 mm× 4 mm (CP-24)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD8133ACP-REEL
AD8133ACP-REEL7
AD8133ACPZ-REEL1
AD8133ACPZ-REEL71
Temperature Package
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
24-Lead LFCSP
24-Lead LFCSP
24-Lead LFCSP
24-Lead LFCSP
Package Outline
CP-24
CP-24
CP-24
CP-24
1 Z = Pb-free part.
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and regis-
tered trademarks are the property of their respective owners.
D04769–0–7/04(0)
Rev. 0 | Page 16 of 16
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