AD8139ACP-EBZ [ADI]
Low Noise, Rail-to-Rail, Differential ADC Driver;
| 型号： | AD8139ACP-EBZ |
| 厂家： | 
ADI |
| 描述： | Low Noise, Rail-to-Rail, Differential ADC Driver |
| 文件： | 总27页 (文件大小：613K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Noise, Rail-to-Rail,
Differential ADC Driver
AD8139
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
AD8139
Fully differential
Low noise
2.25 nV/√Hz
2.1 pA/√Hz
–IN
1
2
3
4
8
7
6
5
+IN
V
NIC
V–
OCM
V+
+OUT
–OUT
Low harmonic distortion
98 dBc SFDR at 1 MHz
85 dBc SFDR at 5 MHz
72 dBc SFDR at 20 MHz
High speed
NIC = NO INTERNAL CONNECTION.
Figure 1. 8-Lead SOIC
AD8139
TOP VIEW
(Not to Scale)
410 MHz, 3 dB BW (G = 1)
800 V/µs slew rate
45 ns settling time to 0.01%
69 dB output balance at 1 MHz
80 dB dc CMRR
+IN
–IN
1
2
3
4
8
7
6
5
V
NIC
V–
OCM
V+
–OUT
+OUT
NIC = NO INTERNAL CONNECTION.
Low offset: 0.5 mV maximum
Low input offset current: 0.5 µA maximum
Differential input and output
Differential-to-differential or single-ended-to-differential
operation
Figure 2. 8-Lead LFCSP
Rail-to-rail output
Adjustable output common-mode voltage
Wide supply voltage range: 5 V to 12 V
Available in a small SOIC package and an 8-lead LFCSP
The AD8139 is manufactured on the proprietary Analog Devices,
Inc., second-generation XFCB process, enabling it to achieve low
levels of distortion with input voltage noise of only 2.25 nV/√Hz.
APPLICATIONS
ADC drivers to 18 bits
Single-ended-to-differential converters
Differential filters
Level shifters
Differential PCB drivers
Differential cable drivers
The AD8139 is available in an 8-lead SOIC package with an
exposed paddle (EP) on the underside of its body and a 3 mm ×
3 mm LFCSP. It is rated to operate over the temperature range
of −40°C to +125°C.
100
GENERAL DESCRIPTION
The AD8139 is an ultralow noise, high performance differential
amplifier with rail-to-rail output. With its low noise, high
SFDR, and wide bandwidth, it is an ideal choice for driving
analog-to-digital converters (ADCs) with resolutions to 18 bits.
The AD8139 is easy to apply, and its internal common-mode
feedback architecture allows its output common-mode voltage
to be controlled by the voltage applied to one pin. The internal
feedback loop also provides outstanding output balance as well
as suppression of even-order harmonic distortion products. Fully
differential and single-ended-to-differential gain configurations
are easily realized by the AD8139. Simple external feedback
networks consisting of four resistors determine the closed-loop
gain of the amplifier.
10
1
10
100
1k
10k
100k
1M
10M
100M
1G
FREQUENCY (Hz)
Figure 3. Input Voltage Noise vs. Frequency
Rev. C
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AD8139* Product Page Quick Links
Last Content Update: 11/01/2016
Comparable Parts
Reference Materials
View a parametric search of comparable parts
Product Selection Guide
• High Speed Amplifiers Selection Table
Tutorials
Evaluation Kits
• Universal Evaluation Board for Single Differential
Amplifiers
• MT-075: Differential Drivers for High Speed ADCs
Overview
• MT-076: Differential Driver Analysis
Documentation
• MT-218: Multiple Feedback Band-Pass Design Example
Application Notes
• AN-0992: Active Filter Evaluation Board for Differential
Amplifiers
Design Resources
• AD8139 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
• AN-1026: High Speed Differential ADC Driver Design
Considerations
• AN-1363: Meeting Biasing Requirements of Externally
Biased RF/Microwave Amplifiers with Active Bias
Controllers
Discussions
• AN-584: Using the AD813X Differential Amplifier
• AN-649: Using the Analog Devices Active Filter Design
Tool
View all AD8139 EngineerZone Discussions
Data Sheet
Sample and Buy
Visit the product page to see pricing options
• AD8139: Low Noise, Rail-to-Rail, Differential ADC Driver
Data Sheet
User Guides
Technical Support
Submit a technical question or find your regional support
number
• UG-474: Evaluation Board for Differential Amplifiers
Offered in 8-Lead SOIC Packages
Tools and Simulations
• ADI DiffAmpCalc™
• AD8139 SPICE Macro Model
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AD8139
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Pin Configurations and Function Descriptions............................8
Typical Performance Characteristics ..............................................9
Test Circuits..................................................................................... 18
Theory of Operation ...................................................................... 19
Typical Connection and Definition of Terms ........................ 19
Applications Information.............................................................. 20
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagrams............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
VS = 5 V, VOCM = 0 V.................................................................. 3
VS = 5 V, V OCM = 2.5 V ................................................................. 5
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
Estimating Noise, Gain, and Bandwidth with Matched
Feedback Networks.................................................................... 20
Outline Dimensions....................................................................... 25
Ordering Guide .......................................................................... 26
REVISION HISTORY
6/2016—Rev. B to Rev. C
8/2004—Rev. 0 to Rev. A
Changed CP-8-2 to CP-8-13 ........................................ Throughout
Changes to Figure 1 and Figure 2................................................... 1
Changes to Figure 5, Figure 6, and Table 5 ................................... 8
Updated Outline Dimensions ....................................................... 25
Changes to Ordering Guide ......................................................... 26
Added 8-Lead LFCSP.........................................................Universal
Changes to General Description Section .......................................1
Changes to Figure 2...........................................................................1
Changes to VS = 5 V, VOCM = 0 V Specifications .........................3
Changes to VS = 5 V, V OCM = 2.5 V Specifications.........................5
Changes to Table 4.............................................................................7
Changes to Maximum Power Dissipation Section........................7
Changes to Figure 26 and Figure 29............................................. 12
Added Figure 39 and Figure 42; Renumbered Sequentially ..... 14
Changes to Figure 45 to Figure 47................................................ 15
Added Figure 48 ............................................................................. 15
Changes to Figure 52 and Figure 53............................................. 16
Changes to Figure 55 and Figure 56............................................. 17
Changes to Table 6.......................................................................... 19
Changes to Voltage Gain Section ................................................. 19
Changes to Driving a Capacitive Load Section.......................... 22
Changes to Ordering Guide.......................................................... 24
Updated Outline Dimensions....................................................... 24
10/2007—Rev. A to Rev. B
Changes to General Description Section ...................................... 1
Added Figure 2; Renumbered Sequentially .................................. 1
Changes to Table 1............................................................................ 3
Changes to Table 2 ............................................................................ 5
Changes to Table 6 and Layout....................................................... 8
Added Figure 6.................................................................................. 8
Changes to Figure 30...................................................................... 12
Changes to Layout .......................................................................... 17
Changes to Figure 63...................................................................... 22
Changes to Exposed Paddle (EP) Section ................................... 23
Updated Outline Dimensions ....................................................... 24
5/2004—Revision 0: Initial Version
Rev. C | Page 2 of 26
Data Sheet
AD8139
SPECIFICATIONS
VS = 5 V, VOCM = 0 V
TA = 25°C, differential gain = 1, RL, dm = 1 kΩ, RF = RG = 200 Ω, unless otherwise noted. TMIN to TMAX = −40°C to +125°C.
Table 1.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
DIFFERENTIAL INPUT PERFORMANCE
Dynamic Performance
−3 dB Small Signal Bandwidth
−3 dB Large Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time to 0.01%
Overdrive Recovery Time
Noise/Harmonic Performance
SFDR
VO, dm = 0.1 V p-p
VO, dm = 2 V p-p
VO, dm = 0.1 V p-p
VO, dm = 2 V step
VO, dm = 2 V step, CF = 2 pF
G = 2, VIN, dm = 12 V p-p triangle wave
340
210
410
240
45
800
45
MHz
MHz
MHz
V/µs
ns
30
ns
VO, dm = 2 V p-p, fC = 1 MHz
VO, dm = 2 V p-p, fC = 5 MHz
VO, dm = 2 V p-p, fC = 20 MHz
VO, dm = 2 V p-p, fC = 10.05 MHz 0.05 MHz
f = 100 kHz
98
85
72
−90
2.25
2.1
dBc
dBc
dBc
dBc
nV/√Hz
pA/√Hz
Third-Order IMD
Input Voltage Noise
Input Current Noise
DC Performance
f = 100 kHz
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Offset Current
Open-Loop Gain
VIP = VIN = VOCM = 0 V
TMIN to TMAX
TMIN to TMAX
−500
150
+500
µV
µV/°C
µA
µA
dB
1.25
2.25
0.12
114
8.0
0.5
Input Characteristics
Input Common-Mode Voltage Range
Input Resistance
−4
80
+4
V
Differential
Common mode
Common mode
∆VICM = 1 V dc, RF = RG = 10 kΩ
600
1.5
1.2
84
kΩ
MΩ
pF
dB
Input Capacitance
CMRR
Output Characteristics
Output Voltage Swing
Each single-ended output, RF = RG = 10 kΩ
Each single-ended output,
−VS + 0.20
−VS + 0.15
+VS – 0.20
+VS − 0.15
V
V
RL, dm = open circuit, RF = RG = 10 kΩ
Output Current
Output Balance Error
VOCM TO VO, cm PERFORMANCE
VOCM Dynamic Performance
−3 dB Bandwidth
Slew Rate
Each single-ended output
f = 1 MHz
100
−69
mA
dB
VO, cm = 0.1 V p-p
VO, cm = 2 V p-p
515
250
1.000 1.001
MHz
V/µs
V/V
Gain
0.999
−3.8
VOCM Input Characteristics
Input Voltage Range
Input Resistance
Input Offset Voltage
Input Voltage Noise
Input Bias Current
CMRR
+3.8
3.5
300
3.5
1.3
88
V
MΩ
µV
nV/√Hz
µA
dB
VOS, cm = VO, cm − VOCM; VIP = VIN = VOCM = 0 V
f = 100 kHz
−900
+900
4.5
∆VOCM/∆VO, dm, ∆VOCM = 1 V
74
Rev. C | Page 3 of 26
AD8139
Data Sheet
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
POWER SUPPLY
Operating Range
Quiescent Current
+PSRR
+4.5
6
25.5
V
24.5
112
109
mA
dB
dB
°C
Change in +VS = 1 V
Change in −VS = 1 V
95
95
−PSRR
OPERATING TEMPERATURE RANGE
−40
+125
Rev. C | Page 4 of 26
Data Sheet
AD8139
VS = 5 V, VOCM = 2.5 V
TA = 25°C, differential gain = 1, RL, dm = 1 kΩ, RF = RG = 200 Ω, unless otherwise noted. TMIN to TMAX = −40°C to +125°C.
Table 2.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
DIFFERENTIAL INPUT PERFORMANCE
Dynamic Performance
−3 dB Small Signal Bandwidth
−3 dB Large Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time to 0.01%
Overdrive Recovery Time
Noise/Harmonic Performance
SFDR
VO, dm = 0.1 V p-p
VO, dm = 2 V p-p
VO, dm = 0.1 V p-p
VO, dm = 2 V step
VO, dm = 2 V step
G = 2, VIN, dm = 7 V p-p triangle wave
330
135
385
165
34
540
55
MHz
MHz
MHz
V/µs
ns
35
ns
VO, dm = 2 V p-p, fC = 1 MHz
VO, dm = 2 V p-p, fC = 5 MHz, RL = 800 Ω
VO, dm = 2 V p-p, fC = 20 MHz, RL = 800 Ω
VO, dm = 2 V p-p, fC = 10.05 MHz 0.05 MHz
f = 100 kHz
99
87
75
−87
2.25
2.1
dBc
dBc
dBc
dBc
nV/√Hz
pA/√Hz
Third-Order IMD
Input Voltage Noise
Input Current Noise
DC Performance
f = 100 kHz
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Offset Current
Open-Loop Gain
VIP = VIN = VOCM = 2.5 V
TMIN to TMAX
TMIN to TMAX
−500
150
1.25
2.2
0.13
112
+500
µV
µV/°C
µA
µA
dB
7.5
0.5
Input Characteristics
Input Common-Mode Voltage Range
Input Resistance
1
4
V
Differential
Common mode
Common mode
ΔVICM = 1 V dc, RF = RG = 10 kΩ
600
1.5
1.2
79
kΩ
MΩ
pF
dB
Input Capacitance
CMRR
75
Output Characteristics
Output Voltage Swing
Each single-ended output, RF = RG = 10 kΩ
Each single-ended output,
−VS + 0.15
−VS + 0.10
+VS − 0.15
+VS − 0.10
V
V
RL, dm = open circuit, RF = RG = 10 kΩ
Output Current
Output Balance Error
VOCM TO VO, cm PERFORMANCE
VOCM Dynamic Performance
−3 dB Bandwidth
Slew Rate
Each single-ended output
f = 1 MHz
80
−70
mA
dB
VO, cm = 0.1 V p-p
VO, cm = 2 V p-p
440
150
1.000 1.001
MHz
V/µs
V/V
Gain
0.999
1.0
VOCM Input Characteristics
Input Voltage Range
Input Resistance
Input Offset Voltage
Input Voltage Noise
Input Bias Current
CMRR
3.8
3.5
0.45 +1.0
3.5
1.3
79
V
MΩ
mV
nV/√Hz
µA
VOS, cm = VO, cm − VOCM; VIP = VIN = VOCM = 2.5 V
f = 100 kHz
−1.0
4.2
ΔVOCM/ΔVO, dm, ΔVOCM = 1 V
67
dB
Rev. C | Page 5 of 26
AD8139
Data Sheet
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
POWER SUPPLY
Operating Range
Quiescent Current
+PSRR
+4.5
6
22.5
V
21.5
97
105
mA
dB
dB
°C
Change in +VS = 1 V
Change in −VS = 1 V
86
92
−PSRR
OPERATING TEMPERATURE RANGE
−40
+125
Rev. C | Page 6 of 26
Data Sheet
AD8139
ABSOLUTE MAXIMUM RATINGS
Table 3.
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). The load current consists of differential
and common-mode currents flowing to the load, as well as
currents flowing through the external feedback networks and
the internal common-mode feedback loop. The internal resistor
tap used in the common-mode feedback loop places a 1 kΩ
differential load on the output. RMS output voltages should be
considered when dealing with ac signals.
Parameter
Rating
Supply Voltage
12 V
VOCM
VS
Power Dissipation
See Figure 4
VS
−65°C to +125°C
−40°C to +125°C
300°C
Input Common-Mode Voltage
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering 10 sec)
Junction Temperature
150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Airflow reduces θJA. In addition, more metal directly in contact
with the package leads from metal traces, through holes, ground,
and power planes reduce the θJA.
Figure 4 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the exposed paddle
(EP) 8-lead SOIC (θJA = 70°C/W) and the 8-lead LFCSP
(θJA = 70°C/W) on a JEDEC standard 4-layer board. θJA
values are approximations.
THERMAL RESISTANCE
4.0
θJA is specified for the worst-case conditions, that is, θJA is specified
for device soldered in circuit board for surface-mount packages.
3.5
3.0
Table 4.
Package Type
θJA
70
70
Unit
°C/W
°C/W
2.5
2.0
8-Lead SOIC with EP/4-Layer
8-Lead LFCSP/4-Layer
1.5
Maximum Power Dissipation
SOIC
AND LFCSP
The maximum safe power dissipation in the AD8139 package
is limited by the associated rise in junction temperature (TJ) on
the die. At approximately 150°C, which is the glass transition
temperature, the plastic changes its properties. Even temporarily
exceeding this temperature limit can change the stresses that the
package exerts on the die, permanently shifting the parametric
performance of the AD8139. Exceeding a junction temperature
of 175°C for an extended period can result in changes in the
silicon devices potentially causing failure.
1.0
0.5
0
–40
–20
0
20
40
60
80
100
120
AMBIENT TEMPERATURE (°C)
Figure 4. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
Rev. C | Page 7 of 26
AD8139
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
+IN
–IN 1
8
7
6
5
–IN
1
2
3
4
8
7
6
5
+IN
AD8139
NIC
V–
V
2
OCM
AD8139
V
NIC
V–
OCM
V+
TOP VIEW
TOP VIEW
(Not to Scale)
V+ 3
(Not to Scale)
–OUT
+OUT 4
+OUT
–OUT
NOTES
NOTES
1. NIC = NO INTERNAL CONNECTION.
2. SOLDER THE EXPOSED PADDLE
ON THE BACK OF THE PACKAGE
TO THE GROUND PLANE OR TO
A POWER PLANE.
1. NIC = NO INTERNAL CONNECTION.
2. SOLDER THE EXPOSED PADDLE
ON THE BACK OF THE PACKAGE
TO THE GROUND PLANE OR TO
A POWER PLANE.
Figure 5. 8-Lead SOIC Pin Configuration
Figure 6. 8-Lead LFCSP Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic
Description
1
2
−IN
VOCM
Inverting Input.
An internal feedback loop drives the output common-mode voltage to be equal to the voltage applied to
the VOCM pin, provided the operation of the amplifier remains linear.
3
4
5
6
7
8
0
V+
Positive Power Supply Voltage.
Positive Side of the Differential Output.
Negative Side of the Differential Output.
Negative Power Supply Voltage.
No Internal Connection.
Noninverting Input.
+OUT
−OUT
V−
NIC
+IN
EP
Exposed Paddle. Solder the exposed paddle on the back of the package to the ground plane or to a power plane.
Rev. C | Page 8 of 26
Data Sheet
AD8139
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise noted, differential gain = +1, RG = RF = 200 Ω, RL, dm = 1 kΩ, VS = ±± V, TA = 2±°C, VOCM = 0 V. Refer to the basic test
circuit in Figure ±7 for the definition of terms.
2
1
2
1
G = 1
G = 1
0
0
G = 2
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
–11
–12
–13
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
–11
–12
–13
G = 5
G = 2
G = 5
G = 10
G = 10
R
= 200Ω
= 2.0V p-p
G
R
= 200Ω
= 0.1V p-p
G
V
O, dm
V
O, dm
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 7. Small Signal Frequency Response for Various Gains
Figure 10. Large Signal Frequency Response for Various Gains
5
4
3
2
V
= +5V
S
3
2
1
0
1
–1
–2
0
V
= ±5V
V
= ±5V
S
S
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
–3
–4
V
= +5V
S
–5
–6
–7
–8
–9
–10
–11
–12
V
= 2.0V p-p
V
= 0.1V p-p
O, dm
O, dm
10
100
FREQUENCY (MHz)
1000
10
100
FREQUENCY (MHz)
1000
Figure 8. Small Signal Frequency Response for Various Power Supplies
Figure 11. Large Signal Frequency Response for Various Power Supplies
3
3
+125°C
+125°C
+85°C
2
2
1
+85°C
1
0
–1
–2
–3
–4
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
–11
–12
–5
–40°C
–6
–7
–8
–9
+25°C
–40°C
–10
–11
V
= 0.1V p-p
O, dm
V
= 2.0V p-p
O, dm
+25°C
–12
10
100
1000
10
100
FREQUENCY (MHz)
1000
FREQUENCY (MHz)
Figure 9. Small Signal Frequency Response at Various Temperatures
Figure 12. Large Signal Frequency Response at Various Temperatures
Rev. C | Page 9 of 26
AD8139
Data Sheet
3
2
2
1
R
= 100Ω
R
= 200Ω
R
= 100Ω
L
L
L
1
0
R
= 500Ω
L
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
–11
–12
–13
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
R
= 500Ω
L
R
= 1kΩ
L
–11
V
–12
10
= 0.1V p-p
V
= 2.0V p-p
O, dm
O, dm
R
= 200Ω
R
= 1kΩ
L
L
10
100
FREQUENCY (MHz)
1000
100
1000
FREQUENCY (MHz)
Figure 16. Large Signal Frequency Response for Various Loads
Figure 13. Small Signal Frequency Response for Various Loads
2
3
C
= 0pF
C
= 1pF
C
= 0pF
F
F
F
1
0
2
1
C
= 1pF
F
–1
0
–2
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
–11
–12
C
= 2pF
F
–3
–4
C
= 2pF
F
–5
–6
–7
–8
–9
–10
–11
–12
–13
V = 2.0V p-p
O, dm
V
= 0.1V p-p
O, dm
10
100
FREQUENCY (MHz)
1000
10
100
FREQUENCY (MHz)
1000
Figure 17. Large Signal Frequency Response for Various CF
Figure 14. Small Signal Frequency Response for Various CF
0.5
0.4
6
5
R
= 100Ω
L
V
= +4.3V
V
= +4V
OCM
OCM
(V
= 0.1V p-p)
O, dm
V
= –4.3V
OCM
4
R
= 100Ω
L
0.3
(V
O, dm
= 2.0V p-p)
3
V
= –4V
OCM
2
R
= 1kΩ
0.2
L
(V
= 2.0V p-p)
1
O, dm
0.1
0
V
= 0V
OCM
R
= 1kΩ
–1
–2
–3
–4
–5
–6
–7
–8
–9
L
0
(V
O, dm
= 0.1V p-p)
–0.1
–0.2
–0.3
–0.4
–0.5
V
= 0.1V p-p
O, dm
1
10
FREQUENCY (Hz)
100
10
100
FREQUENCY (MHz)
1000
Figure 18. 0.1 dB Flatness for Various Loads and Output Amplitudes
Figure 15. Small Signal Frequency Response at Various VOCM
Rev. C | Page 10 of 26
Data Sheet
AD8139
–30
–30
–40
V = 2.0V p-p
O, dm
V
= 2.0V p-p
O, dm
–40
–50
–50
V
= +5V
S
–60
–60
V
= ±5V
S
–70
–70
V
= ±5V
S
–80
–80
V
= +5V
S
–90
–90
–100
–110
–120
–130
–100
–110
–120
–130
0.1
1
10
FREQUENCY (MHz)
100
0.1
1
10
FREQUENCY (MHz)
100
Figure 19. Second Harmonic Distortion vs. Frequency and Supply Voltage
Figure 22. Third Harmonic Distortion vs. Frequency and Supply Voltage
–30
–30
V
= 2.0V p-p
V
= 2.0V p-p
O, dm
O, dm
–40
–50
–40
–50
–60
–60
G = 1
–70
–70
–80
–80
G = 5
–90
–90
–100
–110
–120
–130
–140
–100
–110
–120
–130
–140
G = 2
G = 1
G = 2
G = 5
0.1
1
10
FREQUENCY (MHz)
100
0.1
1
10
FREQUENCY (MHz)
100
Figure 20. Second Harmonic Distortion vs. Frequency and Gain
Figure 23. Third Harmonic Distortion vs. Frequency and Gain
–30
–30
V
= 2.0V p-p
V
= 2.0V p-p
O, dm
O, dm
–40
–50
–40
–50
R
= 100Ω
L
–60
–60
R
= 100Ω
L
R
= 200Ω
L
–70
–70
R
= 200Ω
L
–80
–80
–90
–90
R
= 500Ω
L
–100
–110
–120
–130
–100
–110
–120
–130
R
= 1kΩ
L
R
= 500Ω
L
R
= 1kΩ
L
0.1
1
10
100
0.1
1
10
FREQUENCY (MHz)
100
FREQUENCY (MHz)
Figure 21. Second Harmonic Distortion vs. Frequency and Load
Figure 24. Third Harmonic Distortion vs. Frequency and Load
Rev. C | Page 11 of 26
AD8139
Data Sheet
–30
–30
–40
V
= 2.0V p-p
V
= 2.0V p-p
O, dm
O, dm
–40
–50
–50
–60
–60
–70
–70
R
= 200Ω
F
–80
–80
R
= 500Ω
F
–90
–90
R
= 200Ω
F
–100
–110
–120
–130
–100
–110
–120
–130
R
= 1kΩ
F
R
= 1kΩ
F
R
= 500Ω
F
0.1
1
10
FREQUENCY (MHz)
100
0.1
1
10
FREQUENCY (MHz)
100
Figure 25. Second Harmonic Distortion vs. Frequency and RF
Figure 28. Third Harmonic Distortion vs. Frequency and RF
–80
–80
–90
F = 2MHz
C
F
= 2MHz
C
V
V
= ±5V
= +5V
S
–90
–100
–110
–120
–130
–140
–150
V
= +5V
S
S
–100
–110
–120
–130
–140
–150
V
= ±5V
S
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
V
(V p-p)
V
(V p-p)
O, dm
O, dm
Figure 26. Second Harmonic Distortion vs. Output Amplitude
Figure 29. Third Harmonic Distortion vs. Output Amplitude
–60
–60
–70
V
F
= 2V p-p
V
F
= 2V p-p
= 2MHz
O, dm
= 2MHz
O, dm
C
C
–70
–80
–80
–90
–90
SECOND HARMONIC
SECOND HARMONIC
–100
–110
–120
–130
–100
–110
–120
–130
THIRD HARMONIC
THIRD HARMONIC
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
–5
–4
–3
–2
–1
0
1
2
3
4
5
V
(V)
V
(V)
OCM
OCM
Figure 27. Harmonic Distortion vs. VOCM, VS = +5 V
Figure 30. Harmonic Distortion vs. VOCM, VS = 5 V
Rev. C | Page 12 of 26
Data Sheet
AD8139
100
2.5
2.0
C
= 0pF
V
= 100mV p-p
F
O, dm
4V p-p
2V p-p
75
50
C
= 2pF
F
1.5
C
= 0pF
F
C
= 0pF
(C = 0pF,
1.0
F
V
O, dm
F
C
= 2pF
(C = 2pF, V = ±5V)
F
25
F
S
V
= ±5V)
S
0.5
0
0
–0.5
–1.0
–1.5
–2.0
–2.5
–25
–50
–75
–100
5ns/DIV
5ns/DIV
TIME (ns)
TIME (ns)
Figure 31. Small Signal Transient Response for Various CF
Figure 34. Large Signal Transient Response for Various CF
0.100
0.075
0.050
0.025
0
1.5
R
C
= 63.4Ω
L, dm
R
C
= 31.6Ω
L, dm
S
S
= 15pF
= 30pF
1.0
0.5
R
C
= 31.6Ω
S
= 30pF
L, dm
R
C
= 63.4Ω
S
= 15pF
L, dm
0
–0.025
–0.050
–0.075
–0.100
–0.5
–1.0
–1.5
5ns/DIV
5ns/DIV
TIME (ns)
TIME (ns)
Figure 32. Small Signal Transient Response for Capacitive Loads
Figure 35. Large Signal Transient Response for Capacitive Loads
5
0
–5
1.5
1.0
600
V
F
= 2V p-p
1 = 10MHz
2 = 10.1MHz
C
= 2pF
F
O, dm
V
= 2.0V p-p
C
O, dm
F
C
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
400
200
0
0.5
0
ERROR
–0.5
–1.0
–1.5
–200
–400
–600
V
O, dm
35ns/DIV
V
IN
9.55 9.65 9.75 9.85 9.95 10.05 10.15 10.25 10.35 10.45 10.55
TIME (ns)
FREQUENCY (MHz)
Figure 36. Settling Time (0.01%)
Figure 33. Intermodulation Distortion
Rev. C | Page 13 of 26
AD8139
Data Sheet
6
5
1.5
±5V
4
1.0
V
= +5V
S
3
2
+5V
0.5
1
0
V
= 0.1V p-p
O, cm
–1
–2
–3
–4
–5
–6
–7
–8
–9
0
V
= ±5V
V = ±5V
S
S
V
= 2.0V p-p
O, cm
–0.5
–1.0
–1.5
V
V
= 2V p-p
= 0V
O, cm
IN, dm
V
= +5V
S
10ns/DIV
10
100
FREQUENCY (MHz)
1000
TIME (ns)
Figure 37. VOCM Large Signal Transient Response
Figure 40. VOCM Frequency Response for Various Supplies
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
V
= 0.2V p-p
V
V
= 0.2V p-p
IN, cm
O, cm
CMRR = ∆V
INPUT CMRR = ∆V
/∆V
O, cm
/∆V
O, dm
IN, cm
OCM
O, cm
–10
–20
–30
–40
–50
–60
–70
–80
–90
R
= R = 10kΩ
G
F
R
= R = 200Ω
G
F
1
10
FREQUENCY (MHz)
100
500
1
10
FREQUENCY (MHz)
100
500
Figure 41. VOCM CMRR vs. Frequency
Figure 38. CMRR vs. Frequency
100
10
1
100
10
1
10
100
1k
10k
100k
1M
10M
100M
1G
10
100
1k
10k
100k
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 42. VOCM Voltage Noise vs. Frequency
Figure 39. Input Voltage Noise vs. Frequency
Rev. C | Page 14 of 26
Data Sheet
AD8139
0
14
12
10
8
2 × V
IN, dm
R
= 1kΩ
G = 2
L, dm
PSRR = ∆V
/∆V
O, dm
S
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
V
O, dm
6
4
2
–PSRR
0
+PSRR
–2
–4
–6
–8
–10
–12
–14
50ns/DIV
1
10
FREQUENCY (MHz)
100
500
TIME (ns)
Figure 46. Overdrive Recovery
Figure 43. PSRR vs. Frequency
0
100
10
V
= 1V p-p
O, dm
OUTPUT BALANCE = ∆V
/∆V
O, cm O, dm
V
S
= +5V
–10
–20
–30
–40
–50
–60
–70
–80
V
= ±5V
S
1
0.1
0.01
1
10
100
500
0.1
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 47. Output Balance vs. Frequency
Figure 44. Single-Ended Output Impedance vs. Frequency
300
250
200
150
100
50
–50
700
V
= ±5V
S
600
500
G = 1 (R = R = 200Ω)
R
F
G
= 1kΩ
L, dm
–100
–150
–200
–250
400
V
– V
OP
S+
300
V
V
– V
OP
S+
200
100
V
= +5V
0
V
= ±5V
S
S
–100
–200
–300
–400
–500
–600
–700
– V
S–
ON
V
– V
60
ON
S–
–300
120
–40
–20
0
20
40
80
100
100
1k
RESISTIVE LOAD (Ω)
10k
TEMPERATURE (°C)
Figure 48. Output Saturation Voltage vs. Temperature
Figure 45. Output Saturation Voltage vs. Output Load
Rev. C | Page 15 of 26
AD8139
Data Sheet
3.0
170
145
120
95
26
25
24
23
22
21
20
V
= ±5V
S
I
OS
2.5
2.0
1.5
1.0
I
BIAS
V
= +5V
S
70
–40
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 49. Input Bias and Offset Current vs. Temperature
Figure 52. Supply Current vs. Temperature
10
300
250
200
150
100
50
600
400
200
0
8
6
V
OS, cm
V
= ±5V
S
4
V
= +5V
S
2
0
V
OS, dm
–2
–4
–6
–8
–10
–200
–400
–600
0
–40
–5
–4
–3
–2
–1
0
1
2
3
4
5
–20
0
20
40
60
80
100
120
V
(V)
TEMPERATURE (°C)
ACM
Figure 53. Offset Voltage vs. Temperature
Figure 50. Input Bias Current vs.
Input Common-Mode Voltage
50
45
40
35
30
25
20
15
10
5
5
4
COUNT = 350
MEAN = –50µV
STD DEV = 100µV
V
= ±2.5V
S
3
2
V
= ±5V
S
1
0
–1
–2
–3
–4
–5
0
–5
–4
–3
–2
–1
0
1
2
3
4
5
V
(V)
OCM
V
(µV)
OS, dm
Figure 51. VOUT, cm vs. VOCM Input Voltage
Figure 54. VOS, dm Distribution
Rev. C | Page 16 of 26
Data Sheet
AD8139
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
6
4
V
= ±5V
S
V
= +5V
2
S
0
–2
–4
–6
–5
–4
–3
–2
–1
0
1
2
3
4
5
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
V
(V)
OCM
Figure 55. VOCM Bias Current vs. Temperature
Figure 56. VOCM Bias Current vs. VOCM Input Voltage
Rev. C | Page 17 of 26
AD8139
Data Sheet
TEST CIRCUITS
R
C
F
50Ω
50Ω
F
R
R
= 200Ω
= 200Ω
G
–
60.4Ω
60.4Ω
V
V
R
= 1kΩ
V
TEST
AD8139
OCM
L, dm
O, dm
+
TEST
G
C
F
SIGNAL
SOURCE
R
F
Figure 57. Basic Test Circuit
R
= 200Ω
F
50Ω
50Ω
R
R
R
R
= 200Ω
= 200Ω
S
G
–
60.4Ω
60.4Ω
V
V
C
R
V
TEST
AD8139
OCM
L, dm
L, dm
O, dm
+
TEST
G
S
SIGNAL
SOURCE
R
= 200Ω
F
Figure 58. Capacitive Load Test Circuit, G = +1
Rev. C | Page 18 of 26
Data Sheet
AD8139
THEORY OF OPERATION
The AD8139 is a high speed, low noise differential amplifier
fabricated on the Analog Devices second-generation extra fast
complementary bipolar (XFCB) process. It is designed to
provide two closely balanced differential outputs in response
to either differential or single-ended input signals. Differential
gain is set by external resistors, similar to traditional voltage-
feedback operational amplifiers. The common-mode level of
the output voltage is set by a voltage at the VOCM pin and is
independent of the input common-mode voltage. The AD8139
has an H-bridge input stage for high slew rate, low noise, and
low distortion operation and rail-to-rail output stages that
provide maximum dynamic output range. This set of features
allows for convenient single-ended-to-differential conversion,
a common need to take advantage of modern high resolution
ADCs with differential inputs.
outputs of identical amplitude and exactly 180° out of phase. The
output balance performance does not require tightly matched
external components, nor does it require that the feedback factors
of each loop be equal to each other. Low frequency output balance
is limited ultimately by the mismatch of an on-chip voltage divider,
which is trimmed for optimum performance.
Output balance is measured by placing a well-matched resistor
divider across the differential voltage outputs and comparing
the signal at the midpoint of the divider with the magnitude of
the differential output. By this definition, output balance is
equal to the magnitude of the change in output common-mode
voltage divided by the magnitude of the change in output
differential-mode voltage:
ΔVO, cm
ΔVO, dm
Output Balance
(3)
TYPICAL CONNECTION AND DEFINITION OF
TERMS
The block diagram of the AD8139 in Figure 60 shows the
external differential feedback loop (RF/RG networks and the
differential input transconductance amplifier, GDIFF) and the
internal common-mode feedback loop (voltage divider across
VOP and VON and the common-mode input transconductance
amplifier, GCM). The differential negative feedback drives the
voltages at the summing junctions VAN and VAP to be essentially
equal to each other.
Figure ±9 shows a typical connection for the AD8139, using
matched external RF/RG networks. The differential input terminals
of the AD8139, VAP and VAN, are used as summing junctions.
An external reference voltage applied to the VOCM terminal sets
the output common-mode voltage. The two output terminals,
VOP and VON, move in opposite directions in a balanced fashion
in response to an input signal.
C
F
V
AN = VAP
(4)
The common-mode feedback loop drives the output common-
mode voltage, sampled at the midpoint of the two ±00 Ω resistors,
to equal the voltage set at the VOCM terminal. This ensures that
R
F
R
R
V
V
V
G
AP
ON
V
–
IP
+
V
OCM
R
V
AD8139
L, dm
O, dm
+
VO, dm
2
G
V
AN
OP
V
VOP VOCM
and
(±)
–
IN
R
F
VO, dm
2
C
F
VON VOCM
(6)
Figure 59. Typical Connection
R
R
F
G
V
IN
The differential output voltage is defined as
O, dm = VOP − VON
10pF
V
(1)
(2)
+
+
G
O
V
OP
Common-mode voltage is the average of two voltages. The
output common-mode voltage is defined as
500Ω
500Ω
MIDSUPPLY
V
AN
G
G
CM
DIFF
VOP VON
V
V
V
AP
OCM
VO, cm
2
G
O
ON
Output Balance
Output balance is a measure of how well VOP and VON are
matched in amplitude and how precisely they are 180° out of
phase with each other. It is the internal common-mode feedback
loop that forces the signal component of the output common-mode
towards zero, resulting in the near perfectly balanced differential
10pF
V
IP
R
G
R
F
Figure 60. Block Diagram
Rev. C | Page 19 of 26
AD8139
Data Sheet
APPLICATIONS INFORMATION
Voltage Gain
ESTIMATING NOISE, GAIN, AND BANDWIDTH
WITH MATCHED FEEDBACK NETWORKS
The behavior of the node voltages of the single-ended-to-
differential output topology can be deduced from the previous
definitions. Referring to Figure ±9, (CF = 0) and setting VIN = 0,
one can write
Estimating Output Noise Voltage
The total output noise is calculated as the root-sum-squared
total of several statistically independent sources. Because the
sources are statistically independent, the contributions of each
must be individually included in the root-sum-square calculation.
Table 6 lists recommended resistor values and estimates of
bandwidth and output differential voltage noise for various
closed-loop gains. For most applications, 1% resistors are
sufficient.
VIP VAP VAP VON
(11)
RG
RF
RG
RF RG
VAN VAP VOP
(12)
Solving the above two equations and setting VIP to Vi gives the
gain relationship for VO, dm/Vi.
Table 6. Recommended Values of Gain-Setting Resistors and
Voltage Noise for Various Closed-Loop Gains
3 dB
Gain RG (Ω) RF (Ω) Bandwidth (MHz) Noise (nV/√Hz)
RF
RG
VOP VON VO, dm
V
(13)
i
Total Output
An inverting configuration with the same gain magnitude can
be implemented by simply applying the input signal to VIN and
setting VIP = 0. For a balanced differential input, the gain from
1
2
5
10
200
200
200
200
200
400
1 k
400
160
53
5.8
9.3
19.7
37
VIN, dm to VO, dm is also equal to RF/RG, where VIN, dm = VIP − VIN.
2 k
26
Feedback Factor Notation
The differential output voltage noise contains contributions
from the input voltage noise and input current noise of the
AD8139 as well as those from the external feedback networks.
When working with differential amplifiers, it is convenient to
introduce the feedback factor β, which is defined as
RG
RF RG
The contribution from the input voltage noise spectral density
is computed as
(14)
This notation is consistent with conventional feedback analysis
and is very useful, particularly when the two feedback loops are
not matched.
RF
RG
Vo_n1 v 1
, or equivalently, vn/β
(7)
n
where vn is defined as the input-referred differential voltage
noise. This equation is the same as that of traditional op amps.
Input Common-Mode Voltage
The linear range of the VAN and VAP terminals extends to within
approximately 1 V of either supply rail. Because VAN and VAP are
essentially equal to each other, they are both equal to the input
common-mode voltage of the amplifier. Their range is indicated
in the Specifications tables as input common-mode range. The
voltage at VAN and VAP for the connection diagram in Figure ±9
can be expressed as
The contribution from the input current noise of each input is
computed as
Vo_n2 = in (RF)
(8)
where in is defined as the input noise current of one input.
Each input needs to be treated separately because the two
input currents are statistically independent processes.
VAN VAP VACM
The contribution from each RG is computed as
RF
RF RG
(VIP V )
RG
RF RG
IN
V
(1±)
OCM
RF
RG
2
Vo_n3 4kTRG
(9)
where VACM is the common-mode voltage present at the
amplifier input terminals.
This result can be intuitively viewed as the thermal noise of
each RG multiplied by the magnitude of the differential gain.
Using the β notation, Equation 1± can be written as follows:
The contribution from each RF is computed as
Vo_n4 = √4kTRF
V
ACM = βVOCM + (1 − β)VICM
or equivalently,
ACM = VICM + β(VOCM − VICM
(16)
(17)
(10)
V
)
where VICM is the common-mode voltage of the input signal,
that is, VICM = VIP + VIN/2.
Rev. C | Page 20 of 26
Data Sheet
AD8139
For proper operation, the voltages at VAN and VAP must stay
within their respective linear ranges.
The input impedance of a conventional inverting op amp
configuration is simply RG, but it is higher in Equation 19
because a fraction of the differential output voltage appears at
the summing junctions, VAN and VAP. This voltage partially
bootstraps the voltage across the input resistor RG, leading to
the increased input resistance.
Calculating Input Impedance
The input impedance of the circuit in Figure ±9 depends on
whether the amplifier is being driven by a single-ended or a
differential signal source. For balanced differential input
signals, the differential input impedance (RIN, dm) is simply
Input Common-Mode Swing Considerations
In some single-ended-to-differential applications, when using a
single-supply voltage, attention must be paid to the swing of the
R
IN, dm = 2RG
(18)
For a single-ended signal (for example, when VIN is grounded
and the input signal drives VIP), the input impedance becomes
input common-mode voltage, VACM
.
Consider the case in Figure 61, where VIN is ± V p-p swinging
about a baseline at ground, and VREF is connected to ground.
RG
RF
RIN
(19)
1
The circuit has a differential gain of 1.6 and β = 0.38. VICM has
an amplitude of 2.± V p-p and is swinging about ground. Using
the results in Equation 16, the common-mode voltage at the
inputs of the AD8139, VACM, is a 1.± V p-p signal swinging
about a baseline of 0.9± V. The maximum negative excursion
of VACM in this case is 0.2 V, which exceeds the lower input
common-mode voltage limit.
2(RG RF )
5V
20Ω
0.1µF
0.1µF
0.1µF
324Ω
15Ω
3
2.7nF
2.7nF
200Ω
5
8
2
1
+
AVDD
DVDD
V
OCM
IN–
2.5V
AD8139
+2.5V
V
–
GND
–2.5V
IN
AD7674
4
6
V
IN+
REF
200Ω
324Ω
15Ω
DGND AGND REFGND REF REFBUFIN PDBUF
47µF
+1.7V
V
ACM
= 0
+0.95V
+0.2V
WITH V
REF
ADR431
0.1µF
2.5V
REFERENCE
Figure 61. AD8139 Driving AD7674, 18-Bit, 800 kSPS ADC
Rev. C | Page 21 of 26
AD8139
Data Sheet
One way to avoid the input common-mode swing limitation is
to bias VIN and VREF at midsupply. In this case, VIN is ± V p-p
swinging about a baseline at 2.± V, and VREF is connected to a
low-Z 2.± V source. VICM now has an amplitude of 2.± V p-p and
is swinging about 2.± V. Using the results in Equation 17, VACM
is calculated to be equal to VICM because VOCM = VICM. Therefore,
Estimating DC Errors
Primary differential output offset errors in the AD8139 are due
to three major components: the input offset voltage, the offset
between the VAN and VAP input currents interacting with the
feedback network resistances, and the offset produced by the dc
voltage difference between the input and output common-mode
voltages in conjunction with matching errors in the feedback
network.
V
ACM swings from 1.2± V to 3.7± V, which is well within the
input common-mode voltage limits of the AD8139. Another
benefit seen in this example is that because VOCM = VACM = VICM
no wasted common-mode current flows. Figure 62 illustrates
how to provide the low-Z bias voltage. For situations that do not
require a precise reference, a simple voltage divider suffices to
develop the input voltage to the buffer.
The first output error component is calculated as
RF RG
RG
Vo_e1 VIO
, or equivalently as VIO/β
(21)
where VIO is the input offset voltage. The input offset voltage of the
5V
AD8139 is laser trimmed and guaranteed to be less than ±00 μV.
0.1µF
324Ω
The second error is calculated as
3
200Ω
5
8
2
1
RF RG
RG
RGRF
RF RG
+
Vo_e2 IIO
IIO
RF
(22)
(23)
V
OCM
V
IN
0V TO 5V
AD8139
–
4
where IIO is defined as the offset between the two input bias
6
currents.
200Ω
324Ω
TO AD7674 REFBUFIN
5V
The third error voltage is calculated as
0.1µF
Vo_e3 = Δenr × (VICM − VOCM
)
0.1µF
+
+
AD8031
–
ADR431
2.5V
REFERENCE
10µF
where Δenr is the fractional mismatch between the two
feedback resistors.
The total differential offset error is the sum of these three error
sources.
Figure 62. Low-Z 2.5 V Buffer
Other Impact of Mismatches in the Feedback Networks
Another way to avoid the input common-mode swing limitation is
to use dual power supplies on the AD8139. In this case, the
biasing circuitry is not required.
The internal common-mode feedback network still forces the
output voltages to remain balanced, even when the RF/RG feedback
networks are mismatched. However, the mismatch causes a gain
error proportional to the feedback network mismatch.
Bandwidth vs. Closed-Loop Gain
Ratio-matching errors in the external resistors degrade the ability
to reject common-mode signals at the VAN and VIN input terminals,
much the same as with a four-resistor difference amplifier made
from a conventional op amp. Ratio-matching errors also produce a
differential output component that is equal to the VOCM input
voltage times the difference between the feedback factors (βs).
In most applications using 1% resistors, this component amounts
to a differential dc offset at the output that is small enough to be
ignored.
The 3 dB bandwidth of the AD8139 decreases proportionally
to increasing closed-loop gain in the same way as a traditional
voltage feedback operational amplifier. For closed-loop gains
greater than 4, the bandwidth obtained for a specific gain can be
estimated as
RG
f 3 dB,VOUT,dm
(300 MHz)
(20)
RG RF
or equivalently, β(300 MHz).
This estimate assumes a minimum 90° phase margin for the
amplifier loop, which is a condition approached for gains greater
than 4. Lower gains show more bandwidth than predicted by
the equation due to the peaking produced by the lower
phase margin.
Rev. C | Page 22 of 26
Data Sheet
AD8139
Driving a Capacitive Load
The input resistance presented by the AD8139 input circuitry is
seen in parallel with the termination resistor, and its loading
effect must be taken into account. The Thevenin equivalent
circuit of the driver, its source resistance, and the termination
resistance must all be included in the calculation as well. An
exact solution to the problem requires the solution of several
simultaneous algebraic equations and is beyond the scope of
this data sheet. An iterative solution is also possible and simpler,
especially considering the fact that standard 1% resistor values
are generally used.
A purely capacitive load reacts with the bondwire and pin
inductance of the AD8139, resulting in high frequency ringing
in the transient response and loss of phase margin. One way to
minimize this effect is to place a small resistor in series with
each output to buffer the load capacitance (see Figure ±8 and
Figure 63). The resistor and load capacitance form a first-order,
low-pass filter; therefore, the resistor value should be as small as
possible. In some cases, the ADCs require small series resistors
to be added on their inputs.
5
4
3
2
1
Figure 64 shows the AD8139 in a unity-gain configuration
driving the AD664±, which is a 14-bit, high speed ADC, and
with the following discussion, provides a good example of how
to provide a proper termination in a ±0 Ω environment.
R
C
= 30.1Ω
= 5pF
S
L
R
C
= 30.1Ω
= 15pF
S
L
0
R
C
= 0Ω
S
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
–11
–12
–13
= 0pF
L, dm
The termination resistor, RT, in parallel with the 268 Ω input
resistance of the AD8139 circuit (calculated using Equation 19),
yields an overall input resistance of ±0 Ω that is seen by the signal
source. To have matched feedback loops, each loop must have
the same RG if they have the same RF. In the input (upper) loop,
RG is equal to the 200 Ω resistor in series with the (+) input plus
the parallel combination of RT and the source resistance of ±0 Ω.
In the upper loop, RG is therefore equal to 228 Ω. The closest
standard 1% value to 228 ꢀ is 226 Ω and is used for RG in the
lower loop. Greater accuracy could be achieved by using two
resistors in series to obtain a resistance closer to 228 Ω.
R
C
= 60.4Ω
= 15pF
S
L
R
= 60.4Ω
S
C
= 5pF
L
V
V
= ±5V
S
= 0.1V p-p
O, dm
G = 1 (R = R = 200Ω)
R
F
G
= 1kΩ
L, dm
10M
100M
FREQUENCY (Hz)
1G
Figure 63. Frequency Response for
Various Capacitive Loads and Series Resistances
Things get more complicated when it comes to determining the
feedback resistor values. The amplitude of the signal source
generator VS is two times the amplitude of its output signal when
terminated in ±0 Ω. Therefore, a 2 V p-p terminated amplitude
is produced by a 4 V p-p amplitude from VS. The Thevenin
equivalent circuit of the signal source and RT must be used when
calculating the closed-loop gain, because in the upper loop, RG is
split between the 200 Ω resistor and the Thevenin resistance
looking back toward the source. The Thevenin voltage of the
signal source is greater than the signal source output voltage
when terminated in ±0 Ω because RT must always be greater than
±0 Ω. In this case, RT is 61.9 Ω and the Thevenin voltage and
resistance are 2.2 V p-p and 28 Ω, respectively. Now the upper
input branch can be viewed as a 2.2 V p-p source in series
with 228 Ω. Because this is a unity-gain application, a 2 V p-p
differential output is required, and RF must therefore be 228 ×
(2/2.2) = 206 Ω. The closest standard value to this is 20± Ω.
The Typical Performance Characteristics that illustrate transient
response vs. the capacitive load were generated using series
resistors in each output and a differential capacitive load.
Layout Considerations
Standard high speed PCB layout practices should be adhered
to when designing with the AD8139. A solid ground plane is
recommended, and good wideband power supply decoupling
networks should be placed as close as possible to the supply pins.
To minimize stray capacitance at the summing nodes, the copper
in all layers under all traces and pads that connect to the summing
nodes should be removed. Small amounts of stray summing-node
capacitance cause peaking in the frequency response, and large
amounts can cause instability. If some stray summing-node
capacitance is unavoidable, its effects can be compensated for
by placing small capacitors across the feedback resistors.
Terminating a Single-Ended Input
When generating the Typical Performance Characteristics data,
the measurements were calibrated to take the effects of the
terminations on the closed-loop gain into account.
Controlled impedance interconnections are used in most
high speed signal applications, and they require at least one
line termination. In analog applications, a matched resistive
termination is generally placed at the load end of the line. This
section deals with how to properly terminate a single-ended
input to the AD8139.
Rev. C | Page 23 of 26
AD8139
Data Sheet
Because this is a single-ended-to-differential application on a
single supply, the input common-mode voltage swing must be
checked. From Figure 64, β = 0.±2, VOCM = 2.4 V, and VICM is
1.1 V p-p swinging about ground. Using Equation 16, VACM is
calculated to be 0.±3 V p-p swinging about a baseline of 1.2± V,
and the minimum negative excursion is approximately 1 V.
Exposed Paddle (EP)
The 8-lead SOIC and the 8-lead LFCSP have an exposed paddle
on the bottom of the package. To achieve the specified thermal
resistance, the exposed paddle must be soldered to one of the
PCB planes. The exposed paddle mounting pad should contain
several thermal vias within it to ensure a low thermal path to
the plane.
5V
3.3V
0.01µF
0.01µF
0.01µF
205Ω
25Ω
AV
DV
CC
CC
AIN
AIN
3
2V p-p
50Ω
200Ω
5
8
2
1
+
R
T
61.9Ω
V
OCM
V
S
AD8139
AD6645
SIGNAL
SOURCE
–
4
6
226Ω
GND C1
C2
VREF
205Ω
25Ω
0.1µF
0.1µF
2.4V
Figure 64. AD8139 Driving AD6645, 14-Bit, 80 MSPS/105 MSPS ADC
Rev. C | Page 24 of 26
Data Sheet
AD8139
OUTLINE DIMENSIONS
5.00
4.90
4.80
2.29
0.356
5
4
6.20
6.00
5.80
8
4.00
3.90
3.80
2.29
0.457
1
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
BOTTOM VIEW
45°
1.27 BSC
3.81 REF
TOP VIEW
SECTION OF THIS DATA SHEET.
1.65
1.25
1.75
1.35
0.50
0.25
0.25
0.17
0.10 MAX
0.05 NOM
SEATING
PLANE
8°
0°
0.51
0.31
1.04 REF
1.27
0.40
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MS-012-AA
Figure 65. 8-Lead Standard Small Outline Package with Exposed Pad [SOIC_N_EP]
Narrow Body
(RD-8-1)
Dimensions shown in millimeters
1.84
1.74
1.64
3.10
3.00 SQ
2.90
0.50 BSC
8
5
PIN 1 INDEX
EXPOSED
PAD
1.55
1.45
1.35
AREA
0.50
0.40
0.30
4
1
PIN 1
INDICATOR
(R 0.15)
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.30
0.25
0.20
0.203 REF
COMPLIANT TOJEDEC STANDARDS MO-229-WEED
Figure 66. 8-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-8-13)
Dimensions shown in millimeters
Rev. C | Page 25 of 26
AD8139
Data Sheet
ORDERING GUIDE
Package
Model1
Temperature Range
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
Package Description
Option
RD-8-1
RD-8-1
RD-8-1
CP-8-13
CP-8-13
CP-8-13
Branding
AD8139ARDZ
8-Lead Small Outline Package with Exposed Pad [SOIC_N_EP]
8-Lead Small Outline Package with Exposed Pad [SOIC_N_EP]
8-Lead Small Outline Package with Exposed Pad [SOIC_N_EP]
8-Lead Lead Frame Chip Scale Package [LFCSP]
8-Lead Lead Frame Chip Scale Package [LFCSP]
8-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
AD8139ARDZ-REEL
AD8139ARDZ-REEL7
AD8139ACPZ-R2
AD8139ACPZ-REEL
AD8139ACPZ-REEL7
AD8139ACP-EBZ
HEB#
HEB#
HEB#
1 Z = RoHS Compliant Part, # denotes RoHS product may be top or bottom marked.
©2004–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04679-0-6/16(C)
Rev. C | Page 26 of 26
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