AD8143-EVALZ [ADI]
High Speed, Triple Differential Receiver with Comparators;
| 型号： | AD8143-EVALZ |
| 厂家： | 
ADI |
| 描述： | High Speed, Triple Differential Receiver with Comparators |
| 文件： | 总24页 (文件大小：639K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Speed, Triple Differential
Receiver with Comparators
Data Sheet
AD8143
FEATURES
PIN CONFIGURATION
High speed
160 MHz large signal bandwidth
1000 V/µs slew rate at G = 1, VO = 2 V p-p
High CMRR: 65 dB at 10 MHz
High differential input impedance: 5 MΩ
Input common-mode range: 10.5 V ( 12 V supplies)
User-adjustable gain
Wide power supply range: +5 V to 12 V
Fast settling: 8 ns to 1%
Disable feature
32
31
30
29
28
27
26
25
GND
REF_G
FB_G
1
2
3
4
5
6
7
8
24 GND
23
22
21
20
19
18
17
OUT_B
OUT_G
OUT_R
IN+_G
IN–_G
REF_R
FB_R
AD8143
V
S+
Low offset: 3.4 mV on 5 V supply
2 on-chip comparators
Small packaging: 32-lead, 5 mm × 5 mm LFCSP
COMPB_IN+
COMPB_IN–
GND
B
A
APPLICATIONS
GND
RGB video receivers
Keyboard-video-mouse (KVM)
Unshielded twisted pair (UTP) receivers
9
10
11
12
13
14
15
16
Figure 1.
GENERAL DESCRIPTION
The AD8143 has a wide power supply range from single +5 V
supply to 12 V, which allows for a wide common-mode range.
The wide common-mode input range of the AD8143 maintains
signal integrity in systems where the ground potential is a few
volts different between the drive and receive ends without the
use of isolation transformers.
The AD8143 is a triple, low cost, differential-to-single-
ended receiver specifically designed for receiving red-
green-blue (RGB) signals over twisted pair cable. It can
also be used for receiving any type of analog signal or
high speed data transmission. Two auxiliary comparators
are provided to receive digital or sync signals. The
AD8143 can be used in conjunction with the AD8133
and AD8134 triple, differential drivers to provide a
complete low cost solution for RGB over Category-5
UTP cable applications, including KVM.
The AD8143 is stable at a gain of 1. Closed-loop gain is easily
set using external resistors.
The AD8143 is available in a 5 mm × 5 mm, 32-lead LFCSP and
is rated to work over the extended industrial temperature range
of −40°C to +85°C.
The excellent common-mode rejection (65 dB at
10 MHz) of the AD8143 allows for the use of low cost
unshielded twisted pair cables in noisy environments.
Rev. A
Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject tochange without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Tel: 781.329.4700 ©2005–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD8143
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Overview ..................................................................................... 18
Basic Closed-Loop Gain Configurations ................................ 18
Terminating the Input................................................................ 19
Input Clamping........................................................................... 19
Printed Circuit Board Layout Considerations ....................... 20
Driving a Capacitive Load......................................................... 22
Power-Down ............................................................................... 22
Comparators ............................................................................... 22
Sync Pulse Extraction Using Comparators............................. 22
Outline Dimensions....................................................................... 24
Ordering Guide .......................................................................... 24
Applications....................................................................................... 1
Pin Configuration............................................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 9
Thermal Resistance ...................................................................... 9
ESD Caution.................................................................................. 9
Pin Configuration and Function Descriptions........................... 10
Typical Performance Characteristics ........................................... 11
Theory of Operation ...................................................................... 17
Applications Information .............................................................. 18
REVISION HISTORY
4/16—Rev. 0 to Rev. A
Changes to Figure 3 and Table 6................................................... 10
Updated Outline Dimensions....................................................... 24
Changes to Ordering Guide .......................................................... 24
10/05—Revision 0: Initial Version
Rev. A | Page 2 of 24
Data Sheet
AD8143
SPECIFICATIONS
VS = 12 V, TA = 25°C, REF = 0 V, R L = 150 Ω, CL = 2 pF, G = 1, TMIN to TMAX = −40°C to +85°C, unless otherwise noted.
Table 1.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth
VOUT = 0.2 V p-p
VOUT = 2 V p-p
VOUT = 0.2 V p-p
VOUT = 2 V p-p, RL = 1 kΩ
VOUT = 2 V p-p, 1%
VOUT = 2 V p-p, 0.1%
260
160
45
1000
8
MHz
MHz
MHz
V/µs
ns
Bandwidth for 0.1dB Flatness
Slew Rate
Settling Time
31
ns
Output Overdrive Recovery
NOISE/DISTORTION
Second Harmonic
Third Harmonic
Crosstalk
Input Voltage Noise (RTI)
Differential Gain Error
Differential Phase Error
INPUT CHARACTERISTICS
Common-Mode Rejection
50
ns
VOUT = 2 V p-p, 1 MHz
VOUT = 2 V p-p, 1 MHz
VOUT = 1 V p-p, 10 MHz
f ≥ 10 kHz
NTSC, 200 IRE, RL ≥ 150 Ω
NTSC, 200 IRE, RL ≥ 150 Ω
−70
−80
−70
14
0.03
0.06
dBc
dBc
dB
nV/√Hz
%
Degrees
DC, VCM = −3.5 V to +3.5 V
VCM = 1 V p-p, f = 10 MHz
VCM = 1 V p-p, f = 100 MHz
V+IN − V−IN = 0 V
86
90
65
28
10.5
2.5
5
3
2
3
dB
dB
dB
V
Common-Mode Voltage Range
Differential Operating Range
Resistance
V
Differential
Common-mode
Differential
MΩ
MΩ
pF
pF
Capacitance
Common-mode
DC PERFORMANCE
Open-Loop Gain
Closed-Loop Gain Error
Input Offset Voltage
VOUT = 1 V
DC
70
0.25
dB
%
mV
−4.3
+4.3
TMIN to TMAX
15
µV/°C
µA
µA
Input Bias Current (+IN, −IN)
Input Bias Current (REF, FB)
Input Bias Current Drift
Input Offset Current
Input Offset Current Drift
OUTPUT PERFORMANCE
Voltage Swing
−3.0
−4.6
+3.0
+3.7
TMIN to TMAX (+IN, −IN)
(+IN, −IN, REF, FB)
TMIN to TMAX
16
3
nA/°C
µA
nA/°C
−2.55
+1.45
RLOAD = 1 kΩ
−10.80
+10.82
V
Output Current
40
107/147
mA
mA
Short Circuit Current
COMPARATOR PERFORMANCE
VOH
Short to GND, source/sink
3.135
3.3
0.2
41
3.5
20
15
15
11
V
V
VOL
0.255
Hysteresis Width
mV
µA
ns
ns
ns
ns
Input Bias Current
Propagation Delay, tPLH
Propagation Delay, tPHL
Output Rise Time
Input driven low
RL = 10 kΩ
RL = 10 kΩ
25% to 75%, RL = 10 kΩ
25% to 75%, RL = 10 kΩ
Output Fall Time
Rev. A | Page 3 of 24
AD8143
Data Sheet
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
POWER-DOWN PERFORMANCE
Power-Down VIH
Power-Down VIL
Power-Down IIH
Power-Down IIL
VS+ − 1.5
VS+ − 2.5
1.0
800
0.5
V
V
µA
µA
µs
PD = VCC
PD = GND
Power-Down Assert Time
POWER SUPPLY
Operating Range
4.5
24
V
Quiescent Current, Positive Supply
Quiescent Current, Negative Supply
PSRR, Positive Supply
PSRR, Negative Supply
44.0
37.0
−75
−82
57.5
51.0
−71
−81
mA
mA
dB
dB
DC
DC
Rev. A | Page 4 of 24
Data Sheet
AD8143
VS = 5 V, TA = 25°C, REF = 0 V, R L = 150 Ω, CL = 2 pF, G = 1, TMIN to TMAX = −40°C to +85°C, unless otherwise noted.
Table 2.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth
VOUT = 0.2 V p-p
VOUT = 2 V p-p
VOUT = 0.2 V p-p
VOUT = 2 V p-p, RL = 1 kΩ
VOUT = 2 V p-p, 1%
VOUT = 2 V p-p, 0.1%
230
130
45
1000
10
MHz
MHz
MHz
V/µs
ns
Bandwidth for 0.1dB Flatness
Slew Rate
Settling Time
23
ns
Output Overdrive Recovery
NOISE/DISTORTION
Second Harmonic
Third Harmonic
Crosstalk
Input Voltage Noise (RTI)
Differential Gain Error
Differential Phase Error
INPUT CHARACTERISTICS
Common-Mode Rejection
50
ns
VOUT = 1 V p-p, 1 MHz
VOUT = 1 V p-p, 1 MHz
VOUT = 1 V p-p, 10 MHz
f ≥ 10 kHz
NTSC, 200 IRE, RL ≥ 150 Ω
NTSC, 200 IRE, RL ≥ 150 Ω
−68
−82
−70
14
0.3
0.6
dBc
dBc
dB
nV/√Hz
%
Degrees
DC, VCM = −3.5 V to +3.5 V
VCM = 1 V p-p, f = 10 MHz
VCM = 1 V p-p, f = 100 MHz
V+IN − V−IN = 0 V
84
90
65
28
3.8
2.5
5
3
2
3
dB
dB
dB
V
Common-Mode Voltage Range
Differential Operating Range
Resistance
V
Differential
Common-mode
Differential
MΩ
MΩ
pF
pF
Capacitance
Common-mode
DC PERFORMANCE
Open-Loop Gain
Closed-Loop Gain Error
Input Offset Voltage
VOUT = 1 V
DC
70
0.25
dB
%
mV
−3.7
+3.7
TMIN to TMAX
15
µV/°C
µA
µA
Input Bias Current (+IN, −IN)
Input Bias Current (REF, FB)
Input Bias Current Drift
Input Offset Current
Input Offset Current Drift
OUTPUT PERFORMANCE
Voltage Swing
−3.0
−4.3
+2.7
+3.0
TMIN to TMAX (+IN, −IN, REF, FB)
(+IN, −IN, REF, FB)
TMIN to TMAX
16
3
nA/°C
µA
nA/°C
−2.9
1.9
RLOAD = 150 Ω
−3.53
+3.53
V
Output Current
40
107/147
mA
mA
Short Circuit Current
COMPARATOR PERFORMANCE
VOH
Short to GND, source/sink
RL = 10 kΩ
RL = 10 kΩ
3.02
3.14
0.19
32
3.5
20
15
15
11
V
V
VOL
0.25
Hysteresis Width
mV
µA
ns
ns
ns
ns
Input Bias Current
Propagation Delay, tPLH
Propagation Delay, tPHL
Output Rise Time
Input driven low
10% to 90%
10% to 90%
Output Fall Time
Rev. A | Page 5 of 24
AD8143
Data Sheet
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
POWER-DOWN PERFORMANCE
Power-Down VIH
Power-Down VIL
Power-Down IIH
Power-Down IIL
VS+ − 1.5
VS+ − 2.5
1
230
0.5
V
V
µA
µA
µs
PD = VCC
PD = GND
Power-Down Assert Time
POWER SUPPLY
Operating Range
4.5
24
V
Quiescent Current, Positive Supply
Quiescent Current, Negative Supply
PSRR, Positive Supply
PSRR, Negative Supply
39.0
34.5
−80
−80
49.5
43.5
−74
−75
mA
mA
dB
dB
DC
DC
Rev. A | Page 6 of 24
Data Sheet
AD8143
VS = 5 V, TA = 25°C, REF = +2.5 V, R L = 150 Ω, CL = 2 pF, G = 1, TMIN to TMAX = −40°C to +85°C, unless otherwise noted.
Table 3.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth
VOUT = 0.2 V p-p
VOUT = 2 V p-p
VOUT = 0.2 V p-p
VOUT = 2 V p-p, RL = 1 kΩ
VOUT = 2 V p-p, 1%
VOUT = 2 V p-p, 0.1%
220
125
45
1000
10
MHz
MHz
MHz
V/µs
ns
Bandwidth for 0.1dB Flatness
Slew Rate
Settling Time
23
ns
Output Overdrive Recovery
NOISE
50
ns
Crosstalk
VOUT = 1 V p-p, 10 MHz
f ≥ 10 kHz
−70
14
dB
nV/√Hz
Input Voltage Noise (RTI)
INPUT CHARACTERISTICS
Common-Mode Rejection
DC, VCM = −3.5 V to +3.5 V
VCM = 1 V p-p, f = 10 MHz
VCM = 1 V p-p, f = 100 MHz
V+IN − V−IN = 0 V
76
90
65
32
1.3 to 3.7
dB
dB
dB
V
Common-Mode Voltage Range
Differential Operating Range
Resistance
2.5
V
Differential
Common-mode
Differential
5
3
2
3
MΩ
MΩ
pF
pF
Capacitance
Common-mode
DC PERFORMANCE
Open-Loop Gain
VOUT = 1 V
70
dB
Closed-Loop Gain Error
Input Offset Voltage
DC, measured at G = 11
0.25
%
mV
−3.4
+3.4
TMIN to TMAX
15
µV/°C
µA
µA
Input Bias Current (+IN, −IN)
Input Bias Current (REF, FB)
Input Bias Current Drift
Input Offset Current
Input Offset Current Drift
OUTPUT PERFORMANCE
Voltage Swing
−3
−4.5
+2.7
+3
TMIN to TMAX (+IN, −IN, REF, FB)
(+IN, −IN, REF, FB)
TMIN to TMAX
16
3
nA/°C
µA
nA/°C
−2.3
0.88
+1.3
3.58
RLOAD = 150 Ω
Short to GND
V
mA
mA
Output Current
40
150
Short Circuit Current
COMPARATOR PERFORMANCE
VOH
RL = 10 kΩ
RL = 10 kΩ
3.02
V
V
VOL
0.25
Hysteresis Width
32
3.5
20
15
15
11
mV
µA
ns
ns
ns
ns
Input Bias Current
Propagation Delay, tPLH
Propagation Delay, tPHL
Output Rise Time
Input driven low
10% to 90%
10% to 90%
Output Fall Time
POWER-DOWN PERFORMANCE
Power-Down VIH
Power-Down VIL
Power-Down IIH
Power-Down IIL
VS+ − 1.5
VS+ − 2.5
1
230
0.5
V
V
µA
µA
µs
PD = VCC
PD = GND
Power-Down Assert Time
Rev. A | Page 7 of 24
AD8143
Data Sheet
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
POWER SUPPLY
Operating Range
4.5
24
V
Quiescent Current, Positive Supply
PSRR, Positive Supply
31.5
−86
38.8
−76
mA
dB
DC
Rev. A | Page 8 of 24
Data Sheet
AD8143
ABSOLUTE MAXIMUM RATINGS
Table 4.
power dissipated due to all of the loads is equal to the sum of
the power dissipation due to each individual load. RMS voltages
and currents must be used in these calculations.
Parameter
Rating
Supply Voltage
24 V
Airflow increases heat dissipation, effectively reducing θJA. In
addition, more metal directly in contact with the package leads
from metal traces, through-holes, ground, and power planes
reduces the θJA. The exposed paddle on the underside of the
package must be soldered to a pad on the PCB surface which is
thermally connected to a copper plane to achieve the specified θJA.
Power Dissipation
See Figure 2
–65°C to +125°C
–40°C to +85°C
300°C
Storage Temperature Range
Operating Temperature Range
Lead Temperature Range (Soldering 10 sec)
Junction Temperature
150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Figure 2 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 32-lead LFCSP
(45°C/W) on a JEDEC standard 4-layer board with the underside
paddle soldered to a pad which is thermally connected to a PCB
plane. Extra thermal relief is required for operation at high
supply voltages. See the Applications Information section for
details. θJA values are approximations.
THERMAL RESISTANCE
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
θJA is specified for the worst-case conditions, that is, θJA is
specified for a device soldered in the circuit board with its
exposed paddle soldered to a pad on the PCB surface, which is
thermally connected to a copper plane.
Table 5. Thermal Resistance
Package Type
θJA
θJC
Unit
5 mm × 5 mm, 32-Lead LFCSP
45
7
°C/W
Maximum Power Dissipation
The maximum safe power dissipation in the AD8143 package is
limited by the associated rise in junction temperature (TJ) on
the die. At approximately 150°C, which is the glass transition
temperature, the plastic changes its properties. Even temporarily
exceeding this temperature limit can change the stresses that the
package exerts on the die, permanently shifting the parametric
performance of the AD8143. Exceeding a junction temperature
of 150°C for an extended period can result in changes in the
silicon devices potentially causing failure.
–40
–20
0
20
40
60
80
AMBIENT TEMPERATURE (°C)
Figure 2. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). The power dissipated due to the load
drive depends upon the particular application. For each output,
the power due to load drive is calculated by multiplying the load
current by the associated voltage drop across the device. The
Rev. A | Page 9 of 24
AD8143
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
GND
REF_G
FB_G
IN+_G
IN–_G
REF_R
FB_R
1
2
3
4
5
6
7
8
24 GND
23
22 OUT_G
21 OUT_R
OUT_B
AD8143
TOP VIEW
20
19
V
S+
COMPB_IN+
(Not to Scale)
18 COMPB_IN–
17 GND
GND
NOTES
1. THE EXPOSED PAD ON THE UNDERSIDE OF THE
DEVICE MUST BE CONNECTED TO GROUND.
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 8, 9,16, 17, 24, 25, 32
2
3
4
5
6
7
GND
REF_G
FB_G
IN+_G
IN−_G
REF_R
FB_R
IN+_R
Signal Ground and Thermal Plane Connection (See the Applications Information Section)
Reference Input, Green Channel
Feedback Input, Green Channel
Noninverting Input, Green Channel
Inverting Input, Green Channel
Reference Input, Red Channel
Feedback Input, Red Channel
Noninverting Input, Red Channel
Inverting Input, Red Channel
Positive Input, Comparator A
Negative Input, Comparator A
Output, Comparator A
10
11
12
13
14
15
18
19
20
21
22
23
26
27
28
29
30
31
0
IN−_R
COMPA_IN+
COMPA_IN−
COMPA_OUT
COMPB_OUT
COMPB_IN−
COMPB_IN+
VS+
OUT_R
OUT_G
OUT_B
VS−
DIS/PD
REF_B
FB_B
IN+_B
IN−_B
Output, Comparator B
Negative Input, Comparator B
Positive Input, Comparator B
Positive Power Supply
Output, Red Channel
Output, Green Channel
Output, Blue Channel
Negative Power Supply
Disable/Power Down
Reference Input, Blue Channel
Feedback Input, Blue Channel
Noninverting Input, Blue Channel
Inverting Input, Blue Channel
Exposed Pad. The exposed pad on the underside of the device must be connected to
ground (see the Applications Information section).
EPAD
Rev. A | Page 10 of 24
Data Sheet
AD8143
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise noted, G = 1, RL = 150 Ω, CL = 2 pF, VS = 5 V, T A = 25°C. Refer to the circuit in Figure 38.
3
2
3
2
V
= ±5
S
1
1
V
= ±12
S
0
0
–1
–2
–3
–4
–5
–6
–7
–1
–2
–3
–4
–5
–6
–7
V
= ±12
S
V
= ±5
S
V
= +5
S
V
= 0.2V p-p
V
= 2V p-p
V = +5
S
OUT
OUT
1
10
FREQUENCY (MHz)
100
1
10
FREQUENCY (MHz)
100
Figure 4. Small Signal Frequency Response at Various Power Supplies, G = 1
Figure 7. Large Signal Frequency Response at Various Power Supplies, G = 1
9
8
9
V
= +5
S
8
7
V
= ±5
V = +5
S
S
7
6
V
= ±5
S
6
5
5
V
S
= ±12
V
= ±12
S
4
4
4
3
2
2
1
1
V
= 0.2V p-p
V
= 2V p-p
OUT
OUT
0
0
–1
–1
1
10
FREQUENCY (MHz)
100
1
10
FREQUENCY (MHz)
100
Figure 5. Small Signal Frequency Response at Various Power Supplies, G = 2
Figure 8. Large Signal Frequency Response at Various Power Supplies, G = 2
3
2
3
2
1
R
= 1kΩ
L
1
0
R
= 1kΩ
L
0
–1
–2
–3
–4
–5
–6
–7
–1
–2
–3
–4
–5
–6
–7
R
= 150Ω
R
= 150Ω
L
L
V
= 0.2V p-p
V
= 2V p-p
OUT
OUT
1
10
FREQUENCY (MHz)
100
1
10
FREQUENCY (MHz)
100
Figure 6. Small Signal Frequency Response at Various Loads
Figure 9. Large Signal Frequency Response at Various Loads
Rev. A | Page 11 of 24
AD8143
Data Sheet
5
4
5
4
G = 1, C = 10pF, R
SNUB
= 40Ω
L
3
3
G = 1, C = 2pF
G = 1, C = 10pF, R
= 40Ω
L
L
SNUB
G = 2, C = 10pF, R
SNUB
= 40Ω
2
2
L
G = 2, C = 10pF, R
SNUB
= 40Ω
L
1
1
0
0
G = 2, C = 2pF
L
–1
–2
–3
–1
–2
–3
–4
–5
G = 2, C = 2pF
L
G = 1, C = 2pF
L
R
= 1kΩ
R = 1kΩ
L
OUT
L
–4
–5
V
= 0.2V p-p
V
= 2V p-p
OUT
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 13. Large Signal Frequency Response at Various Gains and 10 pF
Capacitive Load Buffered by 40 Ω Resistor
Figure 10. Small Signal Frequency Response at Various Gains and 10 pF
Capacitive Load Buffered by 40 Ω Resistor
3
2
1
3
2
G = 1
1
0
0
G = 1
–1
–2
–3
–4
–5
–1
–2
G = 2
–3
–4
–5
V
= 2V p-p
V
= 0.2V p-p
OUT
G = 2
OUT
–6
–7
–6
–7
1
10
FREQUENCY (MHz)
100
1
10
100
FREQUENCY (MHz)
Figure 14. Large Signal Frequency Response at Various Gains
Figure 11. Small Signal Frequency Response at Various Gains
80
70
60
50
40
30
20
10
0
0
0.5
0.4
–20
R
= 1kΩ, V
= 2V p-p
L
OUT
0.3
0.2
–40
R
= 1kΩ, V
= 0.2V p-p
MAGNITUDE
L
OUT
–60
0.1
–80
0
–100
–120
–140
–160
–180
PHASE
–0.1
–0.2
–0.3
–0.4
–0.5
R
L
= 150Ω, V
= 0.2V p-p
OUT
R
= 150Ω, V
= 2V p-p
L
OUT
–10
0.001
0.01
0.1
1
10
100
1000
1
10
FREQUENCY (MHz)
100
FREQUENCY (MHz)
Figure 15. Open-Loop Gain and Phase Responses
Figure 12. 0.1 dB Flatness for Various Loads and Output Amplitudes
Rev. A | Page 12 of 24
Data Sheet
AD8143
100
90
80
70
60
50
40
30
20
10
100
V
= ±12V
S
±12V
+5V
±5V
0
0.1
10
0.00001
1
10
FREQUENCY (MHz)
100
1000
0.0001
0.001
0.01
0.1
1
10
FREQUENCY (MHz)
Figure 16. Common-Mode Rejection Ratio vs. Frequency at Various Supplies
Figure 19. Input Referred Voltage Noise vs. Frequency
200
1.5
1.0
V
= 0.2V p-p
V
= 2V p-p
OUT
OUT
150
100
50
0.5
G = 1, R = 150Ω
L
G = 1, R = 150Ω
L
G = 1, R = 1kΩ
L
G = 1, R = 1kΩ
L
G = 2, R = 150Ω
0
0
L
G = 2, R = 150Ω
L
G = 2, R = 1kΩ
L
G = 2, R = 1kΩ
L
–50
–100
–0.5
–1.0
–1.5
–150
–200
0
10
20
30
40
50
60
70
80
90
100
0
10
20
30
40
50
60
70
80
90
100
TIME (ns)
TIME (ns)
Figure 17. Small Signal Transient Response at Various Gains and Loads
Figure 20. Large Signal Transient Response at Various Gains and Loads
200
1.5
G = 2, C = 10pF, R
SNUB
= 40Ω
L
G = 2, C = 2pF
L
G = 2, C = 2pF
L
150
100
50
G = 2, C = 10pF, R
L
= 40Ω
1.0
0.5
SNUB
G = 1, C = 2pF
L
0
0
R
= 1kΩ
–50
–100
–150
–200
L
–0.5
–1.0
–1.5
V
= 2V p-p
OUT
G = 1, C = 2pF
L
G = 1, C = 10pF, R
SNUB
= 40Ω
L
R
= 1kΩ
L
V
= 0.2V p-p
OUT
G = 1, C = 10pF, R
= 40Ω
L
SNUB
0
10
20
30
40
50
60
70
80
90
100
0
10
20
30
40
50
TIME (ns)
60
70
80
90
100
TIME (ns)
Figure 18. Small Signal Transient Response at Various Gains and 10 pF
Capacitive Load Buffered by 40 Ω Resistor
Figure 21. Large Signal Transient Response at Various Gains and 10 pF
Capacitive Load Buffered by 40 Ω Resistor
Rev. A | Page 13 of 24
AD8143
Data Sheet
1.25
1.00
0.5
1400
1200
1000
800
600
400
200
0
0.4
INPUT
0.75
0.50
0.3
0.2
0.25
0.1
ERROR
0
0
+SR, R = 150
L
–SR, R = 150
L
+SR, R = 1k
–0.25
–0.50
–0.75
–1.00
–1.25
–0.1
–0.2
–0.3
–0.4
–0.5
L
–SR, R = 1k
L
OUTPUT
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0
10
20
30
40
50
60
70
80
90
100
OUTPUT VOLTAGE (V p-p)
TIME (ns)
Figure 22. Settling Time (0.1%) at Various Loads
Figure 25. Slew Rate vs. Input Voltage Swing at Various Loads
–50
–55
–60
–65
–70
–75
–80
–30
–40
–50
–60
–70
V
= ±12V
S
V
= ±5V
S
–80
–90
Vs = ±5V
Vs = ±12V
–100
0.1
1
10
FREQUENCY (MHz)
100
0.1
1
10
FREQUENCY (MHz)
100
Figure 23. Second Harmonic Distortion vs. Frequency and Power Supplies,
VO = 2 V p-p, G = 2
Figure 26. Third Harmonic Distortion vs. Frequency and Power Supplies,
VO = 2 V p-p, G = 2
–30
–40
–50
–60
–50
–55
–60
V
= ±12V
S
–65
–70
–75
V
= ±12V
–70
–80
–90
S
V
= ±5V
S
V
= ±5V
S
0.1
1
10
FREQUENCY (MHz)
100
0.1
1
10
FREQUENCY (MHz)
100
Figure 24. Second Harmonic Distortion vs. Frequency and Power Supplies,
VO = 2 V p-p
Figure 27. Third Harmonic Distortion vs. Frequency and Power Supplies,
VO = 2 V p-p
Rev. A | Page 14 of 24
Data Sheet
AD8143
54
52
50
48
46
44
42
40
38
4
3
I +
S
2
1
0
–1
–2
–3
–4
I –
S
V
R
= ±12V
=
S
L
–5
–4
–3
–2
–1
0
1
2
3
4
5
–5
–4
–3
–2
–1
0
1
2
3
4
5
DIFFERENTIAL INPUT VOLTAGE (V)
DIFFERENTIAL INPUT VOLTAGE (V)
Figure 28. Power Supply Current vs. Differential Input Voltage at 12 V Supplies
Figure 31. Differential Input Operating Range
60
50
45
40
35
30
25
R
=
L
I
+, V = ±12V
S
S
55
50
45
40
35
30
25
20
15
10
I
–, V = ±12V
S
S
I +
S
I –
S
I –, V = ±5V
S
S
I
+, V = ±5V
S
S
R
=
L
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90 100
5
6
7
8
9
10
11
12
TEMPERATURE (C)
SUPPLY VOLTAGE (V )
S
Figure 29. Power Supply Current vs. Temperature
Figure 32. Power Supply Current vs. Power Supply Voltage
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
V
= ±5V
S
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
V
= ±5V
S
V
= +5V
S
V
= ±12V
S
V
= ±12V
S
0.01
0.1
1
10
100
1000
0.01
0.1
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 30. Positive Power Supply Rejection Ratio vs. Frequency
Figure 33. Negative Power Supply Rejection Ratio vs. Frequency
Rev. A | Page 15 of 24
AD8143
Data Sheet
15
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
G = +2 (R = R = 499Ω) AND V = ±5V
F
G
S
G = +5 (R = 8.06kΩ R = 2kΩ) AND V = ±12V
F
G
S
V
= ±12V
S
10
5
+V
+V
_±12V
_±5V
SAT
V
= ±5V
S
SAT
0
–5
–10
–15
–V
–V
_±5V
SAT
_±12V
SAT
0
100 200 300 400 500 600 700 800 900 1000
–25 –20 –15 –10
–5
0
5
10
15
20
25
OUTPUT LOAD (Ω)
V
(mV)
IN
Figure 34. Output Saturation Voltage vs. Output Load
Figure 36. Comparator Hysteresis
6
5
2 × V
IN
G = 2
4
3
2
1
0
–1
–2
–3
–4
–5
–6
OUTPUT
0
100 200 300 400 500 600 700 800 900 1000
TIME (ns)
Figure 35. Output Overdrive Recovery
Rev. A | Page 16 of 24
Data Sheet
AD8143
THEORY OF OPERATION
The AD8143 amplifiers use an architecture called active feedback,
which differs from that of conventional op amps. The most
obvious differentiating feature is the presence of two separate
pairs of differential inputs compared to a conventional op amp’s
single pair. Typically, for the active-feedback architecture, one of
these input pairs is driven by a differential input signal, while
the other is used for the feedback. This active stage in the
feedback path is where the term active feedback is derived.
The two differential input stages of the AD8143 are each
transconductance stages that are well-matched. These stages
convert the respective differential input voltages to internal
currents. The currents are then summed and converted to a
voltage, which is buffered to drive the output. The compensation
capacitor is included in the summing circuit. When the feedback
path is closed around the part, the output drives the feedback
input to that voltage which causes the internal currents to sum
to zero. This occurs when the two differential inputs are equal and
opposite; that is, their algebraic sum is zero.
The active feedback architecture offers several advantages over
a conventional op amp in several types of applications. Among
these are excellent common-mode rejection, wide input common-
mode range, and a pair of inputs that are high impedance and
completely balanced in a typical application. In addition, while
an external feedback network establishes the gain response as in
a conventional op amp, its separate path makes it entirely
independent of the signal input. This eliminates any interaction
between the feedback and input circuits, which traditionally
causes problems with CMRR in conventional differential-input
op amp circuits.
In a closed-loop application, a conventional op amp has its
differential input voltage driven to near zero under non-transient
conditions. The AD8143 generally has differential input voltages
at each of its input pairs, even under equilibrium conditions. As
a practical consideration, it is necessary to internally limit the
differential input voltage with a clamp circuit. Thus, the input
dynamic ranges are limited to about 2.5 V for the AD8143 (see
the Specifications section for more detail). For this and other
reasons, it is not recommended to reverse the input and feedback
stages of the AD8143, even though some apparently normal
functionality may be observed under some conditions.
Another advantage of active feedback is the ability to change the
polarity of the gain merely by switching the differential inputs.
A high input impedance inverting amplifier can therefore be
made. Besides high input impedance, a unity-gain inverter with
the AD8143 has noise gain of unity, producing lower output
noise and higher bandwidth than op amps that have noise gain
equal to 2 for a unity-gain inverter.
Rev. A | Page 17 of 24
AD8143
Data Sheet
APPLICATIONS INFORMATION
In this configuration, the voltage applied to the REF pin appears
at the output with a gain of 1 + RF/RG.
OVERVIEW
The AD8143 contains three independent active-feedback
amplifiers that can be effectively applied as differential line
receivers for red-green-blue (RGB) signals or component video,
such as YPbPr, signals transmitted over unshielded-twisted-pair
(UTP) cable. The AD8143 also contains two general-purpose
comparators with hysteresis that can be used to receive digital
signals or to extract video synchronization pulses from received
common-mode signals that contain encoded synchronization
signals.
To achieve unity gain from VREF to VOUT in this configuration,
divide VREF by the same factor used in the feedback loop; the
same RF and RG values can be used. Figure 38 illustrates this
approach.
+5V
0.01µF
+
V
IN
–
An internal linear voltage regulator derives power for the
comparators from the positive supply; therefore, the AD8143
must always have a minimum positive supply voltage of 4.5 V.
+
–
R
F
REF
FB
V
OUT
V
R
REF
G
The AD8143 includes a power-down feature that can be
asserted to reduce the supply current when a particular device
is not in use.
R
R
F
G
0.01µF
–5V
BASIC CLOSED-LOOP GAIN CONFIGURATIONS
As described in the Theory of Operation section, placing a
resistive feedback network between an amplifier output and its
respective feedback amplifier input creates a stable negative
feedback amplifier. It is important to note that the closed-loop
gain of the amplifier used in the signal path is defined as the
amplifier’s single-ended output voltage divided by its differential
input voltage. Therefore, each amplifier in the AD8143 provides
differential-to-single-ended gain. Additionally, the amplifier used
for feedback has two high impedance inputs—the FB input,
where the negative feedback is applied, and the REF input,
which can be used as an independent single-ended input to
apply a dc offset to the output signal. Some basic gain
configurations implemented with an AD8143 amplifier are
shown in Figure 37 through Figure 39.
Figure 38. Basic Gain Circuit: VOUT = VIN (1 + RF/RG) + VREF
The gain equation for the circuit in Figure 38 is
OUT = VIN (1 + RF/RG) + VREF
V
(2)
Another configuration that provides the same gain equation as
Equation 2 is shown in Figure 39. In this configuration, it is
important to keep the source resistance of VREF much smaller
than RG to avoid gain errors.
+5V
0.01µF
+
V
IN
–
+
–
REF
FB
+5V
V
OUT
0.01µF
+
R
R
F
G
V
IN
–
V
REF
+
–
0.01µF
REF
FB
V
OUT
–5V
V
REF
Figure 39. Basic Gain Circuit: VOUT = VIN (1 + RF/RG) + VREF
R
R
F
G
For stability reasons, the inductance of the trace connected to
the REF pin must be kept to less than 10 nH. The typical
inductance of 50 Ω traces on the outer layers of the FR-4 boards
is 7 nH/in, and on the inner layers, it is typically 9 nH/in. Vias
must be accounted for as well. The inductance of a typical via in
a 0.062-inch board is on the order of 1.5 nH. If longer traces are
required, a 200 Ω resistor should be placed in series with the
trace to reduce the Q-factor of the inductance.
0.01µF
–5V
Figure 37. Basic Gain Circuit: VOUT = (VIN + VREF)(1 + RF/RG)
The gain equation for the circuit in Figure 37 is
V
OUT = (VIN + VREF)(1 + RF/RG)
(1)
Rev. A | Page 18 of 24
Data Sheet
AD8143
In many dual-supply applications, VREF can be directly
connected to ground right at the device.
INPUT CLAMPING
The differential input that is assigned to receive the input signal
includes clamping diodes that limit the differential input swing
to approximately 5.5 V p-p at 25°C. Because of this, the input
and feedback stages should never be interchanged. Figure 31
illustrates the clamping action at the signal input stage.
TERMINATING THE INPUT
One of the key benefits of the active-feedback architecture is the
separation that exists between the differential input signal and
the feedback network. Because of this separation, the differential
input maintains its high CMRR and provides high differential
and common-mode input impedances, making line termination
a simple task.
The supply current drawn by the AD8143 has a strong
dependence on input signal magnitude because the input
transconductance stages operate with differential input signals
that can be up to a few volts peak-to-peak. This behavior is
distinctly different from that of traditional op-amps, where the
differential input signal is driven to essentially 0 V by negative
feedback. Figure 28 illustrates the supply current dependence on
input voltage.
Most applications that use the AD8143 involve transmitting
broadband video signals over 100 Ω UTP cable and use
dc-coupled terminations. The two most common types of
dc-coupled terminations are differential and common-mode.
Differential termination of 100 Ω UTP is implemented by
simply connecting a 100 Ω resistor across the amplifier input,
as shown in Figure 40.
For most applications, including receiving RGB video signals,
the input signal magnitudes encountered are well within the
safe operating limits of the AD8143 over its full power supply
and operating temperature ranges. In some extreme applications
where large differential and/or common-mode voltages can be
encountered, external clamping may be necessary. Another
application where external common-mode clamping is sometimes
required is when an unpowered AD8143 receives a signal from
an active driver. In this case, external diodes are required when
the current drawn by the internal ESD diodes cannot be kept to
less than 5 mA.
+5V
0.01µF
+
V
–
100Ω
100Ω
UTP
IN
+
–
REF
FB
V
OUT
R
R
F
G
0.01µF
When using 12 V supplies, the differential input signal must
be kept to less than 4 V p-p. In applications that use 12 V
supplies where the input signals are expected to reach or exceed
4 V p-p, external differential clamping at a maximum of 4 V p-p
is required.
–5V
Figure 40. Differential-Mode Termination
Some applications require common-mode terminations for
common-mode currents generated at the transmitter. In these
cases, the 100 Ω termination resistor is split into two 50 Ω
resistors. The required common-mode termination voltage is
applied at the tap between the two resistors. In many of these
applications, the common-mode tap is connected to ground
(VTERM (CM) = 0). This scheme is illustrated in Figure 41.
Figure 42 shows a general approach to external differential-
mode clamping.
POSITIVE CLAMP
NEGATIVE CLAMP
R
S
+
V
IN
+5V
R
T
+
0.01µF
V
R
S
OUT
50Ω
50Ω
–
–
+
V
–
100Ω
UTP
IN
+
–
REF
FB
V
OUT
Figure 42. Differential-Mode Clamping
V
(CM)
TERM
R
R
F
G
The positive and negative clamps are nonlinear devices that
exhibit very low impedance when the voltage across them
reaches a critical threshold (clamping voltage), thereby limiting
the voltage across the AD8143 input. The positive clamp has a
positive threshold, and the negative clamp has a negative
threshold.
0.01µF
–5V
Figure 41. Common-Mode Termination
Rev. A | Page 19 of 24
AD8143
Data Sheet
V+
2
A diode is a simple example of such a clamp. Schottky diodes
generally have lower clamping voltages than typical signal
diodes. The clamping voltage should be larger than the largest
expected signal amplitude, with enough margin to ensure that
the received signal passes without being distorted.
R
S
3
+
1
V–
HBAT-540C
A simple way to implement a clamp is to use a number of diodes
in series. The resultant clamping voltage is then the sum of the
clamping voltages of individual diodes.
V
R
T
IN
V+
2
+
V
OUT
A 1N4448 diode has a forward voltage of approximately 0.70 V
to 0.75 V at typical current levels that are seen when it is being
used as a clamp, and 2 pF maximum capacitance at 0 V bias.
(The capacitance of a diode decreases as its reverse bias voltage
is increased.) The series connection of two 1N4448 diodes,
therefore, has a clamping voltage of 1.4 V to 1.5 V. Figure 43
shows how to limit the differential input voltage applied to an
AD8143 amplifier to ±1.4 V to ±1.5 V (2.8 V p-p to 3.0 V p-p).
Note that the resulting capacitance of the two series diodes is
half that of one diode. Different numbers of series diodes can be
used to obtain different clamping voltages.
–
R
S
3
–
1
V–
HBAT-540C
Figure 44. External Common-Mode Clamping
The series resistances, RS, limit the current in each leg,
and the Schottky diodes limit the voltages on each input to
approximately 0.3 V to 0.4 V over the positive power supply,
V+ and to 0.3 V to 0.4 V below the negative power supply, V−.
The maximum value of RS is determined by the required signal
bandwidth, the line impedance, and the effective differential
capacitance due to the AD8143 inputs and the diodes.
RT is the differential termination resistor and the series
resistances, RS, limit the current into the diodes. The series
resistors should be highly matched in value to preserve high
frequency CMRR.
As with the differential clamp, the series resistors should be
highly matched in value to preserve high frequency CMRR.
POSITIVE CLAMP
NEGATIVE CLAMP
R
S
PRINTED CIRCUIT BOARD LAYOUT
CONSIDERATIONS
+
The two most important issues with regard to printed circuit
board (PCB) layout are minimizing parasitic signal trace
reactances in the feedback network and providing sufficient
thermal relief.
V
IN
R
T
+
V
R
OUT
S
–
–
Excessive parasitic reactances in the feedback network cause
excessive peaking in the amplifier’s frequency response and
excessive overshoot in its step response due to a reduction in
phase margin. Oscillation occurs when these parasitic
reactances are increased to a critical point where the phase
margin is reduced to zero. Minimizing these reactances is
important to obtain optimal performance from the AD8143.
Figure 43. Using Two 1N4448 Diodes in Series as a Clamp
There are many other nonlinear devices that can be used as
clamps. The best choice for a particular application depends
upon the desired clamping voltage, response time, parasitic
capacitance, and other factors.
When operating at 12 V power, it is important to pay special
attention to removing heat from the AD8143.
When using external differential-mode clamping, it is
important to ensure that the series resistors (RS), the sum of
the parasitic capacitance of the clamping devices, and the input
capacitance of the AD8143 are small enough to preserve the
desired signal bandwidth.
Besides the special layout considerations previously mentioned
and expounded upon in the following sections, general high
speed layout practices must be adhered to when applying the
AD8143. Controlled impedance transmission lines are required
for incoming and outgoing signals, referenced to a ground plane.
Figure 44 shows a specific example of external common-mode
clamping.
Rev. A | Page 20 of 24
Data Sheet
AD8143
Typically, the input signals are received over 100 Ω differential
transmission lines. A 100 Ω differential transmission line is
readily realized on the printed circuit board using two well-
matched, closely-spaced 50 Ω single-ended traces that are
coupled through the ground plane. The traces that carry the
single-ended output signals are most often 75 Ω for video
signals. Output signal connections should include series
termination resistors that are matched to the impedance
of the line they are driving.
A conservative estimate for feedback-loop trace capacitance in
each loop of the layout shown in Figure 45 is 2 pF. This value is
viewed as the minimum load capacitance and is reflected in the
frequency response and transient response plots.
Maximizing Heat Removal
The AD8143 pinout includes ground connections on its corner
pins to facilitate heat removal. These pins should be connected
to the exposed paddle on the underside of the AD8143 and to a
ground plane on the component side of the board. Additionally,
a 5 × 5 array of thermal vias connecting the exposed pad to
internal ground planes should be placed inside the PCB pad
that is soldered to the exposed pad. Using these techniques
is highly recommended in all applications, and is required in
12 V applications where power dissipation is the greatest.
Figure 45 illustrates how to optimize the circuit board layout
for heat removal.
Broadband power supply decoupling networks should be placed
as close as possible to the supply pins. Small surface-mount
ceramic capacitors are recommended for these networks, and
tantalum capacitors are recommended for bulk supply
decoupling.
Minimizing Parasitic Reactances in the Feedback Network
Parasitic trace capacitance and inductance are both reduced
when the traces that connect the feedback network together are
reduced in length. Removing the copper from all planes below
the traces reduces trace capacitance, but increases trace inductance
because the loop area formed by the trace and ground plane is
increased. A reasonable compromise that works well is to void
all copper directly under the feedback loop traces and component
pads with margins on each side approximately equal to one
trace width. Combining this technique with minimizing trace
lengths is effective in keeping parasitic trace reactances in the
feedback loop to a minimum. Additionally, all components used
in the feedback network should be in 0402 surface-mount
packages. Figure 45 illustrates the magnified view of a proven
feedback network layout that provides excellent performance. Note
that the internal layers are not shown.
Designs must often conform to design-for-manufacturing
(DFM) rules that stipulate how to lay out PCBs in such a way
as to facilitate the manufacturing process. Some of these rules
require thermal relief on pads that connect to planes, and the
rules may preclude the use of the technique illustrated in Figure 45.
In these cases, the ground pins should be connected to the exposed
paddle and component-side ground plane using techniques that
conform to the DFM requirements.
GND
R
B
C G
G
F
GND
C B
F
R
G
G
GND
R B
F
R
G
F
It is strongly recommended that the layout shown in Figure 45,
or something very similar, be used for the three AD8143
feedback networks.
GND
= COMPONENT SIDE
= CIRCUIT SIDE
GND
R R
F
R
R
G
GND
C R
F
GND
Figure 45. Recommended Layout for Feedback Loops and Grounding
Rev. A | Page 21 of 24
AD8143
Data Sheet
Small and large signal frequency responses for the High-Z case
with a 40 Ω series resistor and 10 pF load capacitance are shown
in Figure 10 and Figure 13; transient responses for the same
conditions are shown in Figure 18 and Figure 21. In the cable
driving case shown in Figure 47, CS << 2 pF for a well-designed
circuit; therefore, the feedback loop capacitance is the dominant
capacitive load. The feedback loop capacitance is present for all
cases, and its effect is included in the data presented in the
Typical Performance Characteristics and Specifications tables.
DRIVING A CAPACITIVE LOAD
The AD8143 typically drives either high impedance loads,
such as crosspoint switch inputs, or doubly terminated coaxial
cables. A gain of 1 is commonly used in the high impedance
case because the 6 dB transmission line termination loss is not
incurred. A gain of 2 is required when driving cables to
compensate for the 6 dB termination loss.
In all cases, the output must drive the parasitic capacitance
of the feedback loop, conservatively estimated to be 2 pF, in
addition to the capacitance presented by the actual load. When
driving a high impedance input, it is recommended that a small
series resistor be used to buffer the input capacitance of the
device being driven. Clearly, the resistor value must be small
enough to preserve the required bandwidth. In the ideal doubly
terminated cable case, the AD8143 output sees a purely resistive
load. In reality, there is some residual capacitance, and this is
buffered by the series termination resistor. Figure 46 illustrates
the high impedance case, and Figure 47 illustrates the cable-
driving case.
POWER-DOWN
The power-down feature is intended to be used to reduce power
consumption when a particular device is not in use, and does
not place the output in a High-Z state when asserted. The
power-down feature is asserted when the voltage applied to the
power-down pin drops to approximately 2 V below the positive
supply. The AD8143 is enabled by pulling the power-down pin
to the positive supply.
COMPARATORS
In addition to general-purpose applications, the two on-chip
comparators can be used to receive differential digital information
or to decode video sync pulses from received common-mode
voltages. Built-in hysteresis helps to eliminate false triggers
from noise.
+5V
0.01µF
+
V
IN
The comparator outputs are not designed to drive transmission
lines. When the signals detected by the comparators are driven
over cables or controlled impedance printed circuit board
traces, the comparator outputs must be fed to a spare logic gate,
FPGA, or other device that is capable of driving signals over
transmission lines.
–
R
S
REF
FB
C
IN
R
R
F
G
An internal linear voltage regulator derives power for the
comparators from the positive supply; therefore, the AD8143
must always have a minimum positive supply voltage of 4.5 V.
0.01µF
–5V
SYNC PULSE EXTRACTION USING COMPARATORS
Figure 46. Buffering the Input Capacitance of a High-Z Load
The AD8143 is particularly useful in keyboard video mouse
(KVM) applications. KVM networks transmit and receive
computer video signals, which are typically comprised of red,
green, and blue (RGB) video signals and separate horizontal
and vertical sync signals. Because the sync signals are separate
and not embedded in the color signals, it is advantageous to
transmit them using a simple scheme that encodes them among
the three common-mode voltages of the RGB signals. The
AD8134 triple differential driver is a natural complement to the
AD8143 and performs the sync pulse encoding with the
necessary circuitry on-chip.
+5V
0.01µF
+
V
IN
–
R
S
REF
FB
C
R
S
L
R
R
F
G
0.01µF
–5V
Figure 47. Driving a Doubly Terminated Cable
Rev. A | Page 22 of 24
Data Sheet
AD8143
The AD8134 encoding equations are given in Equation 3,
Equation 4, and Equation 5.
where:
Red VCM, Green VCM, and Blue VCM are the transmitted common-
mode voltages of the respective color signals.
K is an adjustable gain constant that is set by the AD8134.
V and H are the vertical and horizontal sync pulses, defined
with a weight of −1 when the pulses are in their low states, and a
weight of +1 when they are in their high states.
K
Red VCM
=
(V − H
)
(3)
(4)
(5)
2
K
GreenVCM
=
(− 2 V
)
2
K
The AD8134 data sheet contains further details regarding the
encoding scheme.
BlueVCM
=
(V + H
)
2
Figure 48 illustrates how the AD8143 comparators can be used
to extract the horizontal and vertical sync pulses that are encoded
on the RGB common-mode voltages by the AD8134.
50Ω
RED CMV
RECEIVED RED VIDEO
RECEIVED GREEN VIDEO
RECEIVED BLUE VIDEO
HSYNC
50Ω
1kΩ
50Ω
GREEN CMV
VSYNC
50Ω
1kΩ
50Ω
BLUE CMV
50Ω
Figure 48. Extracting Sync Signals from Received Common-Mode Signals
Rev. A | Page 23 of 24
AD8143
Data Sheet
OUTLINE DIMENSIONS
5.10
5.00 SQ
4.90
0.30
0.25
0.18
PIN 1
INDICATOR
PIN 1
25
24
32
1
INDICATOR
0.50
BSC
3.25
3.10 SQ
2.95
EXPOSED
PAD
17
16
8
9
0.50
0.40
0.30
0.25 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD.
Figure 49. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 5 mm Body and 0.75 mm Package Height
(CP-32-7)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
CP-32-7
CP-32-7
AD8143ACPZ-R2
AD8143ACPZ-REEL
AD8143ACPZ-REEL7
AD8143-EVALZ
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
32-Lead Lead Frame Chip Scale Package [LFCSP]
32-Lead Lead Frame Chip Scale Package [LFCSP]
32-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
CP-32-7
1 Z = RoHS Compliant Part.
© 2005–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05538-0-4/16(A)
Rev. A | Page 24 of 24
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