AD8147ACPZ-R2_技术文档

Triple Differential Driver

for Wideband Video

AD8146/AD8147/AD8148

FUNCTIONAL BLOCK DIAGRAMS

FEATURES

Triple high speed fully differential driver

700 MHz, −3 dB, 2 V p-p bandwidth (AD8146/AD8148)

600 MHz, −3 dB, 2 V p-p bandwidth (AD8147)

200 MHz, 0.1 dB, 2 V p-p bandwidth

24

23

22

21

20

19

OPD

1

2

3

4

5

18

17

V

C

OCM

AD8146

V

S–

S+

3000 V/μs slew rate

–IN A

+IN A

16 –IN C

15 +IN C

Fixed gain (AD8146/AD8147: G = 2, AD8148: G = 4)

Differential or single-ended input to differential output

Can be used as differential-to-differential receiver

Drives one or two 100 Ω UTP cables

Adjustable output common-mode voltage (AD8146)

Internal common-mode feedback network

Output balance error −50 dB @ 50 MHz

On-chip, sync-on common-mode encoding (AD8147/AD8148)

Output pull-down feature for line isolation

Low power: 57 mA @ 5 V for 3 drivers (AD8146)

Wide supply voltage range: +5 V to 5 V

B

V

14

V

S–

A

C

S–

–OUT A

6

13 –OUT C

7

8

9

10

11

12

Figure 1.

24

23

22

21

20

19

Available in a small 4 mm × 4 mm LFCSP

1

2

3

4

5

18

17

16

15

14

OPD

SYNC LEVEL

V (SYNC)

S+

AD8147/

AD8148

V

APPLICATIONS

S–

×2

B

–IN R

+IN R

–IN B

+IN B

QXGA or 1080p video transmission

KVM networking

Video over unshielded twisted pair (UTP)

Differential signal multiplexing

V

S–

A

C

6

13

–OUT R

–OUT B

7

8

9

10

11

12

Figure 2.

GENERAL DESCRIPTION

The AD8146/AD8147/AD8148 are high speed triple, differential or

single-ended input to differential output drivers. The AD8146

and AD8147 have a fixed gain of 2, and the AD8148 has a fixed

gain of 4. They are all specifically designed for the highest

resolution component video signals but can be used for any

type of analog signals or high speed data transmission over

either Category 5 UTP cable or differential printed circuit

board (PCB) transmission lines.

of 700 MHz and fast slew rates. They have an internal common-

mode feedback feature that provides output amplitude and

phase matching that is balanced to −60 dB at 50 MHz,

suppressing even-order harmonics and minimizing radiated

electromagnetic interference (EMI).

The common-mode voltage of each AD8146 output can be set

to any level, allowing transmission of signals over the common-

mode voltages. The AD8147 and AD8148 encode the vertical

and horizontal sync signals on the common-mode voltages of

the outputs. All outputs can be independently set to low voltage

states to be used with series diodes for line isolation, allowing

easy differential multiplexing over the same twisted pair cable.

These drivers can be used with the AD8145 triple differential-

to-singled-ended receiver, and the AD8117 crosspoint switch to

produce a video distribution system capable of supporting

UXGA or 1080p signals.

Manufactured on the Analog Devices, Inc. second generation

XFCB bipolar process, the drivers have large signal bandwidths

The AD8146/AD8147/AD8148 are available in a 24-lead LFCSP

and operate over a temperature range of −40°C to +85°C.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD8146/AD8147/AD8148

TABLE OF CONTENTS

Features .............................................................................................. 1

Input Common-Mode Voltage Range in Single-Supply

Applications ................................................................................ 15

Applications....................................................................................... 1

Functional Block Diagrams............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 7

Thermal Resistance ...................................................................... 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Typical Performance Characteristics ........................................... 10

Theory of Operation ...................................................................... 14

Definition of Terms.................................................................... 14

Analyzing an Application Circuit............................................. 14

Closed-Loop Gain ...................................................................... 14

Calculating the Input Impedance............................................. 15

Output Common-Mode Control ............................................. 15

Sync-On Common-Mode ......................................................... 15

Applications..................................................................................... 16

Driving RGB Video Signals Over Category-5 UTP Cable.... 16

Video Sync-On Common-Mode.............................................. 16

Driving Two UTP Cables With One Driver ........................... 18

Using the AD8146 as a Receiver............................................... 18

Output Pull-Down (OPD) ........................................................ 19

Layout and Power Supply Decoupling Considerations......... 19

Driving a Capacitive Load......................................................... 19

Adding Pre-Emphasis to the AD8148 ..................................... 20

Exposed Paddle (EP).................................................................. 21

Outline Dimensions....................................................................... 22

Ordering Guide .......................................................................... 22

REVISION HISTORY

5/07—Revision 0: Initial Version

Rev. 0 | Page 2 of 24

AD8146/AD8147/AD8148

SPECIFICATIONS

V_S= 5V, V_OCM= 0 V (AD8146); SYNC LEVEL = 0 V (AD8147/AD8148); T = 25°C; R_L, _dm= 200 Ω, unless otherwise noted.

_MINto T_MAX= −40°C to +85°C.

T

Table 1.

Parameter

Conditions

Min

Typ

Max

Unit

DIFFERENTIAL INPUT AC

Dynamic Performance

−3 dB Small Signal Bandwidth

V_O= 0.2 V p-p,

AD8146 and AD8148/AD8147

V_O= 2 V p-p,

AD8146 and AD8148/AD8147

900/780

700/600

200/235

MHz

−3 dB Large Signal Bandwidth

Bandwidth for 0.1 dB Flatness

V_O= 2 V p-p,

AD8146 and AD8147/AD8148

Slew Rate

Isolation Between Amplifiers

V_O= 2 V p-p, 25% to 75%

f = 10 MHz, between amplifiers,

AD8146 and AD8147/AD8148

3000

−86/−80

V/μs

dB

DIFFERENTIAL INPUT DC

Input Common-Mode Voltage Range

Input Resistance

−5 to +5

1.0

1.13

2

V

Differential

Single-ended input

Differential

ΔV_{OUT, dm}/ΔV_{IN, cm}, ΔV_{IN, cm}= 1 V,

AD8146/AD8147/AD8148

kΩ

pF

dB

Input Capacitance

DC CMRR

−53/−49/−55

2.00

DIFFERENTIAL OUTPUT

Differential Signal Gain

ΔV_{OUT, dm}/ΔV_{IN, dm}; ΔV_{IN, dm}= 1 V,

AD8146 and AD8147

1.95

V/V

ΔV_{OUT, dm}/ΔV_{IN, dm}; ΔV_{IN, dm}= 1 V, AD8148

Each single-ended output,

AD8146/AD8147/AD8148

−3.42

−3/−2.25/−3.42

+3.5

+3.4/+3.4/+3.5

V/V

V

Output Voltage Swing

Output Offset Voltage

Output Offset Drift

Output Balance Error

−19

+19

mV

μV/°C

dB

T_MINto T_MAX

ΔV_{OUT, cm}/ΔV_{IN, dm}, ΔV_{OUT, dm}= 2 V p-p,

f = 50 MHz,

8

−52/−49

AD8146 and AD8147/AD8148

DC, AD8146 and AD8148/AD8147

f = 1 MHz, AD8146 and AD8147/AD8148

Short to GND, source/sink

−41/−44

dB

nV/√Hz

mA

Output Voltage Noise (RTO)

Output Short-Circuit Current

25/42

+87/−67

V_OCMDYNAMIC PERFORMANCE

(AD8146 ONLY)

−3 dB Bandwidth

Slew Rate

DC Gain

ΔV_OCM= 100 mV p-p

V_OCM= −1 V to +1 V, 25% to 75%

ΔV_OCM= 1 V

340

800

MHz

V/μs

V/V

0.986

−20

1.000

V_OCMINPUT CHARACTERISTICS

(AD8146 ONLY)

Input Voltage Range

Input Resistance

Input Offset Voltage

DC CMRR

3

12.5

V

kΩ

mV

dB

+20

−48

ΔV_{OUT, dm}/ΔV_OCM, ΔV_OCM= 1 V

SYNC DYNAMIC PERFORMANCE

(AD8147/AD8148 ONLY)

Slew Rate

V_{OUT, cm}= −1 V to +1 V; 25% to 75%

1000

V/μs

Rev. 0 | Page 3 of 24

AD8146/AD8147/AD8148

Parameter

Conditions

Min

Typ

Max

Unit

H_SYNCAND V_SYNCINPUTS

(AD8147/AD8148 ONLY)

Input Low Voltage

Input High Voltage

1.5 to 1.7

V

SYNC LEVEL INPUT

(AD8147/AD8148 ONLY)

Setting to 0.5 V Pulse Levels

0.5

V

Gain to Red Common-Mode Output

Gain to Green Common-Mode Output ΔV_{O, cm}/ΔV_{SYNC LEVEL}(AD8147/AD8148)

Gain to Blue Common-Mode Output

POWER SUPPLY

ΔV_{O, cm}/ΔV_{SYNC LEVEL}(AD8147/AD8148)

0.93/0.965

1.91/1.935

−1.08/−1.035

1.08/1.04

2.11/2.05

−0.93/−0.965

V/V

ΔV_{O, cm}/ΔV_{SYNC LEVEL}(AD8147/AD8148)

Operating Range

+4.5

5.5

V

Quiescent Current, Positive Supply

AD8146

57

61.5/62.5

6/21.5

mA

dB

AD8147/AD8148

Disabled, AD8146/AD8147 and AD8148

AD8146

AD8147/AD8148

Disabled

Quiescent Current, Negative Supply

−57

−60.5/−62

−37

PSRR

ΔV_{OUT, dm}/ΔV_S; ΔV_S= 1 V

−66/−52/−55

(AD8146/AD8147/AD8148)

OUTPUT PULL-DOWN

OPD Input Low Voltage

OPD Input High Voltage

OPD Input Bias Current

OPD Assert Time

1.1

2.1

V

μA

μs

ns

V

520

1

10

OPD Deassert Time

Output Voltage When OPD Asserted

Each output, OPD input @ V_S+

−4.2

−3.8

Rev. 0 | Page 4 of 24

AD8146/AD8147/AD8148

V_S= +5 V or 2.5 V; V_OCM= midsupply (AD8146); SYNC LEVEL = 0 V (AD8147/AD8148); T = 25°C; R_{L, dm}= 200 Ω, unless otherwise noted.

T_MINto T_MAX= −40°C to +85°C.

Table 2.

Parameter

Conditions

Min

Typ

Max

Unit

DIFFERENTIAL INPUT AC

Dynamic Performance

−3 dB Small Signal Bandwidth

V_O= 0.2 V p-p,

AD8146/AD8147 and AD8148

V_O= 2 V p-p,

AD8147/AD8146 and AD8148

870/680

590/620

165/200

MHz

−3 dB Large Signal Bandwidth

Bandwidth for 0.1 dB Flatness

V_O= 2 V p-p,

AD8146 and AD8147/AD8148

DIFFERENTIAL INPUT DC

Input Common-Mode Voltage Range

Input Resistance

0 to 5

1.0

1.13

2

V

Differential

Single-ended input

Differential

ΔV_{OUT, dm}/ΔV_{IN, cm}; ΔV_{IN, cm}= 1 V,

AD8146/AD8147/AD8148

kΩ

pF

dB

Input Capacitance

DC CMRR

−53/−49/−55

2.013

DIFFERENTIAL OUTPUT

Differential Signal Gain

ΔV_{OUT, dm}/ΔV_{IN, dm}; ΔV_{IN, dm}= 1 V,

AD8146 and AD8147

1.95

V/V

ΔV_{OUT, dm}/ΔV_{IN, dm}; ΔV_{IN, dm}= 1 V, AD8148 3.87

4.00

+1.24/+1.26

V/V

V

Output Voltage Swing

Each single-ended output

−1.17/−1.23

AD8146 and AD8147/AD8148

Output Offset Voltage

Output Offset Drift

Output Balance Error

−17

+17

mV

μV/°C

dB

T_MINto T_MAX

ΔV_{OUT, cm}/ΔV_{IN, dm}, ΔV_{OUT, dm}= 2 V p-p,

f = 50 MHz,

8

−53/−49

AD8146 and AD8147/AD8148

DC, AD8146 and AD8148/AD8147

f = 1 MHz, AD8146, AD8147/AD8148

Short to GND, source/sink

−41/−44

dB

nV/√Hz

mA

Output Voltage Noise (RTO)

Output Short-Circuit Current

25/42

+63/−48

V_OCMDYNAMIC PERFORMANCE

(AD8146 ONLY)

−3 dB Bandwidth

Slew Rate

DC Gain

ΔV_OCM= 100 mV p-p

V_OCM= −1 V to +1 V, 25% to 75%

ΔV_OCM= 1 V, T_MINto T_MAX

310

800

MHz

V/μs

V/V

0.99

−20

1.00

+20

V_OCMINPUT CHARACTERISTICS

(AD8146 ONLY)

Input Voltage Range

Input Resistance

Input Offset Voltage

DC CMRR

1.2

12.5

V

kΩ

mV

dB

ΔV_{O, dm}/ΔV_OCM; ΔV_OCM= 1 V

−42

800

SYNC DYNAMIC PERFORMANCE

(AD8147/AD8148 ONLY)

Slew Rate

V_{OUT, cm}= −1 V to +1 V; 25% to 75%

V/μs

H_SYNCAND V_SYNCINPUTS

(AD8147/AD8148 ONLY)

Input Low Voltage

Input High Voltage

1.3 to 1.5

V

Rev. 0 | Page 5 of 24

AD8146/AD8147/AD8148

Parameter

Conditions

Min

Typ

Max

Unit

SYNC LEVEL INPUT

(AD8147/AD8148 ONLY)

Setting to 0.5 V Pulse Levels

0.5

V

Gain to Red Common-Mode Output ΔV_{O, cm}/ΔV_{SYNC LEVEL}, AD8147/AD8148

Gain to Green Common-Mode Output ΔV_{O, cm}/ΔV_{SYNC LEVEL}, AD8147/AD8148

Gain to Blue Common-Mode Output ΔV_{O, cm}/ΔV_{SYNC LEVEL}, AD8147/AD8148

POWER SUPPLY

0.88/0.925

1.83/1.85

−1.07/−1

1.07/1.00

2.05/2.00

−0.88/−0.925

V/V

Operating Range

+4.5

5.5

50

55.5/52

4/12

V

Quiescent Current Positive Supply

Quiescent Current Negative Supply

PSRR

AD8146

AD8147/AD8148

Disabled, AD8146/AD8147 and AD8148

AD8146

AD8147/AD8148

Disabled, AD8146/AD8147/AD8148

ΔV_{OUT, dm}/ΔV_S; ΔV_S= 1 V,

AD8146/AD8147/AD8148

mA

dB

−50

−55/−51

−14/−18.2/−15

−70/−54/−60

OUTPUT PULL-DOWN

OPD Input Low Voltage

OPD Input High Voltage

OPD Input Bias Current

OPD Assert Time

1.0

2.0

V

μA

ns

V

160

600

10

OPD Deassert Time

Output Voltage When OPD Asserted Each output, OPD input @ V_S+

−1.71

−1.6

Rev. 0 | Page 6 of 24

AD8146/AD8147/AD8148

ABSOLUTE MAXIMUM RATINGS

and common-mode currents flowing to the loads, as well as

currents flowing through the internal differential and common-

mode feedback loops. The internal resistor tap used in the

common-mode feedback loop places a 4 kΩ differential load on

the output. Differential feedback, network resistor values are

given in the Theory of Operation section and Applications

section. RMS output voltages should be considered when

dealing with ac signals.

Table 3.

Parameter

Supply Voltage

All V_OCM

Rating

11 V

V_S

Power Dissipation

See Figure 3

V_S

−65°C to +125°C

−40°C to +85°C

300°C

Input Common-Mode Voltage

Storage Temperature Range

Operating Temperature Range

Lead Temperature (Soldering, 10 sec)

Junction Temperature

Airflow reduces θ_JA. In addition, more metal directly in contact

with the package leads from metal traces, through holes,

ground, and power planes reduces the θ_JA. The exposed paddle

on the underside of the package must be soldered to a pad on

the PCB surface that is thermally connected to a ground plane

to achieve the specified θ_JA.

150°C

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only and functional operation of the device at these or

any other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Figure 3 shows the maximum safe power dissipation in the

package vs. the ambient temperature for the 24-lead LFCSP

(57°C/W) package on a JEDEC standard 4-layer board with the

underside paddle soldered to a pad that is thermally connected

to a ground plane. θ_JAvalues are approximations.

3.5

THERMAL RESISTANCE

θ_JAis specified for the worst-case conditions, that is, θ_JAis

specified for the device soldered in a circuit board in still air.

3.0

2.5

2.0

1.5

1.0

0.5

0

Table 4. Thermal Resistance with the Underside Pad

Connected to the Plane

Package Type/PCB Type

θ_JA

Unit

24-Lead LFCSP/4-Layer

57

°C/W

Maximum Power Dissipation

The maximum safe power dissipation in the AD8146/

AD8147/AD8148 package is limited by the associated rise in

junction temperature (T_J) on the die. At approximately 150°C,

which is the glass transition temperature, the plastic changes its

properties. Even temporarily exceeding this temperature limit

can change the stresses that the package exerts on the die,

permanently shifting the parametric performance of the

AD8146/AD8147/AD8148. Exceeding a junction temperature

of 175°C for an extended time can result in changes in the

silicon devices, potentially causing failure.

–40

–20

0

20

40

60

80

AMBIENT TEMPERATURE (°C)

Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board

ESD CAUTION

The power dissipated in the package (P_D) is the sum of the

quiescent power dissipation and the power dissipated in the

package due to the load drive for all outputs. The quiescent

power is the voltage between the supply pins (V_S) times the

quiescent current (I_S). The load current consists of differential

Rev. 0 | Page 7 of 24

AD8146/AD8147/AD8148

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN 1

INDICATOR

OPD

1

2

3

4

5

6

18 V

17 V

16 –IN C

15 +IN C

C

OCM

V

S–

S+

–IN A

+IN A

AD8146

TOP VIEW

V

14 V

(Not to Scale)

S–

–OUT A

13 –OUT C

Figure 4. AD8146 Pin Configuration

Table 5. AD8146 Pin Function Descriptions

Pin No.

Mnemonic

Description

1

OPD

Output Pull-Down.

2, 5, 14, 21

V_S−

Negative Power Supply Voltage.

3

−IN A

Inverting Input, Amplifier A.

4

+IN A

Noninverting Input, Amplifier A.

6

7

−OUT A

+OUT A

V_S+

Negative Output, Amplifier A.

Positive Output, Amplifier A.

Positive Power Supply Voltage.

8, 11, 17, 24

9

+OUT B

−OUT B

+OUT C

−OUT C

+IN C

Positive Output, Amplifier B.

Negative Output, Amplifier B.

Positive Output, Amplifier C.

Negative Output, Amplifier C.

Noninverting Input, Amplifier C.

Inverting Input, Amplifier C.

The voltage applied to this pin controls output common-mode voltage, Amplifier C.

The voltage applied to this pin controls output common-mode voltage, Amplifier B.

The voltage applied to this pin controls output common-mode voltage, Amplifier A.

Noninverting Input, Amplifier B.

10

12

13

15

16

18

19

20

22

23

−IN C

V_OCM

C

B

A

+IN B

−IN B

Inverting Input, Amplifier B.

Rev. 0 | Page 8 of 24

AD8146/AD8147/AD8148

PIN 1

INDICATOR

OPD

1

2

3

4

5

6

18 SYNC LEVEL

V

17 V (SYNC)

S–

S+

AD8147/

AD8148

16 –IN B

15 +IN B

–IN R

+IN R

TOP VIEW

V

14 V

S–

(Not to Scale)

–OUT R

13 –OUT B

Figure 5. AD8147/AD8148 Pin Configuration

Table 6. AD8147/AD8148 Pin Function Descriptions

Pin No.

Mnemonic

Description

1

OPD

Output Pull-Down.

2, 5, 14

3

4

6

V_S−

−IN R

+IN R

Negative Power Supply Voltage.

Inverting Input, Red Amplifier.

Noninverting Input, Red Amplifier.

Negative Output, Red Amplifier.

Positive Output, Red Amplifier.

Positive Power Supply Voltage.

Positive Output, Green Amplifier.

Negative Output, Green Amplifier.

Positive Output, Blue Amplifier.

Negative Output, Blue Amplifier.

Noninverting Input, Blue Amplifier.

Inverting Input, Blue Amplifier.

Positive Power Supply Voltage for Sync.

−OUT R

+OUT R

V_S+

+OUT G

−OUT G

+OUT B

−OUT B

+IN B

7

8, 11, 24

9

10

12

13

15

16

17

18

−IN B

V_S+(SYNC)

SYNC LEVEL

The voltage applied to this pin controls the amplitude of the sync pulses that are applied to

the common-mode voltages.

19

H_SYNC

Horizontal Sync Pulse Input.

20

V_SYNC

Vertical Sync Pulse Input.

21

22

23

V_S−(SYNC)

+IN G

−IN G

GND

Negative Power Supply Voltage for Sync.

Noninverting Input, Green Amplifier.

Inverting Input, Green Amplifier.

Signal Ground Reference.

Exposed Paddle

Rev. 0 | Page 9 of 24

AD8146/AD8147/AD8148

TYPICAL PERFORMANCE CHARACTERISTICS

V_S= 5V; V_OCM= 0 V (AD8146); SYNC LEVEL = 0 V (AD8147/AD8148); T = 25°C; R_L, _dm= 200 Ω; C_{L, dm}= 0 pF, unless otherwise noted.

T_MINto T_MAX= −40°C to +85°C.

15

14

13

12

11

10

9

V

= 2V p-p

V

= 2V p-p

OUT, dm

8

7

±2.5V

6

±5.0V

5

AD8146 (±2.5V)

AD8146 (±5.0V)

AD8147 (±2.5V)

AD8147 (±5.0V)

4

3

8

2

7

1

6

0

5

10

–1

10

100

FREQUENCY (MHz)

1000

100

1000

FREQUENCY (MHz)

Figure 9. AD8148 Large Signal Frequency Response for Various Supplies

Figure 6. AD8146/AD8147 Large Signal Frequency Response for Various Supplies

15

9

V

= 0.2V p-p

V

= 0.2V p-p

OUT, dm

14

13

12

11

10

9

8

7

6

±5.0V

5

AD8146 (±2.5V)

AD8146 (±5.0V)

AD8147 (±2.5V)

AD8147 (±5.0V)

4

3

±2.5V

8

2

7

1

6

0

5

10

–1

10

100

1000

100

1000

FREQUENCY (MHz)

Figure 10. AD8148 Small Signal Frequency Response for Various Supplies

Figure 7. AD8146/AD8147 Small Signal Frequency Response for Various Supplies

12.5

6.5

V = 2V p-p

OUT, dm

V

= 2V p-p

OUT, dm

12.4

12.3

12.2

12.1

12.0

11.9

11.8

11.7

11.6

11.5

6.4

6.3

6.2

6.1

6.0

5.9

5.8

5.7

5.6

5.5

±2.5V

±5.0V

AD8146 (±2.5V)

AD8146 (±5.0V)

AD8147 (±2.5V)

AD8147 (±5.0V)

1

10

100

1000

1

10

100

1000

FREQUENCY (MHz)

Figure 11. AD8148 Large Signal 0.1 dB Flatness for Various Supplies

Figure 8. AD8146/AD8147 Large Signal 0.1 dB Flatness for Various Supplies

Rev. 0 | Page 10 of 24

AD8146/AD8147/AD8148

1.5

1.0

1.5

1.0

V

= 2V p-p

V

= 2V p-p

OUT, dm

V

= ±2.5V

V

= ±2.5V

S

V

= ±5.0V

S

V

= ±5.0V

S

0.5

0

–0.5

–1.0

–1.5

–0.5

–1.0

–1.5

0

2

4

6

8

10

12

14

16

18

20

0

2

4

6

8

10

12

14

16

18

20

TIME (ns)

Figure 12. AD8146/AD8147 Large Signal Transient Response for Various Supplies

Figure 15. AD8148 Large Signal Transient Response for Various Supplies

150

V

= 0.2V p-p

V

= 0.2V p-p

OUT, dm

V

= ±2.5V

S

V

= ±2.5V

S

100

50

100

50

V

= ±5.0V

V

= ±5.0V

S

0

–50

–100

–150

–50

–100

–150

0

2

4

6

8

10

12

14

16

18

20

0

2

4

6

8

10

12

14

16

18

20

TIME (ns)

Figure 13. AD8146/AD8147 Small Signal Transient Response for Various Supplies

Figure 16. AD8148 Small Signal Transient Response for Various Supplies

–20

ΔV

/ΔV

OUT, dm

= 2V p-p

ΔV

/ΔV

IN, cm

= 2V p-p

OUT, cm

OUT, dm

–25

–30

–35

–40

–45

–50

–55

–60

–65

–70

IN, cm

–30

–40

–50

–60

–70

–80

AD8146

AD8148

AD8147

AD8146

AD8148

1

10

100

1000

1

10

100

1000

FREQUENCY (MHz)

Figure 14. Output Balance vs. Frequency

Figure 17. CMRR vs. Frequency

Rev. 0 | Page 11 of 24

AD8146/AD8147/AD8148

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

ΔV

/ΔV

S–

ΔV

/ΔV

S+

OUT, dm

ΔV = 2V p-p

S

–30

–40

–50

–60

–70

–80

–90

–100

AD8148

AD8147

AD8148

AD8147

AD8146

0.1

1

10

FREQUENCY (MHz)

100

1000

0.1

1

10

FREQUENCY (MHz)

100

1000

Figure 18. Positive Power Supply Rejection vs. Frequency

Figure 21. Negative Power Supply Rejection vs. Frequency

1000

100

10

–20

–30

V

= ±5V

ΔV

B/ΔV

A = 1V p-p

A

IN, dm

S

OUT, dm

IN, dm

–40

AD8148

AD8147

–50

–60

AD8146

–70

AD8146

–80

–90

AD8148

–100

–110

–120

AD8147

0.1

0.01

1

10

100

1000

10000 100000

0.1

1

10

FREQUENCY (MHz)

100

1000

FREQUENCY (kHz)

Figure 19. Output-Referred Voltage Noise vs. Frequency

Figure 22. Amplifier-to-Amplifier Isolation vs. Frequency

10

INPUT × 2 (V = ±5.0V)

INPUT × 4 (V = ±5.0V)

S

8

6

8

6

OUTPUT (V = ±5.0V)

S

INPUT × 2 (V = ±2.5V)

INPUT × 4 (V = ±2.5V)

S

4

2

0

OUTPUT (V = ±2.5V)

S

–2

–4

–6

–8

–10

–2

–4

–6

–8

–10

0

100 200 300 400 500 600 700 800 900 1000

TIME (ns)

0

100 200 300 400 500 600 700 800 900 1000

TIME (ns)

Figure 20. AD8146/AD8147 Output Overdrive Recovery

Figure 23. AD8148 Output Overdrive Recovery

Rev. 0 | Page 12 of 24

AD8146/AD8147/AD8148

59

57

55

53

51

49

47

45

62

60

58

56

54

52

50

48

I + (±5.0V)

S

I + (±5.0V)

S

R

= OPEN CIRCUIT

L, dm

R

= OPEN CIRCUIT

L, dm

I + (±2.5V)

S

I + (±2.5V)

S

–60

–40

–20

0

20

40

60

80

100

120

–60

–40

–20

0

20

40

60

80

100

120

TEMPERATURE (°C)

Figure 24. AD8146 Supply Current vs. Temperature

Figure 26. AD8147/AD8148 Supply Current vs. Temperature

–35

–40

–45

–50

–55

–60

–65

1.5

ΔV

/ΔV

OCM

= 2V p-p

OUT, dm

±V = 5.0V

S

±V = 2.5V

S

OCM

1.0

0.5

AD8146

0

V

= 2V p-p

OUT, cm

–0.5

–1.0

–1.5

1

10

100

1000

0

5

10

15

20

25

30

35

40

FREQUENCY (MHz)

TIME (ns)

Figure 27. AD8146 Large Signal V_OCMTransient Response for Various Supplies

Figure 25. V_OCMCommon-Mode Rejection Ratio

Rev. 0 | Page 13 of 24

AD8146/AD8147/AD8148

THEORY OF OPERATION

Each differential driver differs from a conventional op amp in

that it has two outputs whose voltages move in opposite directions.

Like an op amp, it relies on high open-loop gain and negative

feedback to force these outputs to the desired voltages. The

drivers make it easy to perform single-ended-to-differential

conversion, common-mode level shifting, and amplification of

differential signals.

Common-Mode Voltage

Common-mode voltage refers to the average of two node

voltages with respect to a common reference. The output

common-mode voltage is defined as

V

_{OUT, cm}= (V_OP+ V_ON)/2

Output Balance

Output balance is a measure of how well the differential output

signals are matched in amplitude and how close they are to

exactly 180° apart in phase. Balance is most easily determined

by placing a well-matched resistor divider between the differential

output voltage nodes and comparing the magnitude of the signal at

the divider’s midpoint with the magnitude of the differential

signal. By this definition, output balance error is the magnitude

of the change in output common-mode voltage divided by the

magnitude of the change in output differential mode voltage in

response to a differential input signal.

Previous differential drivers, both discrete and integrated

designs, were based on using two independent amplifiers and

two independent feedback loops, one to control each of the

outputs. When these circuits are driven from a single-ended

source, the resulting outputs are typically not well balanced.

Achieving a balanced output has typically required exceptional

matching of the amplifiers and feedback networks.

DC common-mode level shifting has also been difficult with

previous differential drivers. Level shifting has required the use

of a third amplifier and feedback loop to control the output

common-mode level. Sometimes, the third amplifier was also

used to attempt to correct an inherently unbalanced circuit.

Excellent performance over a wide frequency range has proven

difficult with this approach.

ΔV_{OUT, cm}

Output Balance Error =

ΔV_{OUT, dm}

ANALYZING AN APPLICATION CIRCUIT

Each of the drivers uses two feedback loops to separately

control the differential and common-mode output voltages.

The differential feedback, set by the internal resistors, controls

only the differential output voltage. The internal common-

mode feedback loop controls only the common-mode output

voltage. This architecture makes it easy to transmit signals over

the common-mode voltage channels by simply applying the

signal voltages to the V_OCMinputs. The output common-mode

voltage is forced, by internal common-mode feedback, to equal

the voltage applied to the V_OCMinput, without affecting the

differential output voltage.

The drivers use high open-loop gain and negative feedback to

force their differential and common-mode output voltages to

minimize the differential and common-mode input error

voltages. The differential input error voltage is defined as the

voltage between the differential inputs labeled V_APand V_ANin

Figure 28. For most purposes, this voltage can be assumed to be

zero. Similarly, the difference between the actual output common-

mode voltage and the voltage applied to V_OCMcan also be

assumed to be zero. Starting from these two assumptions,

any application circuit can be analyzed.

CLOSED-LOOP GAIN

The driver architecture results in outputs that are highly

balanced over a wide frequency range without requiring

external components or adjustments. The common-mode

feedback loop forces the signal component of the output

common-mode voltage to be zeroed. The result is nearly

perfectly balanced differential outputs of identical

amplitude that are exactly 180° apart in phase.

The differential mode gain of the circuit in Figure 28 can be

described by

V_OUT,dm

R_F

R_G

=

V_IN,dm

where:

R_Fis 1.0 kΩ and R_Gis 500 Ω nominally for the AD8146 and

AD8147.

R_Fis 2.0 kΩ and R_Gis 500 Ω nominally for the AD8148.

DEFINITION OF TERMS

Differential Voltage

Differential voltage refers to the difference between two node

voltages that are balanced with respect to each other. For

example, in Figure 28 the output differential voltage (or

equivalently output differential mode voltage) is defined as

R

F

V

R

AP

AN

G

+

V

ON

IP

V

R

V

OCM

L, dm

OUT, dm

IN, dm

–

V

OP

IN

V

R

G

V

_{OUT, dm}= (V_OP− V_ON)

R

F

Figure 28. Internal Architecture and Signal Name Definitions

Rev. 0 | Page 14 of 24

AD8146/AD8147/AD8148

CALCULATING THE INPUT IMPEDANCE

OUTPUT COMMON-MODE CONTROL

The effective input impedance of a circuit such as that in

Figure 28 at V_IPand V_INdepends on whether the amplifier is

being driven by a single-ended or differential signal source. For

balanced differential input signals, the differential input impedance,

The AD8146 allows the user to control each of the three

common-mode output levels independently through the three

V_OCMinput pins. The V_OCMpins pass a signal to the common-

mode output level of each of their respective amplifiers with

330 MHz of small signal bandwidth and an internally fixed gain

of 1. In this way, additional control and communication signals

can be embedded on the common-mode levels as users see fit.

R_{IN, dm}, between the inputs V_IPand V_INfor all devices is

R_{IN, dm}= 2 × R_G

In the case of a single-ended input signal (for example, if V_INis

grounded and the input signal is applied to V_IP), the input

impedance becomes

With no external circuitry, the level at the V_OCMinput of each

amplifier defaults to approximately midsupply. An internal

resistive divider with an impedance of approximately 12.5 kΩ

sets this level. To limit common-mode noise in dc common-

mode applications, external bypass capacitors should be

connected from each of the V_OCMinput pins to ground.

⎛

⎜

⎞

⎟

R_G

R_F

R_G+ R_F

⎜

⎟

R_{IN, dm}

=

1−

⎜

⎝

⎟

⎠

2×

(

)

SYNC-ON COMMON-MODE

The single-ended input impedance of the AD8146 and the

AD8147 is therefore 750 Ω, and the single-ended input

impedance of the AD8148 is 833 Ω.

The AD8147 and AD8148 are specifically targeted at driving

RGB video signals over UTP cable using a sync-on common-

mode technique. The common-mode outputs of each of the R,

G, and B differential outputs are set using circuitry contained

within the device. This circuitry embeds the horizontal and

vertical sync pulses on the three common-mode outputs in a

way that also results in low radiated energy. For a more detailed

description of the sync scheme, see the Applications section.

The input impedance of the circuit is effectively higher than it

would be for a conventional op amp connected as an inverter

because a fraction of the differential output voltage appears at

the inputs as a common-mode signal, partially bootstrapping

the voltage across the input resistor R_G.

The sync-on common-mode circuit generates a current based

on the SYNC LEVEL input pin (Pin 18). With the SYNC LEVEL

input tied to GND, the common-mode output of all drivers is

set at (V_S++ V_S−)/2. Using a resistor divider, a voltage can be

applied between GND and SYNC LEVEL that determines the

maximum deviation of the common-mode outputs from their

midsupply level. If, for instance, SYNC LEVEL = 0.5 V and the

supply voltage is 5 V, the common-mode outputs fall within an

envelope of 2.5 V 0.5 V. The state of each V_{OUT, cm}output based

on the H_SYNCand V_SYNCinputs is determined by the equations

defined in the Applications section.

INPUT COMMON-MODE VOLTAGE RANGE IN

SINGLE-SUPPLY APPLICATIONS

The driver inputs are designed to facilitate level-shifting of

ground-referenced input signals on a single power supply. For a

single-ended input, this implies, for example, that the voltage at

V_INin Figure 28 would be 0 V when the negative power supply

voltage of the amplifier is also set to 0 V.

It is important to ensure that the common-mode voltage at the

amplifier inputs, V_APand V_AN, stays within its specified range.

Because voltages V_APand V_ANare driven to be essentially equal

by negative feedback, the input common-mode voltage of the

amplifier can be expressed as a single term, V_ACM. V_ACMcan be

calculated as

In most cases, the sync-on common-mode circuit can be used

by directly applying the H_SYNCand V_SYNCsignals to their respective

AD8147 or AD8148 inputs. The logic thresholds of the H_SYNC

and V_SYNCinputs are set to nominally 1.4 V with respect to

GND, and the exposed paddles of the AD8147 and AD8148

are used as the GND references for the incoming sync pulses.

When 2.5 V supplies are used, however, external protection is

required to limit the positive excursion to less than 2.5 V. For

more details, see the Applications section.

V_OCM+ 2V_ICM

V_ACM

=

3

where V_ICMis the common-mode voltage of the input signal,

that is, V_ICM= (V_IP+ V_IN)/2.

The input paths from the H_SYNCand V_SYNCinputs to the switches

in the current mode level-shifting circuit are well matched to

eliminate false switching transients, maximizing common-

mode balance and minimizing radiated energy.

Rev. 0 | Page 15 of 24

AD8146/AD8147/AD8148

APPLICATIONS

VIDEO SYNC-ON COMMON-MODE

DRIVING RGB VIDEO SIGNALS OVER CATEGORY-5

UTP CABLE

In computer video applications, the horizontal and vertical sync

signals are often separate from the video information signals.

For example, in typical computer monitor applications, the red,

green, and blue (RGB) color signals are transmitted over separate

cables, as are the vertical and horizontal sync signals. When

transmitting these types of video signals over long distances on

UTP cable, it is desirable to reduce the required number of

physical channels. One way to do this is to encode the vertical

and horizontal sync signals as weighted sums and differences of

the output common-mode signals. The RGB color signals are

each transmitted differentially over separate physical channels.

The fact that the differential and common-mode signals are

orthogonal allows the RGB color and sync signals to be

separated at the channel’s receiver.

The foremost application of the drivers is the transmission of

RGB video signals over UTP cable in KVM networks. The

excellent balance of the differential outputs ensures low radiated

energy from each of the twisted pairs. Single-ended video signals

are easily converted to differential signals for transmission over

the cable, and the internally fixed gain of 2 or 4 automatically

compensates for the losses incurred by the source and load

terminations. The common topologies used in KVM networks,

such as daisy-chained, star, and point-to-point, are supported

by the drivers. Figure 29 shows the AD8146 in a triple single-

ended-to-differential application when driven from a 75 Ω

source, which is typical of how RGB video is driven over an

UTP cable.

+5V

Cat-5 cable contains four balanced twisted-pair physical

channels that can support both differential and common-mode

signals. Transmitting typical computer monitor video over this

cable can be accomplished by using three of the twisted pairs for

the RGB and sync signals and one wire of the fourth pair as a

return path for the Schottky diode bias currents. Each color is

transmitted differentially, one on each of the three pairs, and the

encoded sync signals are transmitted among the common-mode

signals of each of the three pairs. To minimize EMI from the

sync signals, the common-mode signals on each of the three

pairs produced by the sync encoding scheme induce electric

and magnetic fields that for the most part cancel each other. A

conceptual block diagram of the sync encoding scheme is

presented in Figure 30. Because the AD8147/AD8148 have the

sync encoding scheme implemented internally, the user simply

applies the horizontal and vertical sync signals to the appropriate

inputs. (See the Specifications tables for the high and low levels

of the horizontal and vertical sync pulse voltages).

0.1µF ON ALL V PINS

S+

V

S+

AD8146

1kΩ

75Ω

500Ω

49.9Ω

–

82.5Ω

+2.5V

V

A

OUT A

+

OCM

500Ω

VIDEO

SOURCE A

39.2Ω

1kΩ

75Ω

500Ω

49.9Ω

–

82.5Ω

+2.5V

V

B

OUT B

+

OCM

VIDEO

SOURCE B

39.2Ω

1kΩ

75Ω

500Ω

49.9Ω

–

82.5Ω

+2.5V

V

C

OUT C

+

OCM

VIDEO

SOURCE C

39.2Ω

1kΩ

OPD

OUTPUT

PULLDOWN

V

S–

Figure 29. AD8146 in Single-Ended-to-Differential Application

Rev. 0 | Page 16 of 24

AD8146/AD8147/AD8148

3.1

1kΩ

AD8147/AD8148

3.0

2.9

G

500Ω

+IN R

–IN R

–OUT R

+OUT R

2.8

2.7

2.6

2.5

2.4

2.3

V

R

OCM

1kΩ

V

SYNC

R

B

H

SYNC

2.2

2.1

2.0

1kΩ

SYNC LEVEL

+IN G

500Ω

–OUT G

+OUT G

5.0

4.5

×2

V

G

OCM

–IN G

1kΩ

4.0

3.5

3.0

2.5

500Ω

+IN B

–IN B

–OUT B

+OUT B

V

B

OCM

H

V

SYNC

2.0

1.5

1.0

SYNC

1kΩ

OPD

0.5

0

V

WEIGHTING EQUATIONS:

K

) + V

SYNC

OCM

0.98 0.99 1.00 1.01 1.02 1.03 1.04 1.05

TIME (µs)

1.06 1.07

RED V

=

(V

– H

OCM

SYNC

(–2V

MIDSUPPLY

2

K

GREEN V

=

K

2

) + V

OCM

SYNC

2

Figure 31. AD8147 Sync-On Common-Mode Signals in Single 5 V Application

BLUE V

=

(V

+ H

) + V

MIDSUPPLY

OCM

SYNC

The transmitted common-mode sync signal magnitudes are

scaled by applying a dc voltage to the SYNC LEVEL input,

referenced to GND. The difference between the voltage applied

to the SYNC LEVEL input and GND sets the peak deviation of

the encoded sync signals about the midsupply, common-mode

voltage. For example, with the SYNC LEVEL input set at 500 mV,

the deviation of the encoded sync pulses about the nominal

midsupply, common-mode voltage is typically 500 mV. The

equations in Figure 30 describe how the V_SYNCand H_SYNCsignals

are encoded on each color’s midsupply common-mode signal.

In these equations, the weights of the V_SYNCand H_SYNCsignals

are 1 (+1 for high and −1 for low), and the constant K is equal

to the peak deviation of the encoded sync signals.

Figure 30. AD8147/AD8148 Sync-On Common-Mode Encoding Scheme

Figure 31 shows how the sync signals appear on each common-

mode voltage in a single 5 V supply application when the voltage

applied to the SYNC LEVEL input is 500 mV, which is the

typical setting for most applications.

Rev. 0 | Page 17 of 24

AD8146/AD8147/AD8148

Sync pulse amplitudes applied to the AD8147 and AD8148

must be less than or equal to the positive supply voltage. In low

positive supply applications, such as those that use 2.5 V supplies,

external limiting may be required because many logic families

produce amplitudes up to 5 V. Figure 32 illustrates how to use a

monolithic triple diode to limit a sync pulse with 5 V amplitude

to an amplitude of approximately 2 V.

Driver bandwidth is affected to a small degree when driving the

100 Ω load presented by the two cables, as compared with

driving a typical 200 Ω load. Figure 34 illustrates the AD8146/

AD8147/AD8148 bandwidths when driving a 100 Ω load.

15

12

AD8148

INCOMING

SYNC PULSE

9

6

+5V

LIMITED

SYNC PULSE

301Ω

+2V

1

6

2

5

3

4

0V

HN2D02FUTW1T1

AD8147

3

AD8146

Figure 32. Limiting Sync Pulse Amplitude in Low Positive Supply Applications

0

R

= 100Ω

= 2V p-p

L, dm

DRIVING TWO UTP CABLES WITH ONE DRIVER

V

OUT

–3

Some applications require driving two UTP cables with a single

driver. Each individual driver of the AD8146/AD8147/AD8148

is capable of driving two doubly terminated cables, which places

a differential load of 100 Ω across the outputs of the driver.

Figure 33 illustrates how to drive two cables.

1

10

100

1000

FREQUENCY (MHz)

Figure 34. Large Signal Frequency Response Driving 100 Ω Loads

USING THE AD8146 AS A RECEIVER

49.9Ω

While the AD8146 excels as a differential driver, it can also be

used as a differential-to-differential receiver applied as an

input buffer that protects a more sophisticated device, such as a

differential crosspoint switch. See Figure 35 for an illustration of

this type of application.

AD8146/AD8147/AD8148

100Ω

UTP

49.9Ω

V

OCM

Because the AD8146 V_OCMinput pins are uncommitted, any

incoming common-mode signal, such as encoded sync pulses,

can be reproduced at the AD8146 outputs by stripping it from

the received signal and applying it directly to the V_OCMpin.

The two series 54.9 Ω resistors form a differential termination

resistor of 109.8 Ω, which when loaded with the 1 kΩ differential

input resistance of the AD8146, provides an overall termination

of approximately 100 Ω. The received common-mode voltages

are available at the center taps between the two resistors.

49.9Ω

100Ω

UTP

100Ω

Figure 33. Driving Two UTP Cables With One Driver

Rev. 0 | Page 18 of 24

AD8146/AD8147/AD8148

V

= +2.5V

VPOS = +2.5V

S+

AD8146

CROSSPOINT SWITCH

1kΩ

10Ω

500Ω

54.9Ω

INPUT I, NEGATIVE PHASE

INPUT I, POSITIVE PHASE

RED

100Ω

V

OCM

CHANNEL UTP

500Ω

1kΩ

10Ω

500Ω

54.9Ω

INPUT J, NEGATIVE PHASE

INPUT J, POSITIVE PHASE

GREEN 100Ω

CHANNEL UTP

V

OCM

1kΩ

10Ω

500Ω

54.9Ω

INPUT K, NEGATIVE PHASE

INPUT K, POSITIVE PHASE

BLUE

100Ω

V

OCM

CHANNEL UTP

1kΩ

V

= –2.5V

VNEG = –2.5V

S–

Figure 35. Using the AD8146 as a Differential Receiver

Terminations are not required between the AD8146 and the

switch if the interconnection lengths are kept short (less than

two inches). The 10 Ω series resistors buffer the input

capacitance of the switch (typically 2 pF) and produce a low-

pass rolloff that is down by only 0.025 dB at 600 MHz.

LAYOUT AND POWER SUPPLY DECOUPLING

CONSIDERATIONS

Standard high speed PCB layout practices should be adhered

to when designing with the drivers. A solid ground plane is

required and good wideband power supply decoupling

networks should be placed as close as possible to the supply

pins. Small surface-mount ceramic capacitors are recommended

for these networks, and tantalum capacitors are recommended

for bulk supply decoupling.

OUTPUT PULL-DOWN (OPD)

The output pull-down feature, when used in conjunction with

series Schottky diodes, offers a convenient means to multiplex a

number of driver outputs together to form a video network. The

OPD pin is a binary input that controls the state of the outputs.

Its binary input level is referenced to GND (see the Specifications

section for the logic levels). When the OPD input is driven to its

low state, the output is enabled and operates in normal fashion.

In this state, the V_OCMinput can be used to provide a positive

bias on the series diodes, allowing the drivers to transmit

signals over the network. When the OPD input is driven to its

high state, the outputs of the drivers are forced to a low voltage,

irrespective of the level on the V_OCMinput, reverse-biasing the

series diodes and thus presenting high impedance to the

network. This feature allows a three-state output to be realized

that maintains its high impedance state even when the drivers

are not powered.

Source termination resistors on the differential outputs must be

placed as close as possible to the output pins to minimize load

capacitance due to the PCB traces.

DRIVING A CAPACITIVE LOAD

A purely capacitive load can react with the output impedance

of any amplifier to produce an undesirable phase shift, which

reduces phase margin and results in high frequency ringing in

the pulse response. The best way to minimize this effect is to

place a small resistor in series with each of the outputs of the

amplifier to buffer the load capacitance. Most applications

include 49.9 Ω source termination resistors, which effectively

buffer any stray load capacitance.

It is recommended that the output pull-down feature only be

used in conjunction with series diodes in such a way as to

ensure that the diodes are reverse-biased when the output pull-

down feature is asserted, because some loading conditions can

prevent the output voltage from being pulled all the way down.

Rev. 0 | Page 19 of 24

AD8146/AD8147/AD8148

Under no circumstances should capacitance be intentionally

added to an output to introduce frequency domain peaking.

Figure 36 and Figure 37 illustrate how adding just 5 pF of

excessive load capacitance influences time and frequency

domain responses.

ADDING PRE-EMPHASIS TO THE AD8148

UTP cables exhibit loss characteristics that are low pass in

nature and are exponential functions of the square root of the

frequency. Over wideband video bandwidths, the losses are

predominantly due to the skin effect, which causes the resistance of

the cable to increase with frequency. Even though the loss

characteristics are nonlinear, suitable linear networks can be

designed to approximately compensate for the losses.

2.0

V

= ±5V

S

R

= 200ꢀ

= 2V p-p

L, dm

1.5

1.0

V

OUT, dm

C

= 5pF

L

Placing the compensation network at the transmitting end of

the cable is referred to as pre-emphasis, because the higher

frequencies are emphasized, or boosted, before they are sent, to

compensate for the low-pass response of the cable. Because the

higher frequencies experience more loss than the lower frequencies

as they pass through the cable, the high and low frequencies

arrive at approximately the same level and at the end of the cable

when a properly designed pre-emphasis network is used at the

transmitter. The ideal cascaded frequency response of the pre-

emphasis network and the cable is therefore nominally flat.

0.5

C

= 0pF

L

0

–0.5

–1.0

–1.5

–2.0

0

2

4

6

8

10

12

14

16

18

20

TIME (ns)

Because the AD8148 has an internally set, closed-loop gain of 4

(12 dB), it is possible to reduce the gain at low frequencies using

external frequency selective components, then use these

components to provide increasing gain with increasing

frequency, back to a value close to 12 dB. These components, along

with the AD8148, form the pre-emphasis network. When properly

designed, the combined frequency response of the pre-emphasis

network and cable is approximately flat with a gain of 2 (6 dB).

Figure 36. Large Signal Transient Responses at Various Capacitive Loads

12

V

= ±5V

S

11

10

9

R

= 200ꢀ

= 2V p-p

L, dm

C

= 5pF

V

L

OUT, dm

8

7

Figure 38 illustrates how to construct a pre-emphasis network

using the AD8148 that compensates for 30 meters of UTP cable.

The network in the lower leg is required to match the transfer

function of the two feedback loops.

6

C

= 0pF

L

5

4

3

At dc, the capacitors are open circuits, and the network has a

gain of approximately 6.5 dB. (The additional 0.5 dB is added to

compensate for the cable flat loss that occurs at frequencies

below where the skin effect begins to take effect.) Moving up in

frequency, the 30 pF capacitor begins to take effect and introduces

a zero into the frequency response, causing the gain to increase

with frequency. Continuing to move up in frequency, the 30 pF

capacitor becomes an effective short, and the 487 Ω resistor

goes in parallel with the 442 Ω resistor, forming a pole in the

response. Continuing to move up in frequency, the 15 pF

capacitor takes effect, introducing another zero, and causes

the gain to further increase with frequency until it becomes

an effective short, and the gain starts to flatten out until the

amplifier response begins to roll off. The gain does not reach

12 dB before the amplifier begins to roll off because the 12 dB

value is a high frequency asymptote. The pole and zero locations

cited in the previous discussion are qualitative, but the

discussion describes the basic principles involved with the

operation of the pre-emphasis network.

2

10

100

FREQUENCY (MHz)

1000

Figure 37. Large Signal Frequency Responses at Various Capacitive Loads

While high frequency peaking is desirable in some cable

equalization applications, it should be implemented using

methods that do not compromise the stability of the driver and

that do not depend on amplifier parasitic elements. The parasitic

elements are affected by process variations and cannot be

depended upon for circuit designs. The amplifier may break

into oscillation when excess load capacitance is intentionally

added. For more information on this topic, see the Adding Pre-

Emphasis to the AD8148 section for a description on how to

introduce a controlled amount of pre-emphasis for 30 meters of

UTP using the AD8148.

Rev. 0 | Page 20 of 24

AD8146/AD8147/AD8148

Figure 39 illustrates the frequency response of the pre-emphasis

network.

EXPOSED PADDLE (EP)

The 24-lead LFCSP has an exposed paddle on the underside of

its body. To achieve the specified thermal resistance, it must

have a good thermal connection to one of the PCB planes. The

exposed paddle must therefore be soldered to a pad on the top

of the board that is connected to an inner plane with several

thermal vias. The AD8147/AD8148 use the paddle as a ground

reference; therefore, for these parts, the PCB plane used must be

the ground plane.

Figure 40 illustrates the frequency response of the pre-emphasis

circuit cascaded with the cable compared with that of the cable

alone. It can be seen that the overall response is flat to within

0.4 dB. The 0.4 dB ripple in the response is due to the fact

that the pre-emphasis network is linear, comprised of two real-

axis pole/zero pairs, and the cable response is nonlinear.

18pF

2kꢀ

30pF

487ꢀ

442ꢀ

75ꢀ

49.9ꢀ

500ꢀ

+

100 FEET

82.5ꢀ

100ꢀ

AD8148

VIDEO

SOURCE

UTP

49.9ꢀ

–

442ꢀ

2kꢀ

487ꢀ

30pF

18pF

39.2ꢀ

Figure 38. Pre-Emphasis Network Using the AD8148 for 30 Meters of UTP Cable

12

11

10

9

V

= ±5V

V

= ±5V

S

6

3

PRE-EMPHASIS

NETWORK

WITH CABLE

0

8

–3

–6

–9

CABLE ALONE

7

6

0.1

1

10

100

0.1

1

10

FREQUENCY (MHz)

100

FREQUENCY (MHz)

Figure 40. AD8148 Pre-Emphasis Network Cascaded With

30 Meters of UTP Cable vs. UTP Cable Alone

Figure 39. AD8148 Pre-Emphasis Network Frequency Response

Rev. 0 | Page 21 of 24

AD8146/AD8147/AD8148

OUTLINE DIMENSIONS

0.60 MAX

4.00

BSC SQ

0.60 MAX

PIN 1

INDICATOR

1

24

19

18

PIN 1

INDICATOR

0.50

BSC

2.25

TOP

VIEW

3.75

BSC SQ

EXPOSED

2.10 SQ

1.95

PAD

(BOTTOM VIEW)

0.50

0.40

0.30

6

13

7

12

0.25 MIN

0.80 MAX

0.65TYP

2.50 REF

1.00

0.85

0.80

12° MAX

0.05 MAX

0.02 NOM

0.30

0.23

0.18

COPLANARITY

0.08

0.20 REF

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2

Figure 41. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

4 mm × 4 mm

(CP-24-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model

Temperature Range

Package Description

Package Option

CP-24-1

AD8146ACPZ-R2¹

AD8146ACPZ-R7¹

AD8146ACPZ-RL¹

AD8147ACPZ-R2¹

AD8147ACPZ-R7¹

AD8147ACPZ-RL¹

AD8148ACPZ-R2¹

AD8148ACPZ-R7¹

AD8148ACPZ-RL¹

−40°C to +85°C

24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

CP-24-1

¹Z = RoHS Compliant Part.

Rev. 0 | Page 22 of 24

AD8146/AD8147/AD8148

NOTES

Rev. 0 | Page 23 of 24

AD8146/AD8147/AD8148

NOTES

registered trademarks are the property of their respective owners.

D06655-0-5/07(0)

Rev. 0 | Page 24 of 24


型号：	AD8147ACPZ-R2
厂家：	ADI
描述：	Triple Differential Driver for Wideband Video 三重差分驱动器，用于宽带视频驱动器消费电路商用集成电路音频放大器视频放大器
文件：	总24页 (文件大小：585K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD8147ACPZ-R2 [ADI]

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