AD816AY [ADI]
500 mA Differential Driver and Dual Low Noise VF Amplifiers; 500毫安差分驱动器和双通道低噪声放大器VF
| 型号： | AD816AY |
| 厂家： | 
ADI |
| 描述： | 500 mA Differential Driver and Dual Low Noise VF Amplifiers |
| 文件： | 总16页 (文件大小：414K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
500 mA Differential Driver and
Dual Low Noise (VF) Amplifiers
a
AD816*
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Flexible Configuration
Two Low Noise Voltage Feedback Amplifiers with
High Current Drive, Ideal for ADSL Receivers or
Drivers for Low Impedance Loads such as CRT Coils
Two High Current Drive Amplifiers, Ideal for an ADSL
Differential Driver or Single Ended Drivers for Low
Impedance Loads such as CRT Coils
Thermal Overload Protection
15
NC
14
13
12
11
10
9
OUT2 RECEIVER
–IN2 RECEIVER
+IN2 RECEIVER
+IN2 DRIVER
TAB IS
+V
S
B
A
–IN2 DRIVER
OUT2 DRIVER
+V
–V
8
S
+V
–V
S
7
S
S
6
OUT1 DRIVER
–IN1 DRIVER
CURRENT FEEDBACK AMPLIFIERS/DRIVERS
High Output Drive
5
4
+IN1 DRIVER
26 dBm Differential Line Drive for ADSL Transmitters
40 V p-p Differential Output Voltage, RL = 50 ⍀ @ 1 MHz
500 mA Continuous Current, RL = 5 ⍀
1 A Peak Current, 1% Duty Cycle, RL = 15 ⍀ for DMT
Low Distortion
3
+IN1 RECEIVER
–IN1 RECEIVER
OUT1 RECEIVER
2
1
NC = NO CONNECT
–68 dB @ 1 MHz THD, RL = 100 ⍀, VO = 40 V p-p
High Speed
120 MHz Bandwidth (–3 dB)
1500 V/s Differential Slew Rate, VO = 10 V p-p, G = +5
70 ns Settling Time to 0.1%
The two high output drive amplifiers are capable of supplying
a minimum of 500 mA continuous output current and up to
1A peak output current, and when configured differentially,
40 V p-p differential output swing can be achieved on ±15 V
supplies into a load of 50 Ω. The drivers have 120 MHz of
bandwidth and 1,500 V/µs of differential slew rate while
featuring total harmonic distortion of –68 dB at 1 MHz into a
100 Ω load, specifications required for high frequency telecom-
munication subscriber line drivers.
VOLTAGE FEEDBACK AMPLIFIERS/RECEIVERS
High Input Performance
4 nV/√Hz Voltage Noise
15 mV Max Input Offset Voltage
Low Distortion
The low noise voltage feedback amplifiers are fully independent
and can be configured differentially for use as receiver amplifi-
ers within a subscriber line hybrid interface or individually for
signal conditioning or filtering. The low noise of 4 nV/√Hz and
distortion of –68 dB at 1 MHz enable low level signals to be
resolved and amplified in the presence of large common-mode
voltages. 100 MHz of bandwidth and 180 V/µs of slew rate
combined with a load drive capability of 70 mA enable these
amplifiers to drive passive filters and low inductance coils. The
AD816 has thermal overload protection for system reliability
and is available in low thermal resistance power packages. The
AD816 operates over the industrial temperature range (–40°C
to +85°C).
–68 dB @ 1 MHz THD, VO = 10 V p-p, RL = 200 ⍀
High Speed
100 MHz Bandwidth (–3 dB)
180 V/s Slew Rate
High Output Drive
70 mA Output Current Drive
APPLICATIONS
ADSL, VDSL and HDSL Line Interface Driver and Receiver
CRT Convergence and Astigmatism Adjustment
Coil and Transformer Drivers
Composite Audio Amplifiers
PRODUCT DESCRIPTION
The AD816 consists of two high current drive and two low
noise amplifiers. These can be configured differentially for driv-
ing low impedance loads and receiving signals over twisted pair
cable or could be used independently for single ended driving
application such as correction circuits within high resolution
CRT Monitors.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1999
AD816–SPECIFICATIONS
(@ TA = +25؇C, VS = ؎15 V dc, RF = 1 k⍀ and RLOAD = 50 ⍀ unless otherwise noted)
DRIVER AMPLIFIERS
AD816A
Typ
Model
Conditions
VS
Min
Max Units
DYNAMIC PERFORMANCE
Small Signal Bandwidth (–3 dB)
G = +2, RF = 499 Ω, VIN = 0.125 V rms,
RL = 100 Ω
G = +2, RF = 499 Ω, VIN = 0.125 V rms,
RL = 100 Ω
G = +2, RF = 499 Ω, VIN = 0.125 V rms,
RL = 100 Ω
±15
±5
100
90
120
110
10
MHz
MHz
Bandwidth (0.1 dB)
±15
±15
±15
MHz
V/µs
ns
Differential Slew Rate
Settling Time to 0.1%
V
OUT = 10 V p-p, G = +5, RL = 100 Ω
1400 1500
70
10 V Step, G = +2
NOISE/HARMONIC PERFORMANCE
Total Harmonic Distortion (Differential)
Input Voltage Noise
f = 1 MHz, RLOAD = 100 Ω, VOUT = 40 V p-p ±15
–68
1.85
1.8
19
0.05
0.45
dBc
f = 10 kHz, G = +2 (Single Ended)
f = 10 kHz, G = +2
f = 10 kHz, G = +2
NTSC, G = +2, RLOAD = 25 Ω
NTSC, G = +2, RLOAD = 25 Ω
±5, ±15
nV/√Hz
pA/√Hz
pA/√Hz
%
Input Current Noise (+IIN
)
±5, ±15
±5, ±15
±15
Input Current Noise (–IIN
Differential Gain Error
Differential Phase Error
)
±15
Degrees
DC PERFORMANCE
Input Offset Voltage
±5
±15
5
10
12
15
25
mV
mV
mV
µV/°C
mV
mV
µV/°C
µA
µA
µA
µA
µA
T
T
T
MIN to TMAX
MIN to TMAX
MIN to TMAX
Input Offset Voltage Drift
Differential Offset Voltage
40
0.5
±5, ±15
2
5
Differential Offset Voltage Drift
–Input Bias Current
5
20
±5, ±15
±5, ±15
±5, ±15
60
100
5
5
50
50
+Input Bias Current
2
TMIN to TMAX
Differential Input Bias Current
Open-Loop Transresistance
10
T
MIN to TMAX
µA
MΩ
MΩ
V
OUT = ±10 V, RL = 1 kΩ
±5, ±15 0.7
2
TMIN to TMAX
0.6
INPUT CHARACTERISTICS
Differential Input Resistance
+Input
–Input
±15
7
15
MΩ
Ω
Differential Input Capacitance
Input Common-Mode Voltage Range
±15
±15
±5
±5, ±15 56
±5, ±15 80
1.4
13.5
3.5
60
pF
±V
±V
dB
dB
Common-Mode Rejection Ratio
Differential Common-Mode Rejection Ratio
TMIN to TMAX
TMIN to TMAX
100
OUTPUT CHARACTERISTICS
Voltage Swing
Single Ended, RLOAD = 25 Ω
Differential, RLOAD = 50 Ω
±15
±5
±15
±15
±15
±5
23
2.2
46
45
500
200
24.5
3.6
49
V p-p
V p-p
V p-p
V p-p
mA
mA
A
T
R
MIN to TMAX
LOAD = 5 Ω
Continuous Output Current
750
100
1.0
1.0
Peak Output Current
Short Circuit Current
10 µs Pulse, 1% Duty Cycle, RL = 15 Ω
Note 1
±15
±15
A
NOTES
1See Power Considerations section.
Specifications subject to change without notice.
–2–
REV. B
AD816
RECEIVER AMPLIFIERS (@ TA = +25؇C, VS = ؎15 V dc, RF = 1 k⍀ and RLOAD = 500 ⍀ unless otherwise noted)
AD816A
Min Typ Max
Model
Conditions
VS
Units
DYNAMIC PERFORMANCE
Small Signal Bandwidth (–3 dB)
G = +2, RL = 100 Ω
G = +2, RL = 100 Ω
G = +2
±15
±5
±15
±5
±15
±15
100
80
30
40
180
45
MHz
MHz
MHz
MHz
V/µs
ns
Bandwidth (0.1 dB)
G = +2
Slew Rate
Settling Time to 0.1%
VOUT = 4 V p-p
VOUT = 10 V p-p Step, G = +2
NOISE/HARMONIC PERFORMANCE
Total Harmonic Distortion
Input Voltage Noise
Current Noise
Differential Gain Error
f = 1 MHz, RLOAD = 200 Ω
f = 10 kHz
f = 10 kHz
±15
–68
4
2
0.04 0.08
0.05 0.1
0.03 0.1
0.06 0.1
dBc
±5, ±15
±5, ±15
±15
±5
±15
nV/√Hz
pA/√Hz
%
%
Degrees
Degrees
NTSC, G = +2, RLOAD = 150 Ω
Differential Phase Error
NTSC, G = +2, RLOAD = 150 Ω
±5
DC PERFORMANCE
Input Offset Voltage
±5, ±15
7.5
15
15
mV
mV
T
MIN to TMAX
Offset Voltage Drift
Input Bias Current
20
5
µV/°C
µA
µA
±5, ±15
±5, ±15
7
15
2
TMIN to TMAX
Input Offset Current
Offset Current Drift
Open-Loop Gain
0.5
1
6
µA
nA/°C
V/mV
V/mV
V
OUT = ±7.5 V, RLOAD = 150 Ω
±15
±15
3
1
TMIN to TMAX
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
300
1.5
+13 +14.3
–12 –13.4
+3.8 +4.3
–2.7 –3.4
kΩ
pF
V
V
V
Input Common-Mode Voltage Range
±15
±15
±5
±5
V
Common-Mode Rejection Ratio
VCM = ±5 V
±15
82
110
dB
OUTPUT CHARACTERISTICS
Output Voltage Swing
Single Ended, RLOAD = 150 Ω
±15
±15
±5
±5
±15
±15
25.2 25.5
25.2
V p-p
V p-p
V p-p
V p-p
mA
T
MIN to TMAX
Single Ended, RLOAD = 150 Ω
MIN to TMAX
6.2
6.0
65
6.4
T
Output Current
Short Circuit Current
RL = 150 Ω
70
105
mA
Specifications subject to change without notice.
LOAD = 50 ⍀ (Driver), RLOAD = 500 ⍀ (Receiver)
COMMON CHARACTERISTICS (@ T = +25؇C, V = ؎15 V dc, R = 1 k⍀ and R
unless otherwise noted)
A
S
F
AD816A
Model
Conditions
VS
Min Typ Max
Units
MATCHING CHARACTERISTICS
Crosstalk:
Driver to Driver
Drivers to Receivers
Receiver to Receiver
f = 1 MHz, VIN = 200 mV rms, RLOAD = 100 Ω ±15
f = 1 MHz, VIN = 200 mV rms, RLOAD = 100 Ω ±15
f = 1 MHz, VIN = 200 mV rms, RLOAD = 500 Ω ±15
–67
–64
–81
dB
dB
dB
POWER SUPPLY
Operating Range
Quiescent Current
±5
±18
56
59
V
±15
±15
±15, ±5
±15, ±5
46
mA
mA
dB
dB
TMIN to TMAX
TMIN to TMAX
TMIN to TMAX
Driver Supply Rejection Ratio
Receiver Supply Rejection Ratio
–49 –66
–69 –75
Specifications subject to change without notice.
REV. B
–3–
AD816
ABSOLUTE MAXIMUM RATINGS1
MAXIMUM POWER DISSIPATION
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V Total
The maximum power that can be safely dissipated by the
AD816 is limited by the associated rise in junction temperature.
The maximum safe junction temperature for the plastic encap-
sulated parts is determined by the glass transition temperature
of the plastic, about 150°C. Exceeding this limit temporarily
may cause a shift in parametric performance due to a change in
the stresses exerted on the die by the package. Exceeding a
junction temperature of 175°C for an extended period can result
in device failure.
Internal Power Dissipation2
Plastic (Y, YS and VR) . . 3.05 W (Observe Derating Curves)
Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ±VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . ±6 V
Output Short Circuit Duration
. . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves
Storage Temperature Range
Y, YS, VR Package . . . . . . . . . . . . . . . . . . –65°C to +125°C
Operating Temperature Range
AD816A . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Lead Temperature Range (Soldering, 10 sec) . . . . . . . +300°C
The AD816 has thermal shutdown protection, which guarantees
that the maximum junction temperature of the die remains below a
safe level. However, shorting the output to ground or either power
supply for an indeterminate period will result in device failure.
To ensure proper operation, it is important to observe the derat-
ing curves and refer to the section on power considerations.
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only. functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2Specification is for device in free air: 15-Lead Through Hole and Surface Mount:
θJA = 41°C/W.
It must also be noted that in high (noninverting) gain configura-
tions (with low values of gain resistor), a high level of input
overdrive can result in a large input error current, which may
result in a significant power dissipation in the input stage. This
power must be included when computing the junction tempera-
ture rise due to total internal power.
PIN CONFIGURATION
Y-15
VR-15, YS-15
14
T
= 150؇C
J
13
12
11
θJA = 16؇C/W
SOLDERED DOWN TO
COPPER HEAT SINK AREA
(STILL AIR = 0FT/MIN)
10
9
AD816 AVR, AY
TOP VIEW
TOP VIEW
8
7
6
θJA = 41؇C/W
(STILL AIR = 0FT/MIN)
NO HEAT SINK
5
4
AD816 AVR, AY
3
2
1
0
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
AMBIENT TEMPERATURE – ؇C
Figure 1. Plot of Maximum Power Dissipation vs. Tem-
perature (Copper Heat Sink Area = 2 in.2)
ORDERING GUIDE
Package
Option
Model
Temperature Range
Package Description
AD816AY
AD816AYS
AD816AVR
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
15-Lead Through-Hole SIP with Staggered Leads and 90° Lead Form
15-Lead Through-Hole SIP with Staggered Leads and Straight Lead Form
15-Lead Surface Mount DDPAK
Y-15
YS-15
VR-15
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD816 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. B
Typical Driver Performance Characteristics–AD816
60
30
25
20
60
V
= ؎15V
S
–I , V = ؎15V
B
S
50
50
40
40
30
20
10
0
30
20
10
0
15
10
–I , V = ؎5V
B
S
V
= ؎5V
S
5
0
+I , V = ؎5V, ؎15V
B
S
10
100
1k
10k
–40
–20
0
20
40
60
80
100
LOAD RESISTANCE – (Differential – ⍀) (Single-Ended – ⍀/2)
JUNCTION TEMPERATURE – ؇C
Figure2. DriverOutputVoltageSwingvs. LoadResistance
Figure 5. Driver Input Bias Current vs. Temperature
100
10
1
100
–40
V
= ؎15V
S
G = +10
= 40V p-p
–50
–60
V
OUT
50⍀
INVERTING INPUT
CURRENT NOISE
100⍀
400⍀
–70
R
= 50⍀
L
(DIFFERENTIAL)
10
–80
NONINVERTING INPUT
CURRENT NOISE
R
= 200⍀
(DIFFERENTIAL)
L
–90
–100
–110
INPUT VOLTAGE
NOISE
1
100k
10
100
1k
10k
100
1k
10k
100k
1M
10M
FREQUENCY – Hz
FREQUENCY – Hz
Figure 3. Driver Input Current and Voltage Noise vs.
Frequency
Figure 6. Driver Total Harmonic Distortion vs. Frequency
80
70
0
–10
–20
V
= ؎15V
S
G = +2
= 100⍀
V
= ؎15V
S
R
L
60
50
40
30
20
10
–30
–40
–50
–PSRR
1k⍀
+PSRR
–60
–70
1k⍀
1k⍀
V
V
OUT
IN
–80
–90
1k⍀
–100
10k
100k
1M
FREQUENCY – Hz
10M
100M
0.01
0.1
1
10
100
300
FREQUENCY – MHz
Figure 4. Driver Power Supply Rejection vs. Frequency
Figure 7. Driver Common-Mode Rejection vs. Frequency
–5–
REV. B
AD816–Typical Driver Performance Characteristics
80
1400
2800
G = +5
= 100⍀
–SR
T
= +25؇C
A
R
L
1200
2400
60
40
20
0
V
= ؎5V
S
DIFFERENTIAL SR
+SR
1000
800
600
400
2000
1600
1200
800
V
= ؎15V
S
V
= ؎10V
S
V
IN
SINGLE
DRIVER
f = 0.1Hz
100⍀
49.9⍀
1k⍀
V
OUT
–20
R =
L
–40
–60
200
0
400
0
5⍀
1k⍀
0
0
5
10
15
20
–2.0 –1.6 –1.2 –0.8 –0.4
0.4
0.8 1.2 1.6
2.0
OUTPUT STEP SIZE – V p-p
LOAD CURRENT – Amps
Figure 8. Driver Slew Rate vs. Output Step Size
Figure 11. Driver Thermal Nonlinearity vs. Output Current
Drive
15
T
= +25؇C
= ؎15V
A
V
= ؎10V
T
= +25؇C
40
S
A
V
S
10
5
V
= ؎15V
S
V
= ؎5V
R
= 100⍀
L
S
30
20
R
R
= 50⍀
= 25⍀
L
0
V
IN
SINGLE
DRIVER
f = 0.1Hz
100⍀
–5
–10
–15
V
L
OUT
49.9⍀
10
0
R =
L
25⍀
1k⍀
1k⍀
R
= 1⍀
L
0
2
4
6
8
10
12
14
–20 –16 –12 –8
–4
V
0
4
8
12
16
20
FREQUENCY – MHz
– Volts
OUT
Figure 9. Driver Gain Nonlinearity vs. Output Voltage
Figure 12. Driver Large Signal Frequency Response
100
10
100
90
V
= ؎5V
S
V
= ؎15V
1
S
0.1
10
0%
0.01
5V
1s
30k
100k 300k
1M
3M
10M
30M 100M 300M
FREQUENCY – Hz
Figure 10. Driver 40 V p-p Differential Sine Wave; RL = 50 Ω,
f = 100 kHz
Figure 13. Driver Closed-Loop Output Resistance vs.
Frequency
–6–
REV. B
AD816
Typical Driver Characteristics–
6
6 BACK TERMINATED LOADS (25⍀)
0
G = +2
0.04
0.03
0.02
0.01
0.00
0.5
0.4
0.3
0.2
R
R
R
= 499⍀
= 100⍀
= 100⍀
F
L
S
3
–3
–6
PHASE
G = +2
= 1k⍀
NTSC
V
= 0.5Vrms
IN
R
F
0
0.1
–0.01
–0.02
–0.03
0.0
–0.1
–0.2
–0.3
–9
–12
–15
–18
–21
–24
–27
–3
–6
–9
GAIN
V
= 0.25Vrms
IN
IN
–0.04
1
2
3
4
5
6
7
8
9
10 11
2 BACK TERMINATED LOADS (75⍀)
0.12
0.10
0.08
0.06
0.04
0.02
0.00
–0.02
–0.04
0.010
0.005
0.000
–0.005
–0.010
–0.015
–0.020
–0.025
–0.030
V
= 125mVrms
–12
PHASE
GAIN
–15
–18
–21
G = +2
V
= 62.5mVrms
1M
R
= 1k⍀
IN
F
NTSC
100k
10M
100M 300M
1
2
3
4
5
6
7
8
9
10 11
FREQUENCY – Hz
Figure 17. Driver Small and Large Signal Frequency
Response, G = +2
Figure 14. Driver Differential Gain and Differential
Phase (Per Amplifier)
2
1
0
V
= 200mVrms
IN
–10
–20
R
= 499⍀
F
DRIVER
B
DRIVER
A
INPUT
100⍀
INPUT
100⍀
OUTPUT
OUTPUT
0
50⍀
50⍀
V
G +5
R
R
= 50mVrms
IN
100⍀
100⍀
–1
–2
–3
–30
–40
R
= 604⍀
499⍀
499⍀
F
499⍀
499⍀
= 100⍀
= 100⍀
L
S
R
= 750⍀
F
0.1
–50
–60
–70
DRIVER A = INPUT
DRIVER B = OUTPUT
–4
–5
0
R
= 604⍀
F
–0.1
R
= 750⍀
F
DRIVER B = INPUT
DRIVER A = OUTPUT
–6
–7
–0.2
–0.3
–0.4
–80
–90
–8
–100
100k
1M
10M
FREQUENCY – Hz
100M 300M
300M
100M
10k
100k
1M
10M
FREQUENCY – Hz
Figure 18. Driver Frequency Response and Flatness,
G = +5
Figure 15. Driver Output-to-Output Crosstalk vs.
Frequency
3
3
G = +1
V
V
= 1.0Vrms
= 0.5Vrms
V
= 200mVrms
IN
IN
R
R
R
= 499⍀
=100⍀
=100⍀
F
L
S
2
1
0
G +2
R
= 499⍀
F
R
R
= 100⍀
L
–3
= 100⍀
S
IN
0
–1
–2
–6
–9
R
= 604⍀
V
= 0.25Vrms
F
IN
–12
–15
–18
–3
–4
R
= 750⍀
F
V
= 125mVrms
IN
–5
–6
–7
–21
–24
V
= 62.5mVrms
1M
IN
–27
100k
100k
1M
10M
FREQUENCY – Hz
100M 300M
300M
10M
100M
FREQUENCY – Hz
Figure 16. Driver Small and Large Signal Frequency
Response, G = +1
Figure 19. Driver Frequency Response vs. RF, G = +2
REV. B
–7–
AD816–Typical Driver Performance Characteristics
499⍀
+15V
1k⍀
10F
0.1F
10F
+15V
0.1F
0.1F
499⍀
8
1k⍀
8
V
IN
AD816
AD816
PULSE
GENERATOR
55⍀
DRIVER A/B
100⍀
DRIVER A/B
100⍀
V
R
= 100⍀
0.1F
IN
L
R
= 100⍀
7
L
7
T
/T = 250ps
F
R
PULSE
GENERATOR
10F
50⍀
10F
–15V
T
/T = 500ps
F
–15V
R
Figure 24. Driver Test Circuit, Gain = +2
Figure 20. Test Circuit Gain = –1
Figure 25. 10 V Step Response, G = +2
Figure 21. Driver 500 mV Step Response, G = –1
Figure 26. Driver 400 mV Step Response, G = +2
Figure 22. Driver 4 V Step Response, G = –1
R
F
10F
+15V
0.1F
R
G
8
AD816
DRIVER A/B
100⍀
0.1F
V
R
= 100⍀
IN
L
7
PULSE
GENERATOR
50⍀
10F
–15V
T /T = 250ps
R
F
Figure 27. Driver 20 V Step Response, G = +5
Figure 23. Test Circuit, Gain = 1 + RF/RG
–8–
REV. B
Typical Receiver Performance Characteristics–AD816
–40
50
40
30
20
10
0
G = +5
V
= 14V p-p
–50
–60
OUT
R
R
= 4k⍀
= 1k⍀
F
L
–70
–80
–90
–100
3
10
100
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
10M
FREQUENCY – Hz
FREQUENCY – Hz
Figure 31. Receiver Harmonic Distortion vs. Frequency
Figure 28. Receiver Input Voltage Noise Spectral Density
3
9
5
V
= 1.0Vrms
= 0.5Vrms
IN
1k⍀
G = +2
4
0
6
3
1k⍀
R
C
R
R
= 1k⍀
= 2.2pF
= 100⍀
= 0⍀
F
F
L
S
V
IN
–3
3
2
V
OUT
V
IN
100⍀
–6
–9
0
V
= ؎15V
50⍀
S
–3
–6
1
V
= 0.25Vrms
IN
–12
0
–1
–2
–3
–15
–18
–9
V
= 0.125Vrms
IN
–12
V
S
= ؎5V
–21
–24
–27
–15
–18
–21
V
= 0.0625Vrms
1M
IN
–4
–5
100k
10M
100M 300M
1M
10M
100M 300M
100k
FREQUENCY – Hz
FREQUENCY – Hz
Figure 29. Receiver Closed-Loop Gain vs. Frequency,
Gain = –1
Figure 32. Receiver Small and Large Signal Frequency
Response, Gain = +2
100
80
100
90
80
70
POSITIVE
SUPPLY
60
60
NEGATIVE
50
1k⍀
1k⍀
SUPPLY
40
V
V
OUT
IN
1k⍀
40
0
30
20
10
1k⍀
1k
10k
100k
FREQUENCY – Hz
1M
10M
100
1k
10k
100k
FREQUENCY – Hz
1M
10M
100M
Figure 30. Receiver Common-Mode Rejection vs.
Frequency
Figure 33. Receiver Power Supply Rejection vs. Frequency
REV. B
–9–
AD816–Typical Receiver Performance Characteristics
2.2pF
1k⍀
+15V
1k⍀
10F
10F
0.1F
10F
+15V
1k⍀
50⍀
0.1F
V
8
IN
1k⍀
8
PULSE
GENERATOR
AD816
REC A/B
V
OUT
AD816
REC A/B
V
0.1F
OUT
R
= 500⍀
7
T /T = 250ps
L
R
F
0.1F
V
IN
R
L
7
10F
PULSE
GENERATOR
50⍀
–15V
–15V
T /T = 500ps
R
F
Figure 38. Test Circuit, Gain = –1
Figure 34. Test Circuit, Gain = +2
50ns
5V
Figure 39. Receiver 10 V Step Response, G = –1
Figure 35. Receiver 10 V Step Response, G = +2
50ns
Figure 40. Receiver 400 mV Step Response, G = –1
Figure 36. Receiver 400 mV Step Response, G = +2
0
0
DRV A
REC A
INPUT
V
= 200mVrms
INPUT
100⍀
50⍀
IN
V
= 200mVrms
IN
OUTPUT
OUTPUT
–10
–20
–10
–20
50⍀
1k⍀
100⍀
100⍀
REC A
REC B
1k⍀
INPUT
INPUT
499⍀
499⍀
OUTPUT OUTPUT
499⍀
1k⍀
2.2pF
2.2pF
50⍀
50⍀
1k⍀
–30
–40
–50
–30
–40
–50
100⍀ 100⍀
1k⍀
50⍀
499⍀
100⍀
50⍀
1k⍀
OUTPUT OUTPUT
1k⍀
1k⍀
INPUT
2.2pF
2.2pF
100⍀
100⍀
INPUT
REC B
DRV B
DRIVER A: INPUT
RECEIVER A: OUTPUT
–60
–70
–60
–70
RECEIVER B : INPUT
RECEIVER A : OUTPUT
DRIVER B: INPUT
RECEIVER A: OUTPUT
DRIVER A: INPUT
RECEIVER B: OUTPUT
–80
–90
–80
–90
RECEIVER A = INPUT
RECEIVER B = OUTPUT
DRIVER B: INPUT
RECEIVER A: OUTPUT
–100
–100
1
10
100 300
1
10
100 300
0.01
0.1
0.01
0.1
FREQUENCY – MHz
FREQUENCY – MHz
Figure 41. Driver-to-Receiver Crosstalk vs. Frequency
Figure 37. Receiver Output-to-Output Crosstalk
vs. Frequency
–10–
REV. B
AD816
THEORY OF OPERATION (DRIVER)
Table I. Driver Resistor Values
The AD816 driver is a dual current feedback amplifier with high
(500 mA) output current capability. Being a current feedback
amplifier, the AD816 driver’s open-loop behavior is expressed
as transimpedance, ∆VO/∆I–IN, or TZ. The open-loop trans-
impedance behaves just as the open-loop voltage gain of a volt-
age feedback amplifier, that is, it has a large dc value and de-
creases at roughly 6 dB/octave in frequency.
RF (⍀)
RG (⍀)
G = +1
–1
604
499
499
499
1k
∞
499
499
125
110
+2
+5
+10
Since RIN is proportional to 1/gM, the equivalent voltage gain is
just TZ × gM, where the gM in question is the transconductance
of the input stage. Figure 42 shows the driver connected as a
follower with gain. Basic analysis yields the following results:
DRIVER DC ERRORS AND NOISE
There are three major noise and offset terms to consider in a
current feedback amplifier. For offset errors refer to the equa-
tion below. For noise error the terms are root-sum-squared to
give a net output error. In the circuit below (Figure 43), they
are input offset (VIO) which appears at the output multiplied by
the noise gain of the circuit (1 + RF/RG), noninverting input
current (IBN × RN) also multiplied by the noise gain, and the
inverting input current, which when divided between RF and RG
and subsequently multiplied by the noise gain always appear at
the output as IBI × RF. The input voltage noise of the AD816 is
less than 4 nV/√Hz. At low gains, however, the inverting input
current noise times RF is the dominant noise source. Careful
layout and device matching contribute to better offset and drift.
The typical performance curves in conjunction with the equations
below can be used to predict the performance of the AD816 in
any application.
TZ
S
( )
VO
VIN
= G ×
TZ S + G × R + RF
( )
IN
where:
RF
RG
1+
G =
R
IN = 1/gM ≈ 25 Ω
R
F
R
G
R
IN
V
OUT
R
N
RF
RG
RF
RG
V
IN
VOUT =VIO 1+
± IBN RN 1+
± IBI RF
Figure 42. Current-Feedback Amplifier Operation
R
F
Recognizing that G × RIN << RF for low gains, it can be seen to
the first order that bandwidth for this amplifier is independent
of gain (G).
I
BI
R
R
G
N
AD816
DRIVERS
I
VIO
V
BN
OUT
Considering that additional poles contribute excess phase at
high frequencies, there is a minimum feedback resistance below
which peaking or oscillation may result. This fact is used to
determine the optimum feedback resistance, RF. In practice
parasitic capacitance at the inverting input terminal will also add
phase in the feedback loop so that picking an optimum value for
RF can be difficult.
Figure 43. Driver Output Offset Voltage
THEORY OF OPERATION (RECEIVER)
Each AD816 receiver is a wide band high performance opera-
tional amplifier. It also provides a constant slew rate, bandwidth
and settling time over its entire specified temperature range.
Achieving and maintaining gain flatness of better than 0.1 dB at
frequencies above 10 MHz requires careful consideration of
several issues.
The AD816 receiver consists of a degenerated NPN differential
pair driving matched PNPs in a folded-cascode gain stage. The
output buffer stage employs emitter followers in a class AB
amplifier which deliver the necessary current to the load while
maintaining low levels of distortion.
Choice of Feedback and Gain Resistors
The fine scale gain flatness will, to some extent, vary with
feedback resistance. It is therefore recommended that once
optimum resistor values have been determined, 1% tolerance
values should be used if it is desired to maintain flatness over a
wide range of production lots. Table I shows optimum values
for several useful gain configurations. These should be used as a
starting point in any application.
A protection resistor in series with the noninverting input is
required in circuits where the input to the receiver could be
subject to transients on continuous overload voltages exceeding
the ±6 V maximum differential limit. The resistor provides
protection for the input transistors, by limiting their maximum
base current.
REV. B
–11–
AD816
PRINTED CIRCUIT BOARD LAYOUT
relationship between junction temperature (TJ) and various
CONSIDERATIONS
components of θJA.
As to be expected for a wideband amplifier, PC board parasitics
can affect the overall closed-loop performance. Of concern are
stray capacitances at the output and the inverting input nodes. If
a ground plane is to be used on the same side of the board as
the signal traces, a space (5 mm min) should be left around the
signal lines to minimize coupling.
TJ =TA + PIN θJA
Equation 1
T
J
θA
(JUNCTION TO
DIE MOUNT)
θ B
(DIE MOUNT
TO CASE)
POWER SUPPLY BYPASSING
T
A
Adequate power supply bypassing can be critical when optimiz-
ing the performance of a high frequency circuit. Inductance in
the power supply leads can form resonant circuits that produce
peaking in the amplifier’s response. In addition, if large current
transients must be delivered to the load, then bypass capacitors
(typically greater than 1 µF) will be required to provide the best
settling time and lowest distortion. A parallel combination of
10.0 µF and 0.1 µF is recommended. Under some low frequency
applications, a bypass capacitance of greater than 10 µF may be
necessary. Due to the large load currents delivered by the AD816,
special consideration must be given to careful bypassing. The
ground returns on both supply bypass capacitors as well as signal
common must be “star” connected as shown in Figure 44.
θA + θ B = θ JC
CASE
θ CA
θ JC
T
J
T
P
A
IN
θ JA
WHERE:
P
T
= DEVICE POWER DISSIPATION
= AMBIENT TEMPERATURE
= JUNCTION TEMPERATURE
IN
A
T
θ
θ
J
= THERMAL RESISTANCE – JUNCTION TO CASE
= THERMAL RESISTANCE – CASE TO AMBIENT
JC
CA
Figure 45. A Breakdown of Various Package Thermal
Resistances
Figure 46 gives the relationship between output voltage swing
into various loads and the power dissipated by the AD816 (PIN).
This data is given for both sine wave and square wave (worst
case) conditions. It should be noted that these graphs are for
mostly resistive (phase < ±10°) loads. When the power dissipation
requirements are known, Equation 1 and the graph on Figure 47
can be used to choose an appropriate heat sinking configuration.
+V
S
RECEIVER A
+IN
IN
R
DRIVER A
OUT
OUT
+OUT
–OUT
R
F
R
F
G
R
G
R
F
(OPTIONAL)
R
F
R
G
f = 1kHz
= ؎15V
R
= 50⍀
DRIVER B
L
V
IN
S
4
3
2
1
–IN
RECEIVER B
SQUARE WAVE
–V
S
SINE WAVE
R
= 100⍀
L
Figure 44. Signal Ground Connected in “Star”
Configuration
POWER CONSIDERATIONS
R
= 200⍀
L
The 500 mA drive capability of the AD816 driver enables it to
drive a 50 Ω load at 40 V p-p when it is configured as a dif-
ferential driver. This implies a power dissipation, PIN, of nearly
5 watts. To ensure reliability, the junction temperature of the
AD816 should be maintained at less than 175°C. For this rea-
son, the AD816 will require some form of heat sinking in most
applications. The thermal diagram of Figure 45 gives the basic
10
20
30
40
V
– Volts p-p
OUT
Figure 46. Total Power Dissipation vs Differential Driver
Output Voltage
–12–
REV. B
AD816
Normally, the AD816 will be soldered directly to a copper pad.
Figure 47 plots θJA against size of copper pad. This data pertains
to copper pads on both sides of G10 epoxy glass board connected
together with a grid of feedthroughs on 5 mm centers.
The AD816 is equipped with a thermal shutdown circuit. This
circuit ensures that the temperature of the AD816 die remains
below a safe level. In normal operation, the circuit shuts down
the AD816 at approximately 180°C and allows the circuit to
turn back on at approximately 140°C. This built-in hysteresis
means that a sustained thermal overload will cycle between
power-on and power-off conditions. The thermal cycling typi-
cally occurs at a rate of 1 ms to several seconds, depending on
the power dissipation and the thermal time constants of the
package and heat sinking. Figures 48 and 49 illustrate the ther-
mal shutdown operation after driving OUT1 to the + rail, and
OUT2 to the – rail, and then short-circuiting to ground each
output of the AD816. The AD816 will not be damaged by
momentary operation in this state, but the overload condition
should be removed.
This data shows that loads of 100 ohms or greater will usually
not require any more than this. This is a feature of the AD816’s
15-lead power SIP package.
An important component of θJA is the thermal resistance of the
package to heatsink. The data given is for a direct soldered
connection of package to copper pad. The use of heatsink
grease either with or without an insulating washer will increase
this number. Several options now exist for dry thermal connec-
tions. These are available from Bergquist as part # SP600-90.
Consult with the manufacturer of these products for details of
their application.
2
COPPER HEAT SINK AREA (TOP AND BOTTOM) – in
1
2
3
35
30
AD816AVR, AY (θ = 2؇C/W)
JC
25
20
Figure 48. OUT2 Shorted to Ground Through a 2 Ω
Resistor, Square Wave Is OUT1, RF = 1 kΩ, RG = 222 Ω
15
10
0
0.5k
1k
1.5k
2k
2.5k
2
COPPER HEAT SINK AREA (TOP AND BOTTOM) – mm
Figure 47. Power Package Thermal Resistance vs. Heat
Sink Area
Other Power Considerations
There are additional power considerations applicable to the
AD816. First, as with many current feedback amplifiers, there is an
increase in supply current when delivering a large peak-to-peak
voltage to a resistive load at high frequencies. This behavior is
affected by the load present at the amplifier’s output. Figure 12
summarizes the full power response capabilities of the AD816
driver. These curves apply to the differential driver applications
(right-hand side of Figure 52). In Figure 12, maximum continu-
ous peak-to-peak output voltage is plotted vs. frequency for
various resistive loads. Exceeding this value on a continuous
basis can damage the AD816.
Figure 49. OUT1 Shorted to Ground Through a 2 Ω
Resistor, Square Wave Is OUT2, RF = 1 kΩ, RG = 222 Ω
REV. B
–13–
AD816
In addition to the passive circuits that have been used over time,
active circuit techniques can enhance the hybrid’s performance.
Figure 50 shows one of the various hybrid circuits that uses the
AD816 in an ADSL application. The high power op amps serve
as the transmitter, while the low noise amplifiers serve as the
receiver.
APPLICATIONS
ADSL Transceiver
The AD816 is designed for the primary purpose of providing an
integrated solution for the transmit and receive functions of an
ADSL modem. ADSL or Asymmetrical Digital Subscriber Line
is a means for delivering up to 6 Mbps from a telephone central
office (CO) into a home over the conventional telephone twisted
pair (local loop) and a few hundred kbps simultaneously in the
opposite direction.
The power amplifiers of the AD816 (D1 and D2) are arranged
in a differential configuration that receives its inputs from the
differential outputs of a D/A converter. The outputs differen-
tially drive the transformer primary with a turns ratio of 1:2.
The line on the secondary side of the transformer has an imped-
ance of 120 Ω. Thus one quarter of this resistance (30 Ω) is
required for back termination on the primary side due to the
impedance scaling by the square of the turns ratio. This resis-
tance is divided in half (15 Ω) and put on each side of the drive
buffers for symmetry (R101 and R201).
The transmit/receive block is commonly referred to as a hybrid,
which is an old telephone term, and the function was originally
performed with passive circuitry in early phone systems. The
hybrid’s function is to deliver maximum transmit power down
the line, while providing the receive circuitry with a maximum
receive signal and a minimized (self) transmit signal. As the line
gets longer, this separation becomes much more difficult, be-
cause the transmit signal must be larger to reach the other end
with acceptable SNR, while the receive signal is more attenu-
ated by the longer line.
The receive section (R1 and R2) is configured as a pair of differ-
ence amplifiers that together produce a differential output that
consists of the receive signal in addition to the transmit signal
attenuated by the trans-hybrid loss.
The figure of merit for the performance of the hybrid is com-
monly called trans-hybrid loss and is a measure of how much
the transmit signal that appears in the receive circuit has been
attenuated relative to the amplitude of the transmit signal itself.
It is measured in dBs and is a function of frequency.
The circuit is highly symmetrical, so a single-ended explanation
can be easily generalized to understand the differential opera-
tion. D1 output terminals (Pin 6 of the AD816) drives the top
of the primary of T1 through R101. A voltage divider is formed
+15V
0.1F
10F
C601
0.1F
8
R101
15⍀
4
5
T1
XFRMR
V+
6
TELEPHONE
D1
1
2
4
715⍀
7
5
806⍀
715⍀
R201
15⍀
10
11
10
9
6
TWISTED PAIR
9
D2
7
8
V–
C602
0.1F
AD816
R102
196⍀
R202
196⍀
R106
348⍀
0.1F
10F
R105
162⍀
R103
196⍀
3
2
–15V
R203
196⍀
RCV OUT+
1
AD816
R104
1.18k⍀
C101
8.2F
R1
R107
1k⍀
R204
1.18k⍀
C201
8.2F
R108
2.37k⍀
L101
12H
R206
348⍀
L201
12H
R205
162⍀
12
RCV OUT–
14
AD816
13
R2
R207
1k⍀
R208
2.37k⍀
Figure 50. AD816 as an ADSL Transceiver
–14–
REV. B
AD816
Dual Composite Amplifier
by R101 and all the downstream circuitry comprised of T1, the
transmission line and its termination. For an ideal transformer,
transmission line and termination, this will appear to be 15 Ω,
and thus the signal appearing at Pins 1 and 2 of T1 will be the
output of D1 divided by two in the ideal case. This signal is
applied to the input of R1 (Receive 1 of the AD816) (Pin 3) via
R105.
A composite amplifier uses two different op amps together in a
circuit to yield an overall performance that has some of the
advantages of each op amp. In the case of the AD816, two com-
posite amplifiers can be constructed that offer the low noise of
the receiver amps in addition to the high current output of the
driver amps.
The circuit in Figure 51 shows an example of such a circuit. It
uses receiver amp R1 for the low noise first stage and driver D1
for the high output current second stage. Both local and overall
feedback are used to get the desired response.
In some ADSL systems (DMT), there is a need to transmit
higher crest factor signals. Typically this is done by increasing
the turns ratio of T1 to as much as 4:1. In this case, R101 and
R201 would be 3.75 Ω, and the peak current of the AD816
(1 A) would be the drive limit of the transmitter.
R1 is configured as a difference amplifier. The negative side
(Pin 2) is driven by another signal that is a divided down version
of the output of D1. This circuit is formed by R102 as one side
of the voltage divider along with R103, C101, R104 and L101
as the other half of the divider. If the frequency dependent
impedance part of this circuit matches the transformer, trans-
mission line and termination impedance, then the signals
applied to both sides of the difference-amp-configured R1 will
be the same, and the transmit signal will be totally subtracted
out by the circuit.
2
4
R1
6
3
V
D1
V
OUT
IN
5
Figure 51. AD816 Composite Amplifier
Creating Differential Signals
If only a single-ended signal is available to drive the AD816 and
a differential output signal is desired, a circuit can be used to
perform the single-ended to differential conversion.
In a real-world situation, it is not practical (or even possible) to
subtract out all of the transmit signal (100% trans-hybrid loss),
but only provide a first order cancellation which goes a long way
toward reducing the dynamic range of the RCVOUT signal.
The overall performance of this circuit depends on the ability to
build a lumped element network that matches the impedance of
the transmission line over the frequency range required for
ADSL (≈ 20 kHz to 1.1 MHz).
The circuit shown in Figure 52 performs this function. It uses
the AD816 with the gain of one receiver set at +1 and the gain
of the other at –1. The 1 kΩ resistor across the input terminals
of the follower makes the noise gain (NG = 2) equal to the
inverter’s. The two receiver outputs then differentially drive the
inputs to the AD816 driver with no common-mode signal to first
order.
The circuits formed by D2 and R2 of the AD816 are totally
symmetric with those formed by D1 and R1 and work in the
same fashion. All the components in the D1, R1 circuits that are
numbered with 100 range numbers are numbered with 200
range numbers in the D2, R2 circuits.
+15V
+15V
0.1F
0.1F
10F
RECEIVER #1
100⍀
The receive signal from the telephone line creates a differential
signal across the primary of T1. There is, however, a two to one
reduction in amplitude due to turns ratio of T1. This differen-
tial signal is applied to the + inputs (Pins 3 and 12) of R1 and
R2. The receive amplifiers buffer this signal and present a differ-
ential output at Pins 1 and 14. There is no significant receive
signal applied to the negative inputs of R1 and R2 due to the
attenuating effects of R101 and R201 and the low output
impedances of D1 and D2.
4
5
8
3
8
6
DRIVER #1
AD816
1
1k⍀
AD816
2
R
F
499⍀
1k⍀
R
G
R
L
100⍀
1k⍀
1k⍀
R
F
499⍀
6
5
10
RECEIVER #2
7
AD816
DRIVER #2
9
AD816
4
11
0.1F
7
Thus, the overall circuit provides first order cancellation of the
transmit signal and differential buffering of the receive signal.
100⍀
10F
0.1F
–15V
–15V
Figure 52. Differential Driver with Single-Ended
Differential Converter
REV. B
–15–
AD816
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
15-Lead Through-Hole SIP with Staggered Leads
15-Lead Surface Mount DDPAK
(VR-15)
and 90؇ Lead Form
(Y-15)
0.110
(2.79)
BSC
0.063 (1.60)
0.057 (1.45)
0.152 (3.86)
0.148 (3.76)
0.110
(2.79)
BSC
0.394
(10.007)
0.063 (1.60)
0.057 (1.45)
0.152 (3.86)
0.148 (3.76)
0.394
(10.007)
0.137
(3.479)
TYP
0.137
(3.479)
TYP
0.516
(13.106)
0.042
(1.066)
TYP
0.671
0.666
±0.006
(17.043
±0.152)
SHORT
LEAD
±0.006
(16.916
±0.152)
LONG
LEAD
0.042
(1.066)
TYP
0.080 (2.03)
0.065 (1.65)
2 PLACES
1
15
0.080 (2.03)
0.146 (3.70)
0.138 (3.50)
1
15
8°
0°
PIN 1
0.065 (1.65)
2 PLACES
0.079 (2.006)
DIA
2 PLACES
0.600 (15.24)
PIN 1
0.079
(2.006) DIA
2 PLACES
BSC
0.024 (0.61)
0.014 (0.36)
0.798 (20.27)
0.778 (19.76)
0.798 (20.27)
0.024 (0.61)
0.014 (0.36)
0.778 (19.76)
0.182 (4.62)
0.172 (4.37)
0.182 (4.62)
0.172 (4.37)
0.100 (2.54) 0.031 (0.79)
0.209 ±0.010
(5.308 ±0.254)
SEATING
PLANE
BSC
SEATING
PLANE
0.024 (0.60)
0.050 0.031 (0.79)
(1.27)
BSC
0.024 (0.60)
0.700 (17.78) BSC
15-Lead Through-Hole SIP with Staggered Leads
and Straight Lead Form
(YS-15)
0.110
(2.79)
BSC
0.152 (3.86)
0.148 (3.76)
0.063 (1.60)
0.057 (1.45)
0.394
(10.007)
0.137
(3.48)
TYP
0.601
±0.010
(15.265
±0.254)
LONG
LEAD
0.627
0.042
(1.07)
TYP
±0.010
(15.926
±0.254)
SHORT
LEAD
0.710 (18.03)
0.690 (17.53)
1
15
0.080 (2.03)
0.065 (1.65)
2 PLACES
0.176 (4.47)
0.150 (3.81)
0.024 (0.61)
0.014 (0.36)
PIN 1
0.079
(2.007) DIA
2 PLACES
0.700 (17.78) BSC
0.200
(5.08)
BSC
0.169
(4.29)
BSC
0.798 (20.27)
0.778 (19.76)
0.182 (4.62)
0.172 (4.37)
SEATING
PLANE
0.050 (1.27)
BSC
0.031 (0.79)
0.024 (0.60)
–16–
REV. B
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