AD8186ARUZ-R7 [ADI]
450 MHz, Single Supply, Triple 2:1, Buffered (G= +1) Multiplexer;
| 型号： | AD8186ARUZ-R7 |
| 厂家： | 
ADI |
| 描述： | 450 MHz, Single Supply, Triple 2:1, Buffered (G= +1) Multiplexer 光电二极管 |
| 文件： | 总20页 (文件大小：1152K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
480 MHz Single-Supply (5 V)
Triple 2:1 Multiplexers
a
AD8186
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Fully Buffered Inputs and Outputs
Fast Channel-to-Channel Switching: 4 ns
Single-Supply Operation (5 V)
High Speed:
480 MHz Bandwidth (–3 dB) 2 V p-p
>1600 V/ꢀs (G = +1)
1
2
3
4
5
6
7
8
9
24
23
22
21
20
19
18
7
V
IN0A
CC
LOGIC
D
OE
GND
SEL A/B
IN1A
SELECT
V
V
ENABLE
REF
CC
0
IN2A
OUT 0
>1500 V/ꢀs (G = +2)
V
V
EE
CC
Fast Settling Time of 7 ns to 0.1%
Low Current: 19 mA/20 mA
Excellent Video Specifications (RL = 150 ꢁ)
0.05% Differential Gain Error
0.05ꢂ Differential Phase Error
Low Glitch
V
OUT 1
EE
V
IN2B
CC
V
16 OUT 2
EE
IN1B
11
15
14
13
V
EE
V
DV
V
EE
N0B 12
CC
CC
A186/AD8187
All Hostile Crosstalk
–84 dB @ 5 MHz
–52 dB @ 100 MHz
High Off Isolation of –95 dB @ 5 MHz
Low Cost
Fast, High Impedance Disable Feature for Connecting
Multiple Outputs
Logic-Shifted Outputs
able I. Truth Table
EL A/B
OE
OUT
0
1
1
0
0
0
1
1
High Z
High Z
IN A
APPLICATIONS
IN B
Switching RGB in LCD and Plasma Displays
RGB Video Switchers and Routers
4.0
3.5
6.0
5.5
GENERAL DESCRIPTION
The AD8186 (G = +1) and AD8187 (G = 2) are peed,
single-supply, triple 2-to-1 multiplexers. The3 dB le signal
bandwidth of over 480 MHz along with a slew rate in exss of
1500 V/µs. With better than –80 hostile alk and
–95 dB OFF isolation, they ay high speed appli-
cations. The differential gain aase error of 0.05%
and 0.05°, along with 0.1 dB flaMHz, make the
AD8186 and AD81profel and component video
multiplexing. Thetching time, making them an
excellent choice fo signals while consuming less
than 20 mA on a si(100 mW). Both devices have a
high speed disable fesets the outputs into a high
impedance state. This allows the building of larger input arrays
while minimizing OFF channel output loading. The devices are
offered in a 24-lead TSSOP package.
3.0
5.0
4.5
4.0
3.5
3.0
INPUT
2.5
2.0
1.5
1.0
0.5
0
OUTPUT
2.5
2.0
–0.5
–1.0
1.5
1.0
15
20
25
0
5
10
TIME (ns)
Figure 1. AD8187 Video Amplitude Pulse
Response, VOUT = 1.4 V p-p, RL = 150 Ω
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
AD8186
AD8186/AD8187
Typ
Parameter
Conditions
Min
Max
Unit
SWITCHING CHARACTERISTICS
Channel-to-Channel Switching Time
50% Logic to 50% Output
Settling, INA = +1 V, INB = –1 V
50% Logic to 50% Output
Settling, INPUT = 1 V
50% Logic to 50% Output
Settling, INPUT = 1 V
3.6/4
4/3.8
ns
ns
ENABLE to Channel ON Time
DISABLE to Channel OFF Time
17/5
ns
Channel Switching Transient (Glitch)
Output Enable Transient (Glitch)
All Channels Grounded
All Channels Grounded
21/45
64/118
mV
mV
DIGITAL INPUTS
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Input Current
Logic 0 Input Current
SEL A/B, OE Inputs
SEL A/B, OE Inputs
SEL A/B, OE = 2.0 V
SEL A/B, OE = 0.5 V
1.6
V
V
nA
A
0.6
45
2
OPERATING TEMPERATURE RANGE
Temperature Range
Operating (Still Air)
Operating (Still Air)
Operating
–40
+85
ºC
ºC/W
ºC/W
8
20
JA
JC
Specifications subject to change without notice.
REV. A
–3–
AD8186
ABSOLUTE MAXIMUM RATINGS1, 2, 3, 4
2.5
2.0
1.5
1.0
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
DVCC to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
DVCC to VEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0 V
VCC to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0 V
IN0A, IN0B, IN1A, IN1B, IN2A, IN2B, VREF . . . VEE ≤ VIN ≤ VCC
SEL A/B, OE . . . . . . . . . . . . . . . . . . . . . . DGND ≤ VIN ≤ DVCC
Output Short Circuit Operation . . . . . . . . . . . . . . . Indefinite
Storage Temperature Range . . . . . . . . . . . . –65ºC to +150ºC
Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300ºC
NOTES
0.5
0
1 Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the Theory of
Operation section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2 Specification is for device in free air (TA = 25ºC).
–50 –40 –30 –20 –10
0
10 30 40 50 60 70 80 90
AMBIENTPERAT(ꢂC)
3 24-lead TSSOP; TJA= 85ºC/W. Maximum internal power dissipation (PD) should be
Figure 2. Maximum Poer Diation vTemperature
derated for ambient temperature (TA) such that PD < (150ºC TA)/TJA
.
4 TJA of 85ЊC/W is on a 4-layer board (2s 2p).
PIN COIGURATION
MAXIMUM POWER DISSIPATION
The maximum safe junction temperature for plastic encapsulated
devices is determined by the glass transition temperature of the
plastic, approximately 150ºC. Temporarily exceeding this limit
may cause a shift in parametric performance due to a change in
the stresses exerted on the die by the package. Exceeding a
junction temperature of 175ºC for an extended period can result
in device failure.
24
23
22
21
20
19
18
17
1
2
3
5
6
7
8
9
V
CC
IN
OE
GND
SEL A/B
IN1A
V
E
CC
AD8186/
AD8187
I
OUT 0
V
V
EE
CC
TOP VIEW
(Not to Scale)
V
OUT 1
EE
While the AD8186/AD8187 is internally short circuit protect
this may not be sufficient to guarantee that the maximum jun
temperature (150ºC) is not exceeded under all conditio
ensure proper operation, it is necessary to observe the ma
power derating curves shown in Figure 2.
V
IN2B
CC
V
16 OUT 2
EE
15
14
13
V
EE
IN1B 10
11
V
DV
V
EE
IN0B 12
CC
CC
ORERING GUIDE
TemperRange Pacge Description
–40ºC 24-Lead Thin Shrink Small Outline Package (TSSOP) RU-24
Model
Package Option
AD8186ARU
AD8186ARU-REEL –40ºC
AD8186ARU-REEL 7 –40ºC to
13" Reel TSSOP
7" Reel TSSOP
24-Lead Thin Shrink Small Outline Package (TSSOP) RU-24
RU-24
RU-24
AD8187ARU
to +8
AD8187ARU-RE+85ºC
AD8187ARU-RE+85ºC
AD8186-EVAL
13" Reel TSSOP
7" Reel TSSOP
Evaluation Board
Evaluation Board
RU-24
RU-24
AD8187-EVAL
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD8186/AD8187 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
–4–
REV. A
Typical Performance Characteristics–
AD8186
3
2
1
0.5
0.4
0.3
0.2
0.6
0.5
0.4
976ꢁ
DUT
0
50ꢁ
52.3ꢁ
GAIN
1
0
–1
–2
–3
–4
GAIN
0.3
0.2
0.1
0
–1
–2
0.1
0
FLATNESS
–3
–4
–0.1
FLATNESS
1
–5
–6
–0.1
–5
–6
–0.2
–0.3
–0.2
10000.0
0.1
1.0
10.0
100.0
1000.0
10000.0
0.1
1.0
10
1000.0
FREQUENCY (MHz)
QUENCHz)
TPC 1. AD8186 Frequency Response,
OUT = 200 mV p-p, RL = 1 kΩ
TPC 4. AD87 Frency Reonse,
VOUT = 20mV p-p, RL 15Ω
V
1
0
1
0
–1
–2
–3
–4
–5
–6
–
–2
–
–4
150ꢁ
976ꢁ
DUT
1.0
–5
–6
50ꢁ
52.3ꢁ
–7
–8
0.1
10.0
FREQUENCY (MHz)
.0
1000.0
0.1
1.0
10.0
100.0
1000.0
FREQUENCY (MHz)
TPC 2. AD8186 Frequency Response,
TPC 5. AD8187 Frequency Response,
VOUT = 2 V p-p, RL = 1
VOUT = 2 V p-p, RL = 150 Ω
1
1
0
85ꢂC
–40ꢂC
+25ꢂC
0
–1
–2
–3
–4
+25ꢂC
–1
–2
–3
–4
+85ꢂC
–40ꢂC
150ꢁ
976ꢁ
DUT
1.0
–5
–6
–5
–6
50ꢁ
52.3ꢁ
0.1
10.0
FREQUENCY (MHz)
100.0
1000.0
0.1
1.0
10.0
100.0
1000.0
FREQUENCY (MHz)
TPC 3. AD8186 Large Signal Bandwidth vs.
Temperature, VOUT = 2 V p-p, RL = 1 kΩ
TPC 6. AD8187 Large Signal Bandwidth vs.
Temperature, VOUT = 2 V p-p, RL = 150 Ω
REV. A
–5–
AD8186
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–110
0.1
0.1
1
10
100
1000
1.0
100.0
1000.0
FREQUENCY (MHz)
FREQCY (MH
TPC 7. AD8186 All Hostile Crosstalk* vs. Frequency
TPC 10. AD8187 All Hstile stalk* Frequency
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
–10
–20
–3
–40
–50
–60
–70
80
–100
–100
–110
–110
–120
0.1
1.0
10.0
100.0
1000.0
0.1
1.0
10.0
100.0
1000.0
FREQUENCY (MHz)
FREQUENCY (MHz)
TPC 8. AD8186 Adjacent Channel Crosstalvsqucy
TPC 11. AD8187 Adjacent Channel Crosstalk* vs. Frequency
0
–10
–20
–30
–40
–50
–60
–70
–80
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–90
–100
10
FREQUENCY (MHz)
0
100
1000
1
10
100
1000
FREQUENCY (MHz)
TPC 9. AD8186 OFF Isolation* vs. Frequency
TPC 12. AD8187 OFF Isolation* vs. Frequency
*All hostile crosstalk—Drive all INA, listen to output with INB selected.
Adjacent channel crosstalk—Drive one INA, listen to an adjacent output with INB selected.
Off isolation—Drive inputs with OE tied low.
–6–
REV. A
AD8186
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
THIRD
THIRD
SECOND
SECOND
10
FREQUENCY (MHz)
100
1
10
EQUENMHz)
100
1
TPC 13. AD8186 Harmonic Distortion vs. Frequency
TPC 16. AD8187 rmoistortivs. Frequency
V
OUT = 2 V p-p, RL = 150 Ω
V
OUT = 2 V p-p, = 150 Ω
0
–
20
–3
–40
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–PSRR
–PSRR
–50
60
–70
–80
+PSRR
+PSRR
0.01
0.10
1
10
100
0.01
0.10
1
10
FREQUENCY (MHz)
FREQUENCY (MHz)
TPC 14. AD8186 PSRR vs. Frequency, RL = 1Ω
TPC 17. AD8187 PSRR vs. Frequency, RL = 150 Ω
20
18
16
14
20
18
16
14
12
12
10
8
10
8
6
6
4
4
2
0
2
0
0.01
0.10
1
10
100
1000
10000
0.01
0.1
1
10
100
1000
10000
FREQUENCY (MHz)
FREQUENCY (MHz)
TPC 18. AD8187 Input Voltage Noise vs. Frequency
TPC 15. AD8186 Input Voltage Noise vs. Frequency
REV. A
–7–
AD8186
10000
10000
1000
100
1000
100
10
10
1
1
0.1
0.1
0.1
1
10
100
1000
0.1
1.0
0
100.0
1000.0
FREQUENCY (MHz)
FRECY (M
TPC 19. AD8186 Input Impedance vs. Frequency
TPC 22. AD8187 Int Impnce vsrequency
1000
1000
100
10
10
10
1
0.1
0.1
0.1
1
10
100
1000
0.1
1.0
10.0
100.0
1000.0
FREQUENCY (MHz)
FREQUENCY (MHz)
TPC 20. AD8186 Enabled Output Impedanvs. qucy
TPC 23. AD8187 Enabled Output Impedance vs. Frequency
10000
1000
100
10000
1000
100
10
10
1
1
0.1
0.1
0.1
1.0
10.0
100.0
1000.0
0.1
1.0
10.0
100.0
1000.0
FREQUENCY (MHz)
FREQUENCY (MHz)
TPC 21. AD8186 Disabled Output Impedance vs. Frequency
TPC 24. AD8187 Disabled Output Impedance vs. Frequency
–8–
REV. A
AD8186
2.80
2.70
3.30
2.8
2.7
3.2
3.1
INPUT
2.60
2.50
2.40
2.30
2.20
2.10
2.00
2.6
3.0
2.9
2.8
2.7
INPUT
2.5
2.4
2.3
2.2
2.1
2.0
2.80
2.6
2.5
2.4
OUTPUT
OUTPUT
1.90
1.80
1.9
1.8
2.3
2.2
2.30
1
20
25
0
5
10
15
20
25
0
5
1
TIME (ns)
TIME (n
TPC 25. AD8186 Small Signal Pulse Response,
OUT = 200 mV p-p, RL = 1 kΩ
TPC 28. AD818Smagnal Pue Response,
VOUT = 200 mp-p, RL = 0 kΩ
V
3.0
2.5
4.0
6.0
5.5
5.0
4.5
4.0
3.5
INPUT
5.0
4.5
4.0
3.5
3.0
2.0
1.5
1.0
0.5
0
INP
2.5
2.0
1.5
1.
.5
0
3.0
OUTPUT
OUTPUT
2.5
2.0
–0.5
–1.0
–0.5
–1.0
1.5
1.0
15
20
25
0
5
10
0
5
10
15
20
25
TIME (ns)
TIME (ns)
TPC 29. AD8187 Video Amplitude Pulse
Response, VOUT = 1.4 V p-p, RL = 150 kΩ
TPC 26. AD8186 Video Signal Pulse Respon
VOUT = 700 mV p-p, RL =
4.0
3.5
6.0
5.5
4.0
3.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
INP
3.0
2.5
2.0
1.5
1.0
0.5
0
5.0
4.5
3.0
2.5
2.0
1.5
1.0
0.5
0
INPUT
4.0
3.5
3.0
2.5
OUTPUT
OUTPUT
2.0
1.5
1.0
–0.5
–1.0
–0.5
–1.0
0.5
0
–1.5
–2.0
1.5
1.0
–1.5
–2.0
0
5
10
15
20
25
0
5
10
15
20
25
TIME (ns)
TIME (ns)
TPC 30. AD8187 Large Signal Pulse Response,
VOUT = 2 V p-p, RL = 150 kΩ
TPC 27. AD8186 Large Signal Pulse Response,
VOUT = 2 V p-p, RL = 1 kΩ
REV. A
–9–
AD8186
t
t
SETTLED
SETTLED
t
t
0
0
TIME (2ns/DIV)
TIME (/DIV)
TPC 31. AD8186 Settling Time (0.1%),
TPC 34. AD8187 SlinTime (0.1%),
VOUT = 2 V Step, RL = 1 kΩ
VOUT = 2 V Sp, RL = Ω
5.5
5.0
2.3
1.8
2.0
1.5
1.0
0.5
0
6.0
5.5
5.0
4.5
SEL A/B
SEL A/B
1.3
4.5
4.0
3.5
3.0
0.8
4.0
0.3
UTPUT
–0.3
–0.8
–1.3
–1.8
OUTPUT
3.5
3.0
2.5
–0.5
2.5
2.0
–1.5
2
1
1.0
1.5
1.0
–2.0
–2.5
–2.3
–2.8
25
25
0
5
10
15
20
0
5
10
15
20
TIME (ns)
TIME (ns)
TPC 32. AD8186 Channel-to-Channehing
Time, VOUT = 2 V p-p, INA = 3.5 V, INB = 1.5 V
TPC 35. AD8187 Channel-to-Channel Switching
Time, VOUT = 2 V p-p, INA = 3.0 V, INB = 2.0 V
3.0
3.00
2.00
2.0
SEL A/B
SEL A/B
2.90
2.80
1.5
1.0
0.5
0
2.9
2.8
2.7
1.50
1.00
0.50
0
2.70
2.60
2.50
2.40
OUTPUT
2.6
2.5
2.4
OUTPUT
–0.50
–1.00
–0.5
–1.0
20
25
30
35
40
0
5
10
15
45
50
20
25
30
35
40
50
0
5
10
15
45
TIME (ns)
TIME (ns)
TPC 33. AD8186 Channel Switching Transient (Glitch),
INA = INB = 0 V
TPC 36. AD8187 Channel Switching Transient
(Glitch), INA = INB = VREF = 0 V
–10–
REV. A
AD8186
5.5
5.0
4.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
2.0
1.5
2.0
1.5
OE
OE
1.0
0.5
1.0
4.0
0.5
0
0
–0.5
–1.0
OUTPUT
3.5
3.0
2.5
OUTPUT
–0.5
–1.0
–1.5
–1.5
–2.0
2.0
200
200
0
40
TIME –
160
0
40
80
120
TIME (ns)
160
TPC 37. AD8186 Enable ON/OFF Time,
VOUT = 0 V to 1 V
TPC 39. AD87 Ee ON/OF Time,
VOUT = 0 o 1 V
1.5
1.0
3.0
2.9
2.00
3.00
2.90
2.80
2.70
50
1.00
0.50
0
OE
OE
2.8
2.7
2
0.5
2.60
OUTPUT
OUTPUT
–0.50
–1.00
2.50
2.40
0
45
50
0
5
10
15
20
25
30
40
50
0
5
10
15
20
25
30
35
40
45
TIME (ns)
TIME (ns)
TPC 38. AD8186 Channel Enable/Disable
Transient (Glitch)
TPC 40. AD8187 Channel Enable/Disable
Transient (Glitch)
REV. A
–11–
AD8186
THEORY OF OPERATION
The peak slew rate is not the same as the average slew rate. The
average slew rate is typically specified as the ratio
The AD8186 (G = +1) and AD8187 (G = +2) are single-supply,
triple 2:1 multiplexers with TTL compatible global input switch-
ing and output-enable control. Optimized for selecting between
two RGB (red, green, blue) video sources, the devices have high
peak slew rates, maintaining their bandwidth for large signals.
Additionally, the multiplexers are compensated for high phase
margin, minimizing overshoot for good pixel resolution. The
multiplexers also have respectable video specifications and are
superior for switching NTSC or PAL composite signals.
∆VOUT
∆ t
measured between the 20% to 80% output levels of a suffi-
ciently large output pulse. For a natural response, the peak slew
rate may be 2.7 times larger than the average slew rate. There-
fore, calculating a full power bandwidth with a specified average
slew rate will give a pessimistic result. In specifying the large
signal performance of these multiplexers, we’ve published the
large-signal bandwidth, the average slew rate, and the measure-
ments of the total harmonic distorti. (Large signal bandwidth
is defined as the –3 dB point meured oa 2 V p-p output
sine wave.) Specifying these thaspeof the signal path’s
large signal dynamics allowthe upredict stem behavior
for either pulse or sinusowaveform
The multiplexers are organized as three independent channels,
each with two input transconductance stages and one output
transimpedance stage. The appropriate input transconductance
stages are selected via one logic pin (SEL A/B) such that all
three outputs switch input connections simultaneously. The
unused input stages are disabled with a proprietary clamp cir-
cuit to provide excellent crosstalk isolation between “on” and
“off” inputs while protecting the disabled devices from damag-
ing reverse base-emitter voltage stress. No additional input
buffering is necessary, resulting in low input capacitance and
high input impedance without additional signal degradation.
Single-Supply Conserns
DC-Coupled Inputs, IntegraReference Buffers, and
Selecting the REF Level on the 8187, (G = +2)
The AD81and A8187 offer superior large signal dynamics.
The trade-is tthe input and output compliance is limited
to ~1.3 V froher rail hen driving a 150 ⍀ load. These
sections address me allenges of designing video systems
ithin a single 5 V pply.
The transconductance stage, a high slew rate, class AB circuit,
sources signal current into a high impedance node. Each output
stage contains a compensation network and is buffered to the
output by a complementary emitter-follower stage. Voltage
feedback sets the gain, with the AD8186 configured as a unity
gain follower and the AD8187 as a gain-of-two amplifier with a
feedback network. This architecture provides drive for a rever
terminated video load (150 ⍀) with low differential gain a
phase errors while consuming relatively little power. Care
chip layout and biasing result in excellent crosstalk isolati
between channels.
ThAD8186
The 818s internally wired as a unity-gain follower. Its
puts autputs can both swing to within ~1.3 V of either
This affords the user 2.4 V of dynamic range at input and
ut, which should be enough for most video signals, whether
nputs are ac- or dc-coupled. In both cases, the choice of
utput termination voltage will determine the quiescent load
current.
High Impedance, Output Disable Feature, aOff Isolation
The output-enable logic pin (OE) controls ethee ee
outputs are enabled or disabled to a high impedance stat
The high impedance disable allows lmatrices to built
by busing the outputs together. In of the AD8187
(G = +2), a feedback isolation that the
impedance of the gain-of-two feeddoes not load
the output. When not in use, the outbe disabled to
reduce power consump
For improved supply rejection, the VREF pin should be tied to
an ac ground (the more quiet supply is a good bet). Internally,
the VREF pin connects to one terminal of an on-chip capacitor.
The capacitor’s other terminal connects to an internal node.
The consequence of building this bypass capacitor on-chip is
twofold. First, the VREF pin on the AD8186 draws no input bias
current. (Contrast this to the case of the AD8187, where the
VREF pin typically draws 2 µA of input bias current). Second,
on the AD8186, the VREF pin may be tied to any voltage within
the supply range.
The reader may have off isolation performance of
the signal path is depevalue of the load resistor,
RL. For calculating off iignal path may be modeled
as a simple high-pass netwoh an effective capacitance of
3 fF. Off isolation will improve as the load resistance is decreased. In
the case of the AD8186, off isolation is specified with a 1 kΩ
load. However, a practical application would likely gang the
outputs of multiple muxes. In this case, the proper load resistance
for the off isolation calculation is the output impedance of an
enabled AD8186, typically less than a 10th of an ohm.
AD8186
MUX SYSTEM
IN0A
OUT0
IN0B
IN1A
OUT1
IN1B
IN2A
OUT2
IN2B
Full Power Bandwidth vs. –3 dB Large Signal Bandwidth
Note that full power bandwidth for an undistorted sinusoidal signal
is often calculated using the peak slew rate from the equation
“C_BYPASS”
V
REF
INTERNAL CAP
Peak Slew Rate
Full Power Bandwidth =
BIAS REFERENCE
2π × Sinusoid Amplitude
DIRECT CONNECTION TO ANY “QUIET” AC GROUND
(FOR EXAMPLE, GND, V , V
CC EE)
Figure 3. VREF Pin Connection for AD8186 (Differs
from AD8187)
–12–
REV. A
AD8186
The AD8187
3) To maximize the output dynamic range, the reference voltage
should be chosen with some care.
The AD8187 uses on-chip feedback resistors to realize the gain-
of-two function. To provide low crosstalk and a high output
impedance when disabled, each set of 500 Ω feedback resistors is
terminated by a dedicated reference buffer. A reference buffer is
a high speed op amp configured as a unity-gain follower. The
three reference buffers, one for each channel, share a single, high
impedance input, the VREF pin (see Figure 4). VREF input bias
current is typically less than 2 µA.
For example, consider amplifying a 700 mV video signal with a
sync pulse 300 mV below black level. The user might decide to set
VREF at black level to preferentially run video signals on the faster
NPN transistor path. The AD8186 would, in this case, allow a
reference voltage as low as 1.3 V + 300 mV = 1.6 V. If the AD8187
is used, the sync pulse would be amplified to 600 mV. Therefore,
the lower limit on VREF becomes 1.3 V + 600 mV = 1.9 V. For
routing RGB video, an advantageous configuration would be to
employ +3 V and –2 V supplies, in which case VREF could be
tied to ground.
5V
A0
OUT 0
1ꢃ
If system considerations preverunning the multiplexer on split
supplies, a false ground reence suld be employed. A low
impedance reference may ynesized with a second opera-
tional amplifier. Alteately, ll bypaed resistor divider
may serve. Refer to e Applicatioecn for further explana-
tion and more emp
5V
B0
500ꢁ
VFO
5V
GBUF 0
500ꢁ
V
REF
VF-1
5V
5V
GBUF 1
OUT1
OUT2
10kꢁ
500ꢁ 500ꢁ
1
VF-2
5V
GBUF 2
0.022ꢀF
V
REF
100ꢁ
500ꢁ 500ꢁ
OP21
1ꢀF
1ꢀF
Figure 4. Conceptual Diagram of a Single
Multiplexer Channel, G = +2
FROM 1992 ADI AMPLIFIER
APPLICATIONS GUIDE
GND
This configuration has a few implications for singl
operation:
Figure 6a. Synthesis of a False Ground Reference
1) On the AD8187, VREF may not be tied tmost n
analog supply, VEE
.
5V
Limits on Reference Voltage (AD818igure
10kꢁ
VEE +1.3V <VREF <.6V
1.3V <VREF < 3.Supplies
V
REF
5V
1ꢀF
10kꢁ
5V
V
= 3.7V
O_MAX
A0
V
OUT
T 0
V
= 1.3V
CAP MUST BE LARGE
ENOUGHTO ABSORB
TRANSIENT CURRENTS
WITH MINIMUM BOUNCE.
O_MIN
1.3V
GND
Figure 6b. Alternate Method for Synthesis of a
False Ground Reference
5V
5V
V
V
REF
1.6V
1.3V
High Impedance Disable
= 3.4V
= 1.3V
O_MAX
Both the AD8186 and the AD8187 may have their outputs
disabled to a high impedance state. In the case of the AD8187,
the reference buffers also disable to a state of high output
impedance. This feature prevents the feedback network of a
disabled channel from loading the output, which is valuable
when busing together the outputs of several muxes.
V
REF
V
O_MIN
GND
Figure 5. Output Compliance of Main Amplifier
Channel and Ground Buffer
2) Signal at the VREF pin appears at each output. Therefore,
VREF should be tied to a well bypassed, low impedance source.
Using superposition, it is easily shown that
VOUT = 2 ×VIN –VREF
REV. A
–13–
AD8186
AC-Coupled Inputs (DC Restore before Mux Input)
1
2
V
CC
IN0A
24
23
22
21
20
19
18
17
15
Using ac-coupled inputs presents an interesting challenge for video
systems operating from a single 5 V supply. In NTSC and PAL
video systems, 700 mV is the approximate difference between the
maximum signal voltage and black level. It is assumed that sync
has been stripped. However, given the two pathological cases
shown in Figure 7, a dynamic range of twice the maximum signal
swing is required if the inputs are to be ac-coupled. A possible
solution would be to use a dc restore circuit before the mux.
D
OE
GND
3
IN1A
SEL A/B
V
4
V
CC
REF
IN2A
5
OUT 0
6
V
MUX0
MUX1
M
V
CC
EE
WHITE LINEWITH BLACK PIXEL
0.1ꢀF
V
REF
V
7
OUT 1
EE
+700mV
V
1ꢀF
AVG
V
AVG
V
IN2B
8
CC
–700mV
V
REF
BLACK LINEWITHWHITE PIXEL
V
OUT 2
9
EE
+5V
IN1B
11
12
V
V
=V
+V
SIGNAL
EE
INPUT
REF
AVG
IS A DCVOLTAGE
V
~V
REF
V
SIGNAL
V
V
14 DV
REF
SET BYTHE RESISTORS
EE
CC
GND
IN
13
V
CC
Figure 7. Pathological Case for
Input Dynamic Range
Figure 8. tail of imary and Secondary Supplies
Split-Supply Open
Tolerance to Capacitive Load
erating from split supplies (e.g., +3 V/–2 V or 2.5 V) simpli-
fies e selectiof the VREF voltage and load resistor termination
voltagen tcase, it is convenient to tie VREF to ground.
e loginputs are level shifted internally to allow the digital
lies and logic inputs to operate from 0 V and 5 V when
ering the analog circuits from split supplies. The maximum
age difference between DVCC and VEE must not exceed 8 V
(see Figure 9).
Op amps are sensitive to reactive loads. A capacitive load at the
output appears in parallel with an effective resistance of REFF
=
(RLʈrO), where RL is the discrete resistive load, and rO is the ope
loop output impedance, approximately 15 Ω for these mu
The load pole, at fLOAD = 1/(2 REFF CL), can seriously de
phase margin and therefore stability. The old workaround is
place a small series resistance directly at the outt tisolate
load pole. While effective, this ruse also affects tdc and tmina-
tion characteristics of a 75 Ω system. The AD86 AD87
are built with a variable compensation scheme that senses t
output reactance and trades bandwidth ase margn, euring
faster settling and lower overshoot apacitive loads.
SPLIT-SUPPLY OPERATION
ANALOG SUPPLIES
(+2.5)
DIGITAL SUPPLIES
V
CC
DV
(+5)
(0V)
CC
8V MAX
Secondary Supplies and Supply
The high current output transistors ar own supply
pins (Pins 15, 17, 19, areduply noise on-chip
and to improve outpunce thse secondary, high
current supply pins d on-chip to the primary
analog supplies (VCC/9, 11, 13, and 24), some
care should be taken to the supply bypass capacitors
are connected to the correct pins. At a minimum, the primary
supplies should be bypassed. Pin 6 and Pin 7 may be a convenient
place to accomplish this. Stacked power and ground planes could
be a convenient way to bypass the high current supply pins.
D
GND
V
EE
(–2.5)
Figure 9. Split-Supply Operation
–14–
REV. A
AD8186
APPLICATION
Single-Supply Operation
there is still enough dynamic range to handle an ac-coupled,
standard video signal with 700 mV p-p amplitude.
The AD8186/AD8187 are targeted mainly for use in single-
supply 5 V systems. For operating on these supplies, both VEE
and DGND should be tied to ground. The control logic pins will
be referenced to ground. Normally, the DVCC supply should be
set to the same positive supply as the driving logic.
If the input is biased at 2.5 V dc, the input signal can potentially go
700 mV both above and below this point. The resulting 1.8 V and
2.2 V are within the input signal range for single 5 V operation.
Since the part is unity-gain, the outputs will follow the inputs,
and there will be adequate range at the output as well.
For dc-coupled single-supply operation, it is necessary to set an
appropriate input dc level that is within the specified range of the
amplifier. For the unity-gain AD8186, the output dc level will
be the same as the input, while for the gain-of-two AD8187, the
VREF input can be biased to obtain an appropriate output dc level.
When using the gain-of-two AD8187 in a simple ac-coupled
application, there will be a dynamic range limitation at the output
caused by its higher gain. At the output, the gain-of-two will
produce a signal swing of 1.4 V, but the ac coupling will double
this required amount to 2.8 V. Te AD8187 outputs can only
swing from 1.4 V to 3.6 V on a V supply, so there are only
2.2 V of dynamic signal swiavailaat the output.
Figure 10 shows a circuit that provides a gain-of-two and is
dc-coupled. The video input signals must have a dc bias
from their source of approximately 1.5 V. This same volt-
age is applied to VREF of the AD8187. The result is that when
the video signal is at 1.5 V, the output will also be at the
same voltage. This is close to the lower dynamic range of
both the input and the output.
A standard means for reducitdynamirange requirements
of an ac-coupled vidsignal is use a restore. This circuit
works to limit the amic range rements by clamping the
black level of thvidegnal to a fixed level at the input to the
amplifier. Tis prevents e video content of the signal from
varying tblack level as haens in a simple ac-coupled circuit.
When the input goes most positive, which is 700 mV above the
black level for a standard video signal, it reaches a value of 2.2 V
and there is enough headroom for the signal. On the output
side, the magnitude of the signal will change by 1.4 V, which
will make the maximum output voltage 2.2 V + 1.4 V = 3.6 V.
This is just within the dynamic range of the output of the part.
After couplia video signal, it is always necessary to use a
dc resttstablish where the black level is. Usually, this
appears at end ovideo signal chain. This dc restore circuit
needs to havhequired accuracy for the system. It compen-
sates for all the offsets of the preceding stages. Therefore, if a
c restore cuit is to be used only for dynamic-range limiting,
ioes nrequire great dc accuracy.
AC Coupling
When a video signal is ac-coupled, the amount of dynamic ra
required to handle the signal can potentially be dou
required for dc-coupled operation. For the unity-gain
3VTO 5V 5V
DV
V
CC
CCAD8187
IN0A
RE
IN1A
OUT0
GRNA
RED
GRN
BLU
ꢃ2
IN2A
BLUA
3.0V
1.5V
5V
1.4V MAX
2.2V
3.48kꢁ
1.5kꢁ
OUT1
1.5V
ꢃ2
V
REF
BLACK
LEVEL
PICAL INPUT LEVELS
(ALL 6 OUTPUTS)
TYPICAL OUTPUT LEVELS
(ALL 3 OUTPUTS)
IN0B
IN1B
OUT2
OE
REDB
ꢃ2
GRNB
BLUB
IN2B
D
V
SEL A/B
GND
EE
Figure 10. DC-Coupled (Bypassing and Logic Not Shown)
REV. A
–15–
AD8186
A dc restore circuit using the AD8187 is shown in Figure 11.
Two separate sources of RGB video are ac-coupled to the
0.1 µF input capacitors of the AD8187. The input points of
the AD8187 are switched to a 1.5 V reference by the ADG786,
which works in the following manner:
The change in voltage is IBIAS times the line time divided by
the capacitance. With an IBIAS of 2.5 µA, a line time of 30 µs,
and a 0.1 µF coupling capacitor, the amount of droop is
0.75 mV. This is roughly 0.1% of the full video amplitude and
will not be observable in the video display.
The SEL A/B signal selects the A or B inputs to the AD8187. It
also selects the switch positions in the ADG786 such that the
same selected inputs will be connected to VREF when EN is low.
High Speed Design Considerations
The AD8186/AD8187 are extremely high speed switching ampli-
fiers for routing the highest resolution graphic signals. Extra care
is required in the circuit design and layout to ensure that the full
resolution of the video is realized.
During the horizontal interval, all of the RGB input signals are at
a flat black level. A logic signal that is low during HSYNC is
applied to the EN of the ADG786. This closes the switches
and clamps the black level to 1.5 V. At all other times, the switches
are off and the node at the inputs to the AD8187 floats.
First, the board should have at least one layer of a solid ground
plane. Long signal paths should be rerenced to a ground plane
as controlled-impedance traces. Alypass capacitors should be
very close to the pins of the parith absutely minimum extra
circuit length in the path. It is alhelul to have a large VCC
plane on a circuit board laythat is ely spacto the ground
plane. This creates a linductance telane capacitance,
which is very helpful sulying the fasransient currents that
the part demands during higesolution signal transitions.
There are two considerations for sizing the input coupling capaci-
tors. One is the time constant during the H-pulse clamping. The
other is the droop associated with the capacitor discharge due to the
input bias current of the AD8187. For the former, it is better to
have a small capacitor; but for the latter, a larger capacitor is better.
The ON resistance of the ADG786 and the coupling capacitor
forms the time constant of the input clamp. The ADG786 ON
resistance is 5 Ω max. With a 0.1 µF capacitor, a time constant
of 0.5 µs is created. Thus, a sync pulse of greater than 2.5 µs will
cause less than 1% error. This is not critical because the black
level from successive lines is very close and the voltage changes
little from line to line.
Evaluation Brd
An evaluatn board as been designed and is offered for run-
ning the A186D8187 on a single supply. The inputs and
outputs are aupled d terminated with 75 Ω resistors.
For the AD818a pentiometer is provided to allow setting
EF at any value bween VCC and ground.
Thogic contrsignals can be statically set by adding or
remog a jper. If it is required to drive the logic pins
th a fignal, an SMA connector can be used to deliver the
al, and a place for a termination resistor is provided.
A rough approximation for the horizontal line time for a graphics
system is 30 µs. This will vary depending on the resolution a
the vertical rate. The coupling capacitor needs to hold the v
relatively constant during this time while the input bias c
of the AD8187 is discharging it.
5V
3VTO 5V 5V
0.1ꢀF
0.1ꢀF
DV
V
CC
DD
CC
IN0A
IN1A
IN2A
REDA
ADG786
S1A
AD8187
OUT0
GRNA
BLUA
1
RED
GRN
BLU
ꢃ2
ꢃ2
ꢃ2
S1B
0.1ꢀF
V
REF
S2A
S2B
V
OUT1
OUT2
OE
.5V
+
REF
D2
V
REF
0.1ꢀF
0.1ꢀF
IN0B
REDB
10ꢀF 0.1ꢀF
S3A
S3B
D3
IN1B
IN2B
D
GRNB
BLUB
GND
EN
V
SS
0.1ꢀF
V
SEL A/B
LOGIC
A0 A1 A2
GND
EE
HSYNC
2.4V MIN
0.8V MIN
SEL A/B
Figure 11. AD8187 AC-Coupled with DC Restore
–16–
REV. A
AD8186
EVALUATION BOARD
Figure 12. Coonent e Bod Layout
Figure 13. Circuit Side Board Layout
REV. A
–17–
AD8186
Figure 14. Componenide Silkscreen
Figure 15. Circuit Side Silkscreen
–18–
REV. A
AD8186
Figure 16. Single-Supply Evaluation Board
–19–
REV. A
AD8186
OUTLINE DIMENSIONS
24-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-24)
Dimensions shown in millimeters
7.90
7.80
7.70
24
13
12
4.50
4.40
4.30
6.40 BSC
1
PIN 1
0.65
BSC
1.20
MAX
0.15
0.05
5
0.60
0.45
8ꢂ
0ꢂ
0.30
0.19
0.20
0.09
SEATING
PLANE
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MOAD
Revision History
Location
Page
6/03—Data Sheet changed from REV. 0 to REV. A.
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Edits to TPCs 32, 35, and 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
REV. A
–20–
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