AD8186ARU_技术文档

480 MHz Single-Supply (5 V)

Triple 2:1 Multiplexers

a

AD8186/AD8187

FUNCTIONAL BLOCK DIAGRAM

FEATURES

Fully Buffered Inputs and Outputs

Fast Channel-to-Channel Switching: 4 ns

Single-Supply Operation (5 V)

High Speed:

480 MHz Bandwidth (–3 dB) 2 V p-p

>1600 V/ꢀs (G = +1)

1

2

3

4

5

6

7

8

9

24

23

22

21

20

19

18

17

V

IN0A

CC

LOGIC

D

OE

GND

SEL A/B

IN1A

SELECT

V

ENABLE

REF

CC

0

1

2

IN2A

OUT 0

>1500 V/ꢀs (G = +2)

V

EE

CC

Fast Settling Time of 7 ns to 0.1%

Low Current: 19 mA/20 mA

Excellent Video Specifications (R_L= 150 ꢁ)

0.05% Differential Gain Error

0.05ꢂ Differential Phase Error

Low Glitch

V

OUT 1

EE

V

IN2B

CC

V

16 OUT 2

EE

IN1B 10

11

15

14

13

V

EE

V

DV

V

EE

IN0B 12

CC

AD8186/AD8187

All Hostile Crosstalk

–84 dB @ 5 MHz

–52 dB @ 100 MHz

High Off Isolation of –95 dB @ 5 MHz

Low Cost

Fast, High Impedance Disable Feature for Connecting

Multiple Outputs

Logic-Shifted Outputs

Table I. Truth Table

SEL A/B

OE

OUT

0

1

0

1

High Z

IN A

APPLICATIONS

IN B

Switching RGB in LCD and Plasma Displays

RGB Video Switchers and Routers

4.0

3.5

6.0

5.5

GENERAL DESCRIPTION

The AD8186 (G = +1) and AD8187 (G = +2) are high speed,

single-supply, triple 2-to-1 multiplexers. They offer –3 dB large signal

bandwidth of over 480 MHz along with a slew rate in excess of

1500 V/µs. With better than –80 dB of all hostile crosstalk and

–95 dB OFF isolation, they are suited for many high speed appli-

cations. The differential gain and differential phase error of 0.05%

and 0.05°, along with 0.1 dB flatness to 85 MHz, make the

AD8186 and AD8187 ideal for professional and component video

multiplexing. They offer 4 ns switching time, making them an

excellent choice for switching video signals while consuming less

than 20 mA on a single 5 V supply (100 mW). Both devices have a

high speed disable feature that sets the outputs into a high

impedance state. This allows the building of larger input arrays

while minimizing OFF channel output loading. The devices are

offered in a 24-lead TSSOP package.

3.0

5.0

4.5

4.0

3.5

3.0

INPUT

2.5

2.0

1.5

1.0

0.5

0

OUTPUT

2.5

2.0

–0.5

–1.0

1.5

1.0

15

20

25

0

5

10

TIME (ns)

Figure 1. AD8187 Video Amplitude Pulse

Response, V_OUT= 1.4 V p-p, R_L= 150 Ω

REV. A

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat

may result from its use. No license is granted by implication or otherwise

under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

www.analog.com

(T_A= 25ꢂC; AD8186: V_S= 5 V, R_L= 1 kꢁ to 2.5 V; AD8187: V_S= 5 V,

AD8186/AD8187–SPECIFICATIONS ^V_REF= 2.5 V, R_L= 150 ꢁ to 2.5 V; unless otherwise noted.)

AD8186/AD8187

Parameter

Conditions

Min

Typ

Max

Unit

DYNAMIC PERFORMANCE

–3 dB Bandwidth (Small Signal)

–3 dB Bandwidth (Large Signal)

0.1 dB Flatness

Slew Rate (10% to 90% Rise Time)

Settling Time to 0.1%

V_OUT= 200 mV p-p

V_OUT= 2 V p-p

V_OUT= 200 mV p-p

V_OUT= 2 V p-p, R_L= 150 Ω

V_IN= 1 V Step, R_L= 150 Ω

1000/1000

450/480

90/85

1600/1500

6/7.5

MHz

V/␮s

ns

NOISE/DISTORTION PERFORMANCE

Differential Gain

Differential Phase

3.58 MHz, R_L= 150 Ω

5 MHz

100 MHz

5 MHz

f = 100 kHz to 100 MHz

0.05/0.05

–84/–78

–52/–48

–90/–85

–84/–95

7/9

%

Degrees

dB

nV/√Hz

All Hostile Crosstalk

Channel-to-Channel Crosstalk, RTI

OFF Isolation

Voltage Noise, RTI

DC PERFORMANCE

Voltage Gain Error

Voltage Gain Error Matching

V_REFGain Error

No Load

Channel A to Channel B

1 kΩ Load

0.1/0.1

0.04/0.04

0.04

0.2/0.5

Ϯ8.0

0.2/0.2

10/5

1.5/1.5

1.0

Ϯ0.3/0.6

Ϯ0.2/0.2

Ϯ0.6

%

mV

␮V/ºC

␮A

Input Offset Voltage

Ϯ6.5/7.0

T_MINto T_MAX

Channel A to Channel B

Input Offset Voltage Matching

Input Offset Drift

Input Bias Current

Ϯ5.0/5.5

4/4

V_REFBias Current (for AD8187 only)

INPUT CHARACTERISTICS

Input Resistance

Input Capacitance

@100 kHz

1.8/1.3

0.9/1.0

MΩ

pF

Input Voltage Range (About Midsupply) IN0A, IN0B, IN1A, IN1B,

IN2A, IN2B

V_REF

Ϯ1.2/Ϯ1.2

+0.9, –1.2

V

OUTPUT CHARACTERISTICS

Output Voltage Swing

R_L= 1 kΩ

3.1/2.8

2.8/2.5

3.2/3.0

3.0/2.7

85

0.2/0.35

1000/600

1.5/2.0

V p-p

mA

Ω

R_L= 150 Ω

Short Circuit Current

Output Resistance

Enabled @ 100 kHz

Disabled @ 100 kHz

Disabled

kΩ

Output Capacitance

pF

POWER SUPPLY

Operating Range

Power Supply Rejection Ratio

3.5

15

5.5

V

+PSRR, V_CC= 4.5 V to 5.5 V,

V_EE= 0 V

–PSRR, V_EE= –0.5 V to +0.5 V,

V_CC= 5.0 V

All Channels ON

All Channels OFF

–72/–61

dB

–76/–72

18.5/19.5

3.5/4.5

dB

Quiescent Current

21.5/22.5

4.5/5.5

23

mA

T_MINto T_MAX, All Channels ON

–2–

REV. A

AD8186/AD8187

Parameter

Conditions

Min

Typ

Max

Unit

SWITCHING CHARACTERISTICS

Channel-to-Channel Switching Time

50% Logic to 50% Output

Settling, INA = +1 V, INB = –1 V

50% Logic to 50% Output

Settling, INPUT = 1 V

50% Logic to 50% Output

Settling, INPUT = 1 V

3.6/4

4/3.8

ns

ENABLE to Channel ON Time

DISABLE to Channel OFF Time

17/5

ns

Channel Switching Transient (Glitch)

Output Enable Transient (Glitch)

All Channels Grounded

21/45

64/118

mV

DIGITAL INPUTS

Logic 1 Voltage

Logic 0 Voltage

Logic 1 Input Current

Logic 0 Input Current

SEL A/B, OE Inputs

SEL A/B, OE = 2.0 V

SEL A/B, OE = 0.5 V

1.6

V

nA

␮A

0.6

45

2

OPERATING TEMPERATURE RANGE

Temperature Range

Operating (Still Air)

Operating

–40

+85

ºC

ºC/W

␪

85

20

JA

␪

JC

Specifications subject to change without notice.

REV. A

–3–

AD8186/AD8187

ABSOLUTE MAXIMUM RATINGS^{1, 2, 3, 4}

2.5

2.0

1.5

1.0

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V

DV_CCto D_GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V

DV_CCto V_EE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0 V

V_CCto D_GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0 V

IN0A, IN0B, IN1A, IN1B, IN2A, IN2B, V_REF. . . V_EE≤ V_IN≤ V_CC

SEL A/B, OE . . . . . . . . . . . . . . . . . . . . . . D_GND≤ V_IN≤ DV_CC

Output Short Circuit Operation . . . . . . . . . . . . . . . Indefinite

Storage Temperature Range . . . . . . . . . . . . –65ºC to +150ºC

Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300ºC

NOTES

0.5

0

¹Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those indicated in the Theory of

Operation section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

²Specification is for device in free air (T_A= 25ºC).

–50 –40 –30 –20 –10

0

10 20 30 40 50 60 70 80 90

AMBIENTTEMPERATURE (ꢂC)

³24-lead TSSOP; T_JA= 85ºC/W. Maximum internal power dissipation (PD) should be

Figure 2. Maximum Power Dissipation vs. Temperature

derated for ambient temperature (T_A) such that PD < (150ºC T_A)/T_JA

.

⁴T_JAof 85ЊC/W is on a 4-layer board (2s 2p).

PIN CONFIGURATION

MAXIMUM POWER DISSIPATION

The maximum safe junction temperature for plastic encapsulated

devices is determined by the glass transition temperature of the

plastic, approximately 150ºC. Temporarily exceeding this limit

may cause a shift in parametric performance due to a change in

the stresses exerted on the die by the package. Exceeding a

junction temperature of 175ºC for an extended period can result

in device failure.

24

23

22

21

20

19

18

17

1

2

3

4

5

6

7

8

9

V

CC

IN0A

OE

D

GND

SEL A/B

IN1A

V

REF

CC

AD8186/

AD8187

IN2A

OUT 0

V

EE

CC

TOP VIEW

(Not to Scale)

V

OUT 1

EE

While the AD8186/AD8187 is internally short circuit protected,

this may not be sufficient to guarantee that the maximum junction

temperature (150ºC) is not exceeded under all conditions. To

ensure proper operation, it is necessary to observe the maximum

power derating curves shown in Figure 2.

V

IN2B

CC

V

16 OUT 2

EE

15

14

13

V

EE

IN1B 10

11

V

DV

V

EE

IN0B 12

CC

ORDERING GUIDE

Temperature Range Package Description

–40ºC to +85ºC 24-Lead Thin Shrink Small Outline Package (TSSOP) RU-24

Model

Package Option

AD8186ARU

AD8186ARU-REEL –40ºC to +85ºC

AD8186ARU-REEL 7 –40ºC to +85ºC

13" Reel TSSOP

7" Reel TSSOP

24-Lead Thin Shrink Small Outline Package (TSSOP) RU-24

RU-24

AD8187ARU

–40ºC to +85ºC

AD8187ARU-REEL –40ºC to +85ºC

AD8187ARU-REEL 7 –40ºC to +85ºC

AD8186-EVAL

13" Reel TSSOP

7" Reel TSSOP

Evaluation Board

RU-24

AD8187-EVAL

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although the

AD8186/AD8187 features proprietary ESD protection circuitry, permanent damage may occur on

devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are

recommended to avoid performance degradation or loss of functionality.

–4–

REV. A

Typical Performance Characteristics–

AD8186/AD8187

3

2

1

0.5

0.4

0.3

0.2

0.6

0.5

0.4

976ꢁ

DUT

0

50ꢁ

52.3ꢁ

GAIN

1

0

–1

–2

–3

–4

GAIN

0.3

0.2

0.1

0

–1

–2

0.1

0

FLATNESS

–3

–4

–0.1

FLATNESS

10.0

–5

–6

–0.1

–0.2

–5

–6

–0.2

–0.3

0.1

1.0

10.0

100.0

1000.0

10000.0

0.1

1.0

100.0

1000.0

FREQUENCY (MHz)

TPC 1. AD8186 Frequency Response,

_OUT= 200 mV p-p, R_L= 1 kΩ

TPC 4. AD8187 Frequency Response,

V_OUT= 200 mV p-p, R_L= 150 Ω

V

1

0

1

0

–1

–2

–3

–4

–5

–6

–1

–2

–3

–4

150ꢁ

976ꢁ

DUT

1.0

–5

–6

50ꢁ

52.3ꢁ

–7

–8

0.1

10.0

FREQUENCY (MHz)

100.0

1000.0

0.1

1.0

10.0

100.0

1000.0

FREQUENCY (MHz)

TPC 2. AD8186 Frequency Response,

TPC 5. AD8187 Frequency Response,

V_OUT= 2 V p-p, R_L= 1 kΩ

V_OUT= 2 V p-p, R_L= 150 Ω

1

0

+85ꢂC

–40ꢂC

+25ꢂC

0

–1

–2

–3

–4

+25ꢂC

–1

–2

–3

–4

+85ꢂC

–40ꢂC

150ꢁ

976ꢁ

DUT

1.0

–5

–6

–5

–6

50ꢁ

52.3ꢁ

0.1

10.0

FREQUENCY (MHz)

100.0

1000.0

0.1

1.0

10.0

100.0

1000.0

FREQUENCY (MHz)

TPC 3. AD8186 Large Signal Bandwidth vs.

Temperature, V_OUT= 2 V p-p, R_L= 1 kΩ

TPC 6. AD8187 Large Signal Bandwidth vs.

Temperature, V_OUT= 2 V p-p, R_L= 150 Ω

REV. A

–5–

AD8186/AD8187

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–100

–110

0.1

1

10

100

1000

1.0

10.0

100.0

1000.0

FREQUENCY (MHz)

TPC 7. AD8186 All Hostile Crosstalk* vs. Frequency

TPC 10. AD8187 All Hostile Crosstalk* vs. Frequency

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

0.1

1.0

10.0

100.0

1000.0

0.1

1.0

10.0

100.0

1000.0

FREQUENCY (MHz)

TPC 8. AD8186 Adjacent Channel Crosstalk* vs. Frequency

TPC 11. AD8187 Adjacent Channel Crosstalk* vs. Frequency

0

–10

–20

–30

–40

–50

–60

–70

–80

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–90

–100

10

FREQUENCY (MHz)

0

100

1000

1

10

100

1000

FREQUENCY (MHz)

TPC 9. AD8186 OFF Isolation* vs. Frequency

TPC 12. AD8187 OFF Isolation* vs. Frequency

*All hostile crosstalk—Drive all INA, listen to output with INB selected.

Adjacent channel crosstalk—Drive one INA, listen to an adjacent output with INB selected.

Off isolation—Drive inputs with OE tied low.

–6–

REV. A

AD8186/AD8187

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

THIRD

SECOND

10

FREQUENCY (MHz)

100

1

10

FREQUENCY (MHz)

100

1

TPC 13. AD8186 Harmonic Distortion vs. Frequency

TPC 16. AD8187 Harmonic Distortion vs. Frequency

V

_OUT= 2 V p-p, R_L= 150 Ω

V

_OUT= 2 V p-p, R_L= 150 Ω

0

–10

–20

–30

–40

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–PSRR

–50

–60

–70

–80

+PSRR

0.01

0.10

1

10

100

0.01

0.10

1

10

100

FREQUENCY (MHz)

TPC 14. AD8186 PSRR vs. Frequency, R_L= 150 Ω

TPC 17. AD8187 PSRR vs. Frequency, R_L= 150 Ω

20

18

16

14

20

18

16

14

12

10

8

10

8

6

4

2

0

2

0

0.01

0.10

1

10

100

1000

10000

0.01

0.1

1

10

100

1000

10000

FREQUENCY (MHz)

TPC 18. AD8187 Input Voltage Noise vs. Frequency

TPC 15. AD8186 Input Voltage Noise vs. Frequency

REV. A

–7–

AD8186/AD8187

10000

1000

100

1000

100

10

1

0.1

1

10

100

1000

0.1

1.0

10.0

100.0

1000.0

FREQUENCY (MHz)

TPC 19. AD8186 Input Impedance vs. Frequency

TPC 22. AD8187 Input Impedance vs. Frequency

1000

100

10

100

10

1

0.1

1

10

100

1000

0.1

1.0

10.0

100.0

1000.0

FREQUENCY (MHz)

TPC 20. AD8186 Enabled Output Impedance vs. Frequency

TPC 23. AD8187 Enabled Output Impedance vs. Frequency

10000

1000

100

10000

1000

100

10

1

0.1

1.0

10.0

100.0

1000.0

0.1

1.0

10.0

100.0

1000.0

FREQUENCY (MHz)

TPC 21. AD8186 Disabled Output Impedance vs. Frequency

TPC 24. AD8187 Disabled Output Impedance vs. Frequency

–8–

REV. A

AD8186/AD8187

2.80

2.70

3.30

2.8

2.7

3.2

3.1

INPUT

2.60

2.50

2.40

2.30

2.20

2.10

2.00

2.6

3.0

2.9

2.8

2.7

INPUT

2.5

2.4

2.3

2.2

2.1

2.0

2.80

2.6

2.5

2.4

OUTPUT

1.90

1.80

1.9

1.8

2.3

2.2

2.30

15

20

25

0

5

10

15

20

25

0

5

10

TIME (ns)

TPC 25. AD8186 Small Signal Pulse Response,

_OUT= 200 mV p-p, R_L= 1 kΩ

TPC 28. AD8187 Small Signal Pulse Response,

V_OUT= 200 mV p-p, R_L= 150 kΩ

V

3.0

2.5

4.0

6.0

5.5

5.0

4.5

4.0

3.5

3.0

INPUT

5.0

4.5

4.0

3.5

3.0

2.0

1.5

1.0

0.5

0

INPUT

2.5

2.0

1.5

1.0

0.5

0

3.0

OUTPUT

2.5

2.0

1.5

1.0

OUTPUT

2.5

2.0

–0.5

–1.0

–0.5

–1.0

1.5

1.0

15

20

25

0

5

10

0

5

10

15

20

25

TIME (ns)

TPC 29. AD8187 Video Amplitude Pulse

Response, V_OUT= 1.4 V p-p, R_L= 150 kΩ

TPC 26. AD8186 Video Signal Pulse Response,

V_OUT= 700 mV p-p, R_L= 1 kΩ

4.0

3.5

6.0

5.5

4.0

3.5

7.0

6.5

6.0

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

INPUT

3.0

2.5

2.0

1.5

1.0

0.5

0

5.0

4.5

3.0

2.5

2.0

1.5

1.0

0.5

0

INPUT

4.0

3.5

3.0

2.5

OUTPUT

2.0

1.5

1.0

–0.5

–1.0

–0.5

–1.0

0.5

0

–1.5

–2.0

1.5

1.0

–1.5

–2.0

0

5

10

15

20

25

0

5

10

15

20

25

TIME (ns)

TPC 30. AD8187 Large Signal Pulse Response,

V_OUT= 2 V p-p, R_L= 150 kΩ

TPC 27. AD8186 Large Signal Pulse Response,

V_OUT= 2 V p-p, R_L= 1 kΩ

REV. A

–9–

AD8186/AD8187

t

SETTLED

t

0

TIME (2ns/DIV)

TPC 31. AD8186 Settling Time (0.1%),

TPC 34. AD8187 Settling Time (0.1%),

V_OUT= 2 V Step, R_L= 1 kΩ

V_OUT= 2 V Step, R_L= 150 Ω

5.5

5.0

2.3

1.8

2.0

1.5

1.0

0.5

0

6.0

5.5

5.0

4.5

SEL A/B

1.3

4.5

4.0

3.5

3.0

0.8

4.0

0.3

OUTPUT

–0.3

–0.8

–1.3

–1.8

OUTPUT

3.5

3.0

2.5

–0.5

2.5

2.0

–1.0

–1.5

2.0

1.5

1.0

1.5

1.0

–2.0

–2.5

–2.3

–2.8

25

0

5

10

15

20

0

5

10

15

20

TIME (ns)

TPC 32. AD8186 Channel-to-Channel Switching

Time, V_OUT= 2 V p-p, INA = 3.5 V, INB = 1.5 V

TPC 35. AD8187 Channel-to-Channel Switching

Time, V_OUT= 2 V p-p, INA = 3.0 V, INB = 2.0 V

3.0

3.00

2.00

2.0

SEL A/B

2.90

2.80

1.5

1.0

0.5

0

2.9

2.8

2.7

1.50

1.00

0.50

0

2.70

2.60

2.50

2.40

OUTPUT

2.6

2.5

2.4

OUTPUT

–0.50

–1.00

–0.5

–1.0

20

25

30

35

40

0

5

10

15

45

50

20

25

30

35

40

50

0

5

10

15

45

TIME (ns)

TPC 33. AD8186 Channel Switching Transient (Glitch),

INA = INB = 0 V

TPC 36. AD8187 Channel Switching Transient

(Glitch), INA = INB = V_REF= 0 V

–10–

REV. A

AD8186/AD8187

5.5

5.0

4.5

6.0

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

2.0

1.5

OE

1.0

0.5

1.0

4.0

0.5

0

–0.5

–1.0

OUTPUT

3.5

3.0

2.5

OUTPUT

–0.5

–1.0

–1.5

–2.0

2.0

200

0

40

80

120

TIME – ns

160

0

40

80

120

TIME (ns)

160

TPC 37. AD8186 Enable ON/OFF Time,

V_OUT= 0 V to 1 V

TPC 39. AD8187 Enable ON/OFF Time,

V_OUT= 0 V to 1 V

1.5

1.0

3.0

2.9

2.00

3.00

2.90

2.80

2.70

1.50

1.00

0.50

0

OE

2.8

2.7

2.6

2.5

2.4

0.5

2.60

OUTPUT

–0.50

–1.00

2.50

2.40

0

45

50

0

5

10

15

20

25

30

35

40

50

0

5

10

15

20

25

30

35

40

45

TIME (ns)

TPC 38. AD8186 Channel Enable/Disable

Transient (Glitch)

TPC 40. AD8187 Channel Enable/Disable

Transient (Glitch)

REV. A

–11–

AD8186/AD8187

THEORY OF OPERATION

The peak slew rate is not the same as the average slew rate. The

average slew rate is typically specified as the ratio

The AD8186 (G = +1) and AD8187 (G = +2) are single-supply,

triple 2:1 multiplexers with TTL compatible global input switch-

ing and output-enable control. Optimized for selecting between

two RGB (red, green, blue) video sources, the devices have high

peak slew rates, maintaining their bandwidth for large signals.

Additionally, the multiplexers are compensated for high phase

margin, minimizing overshoot for good pixel resolution. The

multiplexers also have respectable video specifications and are

superior for switching NTSC or PAL composite signals.

∆V_OUT

∆ t

measured between the 20% to 80% output levels of a suffi-

ciently large output pulse. For a natural response, the peak slew

rate may be 2.7 times larger than the average slew rate. There-

fore, calculating a full power bandwidth with a specified average

slew rate will give a pessimistic result. In specifying the large

signal performance of these multiplexers, we’ve published the

large-signal bandwidth, the average slew rate, and the measure-

ments of the total harmonic distortion. (Large signal bandwidth

is defined as the –3 dB point measured on a 2 V p-p output

sine wave.) Specifying these three aspects of the signal path’s

large signal dynamics allows the user to predict system behavior

for either pulse or sinusoid waveforms.

The multiplexers are organized as three independent channels,

each with two input transconductance stages and one output

transimpedance stage. The appropriate input transconductance

stages are selected via one logic pin (SEL A/B) such that all

three outputs switch input connections simultaneously. The

unused input stages are disabled with a proprietary clamp cir-

cuit to provide excellent crosstalk isolation between “on” and

“off” inputs while protecting the disabled devices from damag-

ing reverse base-emitter voltage stress. No additional input

buffering is necessary, resulting in low input capacitance and

high input impedance without additional signal degradation.

Single-Supply Considerations

DC-Coupled Inputs, Integrated Reference Buffers, and

Selecting the V_REFLevel on the AD8187, (G = +2)

The AD8186 and AD8187 offer superior large signal dynamics.

The trade-off is that the input and output compliance is limited

to ~1.3 V from either rail when driving a 150 ⍀ load. These

sections address some challenges of designing video systems

within a single 5 V supply.

The transconductance stage, a high slew rate, class AB circuit,

sources signal current into a high impedance node. Each output

stage contains a compensation network and is buffered to the

output by a complementary emitter-follower stage. Voltage

feedback sets the gain, with the AD8186 configured as a unity

gain follower and the AD8187 as a gain-of-two amplifier with a

feedback network. This architecture provides drive for a reverse-

terminated video load (150 ⍀) with low differential gain and

phase errors while consuming relatively little power. Careful

chip layout and biasing result in excellent crosstalk isolation

between channels.

The AD8186

The AD8186 is internally wired as a unity-gain follower. Its

inputs and outputs can both swing to within ~1.3 V of either

rail. This affords the user 2.4 V of dynamic range at input and

output, which should be enough for most video signals, whether

the inputs are ac- or dc-coupled. In both cases, the choice of

output termination voltage will determine the quiescent load

current.

High Impedance, Output Disable Feature, and Off Isolation

The output-enable logic pin (OE) controls whether the three

outputs are enabled or disabled to a high impedance state.

The high impedance disable allows larger matrices to be built

by busing the outputs together. In the case of the AD8187

(G = +2), a feedback isolation scheme is used so that the

impedance of the gain-of-two feedback network does not load

the output. When not in use, the outputs can be disabled to

reduce power consumption.

For improved supply rejection, the V_REFpin should be tied to

an ac ground (the more quiet supply is a good bet). Internally,

the V_REFpin connects to one terminal of an on-chip capacitor.

The capacitor’s other terminal connects to an internal node.

The consequence of building this bypass capacitor on-chip is

twofold. First, the V_REFpin on the AD8186 draws no input bias

current. (Contrast this to the case of the AD8187, where the

V_REFpin typically draws 2 µA of input bias current). Second,

on the AD8186, the V_REFpin may be tied to any voltage within

the supply range.

The reader may have noticed that the off isolation performance of

the signal path is dependent upon the value of the load resistor,

R_L. For calculating off isolation, the signal path may be modeled

as a simple high-pass network with an effective capacitance of

3 fF. Off isolation will improve as the load resistance is decreased. In

the case of the AD8186, off isolation is specified with a 1 kΩ

load. However, a practical application would likely gang the

outputs of multiple muxes. In this case, the proper load resistance

for the off isolation calculation is the output impedance of an

enabled AD8186, typically less than a 10th of an ohm.

AD8186

MUX SYSTEM

IN0A

OUT0

IN0B

IN1A

OUT1

IN1B

IN2A

OUT2

IN2B

Full Power Bandwidth vs. –3 dB Large Signal Bandwidth

Note that full power bandwidth for an undistorted sinusoidal signal

is often calculated using the peak slew rate from the equation

“C_BYPASS”

V

REF

INTERNAL CAP

Peak Slew Rate

Full Power Bandwidth =

BIAS REFERENCE

2π × Sinusoid Amplitude

DIRECT CONNECTION TO ANY “QUIET” AC GROUND

(FOR EXAMPLE, GND, V , V

CC EE)

Figure 3. V_REFPin Connection for AD8186 (Differs

from AD8187)

–12–

REV. A

AD8186/AD8187

The AD8187

3) To maximize the output dynamic range, the reference voltage

should be chosen with some care.

The AD8187 uses on-chip feedback resistors to realize the gain-

of-two function. To provide low crosstalk and a high output

impedance when disabled, each set of 500 Ω feedback resistors is

terminated by a dedicated reference buffer. A reference buffer is

a high speed op amp configured as a unity-gain follower. The

three reference buffers, one for each channel, share a single, high

impedance input, the V_REFpin (see Figure 4). V_REFinput bias

current is typically less than 2 µA.

For example, consider amplifying a 700 mV video signal with a

sync pulse 300 mV below black level. The user might decide to set

V_REFat black level to preferentially run video signals on the faster

NPN transistor path. The AD8186 would, in this case, allow a

reference voltage as low as 1.3 V + 300 mV = 1.6 V. If the AD8187

is used, the sync pulse would be amplified to 600 mV. Therefore,

the lower limit on V_REFbecomes 1.3 V + 600 mV = 1.9 V. For

routing RGB video, an advantageous configuration would be to

employ +3 V and –2 V supplies, in which case V_REFcould be

tied to ground.

5V

A0

OUT 0

1ꢃ

If system considerations prevent running the multiplexer on split

supplies, a false ground reference should be employed. A low

impedance reference may be synthesized with a second opera-

tional amplifier. Alternately, a well bypassed resistor divider

may serve. Refer to the Application section for further explana-

tion and more examples.

5V

B0

500ꢁ

VFO

5V

GBUF 0

500ꢁ

V

REF

VF-1

5V

GBUF 1

OUT1

OUT2

10kꢁ

500ꢁ 500ꢁ

100kꢁ

VF-2

5V

GBUF 2

0.022ꢀF

V

REF

100ꢁ

500ꢁ 500ꢁ

OP21

1ꢀF

Figure 4. Conceptual Diagram of a Single

Multiplexer Channel, G = +2

FROM 1992 ADI AMPLIFIER

APPLICATIONS GUIDE

GND

This configuration has a few implications for single-supply

operation:

Figure 6a. Synthesis of a False Ground Reference

1) On the AD8187, V_REFmay not be tied to the most negative

analog supply, V_EE

.

5V

Limits on Reference Voltage (AD8187, see Figure 5):

10kꢁ

V_EE+1.3V <V_REF<V_CC–1.6V

1.3V <V_REF< 3.4V on 0 V /5 V Supplies

V

REF

5V

1ꢀF

1.3V

10kꢁ

5V

V

= 3.7V

O_MAX

A0

V

OUT

OUT 0

V

= 1.3V

CAP MUST BE LARGE

ENOUGHTO ABSORB

TRANSIENT CURRENTS

WITH MINIMUM BOUNCE.

O_MIN

1.3V

GND

Figure 6b. Alternate Method for Synthesis of a

False Ground Reference

5V

V

REF

1.6V

1.3V

High Impedance Disable

= 3.4V

= 1.3V

O_MAX

Both the AD8186 and the AD8187 may have their outputs

disabled to a high impedance state. In the case of the AD8187,

the reference buffers also disable to a state of high output

impedance. This feature prevents the feedback network of a

disabled channel from loading the output, which is valuable

when busing together the outputs of several muxes.

V

REF

V

O_MIN

GND

Figure 5. Output Compliance of Main Amplifier

Channel and Ground Buffer

2) Signal at the V_REFpin appears at each output. Therefore,

V_REFshould be tied to a well bypassed, low impedance source.

Using superposition, it is easily shown that

V_OUT= 2 ×V_IN–V_REF

REV. A

–13–

AD8186/AD8187

AC-Coupled Inputs (DC Restore before Mux Input)

1

2

V

CC

IN0A

24

23

22

21

20

19

18

17

Using ac-coupled inputs presents an interesting challenge for video

systems operating from a single 5 V supply. In NTSC and PAL

video systems, 700 mV is the approximate difference between the

maximum signal voltage and black level. It is assumed that sync

has been stripped. However, given the two pathological cases

shown in Figure 7, a dynamic range of twice the maximum signal

swing is required if the inputs are to be ac-coupled. A possible

solution would be to use a dc restore circuit before the mux.

D

OE

GND

3

IN1A

SEL A/B

V

4

V

CC

REF

IN2A

5

OUT 0

6

V

MUX0

MUX1

MUX2

V

CC

EE

WHITE LINEWITH BLACK PIXEL

0.1ꢀF

V

REF

V

7

OUT 1

EE

+700mV

V

1ꢀF

AVG

V

AVG

V

IN2B

8

CC

–700mV

V

REF

BLACK LINEWITHWHITE PIXEL

V

9

16 OUT 2

EE

+5V

IN1B

10

11

12

15

V

=V

+V

SIGNAL

EE

INPUT

REF

AVG

IS A DCVOLTAGE

V

~V

REF

V

SIGNAL

V

14 DV

REF

SET BYTHE RESISTORS

EE

CC

GND

IN0B

13

V

CC

Figure 7. Pathological Case for

Input Dynamic Range

Figure 8. Detail of Primary and Secondary Supplies

Split-Supply Operation

Tolerance to Capacitive Load

Operating from split supplies (e.g., +3 V/–2 V or 2.5 V) simpli-

fies the selection of the V_REFvoltage and load resistor termination

voltage. In this case, it is convenient to tie V_REFto ground.

The logic inputs are level shifted internally to allow the digital

supplies and logic inputs to operate from 0 V and 5 V when

powering the analog circuits from split supplies. The maximum

voltage difference between DV_CCand V_EEmust not exceed 8 V

(see Figure 9).

Op amps are sensitive to reactive loads. A capacitive load at the

output appears in parallel with an effective resistance of R_EFF

=

(R_Lʈr_O), where R_Lis the discrete resistive load, and r_Ois the open-

loop output impedance, approximately 15 Ω for these muxes.

The load pole, at f_LOAD= 1/(2␲ R_EFFC_L), can seriously degrade

phase margin and therefore stability. The old workaround is to

place a small series resistance directly at the output to isolate the

load pole. While effective, this ruse also affects the dc and termina-

tion characteristics of a 75 Ω system. The AD8186 and AD8187

are built with a variable compensation scheme that senses the

output reactance and trades bandwidth for phase margin, ensuring

faster settling and lower overshoot at higher capacitive loads.

SPLIT-SUPPLY OPERATION

ANALOG SUPPLIES

(+2.5)

DIGITAL SUPPLIES

V

CC

DV

(+5)

(0V)

CC

8V MAX

Secondary Supplies and Supply Bypassing

The high current output transistors are given their own supply

pins (Pins 15, 17, 19, and 21) to reduce supply noise on-chip

and to improve output isolation. Since these secondary, high

current supply pins are not connected on-chip to the primary

analog supplies (V_CC/V_EE, Pins 6, 7, 9, 11, 13, and 24), some

care should be taken to ensure that the supply bypass capacitors

are connected to the correct pins. At a minimum, the primary

supplies should be bypassed. Pin 6 and Pin 7 may be a convenient

place to accomplish this. Stacked power and ground planes could

be a convenient way to bypass the high current supply pins.

D

GND

V

EE

(–2.5)

Figure 9. Split-Supply Operation

–14–

REV. A

AD8186/AD8187

APPLICATION

Single-Supply Operation

there is still enough dynamic range to handle an ac-coupled,

standard video signal with 700 mV p-p amplitude.

The AD8186/AD8187 are targeted mainly for use in single-

supply 5 V systems. For operating on these supplies, both V_EE

and D_GNDshould be tied to ground. The control logic pins will

be referenced to ground. Normally, the DV_CCsupply should be

set to the same positive supply as the driving logic.

If the input is biased at 2.5 V dc, the input signal can potentially go

700 mV both above and below this point. The resulting 1.8 V and

2.2 V are within the input signal range for single 5 V operation.

Since the part is unity-gain, the outputs will follow the inputs,

and there will be adequate range at the output as well.

For dc-coupled single-supply operation, it is necessary to set an

appropriate input dc level that is within the specified range of the

amplifier. For the unity-gain AD8186, the output dc level will

be the same as the input, while for the gain-of-two AD8187, the

V_REFinput can be biased to obtain an appropriate output dc level.

When using the gain-of-two AD8187 in a simple ac-coupled

application, there will be a dynamic range limitation at the output

caused by its higher gain. At the output, the gain-of-two will

produce a signal swing of 1.4 V, but the ac coupling will double

this required amount to 2.8 V. The AD8187 outputs can only

swing from 1.4 V to 3.6 V on a 5 V supply, so there are only

2.2 V of dynamic signal swing available at the output.

Figure 10 shows a circuit that provides a gain-of-two and is

dc-coupled. The video input signals must have a dc bias

from their source of approximately 1.5 V. This same volt-

age is applied to V_REFof the AD8187. The result is that when

the video signal is at 1.5 V, the output will also be at the

same voltage. This is close to the lower dynamic range of

both the input and the output.

A standard means for reducing the dynamic range requirements

of an ac-coupled video signal is to use a dc restore. This circuit

works to limit the dynamic range requirements by clamping the

black level of the video signal to a fixed level at the input to the

amplifier. This prevents the video content of the signal from

varying the black level as happens in a simple ac-coupled circuit.

When the input goes most positive, which is 700 mV above the

black level for a standard video signal, it reaches a value of 2.2 V

and there is enough headroom for the signal. On the output

side, the magnitude of the signal will change by 1.4 V, which

will make the maximum output voltage 2.2 V + 1.4 V = 3.6 V.

This is just within the dynamic range of the output of the part.

After ac coupling a video signal, it is always necessary to use a

dc restore to establish where the black level is. Usually, this

appears at the end of a video signal chain. This dc restore circuit

needs to have the required accuracy for the system. It compen-

sates for all the offsets of the preceding stages. Therefore, if a

dc restore circuit is to be used only for dynamic-range limiting,

it does not require great dc accuracy.

AC Coupling

When a video signal is ac-coupled, the amount of dynamic range

required to handle the signal can potentially be double that

required for dc-coupled operation. For the unity-gain AD8186,

3VTO 5V 5V

DV

V

CC

^CCAD8187

IN0A

REDA

IN1A

OUT0

GRNA

RED

GRN

BLU

ꢃ2

IN2A

0.7V MAX

BLUA

3.0V

1.5V

5V

1.4V MAX

2.2V

3.48kꢁ

1.5kꢁ

1.5V

OUT1

1.5V

ꢃ2

V

REF

BLACK

LEVEL

BLACK

LEVEL

TYPICAL INPUT LEVELS

(ALL 6 OUTPUTS)

TYPICAL OUTPUT LEVELS

(ALL 3 OUTPUTS)

IN0B

IN1B

OUT2

OE

REDB

ꢃ2

GRNB

BLUB

IN2B

D

V

SEL A/B

GND

EE

Figure 10. DC-Coupled (Bypassing and Logic Not Shown)

REV. A

–15–

AD8186/AD8187

A dc restore circuit using the AD8187 is shown in Figure 11.

Two separate sources of RGB video are ac-coupled to the

0.1 µF input capacitors of the AD8187. The input points of

the AD8187 are switched to a 1.5 V reference by the ADG786,

which works in the following manner:

The change in voltage is I_BIAStimes the line time divided by

the capacitance. With an I_BIASof 2.5 µA, a line time of 30 µs,

and a 0.1 µF coupling capacitor, the amount of droop is

0.75 mV. This is roughly 0.1% of the full video amplitude and

will not be observable in the video display.

The SEL A/B signal selects the A or B inputs to the AD8187. It

also selects the switch positions in the ADG786 such that the

same selected inputs will be connected to V_REFwhen EN is low.

High Speed Design Considerations

The AD8186/AD8187 are extremely high speed switching ampli-

fiers for routing the highest resolution graphic signals. Extra care

is required in the circuit design and layout to ensure that the full

resolution of the video is realized.

During the horizontal interval, all of the RGB input signals are at

a flat black level. A logic signal that is low during HSYNC is

applied to the EN of the ADG786. This closes the switches

and clamps the black level to 1.5 V. At all other times, the switches

are off and the node at the inputs to the AD8187 floats.

First, the board should have at least one layer of a solid ground

plane. Long signal paths should be referenced to a ground plane

as controlled-impedance traces. All bypass capacitors should be

very close to the pins of the part with absolutely minimum extra

circuit length in the path. It is also helpful to have a large V_CC

plane on a circuit board layer that is closely spaced to the ground

plane. This creates a low inductance interplane capacitance,

which is very helpful in supplying the fast transient currents that

the part demands during high resolution signal transitions.

There are two considerations for sizing the input coupling capaci-

tors. One is the time constant during the H-pulse clamping. The

other is the droop associated with the capacitor discharge due to the

input bias current of the AD8187. For the former, it is better to

have a small capacitor; but for the latter, a larger capacitor is better.

The ON resistance of the ADG786 and the coupling capacitor

forms the time constant of the input clamp. The ADG786 ON

resistance is 5 Ω max. With a 0.1 µF capacitor, a time constant

of 0.5 µs is created. Thus, a sync pulse of greater than 2.5 µs will

cause less than 1% error. This is not critical because the black

level from successive lines is very close and the voltage changes

little from line to line.

Evaluation Board

An evaluation board has been designed and is offered for run-

ning the AD8186/AD8187 on a single supply. The inputs and

outputs are ac-coupled and terminated with 75 Ω resistors.

For the AD8187, a potentiometer is provided to allow setting

V_REFat any value between V_CCand ground.

The logic control signals can be statically set by adding or

removing a jumper. If it is required to drive the logic pins

with a fast signal, an SMA connector can be used to deliver the

signal, and a place for a termination resistor is provided.

A rough approximation for the horizontal line time for a graphics

system is 30 µs. This will vary depending on the resolution and

the vertical rate. The coupling capacitor needs to hold the voltage

relatively constant during this time while the input bias current

of the AD8187 is discharging it.

5V

3VTO 5V 5V

V

0.1ꢀF

DV

V

CC

DD

CC

IN0A

IN1A

IN2A

REDA

ADG786

S1A

AD8187

OUT0

GRNA

BLUA

D1

RED

GRN

BLU

ꢃ2

S1B

0.1ꢀF

5V

V

REF

S2A

S2B

3.48kꢁ

1.5kꢁ

V

OUT1

OUT2

OE

1.5V

+

REF

D2

V

REF

0.1ꢀF

IN0B

REDB

10ꢀF 0.1ꢀF

S3A

S3B

D3

IN1B

IN2B

D

GRNB

BLUB

GND

EN

V

SS

0.1ꢀF

V

SEL A/B

LOGIC

A0 A1 A2

GND

EE

HSYNC

2.4V MIN

0.8V MIN

SEL A/B

Figure 11. AD8187 AC-Coupled with DC Restore

–16–

REV. A

AD8186/AD8187

EVALUATION BOARD

Figure 12. Component Side Board Layout

Figure 13. Circuit Side Board Layout

REV. A

–17–

AD8186/AD8187

Figure 14. Component Side Silkscreen

Figure 15. Circuit Side Silkscreen

–18–

REV. A

AD8186/AD8187

Figure 16. Single-Supply Evaluation Board

–19–

REV. A

AD8186/AD8187

OUTLINE DIMENSIONS

24-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-24)

Dimensions shown in millimeters

7.90

7.80

7.70

24

13

12

4.50

4.40

4.30

6.40 BSC

1

PIN 1

0.65

BSC

1.20

MAX

0.15

0.05

0.75

0.60

0.45

8ꢂ

0ꢂ

0.30

0.19

0.20

0.09

SEATING

PLANE

0.10 COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-153AD

Revision History

Location

Page

6/03—Data Sheet changed from REV. 0 to REV. A.

Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Edits to TPCs 32, 35, and 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

REV. A

–20–


型号：	AD8186ARU
厂家：	ADI
描述：	480 MHz Single-Supply (5 V) Triple 2:1 Multiplexers 480 MHz的单电源供电（ 5 V ）三2 ： 1多路复用器复用器
文件：	总20页 (文件大小：469K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD8186ARU [ADI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB