AD8197AASTZ [ADI]
4:1 HDMI/DVI Switch with Equalization; 4 ： 1 HDMI / DVI开关，具有均衡
| 型号： | AD8197AASTZ |
| 厂家： | 
ADI |
| 描述： | 4:1 HDMI/DVI Switch with Equalization |
| 文件： | 总28页 (文件大小：775K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
4:1 HDMI/DVI Switch with Equalization
AD8197A
FUNCTIONAL BLOCK DIAGRAM
FEATURES
4 inputs, 1 output HDMI/DVI link
Enables HDMI 1.3-compliant receiver
Pin-to-pin compatible with the AD8191A
4 TMDS channels per link
RESET
PARALLEL
AD8197A
SERIAL
2
2
Supports 250 Mbps to 2.25 Gbps data rates
Supports 25 MHz to 225 MHz pixel clocks
Equalized inputs for operation with long HDMI cables
(20 meters at 2.25 Gbps)
AVCC
DVCC
AMUXVCC
AVEE
DVEE
I2C_SDA
I2C_SCL
I2C_ADDR[2:0]
CONFIG
CONTROL
LOGIC
3
INTERFACE
VTTI
Fully buffered unidirectional inputs/outputs
Globally switchable, 50 Ω on-chip terminations
Pre-emphasized outputs
Low added jitter
Single-supply operation (3.3 V)
VTTO
4
4
+
IP_A[3:0]
IN_A[3:0]
–
+
4
4
IP_B[3:0]
IN_B[3:0]
4
+
–
OP[3:0]
ON[3:0]
SWITCH
CORE
–
+
4
4
4
IP_C[3:0]
IN_C[3:0]
PE
EQ
–
+
4
4
4 auxiliary channels per link
IP_D[3:0]
IN_D[3:0]
–
Bidirectional unbuffered inputs/outputs
Flexible supply operation (3.3 V to 5 V)
HDCP standard compatible
HIGH SPEED
BUFFERED
VTTI
AUX_A[3:0]
AUX_B[3:0]
AUX_C[3:0]
AUX_D[3:0]
4
4
Allows switching of DDC bus and 2 additional signals
Output disable feature
4
SWITCH
CORE
AUX_COM[3:0]
4
4
Reduced power dissipation
Removable output termination
LOW SPEED UNBUFFERED
BIDIRECTIONAL
Allows building of larger arrays
Figure 1.
2 AD8197A devices support HDMI/DVI dual-link
Standards compatible: HDMI receiver, HDCP, DVI
Serial (I2C slave) and parallel control interface
100-lead, 14 mm × 14 mm LQFP, Pb-free package
TYPICAL APPLICATION
GAME CONSOLE
MEDIA CENTER
SET-TOP BOX
HDTV SET
HDMI
RECEIVER
APPLICATIONS
DVD PLAYER
AD8197A
04:20
Multiple input displays
Projectors
Figure 2. Typical HDTV Application
A/V receivers
Set-top boxes
Advanced television (HDTV) sets
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD8197A is an HDMI™/DVI switch featuring equalized
TMDS® inputs and pre-emphasized TMDS outputs, ideal for
systems with long cable runs. Outputs can be set to a high
impedance state to reduce the power dissipation and/or to allow
the construction of larger arrays using the wire-OR technique.
1. Supports data rates up to 2.25 Gbps, enabling 1080p deep
color (12-bit color) HDMI formats, and greater than
UXGA (1600 × 1200) DVI resolutions.
2. Input cable equalizer enables use of long cables at the input
(more than 20 meters of 24 AWG cable at 2.25 Gbps).
3. Auxiliary switch routes a DDC bus and two additional signals
for a single-chip, HDMI 1.3 receive-compliant solution.
The AD8197A is provided in a 100-lead LQFP, Pb-free, surface-
mount package, specified to operate over the −40°C to +85°C
temperature range.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2007 Analog Devices, Inc. All rights reserved.
AD8197A
TABLE OF CONTENTS
Features .............................................................................................. 1
Read Procedure........................................................................... 16
Switching/Update Delay............................................................ 16
Parallel Control Interface .............................................................. 17
Serial Interface Configuration Registers ..................................... 18
High Speed Device Modes Register......................................... 19
Auxiliary Device Modes Register............................................. 19
Receiver Settings Register ......................................................... 19
Input Termination Pulse Register 1 and Register 2 ............... 19
Receive Equalizer Register 1 and Register 2 ........................... 20
Transmitter Settings Register.................................................... 20
Parallel Interface Configuration Registers .................................. 21
High Speed Device Modes Register......................................... 22
Auxiliary Device Modes Register............................................. 22
Receiver Settings Register ......................................................... 22
Input Termination Pulse Register 1 and Register 2 ............... 22
Receive Equalizer Register 1 and Register 2 ........................... 22
Transmitter Settings Register.................................................... 22
Application Information................................................................ 23
Pinout........................................................................................... 23
Cable Lengths and Equalization............................................... 23
PCB Layout Guidelines.............................................................. 24
Outline Dimensions....................................................................... 28
Ordering Guide .......................................................................... 28
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Typical Application........................................................................... 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
Maximum Power Dissipation ..................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 9
Eye Diagrams ................................................................................ 9
Performance Graphs .................................................................. 11
Theory of Operation ...................................................................... 13
Introduction ................................................................................ 13
Input Channels............................................................................ 13
Output Channels ........................................................................ 13
Auxiliary Switch.......................................................................... 14
Serial Control Interface.................................................................. 15
Reset ............................................................................................. 15
Write Procedure.......................................................................... 15
REVISION HISTORY
11/07—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
AD8197A
SPECIFICATIONS
TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, DVCC = 3.3 V, AMUXVCC = 5 V, AVEE = 0 V, DVEE = 0 V,
differential input swing = 1000 mV, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted.
Table 1.
Parameter
Conditions/Comments
Min
Typ Max
Unit
DYNAMIC PERFORMANCE
Maximum Data Rate (DR) per Channel
Bit Error Rate (BER)
Added Deterministic Jitter
Added Random Jitter
Differential Intrapair Skew
Differential Interpair Skew1
EQUALIZATION PERFORMANCE
Receiver (Highest Setting)2
Transmitter (Highest Setting)3
INPUT CHARACTERISTICS
Input Voltage Swing
NRZ
2.25
Gbps
PRBS 223 − 1
10−9
DR ≤ 2.25 Gbps, PRBS 27 − 1, EQ = 12 dB
25
1
1
ps (p-p)
ps (rms)
ps
At output
At output
40
ps
Boost frequency = 825 MHz
Boost frequency = 825 MHz
12
6
dB
dB
Differential
150
AVCC − 800
1200
AVCC
mV
mV
Input Common-Mode Voltage (VICM
OUTPUT CHARACTERISTICS
High Voltage Level
)
Single-ended high speed channel
Single-ended high speed channel
AVCC − 10
AVCC − 600
75
AVCC + 10
mV
Low Voltage Level
Rise/Fall Time (20% to 80%)
AVCC − 400 mV
135 200
ps
Ω
INPUT TERMINATION
Resistance
Single-ended
50
AUXILIARY CHANNELS
On Resistance, RAUX
On Capacitance, CAUX
Input/Output Voltage Range
POWER SUPPLY
AVCC
100
8
Ω
pF
V
DC bias = 2.5 V, ac voltage = 3.5 V, f = 100 kHz
Operating range
DVEE
3
AMUXVCC
3.6
3.3
V
QUIESCENT CURRENT
AVCC
Outputs disabled
30
52
95
5
40
60
44
66
mA
mA
mA
mA
mA
mA
mA
mA
Outputs enabled, no pre-emphasis
Outputs enabled, maximum pre-emphasis
Input termination on4
Output termination on, no pre-emphasis
Output termination on, maximum pre-emphasis 72
3.2
110 122
VTTI
VTTO
40
40
80
7
54
46
90
8
35
DVCC
AMUXVCC
0.01 0.1
POWER DISSIPATION
Outputs disabled
Outputs enabled, no pre-emphasis
Outputs enabled, maximum pre-emphasis
115
384
704
271 361
574 671
910 1050
mW
mW
mW
TIMING CHARACTERISTICS
Switching/Update Delay
High speed switching register: HS_CH
All other configuration registers
200
1.5
ms
ms
ns
RESET Pulse Width
50
Rev. 0 | Page 3 of 28
AD8197A
Parameter
Conditions/Comments
Min
2
Typ Max
Unit
SERIAL CONTROL INTERFACE5
Input High Voltage, VIH
Input Low Voltage, VIL
Output High Voltage, VOH
Output Low Voltage, VOL
PARALLEL CONTROL INTERFACE
Input High Voltage, VIH
Input Low Voltage, VIL
V
V
V
V
0.8
0.4
2.4
2
V
V
0.8
1 Differential interpair skew is measured between the TMDS pairs of a single link.
2 AD8197A output meets the transmitter eye diagram as defined in the DVI Standard Revision 1.0 and the HDMI Standard Revision 1.3.
3 Cable output meets the receiver eye diagram mask as defined in the DVI Standard Revision 1.0 and the HDMI Standard Revision 1.3.
4 Typical value assumes only the selected HDMI/DVI link is active with nominal signal swings and that the unselected HDMI/DVI links are deactivated. Minimum and
maximum limits are measured at the respective extremes of input termination resistance and input voltage swing.
5 The AD8197A is an I2C slave and its serial control interface is based on the 3.3 V I2C bus specification.
Rev. 0 | Page 4 of 28
AD8197A
ABSOLUTE MAXIMUM RATINGS
Table 2.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions: a device soldered
in a 4-layer JEDEC circuit board for surface-mount packages.
θJC is specified for no airflow.
Parameter
AVCC to AVEE
DVCC to DVEE
DVEE to AVEE
VTTI
Rating
3.7 V
3.7 V
0.3 V
Table 3. Thermal Resistance
AVCC + 0.6 V
AVCC + 0.6 V
5.5 V
Package Type
θJA
θJC
Unit
VTTO
AMUXVCC
100-Lead LQFP
56
19
°C/W
Internal Power Dissipation 2.2 W
High Speed Input Voltage AVCC − 1.4V <VIN < AVCC + 0.6 V
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the AD8197A
is limited by the associated rise in junction temperature. The
maximum safe junction temperature for plastic encapsulated
devices is determined by the glass transition temperature of the
plastic, approximately 150°C. Temporarily exceeding this limit
may cause a shift in parametric performance due to a change in
the stresses exerted on the die by the package.
High Speed Differential
Input Voltage
Low Speed Input Voltage
I2C and Parallel Logic
Input Voltage
Storage Temperature
Range
Operating Temperature
Range
Junction Temperature
2.0 V
DVEE − 0.3 V <VIN < AMUXVCC + 0.6 V
DVEE − 0.3 V < VIN < DVCC + 0.6 V
−65°C to +125°C
−40°C to +85°C
150°C
Exceeding a junction temperature of 175°C for an extended
period can result in device failure. To ensure proper operation, it
is necessary to observe the maximum power rating as determined
by the coefficients in Table 3.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. 0 | Page 5 of 28
AD8197A
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
AVCC
IP_C3
IN_C3
AVEE
IP_C2
IN_C2
VTTI
AVCC
PIN 1 INDICATOR
2
IN_B0
3
4
IP_B0
AVEE
IN_B1
IP_B1
VTTI
5
6
7
8
IN_B2
IP_B2
AVEE
IN_B3
IP_B3
AVCC
IN_A0
IP_A0
AVEE
IN_A1
IP_A1
VTTI
IP_C1
IN_C1
AVEE
IP_C0
IN_C0
AVCC
IP_D3
IN_D3
AVEE
IP_D2
IN_D2
VTTI
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
AD8197A
TOP VIEW
(Not to Scale)
IN_A2
IP_A2
AVCC
IN_A3
IP_A3
AVEE
IP_D1
IN_D1
AVCC
IP_D0
IN_D0
AVEE
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Type1
Power
HS I
HS I
Power
HS I
HS I
Power
HS I
HS I
HS I
HS I
HS I
HS I
HS I
HS I
HS I
HS I
HS I
Description
Positive Analog Supply. 3.3 V nominal.
1, 13, 22, 54, 63, 75
2
3
AVCC
IN_B0
IP_B0
AVEE
High Speed Input Complement.
High Speed Input.
Negative Analog Supply. 0 V nominal.
High Speed Input Complement.
High Speed Input.
Input Termination Supply. Nominally connected to AVCC.
High Speed Input Complement.
High Speed Input.
High Speed Input Complement.
High Speed Input.
High Speed Input Complement.
High Speed Input.
High Speed Input Complement.
High Speed Input.
High Speed Input Complement.
High Speed Input.
High Speed Input Complement.
4, 10, 16, 25, 51, 60, 66, 72
5
6
IN_B1
IP_B1
VTTI
7, 19, 57, 69
8
9
IN_B2
IP_B2
IN_B3
IP_B3
IN_A0
IP_A0
IN_A1
IP_A1
IN_A2
IP_A2
IN_A3
11
12
14
15
17
18
20
21
23
Rev. 0 | Page 6 of 28
AD8197A
Pin No.
24
26
27
28
29, 95
30
31
32, 38, 47
33
34
Mnemonic
IP_A3
I2C_ADDR0
I2C_ADDR1
I2C_ADDR2
DVEE
PP_CH0
PP_CH1
DVCC
Type1
HS I
Description
High Speed Input.
I2C Address 1st LSB.
I2C Address 2nd LSB.
I2C Address 3rd LSB.
Negative Digital and Auxiliary Multiplexer Power Supply. 0 V nominal.
High Speed Source Selection Parallel Interface LSB.
High Speed Source Selection Parallel Interface MSB.
Positive Digital Power Supply. 3.3 V nominal.
High Speed Output Complement.
High Speed Output.
Control
Control
Control
Power
Control
Control
Power
HS O
ON0
OP0
HS O
35, 41
36
37
VTTO
ON1
OP1
Power
HS O
HS O
Output Termination Supply. Nominally connected to AVCC.
High Speed Output Complement.
High Speed Output.
39
40
ON2
OP2
HS O
HS O
High Speed Output Complement.
High Speed Output.
42
43
ON3
OP3
HS O
HS O
High Speed Output Complement.
High Speed Output.
44
45
46
48
49
50
52
53
RESET
Control
Control
Control
Control
Control
Control
HS I
Configuration Registers Reset. Normally pulled up to AVCC.
High Speed Pre-Emphasis Selection Parallel Interface LSB.
High Speed Pre-Emphasis Selection Parallel Interface MSB.
High Speed Output Current Level Parallel Interface.
I2C Clock.
PP_PRE0
PP_PRE1
PP_OCL
I2C_SCL
I2C_SDA
IN_D0
I2C Data.
High Speed Input Complement.
High Speed Input.
IP_D0
HS I
55
56
IN_D1
IP_D1
HS I
HS I
High Speed Input Complement.
High Speed Input.
58
59
IN_D2
IP_D2
HS I
HS I
High Speed Input Complement.
High Speed Input.
61
62
IN_D3
IP_D3
HS I
HS I
High Speed Input Complement.
High Speed Input.
64
65
IN_C0
IP_C0
HS I
HS I
High Speed Input Complement.
High Speed Input.
67
68
IN_C1
IP_C1
HS I
HS I
High Speed Input Complement.
High Speed Input.
70
71
IN_C2
IP_C2
HS I
HS I
High Speed Input Complement.
High Speed Input.
73
74
IN_C3
IP_C3
HS I
HS I
High Speed Input Complement.
High Speed Input.
76
77
78
79
80
81
82
83
84
85
86
87
88
89
PP_EN
PP_EQ
AUX_D3
AUX_D2
AUX_D1
AUX_D0
AMUXVCC
AUX_C3
AUX_C2
AUX_C1
AUX_C0
AUX_COM3
AUX_COM2
AUX_COM1
Control
Control
LS I/O
LS I/O
LS I/O
LS I/O
Power
LS I/O
LS I/O
LS I/O
LS I/O
LS I/O
LS I/O
LS I/O
High Speed Output Enable Parallel Interface.
High Speed Equalization Selection Parallel Interface.
Low Speed Input/Output.
Low Speed Input/Output.
Low Speed Input/Output.
Low Speed Input/Output.
Positive Auxiliary Multiplexer Supply. 5 V typical.
Low Speed Input/Output.
Low Speed Input/Output.
Low Speed Input/Output.
Low Speed Input/Output.
Low Speed Common Input/Output.
Low Speed Common Input/Output.
Low Speed Common Input/Output.
Rev. 0 | Page 7 of 28
AD8197A
Pin No.
90
91
92
93
94
96
97
98
Mnemonic
AUX_COM0
AUX_B3
AUX_B2
AUX_B1
AUX_B0
AUX_A3
AUX_A2
AUX_A1
AUX_A0
PP_OTO
Type1
LS I/O
LS I/O
LS I/O
LS I/O
LS I/O
LS I/O
LS I/O
LS I/O
LS I/O
Control
Description
Low Speed Common Input/Output.
Low Speed Input/Output.
Low Speed Input/Output.
Low Speed Input/Output.
Low Speed Input/Output.
Low Speed Input/Output.
Low Speed Input/Output.
Low Speed Input/Output.
99
100
Low Speed Input/Output.
High Speed Output Termination Selection Parallel Interface.
1 HS = high speed, LS = low speed, I = input, O = output.
Rev. 0 | Page 8 of 28
AD8197A
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, DVCC = 3.3 V, AMUXVCC = 5 V, AVEE = 0 V, DVEE = 0 V, differential input
swing = 1000 mV, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, pattern = PRBS 27 − 1, data rate = 2.25 Gbps, unless
otherwise noted.
EYE DIAGRAMS
HDMI CABLE
AD8197A
DIGITAL
PATTERN
GENERATOR
SERIAL DATA
ANALYZER
EVALUATION
BOARD
SMA COAX CABLE
REFERENCE EYE DIAGRAM AT TP1
TP1
TP2
TP3
Figure 4. Test Circuit Diagram for Rx Eye Diagram
0.125UI/DIV AT 2.25Gbps
0.125UI/DIV AT 2.25Gbps
Figure 5. Rx Eye Diagram at TP2 (Cable = 2 meters, 30 AWG)
Figure 7. Rx Eye Diagram at TP3, EQ = 6 dB (Cable = 2 meters, 30 AWG)
0.125UI/DIV AT 2.25Gbps
0.125UI/DIV AT 2.25Gbps
Figure 6. Rx Eye Diagram at TP2 (Cable = 20 meters, 24 AWG)
Figure 8. Rx Eye Diagram at TP3, EQ = 12 dB (Cable = 20 meters, 24 AWG)
Rev. 0 | Page 9 of 28
AD8197A
HDMI CABLE
AD8197A
SERIAL DATA
ANALYZER
DIGITAL
PATTERN
GENERATOR
EVALUATION
BOARD
SMA COAX CABLE
REFERENCE EYE DIAGRAM AT TP1
TP1
TP2
TP3
Figure 9. Test Circuit Diagram for Tx Eye Diagrams
0.125UI/DIV AT 2.25Gbps
0.125UI/DIV AT 2.25Gbps
Figure 10. Tx Eye Diagram at TP2, PE = 2 dB
Figure 12. Tx Eye Diagram at TP3, PE = 2 dB (Cable = 2 meters, 30 AWG)
0.125UI/DIV AT 2.25Gbps
0.125UI/DIV AT 2.25Gbps
Figure 11. Tx Eye Diagram at TP2, PE = 6 dB
Figure 13. Tx Diagram at TP3, PE = 6 dB (Cable = 10 meters, 28 AWG)
Rev. 0 | Page 10 of 28
AD8197A
PERFORMANCE GRAPHS
0.6
0.6
0.5
0.4
0.3
0.2
0.1
0
2m CABLE = 30AWG
5m TO 20m CABLES = 24AWG
2m CABLE = 30AWG
5m TO 20m CABLES = 24AWG
0.5
0.4
2.25Gbps
1.65Gbps, PE OFF
EQ = 12dB
0.3
1.65Gbps
EQ = 6dB
2.25Gbps, PE OFF
2.25Gbps, PE MAX
2.25Gbps
0.2
1.65Gbps
EQ = 12dB
EQ = 6dB
0.1
1.65Gbps, PE MAX
15 20
0
0
5
10
15
20
25
0
5
10
HDMI CABLE LENGTH (m)
HDMI CABLE LENGTH (m)
Figure 14. Jitter vs. Input Cable Length (See Figure 4 for Test Setup)
Figure 17. Jitter vs. Output Cable Length (See Figure 9 for Test Setup)
50
45
40
1200
1000
800
600
400
200
0
35
1080p
8-BIT
30
25
20
15
10
5
1080p
12-BIT
1.65Gbps
480p
480i
1080i/720p
DJ (p-p)
RJ (rms)
0
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
DATA RATE (Gbps)
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
DATA RATE (Gbps)
Figure 15. Jitter vs. Data Rate
Figure 18. Eye Height vs. Data Rate
50
800
700
600
500
400
300
200
100
0
45
40
35
30
25
20
15
10
5
DJ (p-p)
RJ (rms)
0
3.0
3.1
3.2
3.3
3.4
3.5
3.6
2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 16. Jitter vs. Supply Voltage
Figure 19. Eye Height vs. Supply Voltage
Rev. 0 | Page 11 of 28
AD8197A
50
40
30
20
10
50
40
30
20
10
0
DJ (p-p)
DJ (p-p)
RJ (rms)
3.1
RJ (rms)
0.8
0
0
0.2
0.4
0.6
1.0
1.2
1.4
1.6
1.8
2.0
100
100
2.5
2.7
2.9
3.3
3.5
3.7
DIFFERENTIAL INPUT SWING (V)
INPUT COMMON-MODE VOLTAGE (V)
Figure 20. Jitter vs. Differential Input Swing
Figure 23. Jitter vs. Input Common-Mode Voltage
50
45
40
35
30
25
20
15
10
5
120
115
110
105
100
95
DJ (p-p)
90
85
RJ (rms)
0
–40
80
–40
–20
0
20
40
60
80
–20
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 21. Jitter vs. Temperature
Figure 24. Differential Input Termination Resistance vs. Temperature
160
140
120
100
80
FALL TIME
RISE TIME
60
40
20
0
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 22. Rise and Fall Time vs. Temperature
Rev. 0 | Page 12 of 28
AD8197A
THEORY OF OPERATION
VTTI
INTRODUCTION
The AD8197A is a pin-to-pin HDMI 1.3 receive-compliant
replacement for the AD8191A. The primary function of the
AD8197A is to switch one of four (HDMI or DVI) single-link
sources to one output. Each HDMI/DVI link consists of four
differential, high speed channels and four auxiliary single-
ended, low speed control signals. The high speed channels
include a data-word clock and three transition minimized
differential signaling (TMDS) data channels running at 10×
the data-word clock frequency for data rates up to 2.25 Gbps.
The four low speed control signals are 5 V tolerant bidirectional
lines that can carry configuration signals, HDCP encryption,
and other information, depending upon the specific application.
50Ω
50Ω
IP_xx
IN_xx
CABLE
EQ
AVEE
Figure 25. High Speed Input Simplified Schematic
The input equalizer can be manually configured to provide two
different levels of high frequency boost: 6 dB or 12 dB. The user
can individually control the equalization level of the eight high
speed input channels by selectively programming the associated
RX_EQ bits in the receive equalizer register through the serial
control interface. Alternately, the user can globally control the
equalization level of all eight high speed input channels by set-
ting the PP_EQ pin of the parallel control interface. No specific
cable length is suggested for a particular equalization setting
because cable performance varies widely between manufacturers;
however, in general, the equalization of the AD8197A can be set
to 12 dB without degrading the signal integrity, even for short
input cables. At the 12 dB setting, the AD8197A can equalize
more than 20 meters of 24 AWG cable at 2.25 Gbps.
All four high speed TMDS channels in a given link are identical;
that is, the pixel clock can be run on any of the four TMDS chan-
nels. Transmit and receive channel compensation is provided
for the high speed channels where the user can (manually)
select among a number of fixed settings.
The AD8197A has two control interfaces. Users have the option
of controlling the part through either the parallel control interface
or the I2C® serial control interface. The AD8197A has eight
user-programmable I2C slave addresses to allow multiple
2
RESET
AD8197A devices to be controlled by a single I C bus. A
pin is provided to restore the control registers of the AD8197A
to default values. In all cases, serial programming values
override any prior parallel programming values and any use of
the serial control interface disables the parallel control interface
until the AD8197A is reset.
OUTPUT CHANNELS
Each high speed output differential pair is terminated to the
3.3 V VTTO power supply through two 50 Ω on-chip resistors
(see Figure 26). This termination is user-selectable; it can be
turned on or off by programming the TX_PTO bit of the
transmitter settings register through the serial control interface,
or by setting the PP_OTO pin of the parallel control interface.
INPUT CHANNELS
Each high speed input differential pair terminates to the 3.3 V
VTTI power supply through a pair of single-ended 50 Ω on-
chip resistors, as shown in Figure 25. The input terminations
can be optionally disconnected for approximately 100 ms
following a source switch. The user can program which of the
16 high speed input channels employs this feature by selectively
programming the associated RX_PT bits in the input termination
pulse registers through the serial control interface. Additionally,
all the input terminations can be disconnected by programming
the RX_TO bit in the receiver settings register. By default, the
input termination is enabled. The input terminations are enabled
and cannot be switched when programming the AD8197A
through the parallel control interface.
The output termination resistors of the AD8197A back-terminate
the output TMDS transmission lines. These back-terminations,
as recommended in the HDMI 1.3 specification, act to absorb
reflections from impedance discontinuities on the output traces,
improving the signal integrity of the output traces and adding
flexibility to how the output traces can be routed. For example,
interlayer vias can be used to route the AD8197A TMDS outputs
on multiple layers of the PCB without severely degrading the
quality of the output signal.
The AD8197A output has a disable feature that places the out-
puts in a tristate mode. This mode is enabled by programming
the HS_EN bit of the high speed device modes register through
the serial control interface or by setting the PP_EN pin of the
parallel control interface. Larger wire-OR’ed arrays can be
constructed using the AD8197A in this mode.
Rev. 0 | Page 13 of 28
AD8197A
VTTO
When turning off the AD8197A, care needs to be taken with
the AMUXVCC supply to ensure that the auxiliary multiplexer
pins remain in a high impedance state. A scenario that illustrates
this requirement is one where the auxiliary multiplexer is used
to switch the display data channel (DDC) bus. In some applica-
tions, additional devices can be connected to the DDC bus
(such as an EEPROM with EDID information) upstream of
the AD8197A. Extended display identification data (EDID) is a
VESA standard-defined data format for conveying display
configuration information to sources to optimize display use.
EDID devices may need to be available via the DDC bus,
regardless of the state of the AD8197A and any downstream
circuit. For this configuration, the auxiliary inputs of the
powered down AD8197A need to be in a high impedance state
to avoid pulling down on the DDC lines and preventing these
other devices from using the bus.
50Ω
50Ω
OPx
ONx
DISABLE
AVEE
I
OUT
Figure 26. High Speed Output Simplified Schematic
The AD8197A requires output termination resistors when the
high speed outputs are enabled. Termination can be internal
and/or external. The internal terminations of the AD8197A are
enabled by programming the TX_PTO bit of the transmitter
settings register or by setting the PP_OTO pin of the parallel
control interface. The internal terminations of the AD8197A
default to the setting indicated by PP_OTO upon reset. External
terminations can be provided either by on-board resistors or by
the input termination resistors of an HDMI/DVI receiver. If
both the internal terminations are enabled and external termi-
nations are present, set the output current level to 20 mA by
programming the TX_OCL bit of the transmitter settings
register through the serial control interface or by setting the
PP_OCL pin of the parallel control interface. The output
current level defaults to the level indicated by PP_OCL upon
reset. If only external terminations are provided (if the internal
terminations are disabled), set the output current level to 10 mA
by programming the TX_OCL bit of the transmitter settings
register or by setting the PP_OCL pin of the parallel control
interface. The high speed outputs must be disabled if there are
no output termination resistors present in the system.
The AD8197A requires 5 V on its supply pin, AMUXVCC, in
order for the AUXMUX channels to be high impedance. When
a TV is turned off, it cannot provide such a supply; however, it
can be provided from any HDMI source that is plugged into it.
A Schottky diode network, as shown in Figure 28, uses the 5 V
supply (Pin 18) from any HDMI/DVI source to power
AMUXVCC and guarantee high impedance of the auxiliary
multiplexer pins. The AMUXVCC supply does not draw any
significant static current. The use of diodes ensures that
connected HDMI sources do not load this circuit if their 5 V
pin is low impedance when turned off. The 100 kΩ resistor
ensures that a minimum of current flows through the diodes to
keep them forward biased.
This precaution does not need to be taken if the DDC periph-
eral circuitry is connected to the bus downstream of the
AD8197A.
The output pre-emphasis can be manually configured to provide
one of four different levels of high frequency boost. The specific
boost level is selected by programming the TX_PE bits of the
transmitter settings register through the serial control interface,
or by setting the PP_PE bus of the parallel control interface. No
specific cable length is suggested for a particular pre-emphasis
setting because cable performance varies widely between
manufacturers.
+5V INTERNAL
(IF ANY)
PIN 18 HDMI CONNECTOR
PIN 14 DVI CONNECTOR
PIN 18 HDMI CONNECTOR
PIN 14 DVI CONNECTOR
BAT54L BAT54L
BAT54L
SOURCE A +5V
+5V SOURCE C
I<50mA
I<50mA
AMUXVCC
PERIPHERAL
CIRCUITRY
PERIPHERAL
CIRCUITRY
AD8197A
AUXILIARY SWITCH
PERIPHERAL
CIRCUITRY
PERIPHERAL
CIRCUITRY
The auxiliary (low speed) lines have no amplification. They are
routed using a passive switch that is bandwidth compatible with
the standard speed I2C. The schematic equivalent for this
passive connection is shown in Figure 27.
I<50mA
I<50mA
100kΩ
SOURCE B +5V
+5V SOURCE D
BAT54L
BAT54L
R
PIN 18 HDMI CONNECTOR
PIN 14 DVI CONNECTOR
PIN 18 HDMI CONNECTOR
PIN 14 DVI CONNECTOR
AUX
AUX_A0
½C
AUX_COM0
½C
AUX
AUX
Figure 28. Suggested AMUXVCC Power Scheme
Figure 27. Auxiliary Channel Simplified Schematic,
AUX_A0 to AUX_COM0 Routing Example
Rev. 0 | Page 14 of 28
AD8197A
SERIAL CONTROL INTERFACE
3. Send the write indicator bit (0).
RESET
4. Wait for the AD8197A to acknowledge the request.
5. Send the register address (eight bits) to which data is to be
written. This transfer should be MSB first.
6. Wait for the AD8197A to acknowledge the request.
7. Send the data (eight bits) to be written to the register
whose address was set in Step 5. This transfer should be
MSB first.
On initial power-up, or at any point in operation, the AD8197A
register set can be restored to preprogrammed default values by
RESET
pulling the
pin low in accordance with the specifications
RESET
in Table 1. During normal operation, however, the
pin
must be pulled up to 3.3 V. Following a reset, the preprogrammed
default values of the AD8197A register set correspond to the
state of the parallel interface configuration registers, as listed
in Table 18. The AD8197A can be controlled through the
parallel control interface until the first serial control event
occurs. As soon as any serial control event occurs, the serial
programming values, corresponding to the state of the serial
interface configuration registers (see Table 5), override any
prior parallel programming values, and the parallel control
interface is disabled until the part is subsequently reset.
8. Wait for the AD8197A to acknowledge the request.
9. Perform one of the following:
9a. Send a stop condition (while holding the I2C_SCL
line high, pull the I2C_SDA line high) and release
control of the bus to end the transaction (shown in
Figure 29).
9b. Send a repeated start condition (while holding the
I2C_SCL line high, pull the I2C_SDA line low) and
continue with Step 2 in this procedure to perform
another write.
9c. Send a repeated start condition (while holding the
I2C_SCL line high, pull the I2C_SDA line low) and
continue with Step 2 of the read procedure (in the
Read Procedure section) to perform a read from
another address.
WRITE PROCEDURE
To write data to the AD8197A register set, an I2C master (such
as a microcontroller) needs to send the appropriate control
signals to the AD8197A slave device. The signals are controlled
by the I2C master, unless otherwise specified. For a diagram of
the procedure, see Figure 29. The steps for a write procedure are
as follows:
9d. Send a repeated start condition (while holding the
I2C_SCL line high, pull the I2C_SDA line low) and
continue with Step 8 of the read procedure (in the
Read Procedure section) to perform a read from the
same address set in Step 5.
1. Send a start condition (while holding the I2C_SCL line
high, pull the I2C_SDA line low).
2. Send the AD8197A part address (seven bits). The upper
four bits of the AD8197A part address are the static value
[1001] and the three LSBs are set by Input Pin I2C_ADDR2,
Input Pin I2C_ADDR1, and Input Pin I2C_ADDR0 (LSB).
This transfer should be MSB first.
*
I2C_SCL
R/W
GENERAL CASE
I2C_SDA
FIXED PART
ADDR
START
ADDR
REGISTER ADDR
DATA
STOP
ACK
ACK
ACK
EXAMPLE
I2C_SDA
1
2
3
4
5
6
7
8
9
*THE SWITCHING/UPDATE DELAY BEGINS AT THE FALLING EDGE OF THE
LAST DATA BIT; FOR EXAMPLE, THE FALLING EDGE JUST BEFORE STEP 8.
Figure 29. I2C Write Diagram
Rev. 0 | Page 15 of 28
AD8197A
I2C_SCL
R/W
R/W
GENERAL CASE
I2C_SDA
FIXED PART
ADDR
FIXED PART
ADDR
START
ADDR
REGISTER ADDR
SR
ADDR
DATA
STOP
ACK
ACK
ACK
ACK
12
EXAMPLE
I2C_SDA
1
2
3
4
5
6
7
8
9
10 11
13
Figure 30. I2C Read Diagram
13. Perform one of the following:
READ PROCEDURE
13a. Send a stop condition (while holding the I2C_SCL
line high, pull the SDA line high) and release control
of the bus to end the transaction (shown in Figure 30).
13b. Send a repeated start condition (while holding the
I2C_SCL line high, pull the I2C_SDA line low) and
continue with Step 2 of the write procedure (previous
Write Procedure section) to perform a write.
13c. Send a repeated start condition (while holding the
I2C_SCL line high, pull the I2C_SDA line low) and
continue with Step 2 of this procedure to perform a
read from another address.
To read data from the AD8197A register set, an I2C master
(such as a microcontroller) needs to send the appropriate
control signals to the AD8197A slave device. The signals are
controlled by the I2C master, unless otherwise specified. For a
diagram of the procedure, see Figure 30. The steps for a read
procedure are as follows:
1. Send a start condition (while holding the I2C_SCL line
high, pull the I2C_SDA line low).
2. Send the AD8197A part address (seven bits). The upper
four bits of the AD8197A part address are the static value
[1001] and the three LSBs are set by Input Pin I2C_ADDR2,
Input Pin I2C_ADDR1, and Input Pin I2C_ADDR0 (LSB).
This transfer should be MSB first.
13d. Send a repeated start condition (while holding the
I2C_SCL line high, pull the I2C_SDA line low) and
continue with Step 8 of this procedure to perform a
read from the same address.
3. Send the write indicator bit (0).
4. Wait for the AD8197A to acknowledge the request.
5. Send the register address (eight bits) from which data is to
be read. This transfer should be MSB first.
SWITCHING/UPDATE DELAY
There is a delay between when a user writes to the configura-
tion registers of the AD8197A and when that state change takes
physical effect. This update delay occurs regardless of whether
the user programs the AD8197A via the serial or the parallel
control interface. When using the serial control interface, the
update delay begins at the falling edge of I2C_SCL for the last
data bit transferred, as shown in Figure 29. When using the
parallel control interface, the update delay begins at the transition
edge of the relevant parallel interface pin. This update delay is
register specific and the times are specified in Table 1.
6. Wait for the AD8197A to acknowledge the request.
7. Send a repeated start condition (Sr) by holding the
I2C_SCL line high and pulling the I2C_SDA line low.
8. Resend the AD8197A part address (seven bits) from Step 2.
The upper four bits of the AD8197A part address are the
static value [1001] and the three LSBs are set by
the Input Pin I2C_ADDR2, I2C_ADDR1 and Input
Pin I2C_ADDR0 (LSB). This transfer should be MSB first.
9. Send the read indicator bit (1).
10. Wait for the AD8197A to acknowledge the request.
11. The AD8197A serially transfers the data (eight bits) held in
the register indicated by the address set in Step 5. This data
is sent MSB first.
During a delay window, new values can be written to the
configuration registers, but the AD8197A does not physically
update until the end of that register’s delay window. Writing
new values during the delay window does not reset the window;
new values supersede the previously written values. At the end
of the delay window, the AD8197A physically assumes the state
indicated by the last set of values written to the configuration
registers. If the configuration registers are written after the delay
window ends, the AD8197A immediately updates and a new
delay window begins.
12. Acknowledge the data from the AD8197A.
Rev. 0 | Page 16 of 28
AD8197A
PARALLEL CONTROL INTERFACE
The AD8197A can be controlled through the parallel interface
using the PP_EN, PP_CH[1:0], PP_EQ, PP_PRE[1:0], PP_OTO,
and PP_OCL pins. Logic levels for the parallel interface pins
are set in accordance with the specifications listed in Table 1.
Setting these pins updates the parallel control interface
registers, as listed in Table 18. Following a reset, the AD8197A
can be controlled through the parallel control interface until the
first serial control event occurs. As soon as any serial control
event occurs, the serial programming values override any prior
parallel programming values, and the parallel control interface
is disabled until the part is subsequently reset. The default serial
programming values correspond to the state of the serial
interface configuration registers, as listed in Table 5.
Note that after changing the status of the channel selection
(PP_CH[1:0]), it is necessary to assert a low logic level to
RESET
to ensure that the channel-select status is properly
updated.
Rev. 0 | Page 17 of 28
AD8197A
SERIAL INTERFACE CONFIGURATION REGISTERS
The serial interface configuration registers can be read and written using the I2C serial control interface, Pin I2C_SDA, and Pin I2C_SCL.
The least significant bits of the AD8197A I2C part address are set by tying Pin I2C_ADDR2, Pin I2C_ADDR1, and Pin I2C_ADDR0 to
3.3 V (Logic 1) or 0 V (Logic 0). As soon as the serial control interface is used, the parallel control interface is disabled until the AD8197A
is reset, as described in the Serial Control Interface section.
Table 5. Serial (I2C) Interface Register Map
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Addr. Default
High Speed
Device
Modes
High
High speed source select
0x00
0x40
speed
channel
enable
HS_EN
0
0
0
0
0
0
0
0
HS_CH[1]
HS_CH[0]
Auxiliary
Device
Modes
Auxiliary
switch
enable
Auxiliary switch source select
0x01
0x10
0x40
0x01
AUX_EN
AUX_CH[1]
AUX_CH[0]
Receiver
Settings
High speed
channel
input
termination
select
RX_TO
Input
Termination
Pulse
Source A and Source B : input termination pulse-on-source switch select
(disconnect termination for a short period of time)
0x11
0x12
0x00
0x00
RX_PT[7]
RX_PT[6]
RX_PT[5]
RX_PT[4]
RX_PT[3]
RX_PT[2]
RX_PT[1]
RX_PT[0]
Register 1
Input
Termination
Pulse
Source C and Source D : input termination pulse-on-source switch select
(disconnect termination for a short period of time)
RX_PT[15] RX_ PT[14] RX_PT[13] RX_PT[12] RX_PT[11] RX_PT[10] RX_PT[9]
RX_PT[8]
Register 2
Receive
Equalizer 1
Source A and Source B: input equalization level select
0x13
0x14
0x20
0x00
0x00
0x03
RX_EQ[7]
RX_EQ[6]
RX_EQ[5]
Source C and Source D: input equalization level select
RX_EQ[13] RX_EQ[12] RX_EQ[11] RX_EQ[10] RX_EQ[9]
RX_EQ[4]
RX_EQ[3]
RX_EQ[2]
RX_EQ[1]
RX_EQ[0]
RX_EQ[8]
Receive
Equalizer 2
RX_EQ[15] RX_EQ[14]
Transmitter
Settings
High speed output
pre-emphasis level
select
High speed
output
termination
High speed
output
current level
select
select
TX_PE[1]
TX_PE[0]
TX_PTO
TX_OCL
Rev. 0 | Page 18 of 28
AD8197A
HIGH SPEED DEVICE MODES REGISTER
RECEIVER SETTINGS REGISTER
HS_EN: High Speed (TMDS) Channel Enable Bit
RX_TO: High Speed (TMDS) Channels Input Termination
On/Off Select Bit
Table 6. HS_EN Description
HS_EN Description
Table 10. RX_TO Description
RX_TO
Description
0
1
High speed channels off, low power/standby mode
High speed channels on
0
1
Input termination off
Input termination on (can be pulsed on and off
according to settings in the input termination
pulse register)
HS_CH[1:0]: High Speed (TMDS) Switch Source Select Bus
Table 7. HS_CH Mapping
HS_CH[1:0] O[3:0] Description
INPUT TERMINATION PULSE REGISTER 1 AND
REGISTER 2
RX_PT[x]: High Speed (TMDS) Input Channel X
Pulse-On-Source Switch Select Bit
00
01
10
11
A[3:0]
B[3:0]
C[3:0]
D[3:0]
High Speed Source A switched to
output
High Speed Source B switched to
output
High Speed Source C switched to
output
High Speed Source D switched to
output
Table 11. RX_PT[x] Description
RX_PT[x]
Description
0
Input termination for TMDS Channel X always
connected when source is switched
1
Input termination for TMDS Channel X
disconnected for 100 ms when source is
switched
AUXILIARY DEVICE MODES REGISTER
AUX_EN: Auxiliary (Low Speed) Switch Enable Bit
Table 8. AUX_EN Description
Table 12. RX_PT[x] Mapping
AUX_EN
Description
RX_PT[x]
Corresponding Input TMDS Channel
0
1
Auxiliary switch off
Auxiliary switch on
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
B0
B1
B2
B3
A0
A1
A2
A3
C3
C2
C1
C0
D3
D2
D1
D0
AUX_CH[1:0]: Auxiliary (Low Speed) Switch Source
Select Bus
Table 9. AUX_CH Mapping
AUX_CH[1:0] AUX_COM[3:0] Description
00
01
10
11
AUX_A[3:0]
AUX_B[3:0]
AUX_C[3:0]
AUX_D[3:0]
Auxiliary Source A switched
to output
Auxiliary Source B switched
to output
Auxiliary Source C switched
to output
Auxiliary Source D switched
to output
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
Rev. 0 | Page 19 of 28
AD8197A
RECEIVE EQUALIZER REGISTER 1 AND REGISTER 2
TRANSMITTER SETTINGS REGISTER
RX_EQ[x]: High Speed (TMDS) Input X Equalization Level
Select Bit
TX_PE[1:0]: High Speed (TMDS) Output Pre-Emphasis
Level Select Bus (For All TMDS Channels)
Table 13. RX_EQ[x] Description
Table 15. TX_PE[1:0] Description
RX_EQ[x]
Description
TX_PE[1:0]
Description
0
1
Low equalization (6 dB)
High equalization (12 dB)
00
01
10
11
No pre-emphasis (0 dB)
Low pre-emphasis (2 dB)
Medium pre-emphasis (4 dB)
High pre-emphasis (6 dB)
Table 14. RX_EQ[x] Mapping
RX_EQ[x]
Corresponding Input TMDS Channel
TX_PTO: High Speed (TMDS) Output Termination On/Off
Select Bit (For All Channels)
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
B0
B1
B2
B3
A0
A1
A2
A3
C3
C2
C1
C0
D3
D2
D1
D0
Table 16. TX_PTO Description
TX_PTO
Description
0
1
Output termination off
Output termination on
TX_OCL: High Speed (TMDS) Output Current Level Select
Bit (For All Channels)
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
Table 17. TX_OCL Description
TX_OCL
Description
0
1
Output current set to 10 mA
Output current set to 20 mA
Rev. 0 | Page 20 of 28
AD8197A
PARALLEL INTERFACE CONFIGURATION REGISTERS
The parallel interface configuration registers can be directly set using the PP_EN, PP_CH[1:0], PP_EQ, PP_PRE[1:0], PP_OTO, and
PP_OCL pins. This interface is only accessible after the part is reset and before any registers are accessed using the serial control interface.
The state of each pin is set by tying it to 3.3 V (Logic 1) or 0 V (Logic 0).
Table 18. Parallel Interface Register Map
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
High Speed
Device Modes
High speed
channel
enable
High speed source select
PP_EN
0
0
0
0
0
0
0
0
PP_CH[1]
PP_CH[0]
Auxiliary
Device Modes
Auxiliary
switch enable
Auxiliary switch source select
1
PP_CH[1]
PP_CH[0]
Receiver
Settings
Input termination
on/off select
(termination always on)
1
Input
Source A and Source B input termination select (termination always off)
Termination
Pulse 1
0
0
0
0
0
0
0
0
0
0
Input
Termination
Pulse 2
Source C and Source D input termination select (termination always off)
0
0
0
0
0
0
Receive
Equalizer 1
Source A and Source B input equalization level select
PP_EQ PP_EQ PP_EQ PP_EQ
Source C and Source D input equalization level select
PP_EQ PP_EQ
PP_EQ PP_EQ
PP_EQ
PP_EQ
PP_EQ
PP_EQ
Receive
Equalizer 2
PP_EQ
PP_EQ
PP_EQ
PP_EQ
Transmitter
Settings
High speed output
pre-emphasis level
select
High speed
output
termination
on/off select
High speed output
current level select
PP_PE[1] PP_PE[0] PP_OTO
PP_OCL
Rev. 0 | Page 21 of 28
AD8197A
HIGH SPEED DEVICE MODES REGISTER
PP_EN: High Speed (TMDS) Channel Enable Bit
INPUT TERMINATION PULSE REGISTER 1 AND
REGISTER 2
High speed input (TMDS) channels pulse-on-source switching
fixed to off when using the parallel interface.
Table 19. PP_EN Description
PP_EN Description
0
1
High speed channels off, low power/standby mode
High speed channels on
RECEIVE EQUALIZER REGISTER 1 AND REGISTER 2
PP_EQ: High Speed (TMDS) Input Equalization Level
Select Bit (For All TMDS Input Channels)
PP_CH[1:0]: High Speed (TMDS) Switch Source Select Bus
The input equalization cannot be set individually (per channel)
when using the parallel interface; one equalization setting
affects all input channels.
Table 20. High Speed Switch Mapping
PP_CH[1:0] O[3:0] Description
00
01
10
11
A[3:0]
B[3:0]
C[3:0]
D[3:0]
High Speed Source A switched to
output
High Speed Source B switched to
output
High Speed Source C switched to
output
High Speed Source D switched to
output
Table 22. PP_EQ Description
PP_EQ
Description
0
1
Low equalization (6 dB)
High equalization (12 dB)
TRANSMITTER SETTINGS REGISTER
PP_PE[1:0]: High Speed (TMDS) Output Pre-Emphasis
Level Select Bus (For All TMDS Channels)
AUXILIARY DEVICE MODES REGISTER
Table 23. PP_PE[1:0] Description
The auxiliary (low speed) switch is always enabled when using
the parallel interface.
PP_PE[1:0]
Description
00
01
10
11
No pre-emphasis (0 dB)
Low pre-emphasis (2 dB)
Medium pre-emphasis (4 dB)
High pre-emphasis (6 dB)
PP_CH[1:0]: Auxiliary Switch Source Select Bus
Table 21. Auxiliary Switch Mapping
PP_CH[1:0] AUX_COM[3:0] Description
00
01
10
11
AUX_A[3:0]
AUX_B[3:0]0
AUX_C[3:0]
AUX_D[3:0]
Auxiliary Source A switched to
output
Auxiliary Source B switched to
output
Auxiliary Source C switched to
output
Auxiliary Source D switched to
output
PP_OTO: High Speed (TMDS) Output Termination On/Off
Select Bit (For All TMDS Channels)
Table 24. PP_OTO Description
PP_OTO
Description
0
1
Output termination off
Output termination on
RECEIVER SETTINGS REGISTER
PP_OCL: High Speed (TMDS) Output Current Level Select
Bit (For All TMDS Channels)
High speed (TMDS) channels input termination is fixed to on
when using the parallel interface.
Table 25. TX_OCL Description
PP_OCL
Description
0
1
Output current set to 10 mA
Output current set to 20 mA
Rev. 0 | Page 22 of 28
AD8197A
APPLICATION INFORMATION
Figure 31. Layout of the TMDS Traces on the AD8197A Evaluation Board (Only Top Signal Routing Layer is Shown)
The AD8197A is an HDMI/DVI switch, featuring equalized
TMDS inputs and pre-emphasized TMDS outputs. It is in-
tended for use as a 4:1 switch in systems with long cable runs
on both the input and/or the output, and is fully HDMI 1.3
receive-compliant.
data eye and transmits a full-swing HDMI signal to an end
receiver. More information on the specific performance metrics
of the AD8197A can be found in the Typical Performance
Characteristics section.
The AD8197A also provides a distinct advantage in receive-type
applications because it is a fully buffered HDMI/DVI switch.
Although inverting the output pin order of the AD8197A on
the PCB requires a designer to place vias in the high speed
signal path, the AD8197A fully buffers and electrically decouples
the outputs from the inputs. Therefore, the effects of the vias
placed on the output signal lines are not seen at the input of
the AD8197A. The programmable output terminations also
improve signal quality at the output of the AD8197A. The
PCB designer, therefore, has significantly improved flexibility
in the placement and routing of the output signal path with
the AD8197A over other solutions.
PINOUT
The AD8197A is designed to have an HDMI/DVI receiver
pinout at its input and a transmitter pinout at its output, which
makes the AD8197A ideal for use in AVR-type applications
where a designer routes both the inputs and the outputs directly
to HDMI/DVI connectors, as shown in Figure 31. When the
AD8197A is used in receiver type applications, it is necessary to
change the order of the output pins on the PCB to align with the
on-board receiver.
One advantage of the AD8197A in an AVR-type application is
that all of the high speed signals can be routed on one side (the
top side) of the board, as shown in Figure 31. In addition to
12 dB of input equalization, the AD8197A provides up to 6 dB
of output pre-emphasis that boosts the output TMDS signals
and allows the AD8197A to precompensate when driving long
PCB traces or output cables. The net effect of the input
equalization and output pre-emphasis of the AD8197A is that
the AD8197A can compensate for the signal degradation of
both input and output cables; it acts to reopen a closed input
CABLE LENGTHS AND EQUALIZATION
The AD8197A offers two levels of programmable equalization
for the high speed inputs: 6 dB and 12 dB. The equalizer of
the AD8197A supports video data rates of up to 2.25 Gbps,
and as shown in Figure 14, it can equalize more than 20 meters
of 24 AWG HDMI cable at 2.25 Gbps, which corresponds to the
video format, 1080p with deep color.
Rev. 0 | Page 23 of 28
AD8197A
The length of cable that can be used in a typical HDMI/DVI
application depends on a large number of factors, including:
conform to the I2C bus standard and do not have excessive
capacitive loading.
TMDS Signals
•
Cable quality: the quality of the cable in terms of conductor
wire gauge and shielding. Thicker conductors have lower
signal degradation per unit length.
Data rate: the data rate being sent over the cable. The signal
degradation of HDMI cables increases with data rate.
Edge rates: the edge rates of the source input. Slower input
edges result in more significant data eye closure at the end
of a cable.
In the HDMI/DVI standard, four differential pairs carry the
TMDS signals. In DVI, three of these pairs are dedicated to
carrying RGB video and sync data. For HDMI, audio data is
interleaved with the video data; the DVI standard does not
incorporate audio information. The fourth high speed differ-
ential pair is used for the AV data-word clock, and runs at
one-tenth the speed of the TMDS data channels.
•
•
•
Receiver sensitivity: the sensitivity of the terminating
receiver.
The four high speed channels of the AD8197A are identical.
No concession was made to lower the bandwidth of the fourth
channel for the pixel clock; therefore, any channel can be used
for any TMDS signal. The user chooses which signal is routed
over which channel. Additionally, the TMDS channels are
symmetrical; therefore, the p and n of a given differential pair are
interchangeable, provided the inversion is consistent across all
inputs and outputs of the AD8197A. However, the routing
between inputs and outputs through the AD8197A is fixed.
As such, specific cable types and lengths are not recommended
for use with a particular equalizer setting. In nearly all applica-
tions, the AD8197A equalization level can be set to high, or
12 dB, for all input cable configurations at all data rates, without
degrading the signal integrity.
PCB LAYOUT GUIDELINES
The AD8197A is used to switch two distinctly different types of
signals, both of which are required for HDMI and DVI video.
These signal groups require different treatment when laying out
a PCB.
The AD8197A buffers the TMDS signals and the input traces
can be considered electrically independent of the output traces.
In most applications, the quality of the signal on the input
TMDS traces is more sensitive to the PCB layout. Regardless of
the data being carried on a specific TMDS channel, or whether
the TMDS line is at the input or the output of the AD8197A, all
four high speed signals should be routed on a PCB in accor-
dance with the same RF layout guidelines.
The first group of signals carries the audiovisual (AV) data.
HDMI/DVI video signals are differential, unidirectional, and
high speed (up to 2.25 Gbps). The channels that carry the video
data must be controlled impedance, terminated at the receiver,
and capable of operating at the maximum specified system data
rate. It is especially important to note that the differential traces
that carry the TMDS signals should be designed with a controlled
differential impedance of 100 Ω. The AD8197A provides single-
ended, 50 Ω terminations on-chip for both its inputs and
outputs, and both the input and output terminations can be
enabled or disabled through the serial control interface. The
output terminations can also be enabled or disabled through the
parallel control interface. Transmitter termination is not required
by the HDMI 1.3 standard, but its inclusion improves the overall
system signal integrity.
Layout for the TMDS Signals
The TMDS differential pairs can be either microstrip traces,
routed on the outer layer of a board, or stripline traces, routed
on an internal layer of the board. If microstrip traces are used,
there should be a continuous reference plane on the PCB layer
directly below the traces. If stripline traces are used, they must
be sandwiched between two continuous reference planes in the
PCB stack-up. Additionally, the p and n of each differential pair
must have a controlled differential impedance of 100 Ω. The
characteristic impedance of a differential pair is a function of
several variables including the trace width, the distance separating
the two traces, the spacing between the traces and the reference
plane, and the dielectric constant of the PCB binder material.
Interlayer vias introduce impedance discontinuities that can
cause reflections and jitter on the signal path, therefore, it is
preferable to route the TMDS lines exclusively on one layer of the
board, particularly for the input traces.
The audiovisual (AV) data carried on these high speed channels
is encoded by a technique called transmission minimized differ-
ential signaling (TMDS) and in the case of HDMI, is also encrypted
according to the high bandwidth digital copy protection (HDCP)
standard.
The second group of signals consists of low speed auxiliary
control signals used for communication between a source and a
sink. Depending upon the application, these signals can include
the DDC bus (this is an I2C bus used to send EDID information
and HDCP encryption keys between the source and the sink),
the consumer electronics control (CEC) line, and the hot plug
detect (HPD) line. These auxiliary signals are bidirectional, low
speed, and transferred over a single-ended transmission line
that does not need to have controlled impedance. The primary
concern with laying out the auxiliary lines is ensuring that they
In some applications, such as using multiple AD8197A devices to
construct large input arrays, the use of interlayer vias becomes
unavoidable. In these situations, the input termination feature of
the AD8197A improves system signal integrity by absorbing
reflections. Take care to use vias minimally and to place vias
symmetrically for each side of a given differential pair.
Furthermore, to prevent unwanted signal coupling and
Rev. 0 | Page 24 of 28
AD8197A
interference, route the TMDS signals away from other signals
and noise sources on the PCB.
longer so strongly coupled, the width of the traces should be
increased to yield a differential impedance of 100 Ω in the new
configuration.
Both traces of a given differential pair must be equal in length
to minimize intrapair skew. Maintaining the physical symmetry
of a differential pair is integral to ensuring its signal integrity;
excessive intrapair skew can introduce jitter through duty cycle
distortion (DCD). The p and n of a given differential pair should
always be routed together to establish the required 100 Ω differ-
ential impedance. Enough space should be left between the
differential pairs of a given group so that the n of one pair does
not couple to the p of another pair. For example, one technique is
to make the interpair distance 4 to 10 times wider than the
intrapair spacing.
Ground Current Return
In some applications, it can be necessary to invert the output
pin order of the AD8197A. This requires a designer to route the
TMDS traces on multiple layers of the PCB. When routing
differential pairs on multiple layers, it is also necessary to
reroute the corresponding reference plane to provide one
continuous ground current return path for the differential
signals. Standard plated through-hole vias are acceptable for
both the TMDS traces and the reference plane. An example of
this is illustrated in Figure 32.
Any group of four TMDS channels (Input A, Input B, Input C,
Input D, or the output) should have closely matched trace
lengths to minimize interpair skew. Severe interpair skew can
cause the data on the four different channels of a group to arrive
out of alignment with one another. A good practice is to match
the trace lengths for a given group of four channels to within
0.05 inches on FR4 material.
THROUGH-HOLE VIAS
SILKSCREEN
LAYER 1: SIGNAL (MICROSTRIP)
PCB DIELECTRIC
LAYER 2: GND (REFERENCE PLANE)
PCB DIELECTRIC
Minimizing intrapair and interpair skew becomes increasingly
important as data rates increase. Any introduced skew consti-
tutes a correspondingly larger fraction of a bit period at higher
data rates.
LAYER 3: PWR
(REFERENCE PLANE)
PCB DIELECTRIC
Though the AD8197A features input equalization and output
pre-emphasis, the length of the TMDS traces should be mini-
mized to reduce overall signal degradation. Commonly used
PCB material such as FR4 is lossy at high frequencies; therefore,
long traces on the circuit board increase signal attenuation
resulting in decreased signal swing and increased jitter through
intersymbol interference (ISI).
LAYER 4: SIGNAL (MICROSTRIP)
SILKSCREEN
KEEP REFERENCE PLANE
ADJACENT TO SIGNAL ON ALL
LAYERS TO PROVIDE CONTINUOUS
GROUND CURRENT RETURN PATH.
Figure 32. Example Routing of Reference Plane
TMDS Terminations
Controlling the Characteristic Impedance of a TMDS
Differential Pair
The AD8197A provides internal, 50 Ω single-ended termina-
tions for all of its high speed inputs and outputs. It is not
necessary to include external termination resistors for the
TMDS differential pairs on the PCB.
The characteristic impedance of a differential pair depends
on a number of variables, including the trace width, the
distance between the two traces, the height of the dielectric
material between the trace and the reference plane below it,
and the dielectric constant of the PCB binder material. To
a lesser extent, the characteristic impedance also depends
upon the trace thickness and the presence of solder mask.
There are many combinations that can produce the correct
characteristic impedance. Generally, working with the PCB
fabricator is required to obtain a set of parameters to produce
the desired results.
The output termination resistors of the AD8197A back-terminate
the output TMDS transmission lines. These back-terminations
act to absorb reflections from impedance discontinuities on the
output traces, improving the signal integrity of the output traces
and adding flexibility to how the output traces can be routed.
For example, interlayer vias can be used to route the AD8197A
TMDS outputs on multiple layers of the PCB without severely
degrading the quality of the output signal.
Auxiliary Control Signals
One consideration is how to guarantee a differential pair with
a differential impedance of 100 Ω over the entire length of the
trace. One technique to accomplish this is to change the width
of the traces in a differential pair based on how closely one trace
is coupled to the other. When the two traces of a differential
pair are close and strongly coupled, they should have a width
that produces a 100 Ω differential impedance. When the traces
split apart (to go into a connector, for example) and are no
There are four single-ended control signals associated with each
source or sink in an HDMI/DVI application: hot plug detect
(HPD), consumer electronics control (CEC), and two display
data channel (DDC) lines. The two signals on the DDC bus are
SDA and SCL (serial data and serial clock, respectively). These
four signals can be switched through the auxiliary bus of the
Rev. 0 | Page 25 of 28
AD8197A
AD8197A and do not need to be routed with the same strict
considerations as the high speed TMDS signals.
HPD is a dc signal presented by a sink to a source to indicate
that the source EDID is available for reading. The placement
of this signal is not critical, but it should be routed as directly
as possible.
In general, it is sufficient to route each auxiliary signal as a
single-ended trace. These signals are not sensitive to impedance
discontinuities, do not require a reference plane, and can be
routed on multiple layers of the PCB. However, it is best to
follow strict layout practices whenever possible to prevent the
PCB design from affecting the overall application. The specific
routing of the HPD, CEC, and DDC lines depends upon the
application in which the AD8197A is being used.
When the AD8197A is powered up, one set of the auxiliary in-
puts is passively routed to the outputs. In this state, the
AD8197A looks like a 100 Ω resistor between the selected
auxiliary inputs and the corresponding outputs as illustrated in
Figure 27. The AD8197A does not buffer the auxiliary signals,
therefore, the input traces, output traces, and the connection
through the AD8197A all must be considered when designing a
PCB to meet HDMI/DVI specifications. The unselected auxiliary
inputs of the AD8197A are placed into a high impedance mode
when the device is powered up. To ensure that all of the
auxiliary inputs of the AD8197A are in a high impedance mode
when the device is powered off, it is necessary to power the
AMUXVCC supply as illustrated in Figure 28.
For example, the maximum speed of signals present on the
auxiliary lines is 100 kHz I2C data on the DDC lines; therefore,
any layout that enables 100 kHz I2C to be passed over the DDC
bus should suffice. The HDMI 1.3 specification, however, places
a strict 50 pF limit on the amount of capacitance that can be
measured on either SDA or SCL at the HDMI input connector.
This 50 pF limit includes the HDMI connector, the PCB, and
whatever capacitance is seen at the input of the AD8197A, or an
equivalent receiver. There is a similar limit of 100 pF of input
capacitance for the CEC line.
In contrast to the auxiliary signals, the AD8197A buffers the
TMDS signals, allowing a PCB designer to layout the TMDS
inputs independently of the outputs.
The parasitic capacitance of traces on a PCB increases with
trace length. To help ensure that a design satisfies the HDMI
specification, the length of the CEC and DDC lines on the PCB
should be made as short as possible. Additionally, if there is a
reference plane in the layer adjacent to the auxiliary traces in
the PCB stackup, relieving or clearing out this reference plane
directly under the auxiliary traces significantly decreases the
amount of parasitic trace capacitance. An example of the board
stackup is shown in Figure 33.
Power Supplies
The AD8197A has five separate power supplies referenced to
two separate grounds. The supply/ground pairs are:
•
•
•
•
•
AVCC/AVEE
VTTI/AVEE
VTTO/AVEE
DVCC/DVEE
AMUXVCC/DVEE
3W
W
3W
The AVCC/AVEE (3.3 V) and DVCC/DVEE (3.3 V) supplies
power the core of the AD8197A. The VTTI/AVEE supply
(3.3 V) powers the input termination (see Figure 25). Similarly,
the VTTO/AVEE supply (3.3 V) powers the output termination
(see Figure 26). The AMUXVCC/DVEE supply (3.3 V to 5 V)
powers the auxiliary multiplexer core and determines the
maximum allowed voltage on the auxiliary lines. For example,
if the DDC bus is using 5 V I2C, AMUXVCC should be
connected to 5 V relative to DVEE.
SILKSCREEN
LAYER 1: SIGNAL (MICROSTRIP)
PCB DIELECTRIC
LAYER 2: GND (REFERENCE PLANE)
PCB DIELECTRIC
LAYER 3: PWR (REFERENCE PLANE)
PCB DIELECTRIC
In a typical application, all pins labeled AVEE or DVEE should
be connected directly to ground. All pins labeled AVCC,
DVCC, VTTI, or VTTO should be connected to 3.3 V, and
Pin AMUXVCC tied to 5 V. The supplies can also be powered
individually, but care must be taken to ensure that each stage of
the AD8197A is powered correctly.
LAYER 4: SIGNAL (MICROSTRIP)
SILKSCREEN
REFERENCE LAYER
RELIEVED UNDERNEATH
MICROSTRIP
Figure 33. Example Board Stackup
Rev. 0 | Page 26 of 28
AD8197A
Power Supply Bypassing
0.01 μF capacitors, and one 4.7 μF capacitor. The capacitors
should via down directly to the supply planes and be placed
within a few centimeters of the AD8197A. The AMUXVCC
supply does not require additional bypassing. This bypassing
scheme is illustrated in Figure 35.
The AD8197A requires minimal supply bypassing. When
powering the supplies individually, place a 0.01 μF capacitor
between each 3.3 V supply pin (AVCC, DVCC, VTTI, and VTTO)
and ground to filter out supply noise. Generally, bypass capacitors
should be placed near the power pins and should connect directly
to the relevant supplies (without long intervening traces). For
example, to improve the parasitic inductance of the power supply
decoupling capacitors, minimize the trace length between
capacitor landing pads and the vias, as shown in Figure 34.
RECOMMENDED
DECOUPLING
CAPACITORS
AD8197A
EXTRA ADDED INDUCTANCE
AUXILIARY LINES
TMDS TRACES
NOT RECOMMENDED
Figure 34. Recommended Pad Outline for Bypass Capacitors
Figure 35. Example Placement of Power Supply Decoupling Capacitors
Around the AD8197A
In applications where the AD8197A is powered by a single 3.3 V
supply, it is recommended to use two reference supply planes
and bypass the 3.3 V reference plane to the ground reference
plane with one 220 pF capacitor, one 1000 pF capacitor, two
Rev. 0 | Page 27 of 28
AD8197A
OUTLINE DIMENSIONS
16.20
16.00 SQ
15.80
1.60 MAX
0.75
0.60
0.45
100
1
76
75
PIN 1
14.20
14.00 SQ
13.80
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.20
0.09
7°
3.5°
0°
25
51
50
0.15
0.05
26
SEATING
PLANE
0.08
0.27
0.22
0.17
COPLANARITY
VIEW A
0.50
BSC
LEAD PITCH
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BED
Figure 36. 100-Lead Low Profile Quad Flat Package [LQFP]
(ST-100)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range Package Description
Package Option Ordering Quantity
AD8197AASTZ1
AD8197AASTZ-RL1
AD8197A-EVALZ1
−40°C to +85°C
−40°C to +85°C
100-Lead Low Profile Quad Flat Package [LQFP]
100-Lead Low Profile Quad Flat Package [LQFP], Reel
Evaluation Board
ST-100
ST-100
1,000
1 Z = RoHS Compliant Part.
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07014-0-11/07(0)
Rev. 0 | Page 28 of 28
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