AD8202YR-REEL [ADI]
High Common-Mode Voltage, Single-Supply Difference Amplifier; 高共模电压，单电源差动放大器
| 型号： | AD8202YR-REEL |
| 厂家： | 
ADI |
| 描述： | High Common-Mode Voltage, Single-Supply Difference Amplifier |
| 文件： | 总12页 (文件大小：266K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Common-Mode Voltage,
Single-Supply Difference Amplifier
AD8202
FEATURES
FUNCTIONAL BLOCK DIAGRAM
High common-mode voltage range
−8 V to +28 V at a 5 V supply voltage
Operating temperature range: −40°C to +125°C
Supply voltage range: 3.5 V to 12 V
Low-pass filter (1-pole or 2-pole)
NC
7
A1
3
A2
4
+V
S
6
AD8202
100kΩ
G = ×10
+IN
A1
–IN
G = ×2
+IN
A2
–IN
8
1
+IN
–IN
5
OUT
EXCELLENT AC AND DC PERFORMANCE
10kΩ
1 mV voltage offset
200kΩ
200kΩ
1 ppmꢀ°C typ gain drift
80 dB CMRR min dc to 10 kHz
10kΩ
2
PLATFORMS
NC = NO CONNECT
GND
Transmission control
Figure 1. SOIC (R) Package Die Form
Diesel injection control
Engine management
Adaptive suspension control
Vehicle dynamics control
INDUCTIVE
LOAD
5V
CLAMP
DIODE
OUTPUT
GENERAL DESCRIPTION
+IN
NC +VS OUT
The AD8202 is a single-supply difference amplifier for amplifying
and low-pass filtering small differential voltages in the presence of a
large common-mode voltage. The input CMV range extends from
−8 V to +28 V at a typical supply voltage of 5 V.
BATTERY
14V
4-TERM
SHUNT
AD8202
–IN GND A1
A2
POWER
DEVICE
The AD8202 is offered in die and packaged form. Both package
options are specified over a wide temperature range of −40°C to
+125°C, making the AD8202 well-suited for use in many auto-
motive platforms.
COMMON
NC = NO CONNECT
Figure 2. High-Line Current Sensor
Automotive platforms demand precision components for better
system control. The AD8202 provides excellent ac and dc
performance, which keeps errors to a minimum in the user’s
system. Typical offset and gain drift in the SOIC package are
5 µV/°C and 1 ppm/°C, respectively. The device also delivers a
minimum CMRR of 80 dB from dc to 10 kHz.
POWER
DEVICE
5V
OUTPUT
+IN
NC +VS OUT
BATTERY
14V
4-TERM
SHUNT
AD8202
The AD8202 features an externally accessible 100 kΩ resistor at
the output of the preamp A1, which can be used for low-pass
filter applications and for establishing gains other than 20.
–IN GND A1
A2
CLAMP
DIODE
INDUCTIVE
LOAD
COMMON
NC = NO CONNECT
Figure 3. Low-Line Current Sensor
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
AD8202
TABLE OF CONTENTS
Specifications—Single Supply......................................................... 3
Gain Trim .................................................................................... 10
Low-Pass Filtering...................................................................... 10
Absolute Maximum Ratings............................................................ 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Typical Performance Characteristics ............................................. 6
Theory of Operation ........................................................................ 8
Applications....................................................................................... 9
Current Sensing ............................................................................ 9
Gain Adjustment........................................................................... 9
High-Line Current Sensing with LPF
and Gain Adjustment................................................................. 11
Driving Charge Redistribution ADCs..................................... 11
Outline Dimensions....................................................................... 12
Ordering Guide .......................................................................... 12
REVISION HISTORY
11/04—Rev. 0 to a Rev. A
Changes to the Features................................................................... 1
Changes to the General Description.............................................. 1
Changes to Specifications (Table 1) ............................................... 3
Changes to Absolute Maximum Ratings (Table 2)....................... 4
Changes to Pin Function Descriptions (Table 3) ......................... 5
Changes to Figure 5.......................................................................... 5
Changes to Figure 9 and Figure 10................................................. 6
Updated Outline Dimensions....................................................... 12
Changes to the Ordering Guide.................................................... 12
7/04—Revision 0: Initial Version
Rev. A | Page 2 of 12
AD8202
SPECIFICATIONS—SINGLE SUPPLY
TA = operating temperature range, VS = 5 V, unless otherwise noted.
Table 1.
AD8202 SOIC
AD8202 DIE
Parameter
Conditions
Min
Typ
20
1
Max
Min
Typ
20
1
Max
Unit
SYSTEM GAIN
Initial
Error
vs. Temperature
VOLTAGE OFFSET
Input Offset (RTI)
vs. Temperature
V/V
%
ppm/°C
0.02 ≤ VOUT ≤ 4.8 V dc
−0.3
+0.3
20
−0.3
+0.3
30
VCM = 0.15 V; 25°C
−40°C to +125°C
−40°C to +150°C
−1
−10
+1
+10
−1
−10
−15
+1
mV
µV/°C
µV/°C
+0.3
+0.3 +10
+5
+15
INPUT
Input Impedance
Differential
Common-Mode
CMV
Common-Mode Rejection1
260
135
−8
325
170
390
205
+28
260
135
−8
325
170
390
205
+28
kΩ
kΩ
V
Continuous
VCM = 0 V to 10 V
f = DC
f = 1 kHz
f = 10 kHz2
82
82
80
82
82
80
dB
dB
dB
PREAMPLIFIER
Gain
Gain Error
Output Voltage Range
Output Resistance
OUTPUT BUFFER
Gain
10
10
V/V
%
V
−0.3
0.02
97
+0.3
4.8
103
−0.3
0.02
97
+0.3
4.8
103
100
2
100
2
kΩ
V/V
%
V
nA
Ω
Gain Error
0.02 ≤ VOUT ≤ 4.8 V dc
−0.3
0.02
+0.3
4.8
−0.3
0.02
+0.3
4.8
Output Voltage Range
Input Bias Current
Output Resistance
DYNAMIC RESPONSE
System Bandwidth
Slew Rate
40
2
40
2
VIN = 0.01 V dc, VOUT = 0.2 V p-p
VIN = 0.2 V dc, VOUT = 4 V Step
30
50
0.28
30
50
0.28
kHz
V/µs
NOISE
0.1 Hz to 10 Hz
10
10
µV p-p
Spectral Density, 1 kHz (RTI)
POWER SUPPLY
Operating Range
Quiescent Current vs. Temperature
PSRR
275
275
nV/√Hz
3.5
75
12
1.0
3.5
75
12
1.0
V
mA
dB
VO = 0.1 V dc
VS = 3.5 V to 12 V
0.25
83
0.25
83
TEMPERATURE RANGE
For Specified Performance
−40
+125
−40
+150
°C
1 Source imbalance < 2 Ω.
2 The AD8202 preamplifier exceeds 80 dB CMRR at 10 kHz. However, since the signal is available only by way of a 100 kΩ resistor, even the small amount of pin-to-pin
capacitance between Pins 1, 8 and 3, 4 may couple an input common-mode signal larger than the greatly attenuated preamplifier output. The effect of pin-to-pin
coupling may be neglected in all applications by using filter capacitors at Node 3.
Rev. A | Page 3 of 12
AD8202
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Rating
Supply Voltage
Transient Input Voltage (400 ms)
12.5 V
44 V
Continuous Input Voltage
(Common Mode)
Reversed Supply Voltage Protection
Operating Temperature Range
Die
35 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
0.3 V
−40°C to +150°C
−40°C to +125°C
−65°C to +150°C
Indefinite
SOIC
Storage Temperature
Output Short-Circuit Duration
Lead Temperature Range
(Soldering 10 sec)
300°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 4 of 12
AD8202
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
–IN
GND
A1
1
2
3
4
8
7
6
5
+IN
NC
+V
AD8202
1036µm
TOP VIEW
(Not to Scale)
+V
S
S
A2
OUT
NC = NO CONNECT
Figure 4. 8-Lead SOIC
OUT
+IN
Table 3. 8-Lead SOIC Pin Function Descriptions
Pin No.
Mnemonic
X
Y
1048µm
1
2
3
4
5
6
7
8
−IN
GND
A1
A2
OUT
+Vs
−409.0
−244.6
+229.4
+410.0
+410.0
+121.0
NA
−205.2
−413.0
−413.0
−308.6
+272.4
+417.0
NA
–IN
A2
NC
+IN
−409.0
+205.2
GND
A1
Figure 5. Metallization Photograph
Rev. A | Page 5 of 12
AD8202
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = 5 V, VCM = 0 V, RL = 10 kΩ, unless otherwise noted.
90
80
70
60
0
–5
–55
–40
°
°
C
C
–10
–15
–20
–25
50
40
30
+25
°
C
+125
°
C
C
20
10
0
–30
–35
+150
°
10
100
1k
10k
100k
3
4
5
6
7
8
9
10
11
12
13
FREQUENCY (Hz)
POWER SUPPLY (V)
Figure 6. Power Supply Rejection Ratio vs. Frequency
Figure 9. Negative Common-Mode Voltage vs. Voltage Supply
30
25
40
35
30
–55°C
20
15
25
+150°C
20
15
+125
°
C
10
–40°C
10
+25°C
5
0
5
0
100
1k
10k
100k
1M
3
4
5
6
7
8
9
10
11
12
13
FREQUENCY (Hz)
POWER SUPPLY (V)
Figure 7. AD8202 Bandwidth
Figure 10. Positive Common-Mode Voltage vs. Voltage Supply
100
95
5.0
4.5
4.0
3.5
3.0
2.5
2.0
90
85
80
1.5
1.0
75
70
0.5
0
10
100
1k
10k
100k
10
100
1k
10k
FREQUENCY (Hz)
LOAD RESISTANCE (Ω)
Figure 8. Common-Mode Rejection Ratio vs. Frequency
Figure 11. Output Swing vs. Load Resistance
Rev. A | Page 6 of 12
AD8202
0
–10
–20
–30
–40
OUTPUT
INF LOAD
10k LOAD
INPUT
1
2
–50
–60
–70
CH1 500mVΩ CH2 50mVΩ M 20µs 2.5MS/s 400NS/PT
3
4
5
6
7
8
9
10
11
12
13
A CH1 1.73V
SUPPLY VOLTAGE (V)
Figure 13. Pulse Response
Figure 12. Swing Minus Supply vs. Supply Voltage
Rev. A | Page 7 of 12
AD8202
THEORY OF OPERATION
The AD8202 consists of a preamp and buffer arranged as shown
in Figure 14. Like-named resistors have equal values.
To minimize these errors while extending the common-mode
range, a dedicated feedback loop is employed to reduce the
range of common-mode voltage applied to A1 for a given over-
all range at the inputs. By offsetting the range of voltage applied
to the compensator, the input common-mode range is also
offset to include voltages more negative than the power supply.
Amplifier A3 detects the common-mode signal applied to A1
and adjusts the voltage on the matched RCM resistors to reduce
the common-mode voltage range at the A1 inputs. By adjusting
the common voltage of these resistors, the common-mode input
range is extended while, at the same time, the normal mode
signal attenuation is reduced, leading to better performance
referred to input.
The preamp incorporates a dynamic bridge (subtractor) circuit.
Identical networks (within the shaded areas), consisting of RA,
RB, RC, and RG, attenuate input signals applied to Pins 1 and 8.
Note that when equal amplitude signals are asserted at inputs 1
and 8, and the output of A1 is equal to the common potential
(i.e., zero), the two attenuators form a balanced-bridge network.
When the bridge is balanced, the differential input voltage at A1,
and thus its output, is zero.
Any common-mode voltage applied to both inputs keeps the
bridge balanced and the A1 output at zero. Because the resistor
networks are carefully matched, the common-mode signal
rejection approaches this ideal state.
The output of the dynamic bridge taken from A1 is connected
to Pin 3 by way of a 100 kΩ series resistor, provided for low-
pass filtering and gain adjustment. The resistors in the input
networks of the preamp and the buffer feedback resistors are
ratio trimmed for high accuracy.
However, if the signals applied to the inputs differ, the result is a
difference at the input to A1. A1 responds by adjusting its output
to drive RB, by way of RG, to adjust the voltage at its inverting
input until it matches the voltage at its noninverting input.
The output of the preamp drives a gain-of-2 buffer amplifier,
A2, implemented with carefully matched feedback resistors RF.
By attenuating voltages at Pins 1 and 8, the amplifier inputs are
held within the power supply range, even if Pin 1 and Pin 8
input levels exceed the supply, or fall below common (ground).
The input network also attenuates normal (differential) mode
voltages. RC and RG form an attenuator that scales A1 feedback,
forcing large output signals to balance relatively small differen-
tial inputs. The resistor ratios establish the preamp gain at 10.
The 2-stage system architecture of the AD8202 enables the user
to incorporate a low-pass filter prior to the output buffer. By
separating the gain into two stages, a full-scale, rail-to-rail signal
from the preamp can be filtered at Pin 3, and a half-scale signal,
resulting from filtering, can be restored to full scale by the
output buffer amp. The source resistance seen by the inverting
input of A2 is approximately 100 kΩ to minimize the effects of
A2’s input bias current. However, this current is quite small and
errors resulting from applications that mismatch the resistance
are correspondingly small.
Because the differential input signal is attenuated and then
amplified to yield an overall gain of 10, Amplifier A1 operates at
a higher noise gain, multiplying deficiencies such as input offset
voltage and noise with respect to Pins 1 and 8.
+IN
8
–IN
1
R
R
A
A
100kΩ
3
4
A1
5
(TRIMMED)
A2
R
R
R
R
F
F
CM
CM
A3
R
R
R
B
B
C
R
R
R
G
AD8202
G
C
2
COM
Figure 14. Simplified Schematic
Rev. A | Page 8 of 12
AD8202
APPLICATIONS
+V
+V
S
The AD8202 difference amplifier is intended for applications
where it is required to extract a small differential signal in the
presence of large common-mode voltages. The input resistance
is nominally 170 kΩ, and the device can tolerate common-mode
voltages higher than the supply voltage and lower than ground.
OUT
+IN
NC
OUT
S
V
V
DIFF
2
10kΩ
10kΩ
20R
EXT
GAIN =
R
+ 100kΩ
EXT
AD8202
GAIN
20 – GAIN
DIFF
2
R
= 100kΩ
V
The open collector output stage sources current to within
20 mV of ground and to within 200 mV of VS.
100kΩ
EXT
CM
–IN GND
A1
A2
CURRENT SENSING
High-Line, High Current Sensing
R
EXT
Basic automotive applications making use of the large common-
mode range are shown in Figure 2 and Figure 3. The capability
of the device to operate as an amplifier in primary battery sup-
ply circuits is shown in Figure 2; Figure 3 illustrates the ability
of the device to withstand voltages below system ground.
NC = NO CONNECT
Figure 16. Adjusting for Gains Less than 20
The overall bandwidth is unaffected by changes in gain by using
this method, although there may be a small offset voltage due to
the imbalance in source resistances at the input to the buffer. In
many cases this can be ignored, but if desired, it can be nulled
by inserting a resistor equal to 100 kΩ minus the parallel sum of
REXT and 100 kΩ, in series with Pin 4. For example, with REXT
100 kΩ (yielding a composite gain of ×10), the optional offset
nulling resistor is 50 kΩ.
Low Current Sensing
The AD8202 can also be used in low current sensing applications,
such as the 4 to 20 mA current loop shown in Figure 15. In such
applications, the relatively large shunt resistor can degrade the
common-mode rejection. Adding a resistor of equal value on the
low impedance side of the input corrects for this error.
=
10Ω
1%
Gains Greater than 20
5V
OUTPUT
Connecting a resistor from the output of the buffer amplifier to
its noninverting input, as shown in Figure 17, increases the gain.
The gain is now multiplied by the factor REXT/(REXT − 100 kΩ);
for example, it is doubled for REXT = 200 kΩ. Overall gains as
high as 50 are achievable in this way. Note that the accuracy of
the gain becomes critically dependent on the resistor value at
high gains. Also, the effective input offset voltage at Pin 1 and
Pin 8 (about six times the actual offset of A1) limits the part’s
use in high gain, dc-coupled applications.
+IN
NC
+VS OUT
+
10Ω
1%
AD8202
–IN GND A1
A2
+V
S
NC = NO CONNECT
OUT
Figure 15. 4 to 20 mA Current Loop Receiver
+IN
NC
+VS OUT
GAIN ADJUSTMENT
V
V
DIFF
2
10kΩ
10kΩ
20R
EXT
GAIN =
R
– 100kΩ
EXT
The default gain of the preamplifier and buffer are ×10 and ×2,
respectively, resulting in a composite gain of ×20. With the
addition of external resistor(s) or trimmer(s), the gain may be
lowered, raised, or finely calibrated.
AD8202
R
EXT
GAIN
GAIN – 20
DIFF
2
R
= 100kΩ
V
100kΩ
EXT
CM
–IN GND
A1
A2
Gains Less than 20
NC = NO CONNECT
Since the preamplifier has an output resistance of 100 kΩ, an
external resistor connected from Pins 3 and 4 to GND decreases
the gain by a factor REXT/(100 kΩ + REXT) (see Figure 16).
Figure 17. Adjusting for Gains Greater than 20
Rev. A | Page 9 of 12
AD8202
Low-pass filters can be implemented in several ways by using
the features provided by the AD8202. In the simplest case, a
single-pole filter (20 dB/decade) is formed when the output of
A1 is connected to the input of A2 via the internal 100 kΩ resis-
tor by strapping Pins 3 and 4 and a capacitor added from this
node to ground, as shown in Figure 19. If a resistor is added
across the capacitor to lower the gain, the corner frequency
increases; it should be calculated using the parallel sum of the
resistor and 100 kΩ.
GAIN TRIM
Figure 18 shows a method for incremental gain trimming by
using a trim potentiometer and external resistor REXT
.
The following approximation is useful for small gain ranges.
ΔG ≈ (10 MΩ ÷ REXT)%
Thus, the adjustment range is 2% for REXT = 5 MΩ; 10% for
REXT = 1 MΩ, and so on.
5V
5V
OUTPUT
OUT
+IN
NC +VS OUT
+IN
NC +VS OUT
V
V
DIFF
2
V
V
DIFF
2
1
F
=
C
5
2πC10
AD8202
AD8202
DIFF
2
C IN FARADS
V
CM
DIFF
2
V
CM
–IN GND A1
A2
–IN GND A1
A2
GAIN TRIM
20kΩ MIN
R
EXT
C
NC = NO CONNECT
NC = NO CONNECT
Figure 19. Single-Pole, Low-Pass Filter Using the Internal 100 kΩ Signal
Figure 18. Incremental Gain Trim
If the gain is raised using a resistor, as shown in Figure 17, the
corner frequency is lowered by the same factor as the gain is
raised. Thus, using a resistor of 200 kΩ (for which the gain
would be doubled), the corner frequency is now 0.796 Hz µF
(0.039 µF for a 20 Hz corner frequency.)
Internal Signal Overload Considerations
When configuring gain for values other than 20, the maximum
input voltage with respect to the supply voltage and ground
must be considered, since either the preamplifier or the output
buffer reaches its full-scale output (approximately VS – 0.2 V)
with large differential input voltages. The input of the AD8202
is limited to (VS – 0.2) ÷ 10 for overall gains ≤ 10, since the pre-
amplifier, with its fixed gain of ×10, reaches its full-scale output
before the output buffer. For gains greater than 10, the swing at
the buffer output reaches its full scale first and limits the
AD8202 input to (VS – 0.2) ÷ G, where G is the overall gain.
5V
OUT
+IN
NC +VS OUT
V
V
DIFF
2
C
AD8202
DIFF
2
V
CM
–IN GND A1
A2
LOW-PASS FILTERING
255kΩ
FC = 1Hz – µF
In many transducer applications, it is necessary to filter the sig-
nal to remove spurious high frequency components including
noise, or to extract the mean value of a fluctuating signal with a
peak-to-average ratio (PAR) greater than unity. For example, a
full-wave rectified sinusoid has a PAR of 1.57, a raised cosine
has a PAR of 2, and a half-wave sinusoid has a PAR of 3.14.
Signals having large spikes may have PARs of 10 or more.
C
NC = NO CONNECT
Figure 20. 2-Pole, Low-Pass Filter
A 2-pole filter (with a roll-off of 40 dB/decade) can be imple-
mented using the connections shown in Figure 20. This is a
Sallen-Key form based on a ×2 amplifier. It is useful to remember
that a 2-pole filter with a corner frequency f2 and a 1-pole filter
with a corner at f1 have the same attenuation at the frequency
(f22/f1). The attenuation at that frequency is 40 log (f2/f1), which is
illustrated in Figure 21. Using the standard resistor value shown
and equal capacitors (Figure 20), the corner frequency is conven-
iently scaled at 1 Hz µF (0.05 µF for a 20 Hz corner). A maximally
flat response occurs when the resistor is lowered to 196 kΩ and
the scaling is then 1.145 Hz µF. The output offset is raised by
approximately 5 mV (equivalent to 250 µV at the input pins).
When implementing a filter, the PAR should be considered so
that the output of the AD8202 preamplifier (A1) does not clip
before A2, since this nonlinearity would be averaged and appear
as an error at the output. To avoid this error, both amplifiers
should be made to clip at the same time. This condition is
achieved when the PAR is no greater than the gain of the sec-
ond amplifier (2 for the default configuration). For example, if a
PAR of 5 is expected, the gain of A2 should be increased to 5.
Rev. A | Page 10 of 12
AD8202
FREQUENCY
by a 1-pole, low-pass filter, here set with a corner frequency of
3.6 Hz, which provides about 30 dB of attenuation at 100 Hz. A
higher rate of attenuation can be obtained using a 2-pole filter
with fC = 20 Hz, as shown in Figure 23. Although this circuit
uses two separate capacitors, the total capacitance is less than
half that needed for the 1-pole filter.
40dB/DECADE
20dB/DECADE
INDUCTIVE
LOAD
40LOG (f /f )
2
1
5V
CLAMP
DIODE
OUTPUT
+IN
NC +VS OUT
A 1-POLE FILTER, CORNER f , AND
1
432kΩ
BATTERY
14V
A 2-POLE FILTER, CORNER f , HAVE
2
4-TERM
SHUNT
THE SAME ATTENUATION –40LOG (f /f )
C
2
1
AD8202
2
f /f
2 1
AT FREQUENCY
50kΩ
2
f /f
2 1
–IN GND A1
A2
f
f
1
2
POWER
DEVICE
127kΩ
Figure 21. Comparative Responses of 1-Pole and 2-Pole Low-Pass Filters
C
f
HIGH-LINE CURRENT SENSING WITH LPF AND
GAIN ADJUSTMENT
NC = NO CONNECT
COMMON
= 1Hz µF
C
(0.05µF FOR f = 20Hz)
C
Figure 22 is another refinement of Figure 2, including gain
adjustment and low-pass filtering.
Figure 23. 2-Pole Low-Pass Filter
DRIVING CHARGE REDISTRIBUTION ADCS
INDUCTIVE
LOAD
5V
OUT
CLAMP
DIODE
When driving CMOS ADCs such as those embedded in popular
microcontrollers, the charge injection (ΔQ) can cause a
significant deflection in the output voltage of the AD8202.
Though generally of short duration, this deflection may persist
until after the sample period of the ADC has expired due to the
relatively high open-loop output impedance of the AD8202.
Including an R-C network in the output can significantly reduce
the effect. The capacitor helps to absorb the transient charge,
effectively lowering the high frequency output impedance of the
AD8202. For these applications, the output signal should be
taken from the midpoint of the RLAG − CLAG combination as
shown in Figure 24.
4V/AMP
+IN
NC +VS OUT
191kΩ
BATTERY
14V
4-TERM
SHUNT
AD8202
20kΩ
–IN GND A1
A2
POWER
DEVICE
V
OS/IB
NULL
C
NC = NO CONNECT
COMMON
5% CALIBRATION RANGE
= 0.796Hz µF
(0.22µF FOR f = 3.6Hz)
f
C
C
Figure 22. High-Line Current Sensor Interface;
Gain = ×40, Single-Pole, Low-Pass Filter
Since the perturbations from the analog-to-digital converter are
small, the output impedance of the AD8202 appears to be low. The
transient response, therefore, has a time constant governed by the
product of the two LAG components, CLAG × RLAG. For the values
shown in Figure 24, this time constant is programmed at approxi-
mately 10 µs. Therefore, if samples are taken at several tens of
microseconds or more, there is negligible charge stack-up.
A power device that is either on or off controls the current in
the load. The average current is proportional to the duty cycle
of the input pulse and is sensed by a small value resistor. The
average differential voltage across the shunt is typically 100 mV,
although its peak value is higher by an amount that depends on
the inductance of the load and the control frequency. The
common-mode voltage, on the other hand, extends from
roughly 1 V above ground for the on condition to about 1.5 V
above the battery voltage in the off condition. The conduction
of the clamping diode regulates the common-mode potential
applied to the device. For example, a battery spike of 20 V may
result in an applied common-mode potential of 21.5 V to the
input of the devices.
5V
4
6
AD8202
+IN
–IN
RLAG
1kΩ
A2
MICROPROCESSOR
A/D
5
CLAG
0.01µF
10kΩ
10kΩ
To produce a full-scale output of 4 V, a gain ×40 is used, adjust-
able by 5% to absorb the tolerance in the shunt. There is
sufficient headroom to allow 10% overrange (to 4.4 V). The
roughly triangular voltage across the sense resistor is averaged
2
Figure 24. Recommended Circuit for Driving CMOS A/D
Rev. A | Page 11 of 12
AD8202
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2440)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
0.50 (0.0196)
0.25 (0.0099)
× 45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0.51 (0.0201)
0.31 (0.0122)
0° 1.27 (0.0500)
COPLANARITY
0.10
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 25. 8-Lead Standard Small Outline Package [SOIC]
Narrow Body (R-8)
Dimensions shown in millimeters (inches)
ORDERING GUIDE
Model
AD8202YR
AD8202YR-REEL
AD8202YR-REEL7
AD8202YCSURF
Temperature Package
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
Package Outline
8 Lead Standard Small Outline Package (SOIC)
8-Lead Standard Small Outline Package (SOIC)
8-Lead Standard Small Outline Package (SOIC)
Die
R-8
R-8
R-8
©
2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04981–0–11ꢀ04(A)
Rev. A | Page 12 of 12
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