AD820AN [ADI]
Single Supply, Rail to Rail Low Power FET-Input Op Amp; 单电源，轨至轨低功耗FET输入运算放大器
| 型号： | AD820AN |
| 厂家： | 
ADI |
| 描述： | Single Supply, Rail to Rail Low Power FET-Input Op Amp |
| 文件： | 总16页 (文件大小：240K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Single Supply, Rail to Rail
a
Low Power FET-Input Op Amp
AD820
CONNECTION DIAGRAMS
FEATURES
True Single Supply Operation
Output Swings Rail-to-Rail
8-Lead Plastic Mini-DIP
8-Lead SOIC
Input Voltage Range Extends Below Ground
Single Supply Capability from +3 V to +36 V
Dual Supply Capability from ؎1.5 V to ؎18 V
Excellent Load Drive
Capacitive Load Drive Up to 350 pF
Minimum Output Current of 15 mA
Excellent AC Performance for Low Power
800 A Max Quiescent Current
Unity Gain Bandwidth: 1.8 MHz
Slew Rate of 3.0 V/s
NULL
–IN
1
2
8
7
NC
+V
AD820
AD820
NC
–IN
+IN
1
2
3
8
7
6
NC
+V
S
S
+IN
3
4
6
5
V
OUT
V
OUT
TOP VIEW
(Not to Scale)
–V
S
TOP VIEW
(Not to Scale)
NULL
–V
S
4
5
NC
NC = NO CONNECT
allowing the AD820 to accommodate input signals below
Excellent DC Performance
ground in the single supply mode. Output voltage swing extends
to within 10 mV of each rail providing the maximum output
dynamic range.
800 V Max Input Offset Voltage
1 V/؇C Typ Offset Voltage Drift
25 pA Max Input Bias Current
Low Noise
Offset voltage of 800 µV max, offset voltage drift of 1 µV/°C, typ
input bias currents below 25 pA and low input voltage noise
provide dc precision with source impedances up to a Gigaohm.
1.8 MHz unity gain bandwidth, –93 dB THD at 10 kHz and
3 V/µs slew rate are provided for a low supply current of
800 µA. The AD820 drives up to 350 pF of direct capacitive
load and provides a minimum output current of 15 mA. This
allows the amplifier to handle a wide range of load conditions.
This combination of ac and dc performance, plus the outstand-
ing load drive capability, results in an exceptionally versatile
amplifier for the single supply user.
13 nV/√Hz @ 10 kHz
APPLICATIONS
Battery Powered Precision Instrumentation
Photodiode Preamps
Active Filters
12- to 14-Bit Data Acquisition Systems
Medical Instrumentation
Low Power References and Regulators
PRODUCT DESCRIPTION
The AD820 is a precision, low power FET input op amp that
can operate from a single supply of +3.0 V to 36 V, or dual
supplies of ±1.5 V to ±18 V. It has true single supply capability
with an input voltage range extending below the negative rail,
The AD820 is available in three performance grades. The A and
B grades are rated over the industrial temperature range of
–40°C to +85°C. There is 3 V grade—the AD820A-3V, rated
over the industrial temperature range.
The AD820 is offered in two varieties of 8-lead package: plastic
DIP, and surface mount (SOIC).
50
45
40
35
30
25
20
15
10
5
0
0
1
2
3
4
5
6
7
8
9
10
INPUT BIAS CURRENT – pA
Figure 2. Gain of +2 Amplifier; VS = +5, 0, VIN = 2.5 V Sine
Centered at 1.25 Volts
Figure 1. Typical Distribution of Input Bias Current
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1999
(VS = 0, 5 volts @ TA = +25؇C, VCM = 0 V, VOUT = 0.2 V unless otherwise noted)
AD820–SPECIFICATIONS
AD820A
Typ
AD820B
Typ
Parameter
Conditions
Min
Max
Min
Max
Units
DC PERFORMANCE
Initial Offset
Max Offset over Temperature
Offset Drift
Input Bias Current
at TMAX
Input Offset Current
at TMAX
0.1
0.5
2
2
0.5
2
0.8
1.2
0.1
0.5
2
2
0.5
2
0.4
0.9
mV
mV
µV/°C
pA
nA
pA
V
O = 0 V to 4 V
25
5
20
10
2.5
10
0.5
0.5
nA
Open-Loop Gain
V
O = 0.2 V to 4 V
RL = 100k
RL = 10k
RL = 1k
400
400
80
80
15
1000
150
30
500
400
80
80
15
1000
150
30
V/mV
V/mV
V/mV
V/mV
V/mV
V/mV
T
T
MIN to TMAX
MIN to TMAX
TMIN to TMAX
10
10
NOISE/HARMONIC PERFORMANCE
Input Voltage Noise
0.1 Hz to 10 Hz
f = 10 Hz
2
2
µV p-p
25
21
16
13
25
21
16
13
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
f = 100 Hz
f = 1 kHz
f = 10 kHz
Input Current Noise
0.1 Hz to 10 Hz
f = 1 kHz
Harmonic Distortion
f = 10 kHz
18
0.8
18
0.8
fA p-p
fA/√Hz
RL = 10k to 2.5 V
VO = 0.25 V to 4.75 V
–93
–93
dB
DYNAMIC PERFORMANCE
Unity Gain Frequency
Full Power Response
Slew Rate
1.8
210
3
1.8
210
3
MHz
kHz
V/µs
VO p-p = 4.5 V
Settling Time
to 0.1%
to 0.01%
V
O = 0.2 V to 4.5 V
1.4
1.8
1.4
1.8
µs
µs
INPUT CHARACTERISTICS
Common-Mode Voltage Range1
–0.2
–0.2
66
4
4
–0.2
–0.2
72
4
4
V
V
dB
dB
T
MIN to TMAX
CMRR
V
CM = 0 V to +2 V
80
80
T
MIN to TMAX
66
66
Input Impedance
Differential
Common Mode
1013ʈ0.5
1013ʈ0.5
1013ʈ2.8
ΩʈpF
ΩʈpF
1013ʈ2.8
OUTPUT CHARACTERISTICS
Output Saturation Voltage2
VOL–VEE
ISINK = 20 µA
5
7
10
14
20
55
80
110
160
500
1000
1500
1900
5
7
10
14
20
55
80
110
160
500
1000
1500
1900
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mA
mA
mA
pF
T
MIN to TMAX
CC–VOH
MIN to TMAX
OL–VEE
MIN to TMAX
CC–VOH
MIN to TMAX
OL–VEE
MIN to TMAX
CC–VOH
MIN to TMAX
Operating Output Current
MIN to TMAX
V
V
V
V
V
ISOURCE = 20 µA
ISINK = 2 mA
10
40
80
300
800
10
40
80
300
800
T
T
ISOURCE = 2 mA
ISINK = 15 mA
ISOURCE = 15 mA
T
T
T
15
12
15
12
T
Short Circuit Current
Capacitive Load Drive
25
350
25
350
POWER SUPPLY
Quiescent Current
Power Supply Rejection
TMIN to TMAX
TMIN to TMAX
VS+ = 5 V to 15 V
620
80
800
620
80
800
µA
dB
dB
70
70
66
66
–2–
REV. B
AD820
(VS = +5 volts @ TA = +25؇C, VCM = 0 V, VOUT = 0 V unless otherwise noted)
AD820A
Typ
AD820B
Typ
Parameter
Conditions
Min
Max
Min
Max
Units
DC PERFORMANCE
Initial Offset
Max Offset over Temperature
Offset Drift
Input Bias Current
at TMAX
Input Offset Current
at TMAX
0.1
0.5
2
2
0.5
2
0.8
1.5
0.3
0.5
2
2
0.5
2
0.4
1
mV
mV
µV/°C
pA
nA
pA
V
V
CM = –5 V to 4 V
O = 4 V to –4 V
25
5
20
10
2.5
10
0.5
0.5
nA
Open-Loop Gain
RL = 100k
RL = 10k
RL = 1k
400
400
80
80
20
1000
150
30
400
400
80
80
20
1000
150
30
V/mV
V/mV
V/mV
V/mV
V/mV
V/mV
T
T
MIN to TMAX
MIN to TMAX
TMIN to TMAX
10
10
NOISE/HARMONIC PERFORMANCE
Input Voltage Noise
0.1 Hz to 10 Hz
f = 10 Hz
2
2
µV p-p
25
21
16
13
25
21
16
13
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
f = 100 Hz
f = 1 kHz
f = 10 kHz
Input Current Noise
0.1 Hz to 10 Hz
f = 1 kHz
Harmonic Distortion
f = 10 kHz
18
0.8
18
0.8
fA p-p
fA/√Hz
RL = 10k
VO = ±4.5 V
–93
–93
dB
DYNAMIC PERFORMANCE
Unity Gain Frequency
Full Power Response
Slew Rate
1.9
105
3
1.8
105
3
MHz
kHz
V/µs
VO p-p = 9 V
Settling Time
to 0.1%
to 0.01%
V
O = 0 V to ±4.5 V
1.4
1.8
1.4
1.8
µs
µs
INPUT CHARACTERISTICS
Common-Mode Voltage Range1
–5.2
–5.2
66
4
4
–5.2
–5.2
72
4
4
V
V
dB
dB
T
MIN to TMAX
CMRR
V
CM = –5 V to +2 V
80
80
T
MIN to TMAX
66
66
Input Impedance
Differential
Common Mode
1013ʈ0.5
1013ʈ0.5
1013ʈ2.8
ΩʈpF
ΩʈpF
1013ʈ2.8
OUTPUT CHARACTERISTICS
Output Saturation Voltage2
VOL–VEE
ISINK = 20 µA
5
7
10
14
20
55
80
110
160
500
1000
1500
1900
5
7
10
14
20
55
80
110
160
500
1000
1500
1900
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mA
mA
mA
pF
T
MIN to TMAX
CC–VOH
MIN to TMAX
OL–VEE
MIN to TMAX
CC–VOH
MIN to TMAX
OL–VEE
MIN to TMAX
CC–VOH
MIN to TMAX
Operating Output Current
MIN to TMAX
V
V
V
V
V
ISOURCE = 20 µA
ISINK = 2 mA
10
40
80
300
800
10
40
80
300
800
T
T
ISOURCE = 2 mA
ISINK = 15 mA
ISOURCE = 15 mA
T
T
T
15
12
15
12
T
Short Circuit Current
Capacitive Load Drive
30
350
30
350
POWER SUPPLY
Quiescent Current
Power Supply Rejection
TMIN to TMAX
TMIN to TMAX
VS+ = 5 V to 15 V
650
80
800
620
80
800
µA
dB
dB
70
70
70
70
REV. B
–3–
(VS = ؎15 volts @ TA = +25؇C, VCM = 0 V, VOUT = 0 V unless otherwise noted)
AD820–SPECIFICATIONS
AD820A
Typ
AD820B
Typ
Parameter
Conditions
Min
Max
Min
Max
Units
DC PERFORMANCE
Initial Offset
Max Offset over Temperature
Offset Drift
Input Bias Current
0.4
0.5
2
2
3
0.3
0.5
2
1.0
2
mV
mV
µV/°C
pA
V
CM = 0 V
2
25
2
10
VCM = –10 V
VCM = 0 V
40
0.5
2
40
0.5
2
pA
at TMAX
5
20
2.5
10
nA
Input Offset Current
at TMAX
pA
0.5
0.5
nA
Open-Loop Gain
VO = +10 V to –10 V
RL = 100k
500
500
100
100
30
2000
500
45
500
500
100
100
30
2000
500
45
V/mV
V/mV
V/mV
V/mV
V/mV
V/mV
T
MIN to TMAX
RL = 10k
RL = 1k
TMIN to TMAX
TMIN to TMAX
20
20
NOISE/HARMONIC PERFORMANCE
Input Voltage Noise
0.1 Hz to 10 Hz
f = 10 Hz
2
2
µV p-p
25
21
16
13
25
21
16
13
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
f = 100 Hz
f = 1 kHz
f = 10 kHz
Input Current Noise
0.1 Hz to 10 Hz
f = 1 kHz
Harmonic Distortion
f = 10 kHz
18
0.8
18
0.8
fA p-p
fA/√Hz
RL = 10k
VO = ±10 V
–85
–85
dB
DYNAMIC PERFORMANCE
Unity Gain Frequency
Full Power Response
Slew Rate
1.9
45
3
1.9
45
3
MHz
kHz
V/µs
VO p-p = 20 V
Settling Time
to 0.1%
to 0.01%
VO = 0 V to ±10 V
4.1
4.5
4.1
4.5
µs
µs
INPUT CHARACTERISTICS
Common-Mode Voltage Range1
TMIN to TMAX
–15.2
–15.2
70
14
14
–15.2
–15.2
74
14
14
V
V
CMRR
VCM = –15 V to 12 V
80
90
dB
dB
TMIN to TMAX
70
74
Input Impedance
Differential
Common Mode
1013ʈ0.5
1013ʈ2.8
1013ʈ0.5
1013ʈ2.8
ΩʈpF
ΩʈpF
OUTPUT CHARACTERISTICS
Output Saturation Voltage2
VOL–VEE
ISINK = 20 µA
5
7
5
7
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mA
mA
mA
TMIN to TMAX
10
10
VCC–VOH
ISOURCE = 20 µA
ISINK = 2 mA
10
40
80
300
800
14
10
40
80
300
800
14
TMIN to TMAX
20
20
VOL–VEE
55
55
TMIN to TMAX
80
80
VCC–VOH
ISOURCE = 2 mA
ISINK = 15 mA
ISOURCE = 15 mA
110
160
500
1000
1500
1900
110
160
500
1000
1500
1900
TMIN to TMAX
VOL–VEE
TMIN to TMAX
VCC–VOH
TMIN to TMAX
Operating Output Current
TMIN to TMAX
20
15
20
15
Short Circuit Current
Capacitive Load Drive
45
350
45
350
POWER SUPPLY
Quiescent Current
Power Supply Rejection
TMIN to TMAX
TMIN to TMAX
VS+ = 5 V to 15 V
700
80
900
700
80
900
µA
dB
dB
70
70
70
70
–4–
REV. B
AD820
(VS = 0, 3 volts @ TA = +25؇C, VCM = 0 V, VOUT = 0.2 V unless otherwise noted)
AD820A-3V
Typ
Parameter
Conditions
Min
Max
Units
DC PERFORMANCE
Initial Offset
Max Offset over Temperature
Offset Drift
Input Bias Current
at TMAX
Input Offset Current
at TMAX
0.2
0.5
1
2
0.5
2
1
1.5
mV
mV
µV/°C
pA
nA
pA
V
V
CM = 0 V to +2 V
O = 0.2 V to 2 V
25
5
20
0.5
nA
Open-Loop Gain
RL = 100k
RL = 10k
RL = 1k
300
400
60
80
10
8
1000
150
30
V/mV
V/mV
V/mV
V/mV
V/mV
V/mV
T
T
MIN to TMAX
MIN to TMAX
TMIN to TMAX
NOISE/HARMONIC PERFORMANCE
Input Voltage Noise
0.1 Hz to 10 Hz
f = 10 Hz
2
µV p-p
25
21
16
13
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
f = 100 Hz
f = 1 kHz
f = 10 kHz
Input Current Noise
0.1 Hz to 10 Hz
f = 1 kHz
Harmonic Distortion
f = 10 kHz
18
0.8
fA p-p
fA/√Hz
RL = 10k to 1.5 V
VO = ±1.25 V
–92
dB
DYNAMIC PERFORMANCE
Unity Gain Frequency
Full Power Response
Slew Rate
Settling Time
to 0.1%
1.5
240
3
MHz
kHz
V/µs
V
V
O p-p = 2.5 V
O = 0.2 V to 2.5 V
1
1.4
µs
µs
to 0.01%
INPUT CHARACTERISTICS
Common-Mode Voltage Range1
–0.2
–0.2
60
2
2
V
V
dB
dB
T
MIN to TMAX
CMRR
V
CM = 0 V to +1 V
74
T
MIN to TMAX
60
Input Impedance
Differential
Common Mode
1013ʈ0.5
1013ʈ2.8
ΩʈpF
ΩʈpF
OUTPUT CHARACTERISTICS
Output Saturation Voltage2
VOL–VEE
ISINK = 20 µA
5
7
10
14
20
55
80
110
160
400
400
1000
1000
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mA
mA
mA
mA
pF
T
MIN to TMAX
CC–VOH
MIN to TMAX
OL–VEE
MIN to TMAX
CC–VOH
MIN to TMAX
OL–VEE
MIN to TMAX
CC–VOH
MIN to TMAX
Operating Output Current
MIN to TMAX
Short Circuit Current
MIN to TMAX
V
V
V
V
V
ISOURCE = 20 µA
ISINK = 2 mA
10
40
80
200
500
T
T
ISOURCE = 2 mA
ISINK = 10 mA
ISOURCE = 10 mA
T
T
T
15
12
18
15
T
25
T
Capacitive Load Drive
350
POWER SUPPLY
Quiescent Current
Power Supply Rejection
TMIN to TMAX
T
MIN to TMAX
620
80
800
µA
dB
dB
VS+ = 3 V to 15 V
70
70
REV. B
–5–
AD820–SPECIFICATIONS
NOTES
1This is a functional specification. Amplifier bandwidth decreases when the input common-mode voltage is driven in the range (+ VS – 1 V) to +VS.
Common-mode error voltage is typically less than 5 mV with the common-mode voltage set at 1 volt below the positive supply.
2VOL–VEE is defined as the difference between the lowest possible output voltage (VOL) and the minus voltage supply rail (VEE).
VCC–VOH is defined as the difference between the highest possible output voltage (VOH) and the positive supply voltage (VCC).
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS1
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
28-Lead Plastic DIP Package: θJA = 90°C/Watt
Internal Power Dissipation2
Plastic DIP (N) . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 Watts
SOIC (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 Watts
Input Voltage . . . . . . . . . . . . . . (+VS + 0.2 V) to – (20 V + VS)
Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ±30 V
Storage Temperature Range (N) . . . . . . . . . –65°C to +125°C
Storage Temperature Range (R) . . . . . . . . . –65°C to +150°C
Operating Temperature Range
8-Lead SOIC Package: θJA = 160°C/Watt
AD820A/B . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Lead Temperature Range
(Soldering 60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+260°C
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Options
Model
AD820AN
AD820BN
AD820AR
AD820BR
AD820AR-3V
AD820AN-3V
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
8-Lead Plastic Mini-DIP
8-Lead Plastic Mini-DIP
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
N-8
N-8
R-8
R-8
R-8
N-8
8-Lead Plastic Mini-DIP
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD820 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–6–
REV. B
Typical Characteristics–AD820
50
40
30
20
10
0
5
V
= 0V, 5V
S
0
V
= 0V, +5V AND ؎5V
S
V
= ؎5V
S
–5
–0.5 –0.4 –0.3 –0.2 –0.1
0
0.1
0.2
0.3
0.4
0.5
–5
–4
–3
–2
–1
0
1
2
3
4
5
OFFSET VOLTAGE – mV
COMMON-MODE VOLTAGE – Volts
Figure 3. Typical Distribution of Offset Voltage (248 Units)
Figure 6. Input Bias Current vs. Common-Mode
Voltage; VS = +5 V, 0 V and VS = ±5 V
48
1k
V
V
= ؎5V
S
S
40
32
24
16
8
= ؎15V
100
10
1
0
–10
0.1
–16
–8
–6
–4
–2
0
2
4
6
8
10
–12
–8
–4
0
4
8
12
16
COMMON-MODE VOLTAGE – Volts
OFFSET VOLTAGE DRIFT – V/؇C
Figure 4. Typical Distribution of Offset Voltage Drift
(120 Units)
Figure 7. Input Bias Current vs. Common-Mode
Voltage; VS = ±15 V
50
45
40
35
30
25
20
15
10
5
100k
10k
1k
100
10
1
0
0.1
20
0
1
2
3
4
5
6
7
8
9
10
40
60
80
100
120
140
INPUT BIAS CURRENT – pA
TEMPERATURE – ؇C
Figure 5. Typical Distribution of Input Bias Current
(213 Units)
Figure 8. Input Bias Current vs. Temperature;
VS = 5 V, VCM = 0
REV. B
–7–
AD820–Typical Characteristics
40
20
10M
POS RAIL
NEG RAIL
R
= 2k⍀
L
V
= ؎15V
S
R
= 20k⍀
1M
100k
10k
L
V
= 0V, 5V
S
POS
RAIL
0
POS RAIL
V
= 0V, 3V
S
–20
–40
NEG RAIL
NEG RAIL
R
= 100k⍀
L
100
1k
10k
100k
0
60
120
180
240
300
LOAD RESISTANCE – ⍀
OUTPUT VOLTAGE FROM VOLTAGE RAILS – mV
Figure 9. Open-Loop Gain vs. Load Resistance
Figure 12. Input Error Voltage with Output Voltage within
300 mV of Either Supply Rail for Various Resistive Loads;
VS = ±5 V
10M
1k
100
10
V
V
= ؎15V
R
= 100k⍀
= 10k⍀
S
L
1M
100k
10k
= 0V, 5V
S
V
= ؎15V
S
S
R
L
V
= 0V, 5V
V
= ؎15V
S
R
= 600⍀
L
V
= 0V, 5V
S
1
1
10
100
1k
10k
–60 –40 –20
0
20
40
60
80
100 120 140
FREQUENCY – Hz
TEMPERATURE – ؇C
Figure 10. Open-Loop Gain vs. Temperature
Figure 13. Input Voltage Noise vs. Frequency
–40
300
200
R
A
= 10k⍀
L
–50
–60
= –1
CL
100
R
= 10k⍀
L
R
= 100k⍀
V
= 0V, 3V; V
= 2.5V p-p
L
S
OUT
–70
0
–80
V
= ؎15V; V
= 20V p-p
S
OUT
–100
–90
V
V
= ؎5V; V
= 9V p-p
S
OUT
R
4
= 600⍀
–200
–300
L
–100
= 0V, 5V; V
= 4.5V p-p
S
OUT
–110
100
1k
10k
FREQUENCY – Hz
100k
–16
–12
–8
–4
0
8
12
16
OUTPUT VOLTAGE – Volts
Figure 11. Input Error Voltage vs. Output Voltage for
Resistive Loads
Figure 14. Total Harmonic Distortion vs. Frequency
REV. B
–8–
AD820
100
80
100
80
60
40
20
0
100
90
80
70
60
50
40
30
20
10
0
PHASE
60
40
20
0
V
V
= 0V, 5V
AND
= 0V, 3V
V
= ؎15V
S
GAIN
S
S
R
C
= 2k⍀
= 100pF
L
L
–20
–20
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
FREQUENCY – Hz
FREQUENCY – Hz
Figure 15. Open-Loop Gain and Phase Margin vs.
Frequency
Figure 18. Common-Mode Rejection vs. Frequency
5
4
1k
A
= +1
= ؎15V
CL
V
S
100
10
POSITIVE
RAIL
NEGATIVE
RAIL
3
2
1
0
+25؇C
1
+125؇C
+125؇C
0.1
0.01
–55؇C
–55؇C
100
1k
10k
100k
1M
10M
–1
0
1
2
3
FREQUENCY – Hz
COMMON-MODE VOLTAGE FROM SUPPLY RAILS – Volts
Figure 16. Output Impedance vs. Frequency
Figure 19. Absolute Common-Mode Error vs. Common-
Mode Voltage from Supply Rails (VS – VCM
)
16
12
1000
100
10
1%
8
4
V
– V
OH
S
0
–4
0.1%
0.01%
ERROR
V
– V
OL
S
–8
1%
1.0
–12
–16
0.0
0
2.0
3.0
4.0
5.0
0.001
0.01
0.1
1
10
100
LOAD CURRENT – mA
SETTLING TIME – s
Figure 17. Output Swing and Error vs. Settling Time
Figure 20. Output Saturation Voltage vs Load Current
-
REV. B
–9–
AD820–Typical Characteristics
1000
120
110
100
90
80
70
60
50
40
30
20
10
0
I
= 10mA
SOURCE
I
= 10mA
SINK
100
10
1
I
= 1mA
SOURCE
I
= 1mA
SINK
+PSRR
–PSRR
I
= 10A
SOURCE
I
= 10A
SINK
–60 –40 –20
0
20
40
60
80
100 120 140
10
100
1k
10k
100k
1M
10M
TEMPERATURE – ؇C
FREQUENCY – Hz
Figure 21. Output Saturation Voltage vs. Temperature
Figure 24. Power Supply Rejection vs. Frequency
30
80
70
R1 = 2k⍀
25
V
= ؎15V
S
60
50
40
30
20
10
0
V
= ؎15V
S
20
15
10
5
–OUT
+
V
= ؎15V
S
V
V
= 0V, 5V
= 0V, 3V
S
S
–
–
V
= 0V, 5V
= 0V ,3V
+
+
S
V
= 0V, 3V
V
= 0V, 5V
S
S
V
S
0
10k
–60 –40 –20
0
20
40
60
80
100 120 140
100k
1M
10M
FREQUENCY – Hz
TEMPERATURE – ؇C
Figure 22. Short Circuit Current Limit vs. Temperature
Figure 25. Large Signal Frequency Response
800
T = +125؇C
700
T = +25؇C
600
T = –55؇C
500
400
300
200
100
0
0
4
8
12
16
20
24
28
30
36
TOTAL SUPPLY VOLTAGE – Volts
Figure 23. Quiescent Current vs. Supply Voltage vs.
Temperature
REV. B
–10–
AD820
+V
7
S
0.01F
3
2
V
IN
6
AD820
V
OUT
R
100pF
L
0.01F
4
–V
S
Figure 26. Unity-Gain Follower
Figure 29. Large Signal Response Unity Gain Follower;
VS = ±15 V, RL = 10 kΩ
Figure 27. 20 V, 25 kHz Sine Input; Unity Gain Follower;
RL = 600 Ω, VS = ±15 V
Figure 30. Small Signal Response Unity Gain Follower;
VS = ±15 V, RL = 10 kΩ
GND
GND
Figure 28. VS = +5 V, 0 V; Unity Gain Follower Response
to 0 V to 4 V Step
Figure 31. VS = +5 V, 0 V; Unity Gain Follower Response
to 0 V to 5 V Step
REV. B
–11–
AD820
+V
7
S
0.01F
3
2
V
IN
6
AD820
V
OUT
100pF
R
L
4
GND
Figure 32. Unity-Gain Follower
Figure 35. VS = +5 V, 0 V; Unity Gain Follower Response
to 40 mV Step Centered 40 mV Above Ground
10k⍀
20k⍀
100
V
IN
V
+V
S
OUT
0.01F
7
2
3
6
AD820
100pF
R
L
4
GND
Figure 33. Gain of Two Inverter
Figure 36. VS = +5 V, 0 V; Gain of Two Inverter Response
to 20 mV Step, Centered 20 mV Below Ground
GND
GND
Figure 34. VS = +5 V, 0 V; Gain of Two Inverter Response
to 2.5 V Step Centered –1.25 V Below Ground
Figure 37. VS = 3 V, 0 V; Gain of Two Inverter, VIN = 1.25 V,
25 kHz, Sine Wave Centered at –0.75 V, RL = 600 Ω
–12–
REV. B
AD820
APPLICATION NOTES
INPUT CHARACTERISTICS
A current limiting resistor should be used in series with the
input of the AD820 if there is a possibility of the input voltage
exceeding the positive supply by more than 300 mV, or if an
input voltage will be applied to the AD820 when ±VS = 0. The
amplifier will be damaged if left in that condition for more than
10 seconds. A 1 kΩ resistor allows the amplifier to withstand up
to 10 volts of continuous overvoltage, and increases the input
voltage noise by a negligible amount.
In the AD820, n-channel JFETs are used to provide a low off-
set, low noise, high impedance input stage. Minimum input
common-mode voltage extends from 0.2 V below –VS to 1 V
less than +VS. Driving the input voltage closer to the positive
rail will cause a loss of amplifier bandwidth (as can be seen by
comparing the large signal responses shown in Figures 28 and
31) and increased common-mode voltage error as illustrated in
Figure 19.
Input voltages less than –VS are a completely different story.
The amplifier can safely withstand input voltages 20 volts below
the minus supply voltage as long as the total voltage from the
positive supply to the input terminal is less than 36 volts. In
addition, the input stage typically maintains picoamp level input
currents across that input voltage range.
The AD820 does not exhibit phase reversal for input voltages
up to and including +VS. Figure 38a shows the response of an
AD820 voltage follower to a 0 V to +5 V (+VS) square wave
input. The input and output are superimposed. The output
polarity tracks the input polarity up to +VS—no phase reversal.
The reduced bandwidth above a 4 V input causes the rounding
of the output wave form. For input voltages greater than +VS, a
resistor in series with the AD820’s plus input will prevent phase
reversal, at the expense of greater input voltage noise. This is
illustrated in Figure 38b.
The AD820 is designed for 13 nV/√Hz wideband input voltage
noise and maintains low noise performance to low frequencies
(refer to Figure 13). This noise performance, along with the
AD820’s low input current and current noise means that the
AD820 contributes negligible noise for applications with source
resistances greater than 10 kΩ and signal bandwidths greater
than 1 kHz. This is illustrated in Figure 39.
Since the input stage uses n-channel JFETs, input current dur-
ing normal operation is negative; the current flows out from the
input terminals. If the input voltage is driven more positive than
+VS – 0.4 V, the input current will reverse direction as internal
device junctions become forward biased. This is illustrated in
Figure 6.
100k
WHENEVER JOHNSON NOISE IS GREATER THAN
AMPLIFIER NOISE, AMPLIFIER NOISE CAN BE
CONSIDERED NEGLIGIBLE FOR APPLICATION.
10k
1kHz
1k
RESISTOR JOHNSON
NOISE
100
10
10Hz
1
AMPLIFIER-GENERATED
NOISE
GND
0.1
10k
100k
1M
10M
100M
1G
10G
SOURCE IMPEDANCE – ⍀
(a)
Figure 39. Total Noise vs. Source Impedance
OUTPUT CHARACTERISTICS
The AD820’s unique bipolar rail-to-rail output stage swings
within 5 mV of the minus supply and 10 mV of the positive
supply with no external resistive load. The AD820’s approxi-
mate output saturation resistance is 40 Ω sourcing and 20 Ω
sinking. This can be used to estimate output saturation voltage
when driving heavier current loads. For instance, when sourcing
5 mA, the saturation voltage to the positive supply rail will be
200 mV, when sinking 5 mA, the saturation voltage to the
minus rail will he 100 mV.
+V
S
GND
(b)
The amplifier’s open-loop gain characteristic will change as a
function of resistive load, as shown in Figures 9 through 12. For
load resistances over 20 kΩ, the AD820’s input error voltage is
virtually unchanged until the output voltage is driven to 180 mV
of either supply.
+5V
R
P
V
IN
AD820
V
OUT
If the AD820’s output is driven hard against the output satura-
tion voltage, it will recover within 2 µs of the input returning to
the amplifier’s linear operating region.
Figure 38. (a) Response with RP = 0; VIN from 0 to +VS
Figure 36. (b) VIN = 0 to +VS + 200 mV
VOUT = 0 to +VS
RP = 49.9 kΩ
REV. B
–13–
AD820
+V
7
Direct capacitive load will interact with the amplifier’s effective
output impedance to form an additional pole in the amplifier’s
feedback loop, which can cause excessive peaking on the pulse
response or loss of stability. Worst case is when the amplifier is
used as a unity gain follower. Figure 40 shows the AD820’s
pulse response as a unity gain follower driving 350 pF. This
amount of overshoot indicates approximately 20 degrees of
phase margin—the system is stable, but is nearing the edge.
Configurations with less loop gain, and as a result less loop
bandwidth, will be much less sensitive to capacitance load ef-
fects. Figure 41 is a plot of capacitive load that will result in a
20 degree phase margin versus noise gain for the AD820. Noise
gain is the inverse of the feedback attenuation factor provided
by the feedback network in use.
S
0.01F
3
2
V
IN
100⍀
20k⍀
6
AD820
V
OUT
0.01F
4
–V
S
20pF
Figure 42. Extending Unity Gain Follower Capacitive Load
Capability Beyond 350 pF
OFFSET VOLTAGE ADJUSTMENT
The AD820’s offset voltage is low, so external offset voltage
nulling is not usually required. Figure 43 shows the recom-
mended technique for AD820’s packaged in plastic DIPs.
Adjusting offset voltage in this manner will change the offset
voltage temperature drift by 4 µV/°C for every millivolt of in-
duced offset. The null pins are not functional for AD820s in the
SO-8 “R” package.
+V
S
7
3
6
AD820
5
1
2
20k⍀
Figure 40. Small Signal Response of AD820 as Unity Gain
Follower Driving 350 pF Capacitive Load
4
–V
S
5
4
3
Figure 43. Offset Null
APPLICATIONS
Single Supply Half-Wave and Full-Wave Rectifiers
An AD820 configured as a unity gain follower and operated
with a single supply can be used as a simple half-wave rectifier.
The AD820’s inputs maintain picoamp level input currents even
when driven well below the minus supply. The rectifier puts that
behavior to good use, maintaining an input impedance of over
1011 Ω for input voltages from 1 volt from the positive supply to
20 volts below the negative supply.
2
1
The full and half-wave rectifier shown in Figure 44 operates as
follows: when VIN is above ground, R1 is bootstrapped through
the unity gain follower A1 and the loop of amplifier A2. This
forces the inputs of A2 to be equal, thus no current flows through
R1 or R2, and the circuit output tracks the input. When VIN is
below ground, the output of A1 is forced to ground. The non-
inverting input of amplifier A2 sees the ground level output of
A1, therefore A2 operates as a unity gain inverter. The output at
node C is then a full-wave rectified version of the input. Node B
is a buffered half-wave rectified version of the input. Input volt-
ages up to ±18 volts can be rectified, depending on the voltage
supply used.
300
1k
3k
10k
30k
CAPACITIVE LOAD FOR 20؇ PHASE MARGIN – pF
R
F
R
I
Figure 41. Capacitive Load Tolerance vs. Noise Gain
Figure 42 shows a possible configuration for extending capaci-
tance load drive capability for a unity gain follower. With these
component values, the circuit will drive 5,000 pF with a 10%
overshoot.
–14–
REV. B
AD820
Low Power Three-Pole Sallen Key Low-Pass Filter
R1
100k⍀
R2
100k⍀
The AD820’s high input impedance makes it a good selection
for active filters. High value resistors can be used to construct
low frequency filters with capacitors much less than 1 µF. The
AD820’s picoamp level input currents contribute minimal dc
errors.
+V
S
+V
0.01F
S
7
0.01F
3
2
A
7
C
3
2
6
A2
V
6
IN
FULL-WAVE
RECTIFIED OUTPUT
Figure 46 shows an example, a 10 Hz three-pole Sallen Key
Filter. The high value used for R1 minimizes interaction with
signal source resistance. Pole placement in this version of the
filter minimizes the Q associated with the two-pole section of
the filter. This eliminates any peaking of the noise contribution
of resistors R1, R2, and R3, thus minimizing the inherent out-
put voltage noise of the filter.
A1
AD820
4
AD820
4
B
HALF-WAVE
RECTIFIED OUTPUT
C2
0.022F
A
+V
S
0.01F
R2
243k⍀
R3
243k⍀
R1
243k⍀
7
3
2
B
C
V
IN
C3
0.022F
C1
6
0.022F
AD820
V
OUT
0.01F
4
–V
S
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
Figure 44. Single Supply Half- and Full-Wave Rectifier
4.5 Volt Low Dropout, Low Power Reference
The rail-to-rail performance of the AD820 can be used to pro-
vide low dropout performance for low power reference circuits
powered with a single low voltage supply. Figure 45 shows a
4.5 volt reference using the AD820 and the AD680, a low power
2.5 volt bandgap reference. R2 and R3 set up the required gain
of 1.8 to develop the 4.5 volt output. R1 and C2 form a low-
pass RC filter to reduce the noise contribution of the AD680.
+2.5V
OUTPUT
–100
0.1
1
10
100
1k
+4.5V
FREQUENCY – Hz
OUTPUT
U2
6
+5V
AD820
Figure 46. 10 Hz Sallen Key Low-Pass Filter
R2
80k⍀
7
4
(20k⍀)
2
+2.5V ؎10mV
3
2
C3
3
6
U1
10F/25V
AD680
R1
100k⍀
R3
100k⍀
(25k⍀)
C2
0.1F FILM
4
C1
0.1F
REF
COMMON
Figure 45. Single Supply 4.5 Volt Low Dropout Reference
With a 1 mA load, this reference maintains the 4.5 volt output
with a supply voltage down to 4.7 volts. The amplitude of the
recovery transient for a 1 mA to 10 mA step change in load
current is under 20 mV, and settles out in a few microseconds.
Output voltage noise is less than 10 µV rms in a 25 kHz noise
bandwidth.
REV. B
–15–
AD820
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Mini-DIP Package
(N-8)
0.39 (9.91)
MAX
8
5
0.31
(7.87)
0.25
(6.35)
1
4
PIN 1
0.30 (7.62)
REF
0.10 (2.54)
BSC
0.035 ؎ 0.01
(0.89 ؎ 0.25)
0.165 ؎ 0.01
(4.19 ؎ 0.25)
0.011 ؎0.003
(0.28 ؎ 0.08)
0.18 ؎0.03
(4.57 ؎ 0.75)
0.125 (3.18)
MIN
15؇
0؇
0.018 ؎0.003
(0.46 ؎ 0.08)
SEATING
PLANE
0.033
(0.84)
NOM
SOIC Package
(R-8)
0.150 (3.81)
8
1
5
4
0.244 (6.20)
0.228 (5.79)
0.157 (3.99)
0.150 (3.81)
0.020 (0.051)
؋
45؇ CHAMF
PIN 1
0.190 (4.82)
0.170 (4.32)
0.197 (5.01)
0.189 (4.80)
8؇
0؇
0.102 (2.59)
0.094 (2.39)
0.090
(2.29)
0.010 (0.25)
0.004 (0.10)
10؇
0؇
0.030 (0.76)
0.018 (0.46)
0.050 0.019 (0.48)
SEATING
PLANE
0.098 (0.2482)
0.075 (0.1905)
(1.27)
0.014 (0.36)
BSC
–16–
REV. B
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