AD8221ARMZ-REEL [ADI]
INSTRUMENTATION AMPLIFIER, 60uV OFFSET-MAX, 0.825MHz BAND WIDTH, PDSO8, MO-187AA, MSOP-8;
| 型号： | AD8221ARMZ-REEL |
| 厂家： | 
ADI |
| 描述： | INSTRUMENTATION AMPLIFIER, 60uV OFFSET-MAX, 0.825MHz BAND WIDTH, PDSO8, MO-187AA, MSOP-8 仪表放大器 |
| 文件： | 总24页 (文件大小：718K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Precision Instrumentation Amplifier
AD8221
CONNECTION DIAGRAM
FEATURES
Easy to use
1
2
3
4
8
7
6
5
+V
V
–IN
S
Available in space-saving MSOP
Gain set with 1 external resistor (gain range 1 to 1000)
Wide power supply range: 2.3 V to 18 V
Temperature range for specified performance:
−40°C to +85°C
R
G
OUT
R
REF
–V
G
+IN
S
AD8221
TOP VIEW
Figure 1.
Operational up to 125°C1
Excellent AC specifications
80 dB minimum CMRR to 10 kHz ( G = 1)
825 kHz, –3 dB bandwidth (G = 1)
2 V/μs slew rate
120
110
100
90
AD8221
Low noise
8 nV/√Hz, @ 1 kHz, maximum input voltage noise
0.25 μV p-p input noise (0.1 Hz to 10 Hz)
High accuracy dc performance (AD8221BR)
90 dB minimum CMRR (G = 1)
25 μV maximum input offset voltage
0.3 μV/°C maximum input offset drift
0.4 nA maximum input bias current
COMPETITOR 1
80
70
60
COMPETITOR 2
50
APPLICATIONS
40
10
100
1k
FREQUENCY (Hz)
10k
100k
Weigh scales
Industrial process controls
Bridge amplifiers
Figure 2. Typical CMRR vs. Frequency for G = 1
Precision data acquisition systems
Medical instrumentation
Strain gages
Low voltage offset, low offset drift, low gain drift, high gain
accuracy, and high CMRR make this part an excellent choice
in applications that demand the best dc performance possible,
such as bridge signal conditioning.
Transducer interfaces
GENERAL DESCRIPTION
Programmable gain affords the user design flexibility. A single
resistor sets the gain from 1 to 1000. The AD8221 operates on
both single and dual supplies and is well suited for applications
where 10 ꢀ input voltages are encountered.
The AD8221 is a gain programmable, high performance
instrumentation amplifier that delivers the industry’s highest
CMRR over frequency in its class. The CMRR of instrumentation
amplifiers on the market today falls off at 200 Hz. In contrast,
the AD8221 maintains a minimum CMRR of 80 dB to 10 kHz
for all grades at G = 1. High CMRR over frequency allows the
AD8221 to reject wideband interference and line harmonics,
greatly simplifying filter requirements. Possible applications
include precision data acquisition, biomedical analysis, and
aerospace instrumentation.
The AD8221 is available in a low cost 8-lead SOIC and 8-lead
MSOP, both of which offer the industry’s best performance. The
MSOP requires half the board space of the SOIC, making it ideal
for multichannel or space-constrained applications.
Performance is specified over the entire industrial temperature
range of −40°C to +85°C for all grades. Furthermore, the AD8221
is operational from −40°C to +125°C1.
1 See Typical Performance Characteristics for expected operation from
85°C to 125°C.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2003–2007 Analog Devices, Inc. All rights reserved.
AD8221
TABLE OF CONTENTS
Features .............................................................................................. 1
Layout .......................................................................................... 17
Reference Terminal .................................................................... 18
Power Supply Regulation and Bypassing ................................ 18
Input Bias Current Return Path ............................................... 18
Input Protection ......................................................................... 18
RF Interference ........................................................................... 19
Precision Strain Gage................................................................. 19
Applications....................................................................................... 1
General Description......................................................................... 1
Connection Diagram ....................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 8
Thermal Characteristics .............................................................. 8
ESD Caution.................................................................................. 8
Typical Performance Characteristics ............................................. 9
Theory of Operation ...................................................................... 16
Gain Selection............................................................................. 17
Conditioning 10 ꢀ Signals for a +5 ꢀ Differential Input
ADC ............................................................................................. 19
AC-Coupled Instrumentation Amplifier................................ 20
Outline Dimensions....................................................................... 21
Ordering Guide .......................................................................... 22
REVISION HISTORY
9/07—Rev. A to Rev. B
Changes to Features.......................................................................... 1
Changes to Table 1 Layout............................................................... 3
Changes to Table 2 Layout............................................................... 5
Changes to Figure 15...................................................................... 11
Changes to Figures 32 .................................................................... 13
Changes to Figure 33, Figure 34, and Figure 35 ......................... 14
Updated Outline Dimensions....................................................... 21
Changes to Ordering Guide .......................................................... 22
11/03—Rev. 0 to Rev. A
Changes to Features.......................................................................... 1
Changes to Specifications Section.................................................. 4
Changes to Theory of Operation Section.................................... 13
Changes to Gain Selection Section............................................... 14
10/03—Revision 0: Initial Version
Rev. B | Page 2 of 24
AD8221
SPECIFICATIONS
ꢀS = 15 ꢀ, ꢀREF = 0 ꢀ, TA = 25°C, G = 1, RL = 2 kΩ, unless otherwise noted.
Table 1.
AR Grade
BR Grade
Parameter
Conditions
Min
Typ
Max
Min
Typ
Max
Unit
COMMON-MODE REJECTION RATIO
CMRR DC to 60 Hz with 1 kΩ
Source Imbalance
VCM = −10 V to +10 V
G = 1
G = 10
G = 100
G = 1000
CMRR at 10 kHz
G = 1
G = 10
G = 100
G = 1000
80
90
dB
dB
dB
dB
100
120
130
110
130
140
VCM = −10 V to +10 V
80
90
100
100
80
dB
dB
dB
dB
100
110
110
RTI noise =
√
NOISE
eNI2 + (eNO/G)2
Voltage Noise, 1 kHz
Input Voltage Noise, eNI
Output Voltage Noise, eNO
RTI
VIN+, VIN−, VREF = 0
8
75
8
75
nV/√Hz
nV/√Hz
f = 0.1 Hz to 10 Hz
G = 1
G = 10
G = 100 to 1000
Current Noise
2
2
μV p-p
μV p-p
μV p-p
fA/√Hz
pA p-p
0.5
0.25
40
6
0.5
0.25
40
6
f = 1 kHz
f = 0.1 Hz to 10 Hz
VOLTAGE OFFSET1
Input Offset, VOSI
Over Temperature
Average TC
Output Offset, VOSO
Over Temperature
Average TC
VS = 5 V to 15 V
T = −40°C to +85°C
60
86
0.4
300
0.66
6
25
45
0.3
200
0.45
5
μV
μV
μV/°C
μV
mV
VS = 5 V to 15 V
T = −40°C to +85°C
μV/°C
Offset RTI vs. Supply (PSR)
G = 1
G = 10
G = 100
G = 1000
VS = 2.3 V to 18 V
90
110
120
130
140
94
110
130
140
150
dB
dB
dB
dB
110
124
130
114
130
140
INPUT CURRENT
Input Bias Current
Over Temperature
Average TC
Input Offset Current
Over Temperature
Average TC
0.5
1.5
2.0
0.2
0.4
1
nA
nA
pA/°C
nA
nA
T = −40°C to +85°C
T = −40°C to +85°C
1
0.2
1
0.1
0.6
0.8
0.4
0.6
1
1
pA/°C
REFERENCE INPUT
RIN
IIN
Voltage Range
Gain to Output
20
50
20
50
kΩ
μA
V
VIN+, VIN−, VREF = 0
60
+VS
0.0001
60
+VS
0.0001
–VS
–VS
1
1
V/V
Rev. B | Page 3 of 24
AD8221
AR Grade
BR Grade
Parameter
Conditions
Min
Typ
Max
Min
Typ
Max
Unit
POWER SUPPLY
Operating Range
Quiescent Current
Over Temperature
DYNAMIC RESPONSE
Small Signal −3 dB Bandwidth
G = 1
VS = 2.3 V to 18 V
T = −40°C to +85°C
2.3
18
2.3
18
V
mA
mA
0.9
1
1
0.9
1
1
1.2
1.2
825
562
100
14.7
825
562
100
14.7
kHz
kHz
kHz
kHz
G = 10
G = 100
G = 1000
Settling Time 0.01%
G = 1 to 100
G = 1000
Settling Time 0.001%
G = 1 to 100
G = 1000
10 V step
10 V step
10
80
10
80
μs
μs
13
110
2
13
110
2
μs
μs
V/μs
V/μs
Slew Rate
G = 1
G = 5 to 100
G = 1 + (49.4 kΩ/RG)
1.5
2
1.5
2
2.5
2.5
GAIN
Gain Range
1
1000
1
1000
V/V
Gain Error
VOUT 10 V
G = 1
G = 10
G = 100
G = 1000
0.03
0.3
0.3
0.02
0.15
0.15
0.15
%
%
%
%
0.3
Gain Nonlinearity
G = 1 to 10
G = 100
VOUT = −10 V to +10 V
RL = 10 kΩ
RL = 10 kΩ
RL = 10 kΩ
RL = 2 kΩ
3
5
10
10
10
15
40
95
3
5
10
10
10
15
40
95
ppm
ppm
ppm
ppm
G = 1000
G = 1 to 100
Gain vs. Temperature
G = 1
3
10
–50
2
5
–50
ppm/°C
ppm/°C
G > 12
INPUT
Input Impedance
Differential
100||2
100||2
100||2
100||2
GΩ||pF
GΩ||pF
V
V
V
V
Common Mode
Input Operating Voltage Range3
Over Temperature
Input Operating Voltage Range
Over Temperature
OUTPUT
VS = 2.3 V to 5 V
T = −40°C to +85°C
VS = 5 V to 18 V
T =−40°C to +85°C
RL = 10 kΩ
–VS + 1.9
–VS + 2.0
–VS + 1.9
–VS + 2.0
+VS − 1.1 –VS + 1.9
+VS − 1.2 –VS + 2.0
+VS − 1.2 –VS + 1.9
+VS − 1.2 –VS + 2.0
+VS − 1.1
+VS − 1.2
+VS − 1.2
+VS − 1.2
Output Swing
Over Temperature
Output Swing
Over Temperature
Short-Circuit Current
VS = 2.3 V to 5 V
T = −40°C to +85°C
VS = 5 V to 18 V
T = –40°C to +85°C
–VS + 1.1
–VS + 1.4
–VS + 1.2
–VS + 1.6
+VS − 1.2 –VS + 1.1
+Vs − 1.3 –VS + 1.4
+VS − 1.4 –VS + 1.2
+VS − 1.5 –VS + 1.6
+VS − 1.2
+VS − 1.3
+VS − 1.4
+VS − 1.5
V
V
V
V
18
18
mA
Rev. B | Page 4 of 24
AD8221
AR Grade
Typ Max
BR Grade
Parameter
Conditions
Min
Min
Typ
Max
Unit
TEMPERATURE RANGE
Specified Performance
Operating Range4
–40
–40
+85
+125
–40
–40
+85
+125
°C
°C
1 Total RTI VOS = (VOSI) + (VOSO/G).
2 Does not include the effects of external resistor RG.
3 One input grounded. G = 1.
4 See Typical Performance Characteristics for expected operation between 85°C to 125°C.
Table 2.
ARM Grade
Parameter
Conditions
Unit
Min
Typ
Max
COMMON-MODE REJECTION RATIO (CMRR)
CMRR DC to 60 Hz with 1 kΩ Source Imbalance
VCM = −10 V to +10 V
G = 1
G = 10
G = 100
G = 1000
CMRR at 10 kHz
G = 1
G = 10
G = 100
G = 1000
80
dB
dB
dB
dB
100
120
130
VCM = –10 V to +10 V
80
90
100
100
dB
dB
dB
dB
eNI2 + (eNO/G)2
RTI noise = √
NOISE
Voltage Noise, 1 kHz
Input Voltage Noise, eNI
Output Voltage Noise, eNO
RTI
VIN+, VIN−, VREF = 0
8
75
nV/√Hz
nV/√Hz
f = 0.1 Hz to 10 Hz
G = 1
G = 10
G = 100 to 1000
Current Noise
2
μV p-p
μV p-p
μV p-p
fA/√Hz
pA p-p
0.5
0.25
40
6
f = 1 kHz
f = 0.1 Hz to 10 Hz
VOLTAGE OFFSET1
Input Offset, VOSI
Over Temperature
Average TC
Output Offset, VOSO
Over Temperature
Average TC
VS = 5 V to 15 V
T = −40°C to +85°C
70
μV
μV
μV/°C
μV
mV
135
0.9
600
1.00
9
VS = 5 V to 15 V
T = −40°C to +85°C
μV/°C
Offset RTI vs. Supply (PSR)
G = 1
G = 10
G = 100
G = 1000
VS = 2.3 V to 18 V
90
100
120
140
140
dB
dB
dB
dB
100
120
120
INPUT CURRENT
Input Bias Current
Over Temperature
Average TC
Input Offset Current
Over Temperature
Average TC
0.5
2
3
nA
nA
pA/°C
nA
nA
T = −40°C to +85°C
T = −40°C to +85°C
Rev. B | Page 5 of 24
3
0.3
1
1.5
3
pA/°C
AD8221
ARM Grade
Typ
Parameter
Conditions
Unit
Min
Max
REFERENCE INPUT
RIN
IIN
20
50
kΩ
μA
V
VIN+, VIN−, VREF = 0
60
+VS
Voltage Range
Gain to Output
POWER SUPPLY
Operating Range
Quiescent Current
Over Temperature
DYNAMIC RESPONSE
Small Signal –3 dB Bandwidth
G = 1
−VS
2.3
1
0.0001
V/V
VS = 2.3 V to 18 V
T = −40°C to +85°C
18
1
1.2
V
mA
mA
0.9
1
825
562
100
14.7
kHz
kHz
kHz
kHz
G = 10
G = 100
G = 1000
Settling Time 0.01%
G = 1 to 100
G = 1000
Settling Time 0.001%
G = 1 to 100
G = 1000
10 V step
10 V step
10
80
μs
μs
13
110
2
μs
μs
V/μs
V/μs
Slew Rate
G = 1
G = 5 to 100
G = 1 + (49.4 kΩ/RG)
1.5
2
2.5
GAIN
Gain Range
1
1000
V/V
Gain Error
VOUT 10 V
G = 1
G = 10
G = 100
G = 1000
0.1
0.3
0.3
0.3
%
%
%
%
Gain Nonlinearity
G = 1 to 10
G = 100
G = 1000
G = 1 to 100
VOUT = −10 V to +10 V
RL = 10 kΩ
RL = 10 kΩ
RL = 10 kΩ
RL = 2 kΩ
5
7
10
15
15
20
50
100
ppm
ppm
ppm
ppm
Gain vs. Temperature
G = 1
G > 12
3
10
–50
ppm/°C
ppm/°C
INPUT
Input Impedance
Differential
100||2
100||2
GΩ/pF
GΩ/pF
Common Mode
Input Operating Voltage Range3
Over Temperature
Input Operating Voltage Range
Over Temperature
OUTPUT
VS = 2.3 V to 5 V
T = −40°C to +85°C
VS = 5 V to 18 V
T = −40°C to +85°C
RL = 10 kΩ
–VS + 1.9
–VS + 2.0
–VS + 1.9
–VS + 2.0
+VS − 1.1
V
V
V
V
+VS − 1.2
+VS − 1.2
+VS − 1.2
Output Swing
Over Temperature
Output Swing
Over Temperature
Short-Circuit Current
VS = 2.3 V to 5 V
T = −40°C to +85°C
VS = 5 V to 18 V
T = −40°C to +85°C
–VS + 1.1
–VS + 1.4
–VS + 1.2
–VS + 1.6
+VS − 1.2
+VS − 1.3
+VS − 1.4
+VS − 1.5
V
V
V
V
18
mA
Rev. B | Page 6 of 24
AD8221
ARM Grade
Typ
Parameter
Conditions
Unit
Min
Max
TEMPERATURE RANGE
Specified Performance
Operating Range4
−40
−40
+85
+125
°C
°C
1 Total RTI VOS = (VOSI) + (VOSO/G).
2 Does not include the effects of external resistor RG.
3 One input grounded. G = 1.
4 See Typical Performance Characteristics for expected operation between 85°C to 125°C.
Rev. B | Page 7 of 24
AD8221
ABSOLUTE MAXIMUM RATINGS
Table 3.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
Supply Voltage
18 V
Internal Power Dissipation
Output Short-Circuit Current
Input Voltage (Common-Mode)
Differential Input Voltage
Storage Temperature Range
Operating Temperature Range1
200 mW
Indefinite
VS
VS
−65°C to +150°C
−40°C to +125°C
THERMAL CHARACTERISTICS
Specification for a device in free air.
1 Temperature range for specified performance is –40°C to +85°C. See Typical
Performance Characteristics for expected operation from 85°C to 125°C.
Table 4.
Package
θJA
Unit
°C/W
°C/W
8-Lead SOIC, 4-Layer JEDEC Board
8-Lead MSOP, 4-Layer JEDEC Board
121
135
ESD CAUTION
Rev. B | Page 8 of 24
AD8221
TYPICAL PERFORMANCE CHARACTERISTICS
T = 25°C, ꢀS = 15 ꢀ, RL = 10 kΩ, unless otherwise noted.
1600
3500
3000
2500
2000
1500
1000
500
1400
1200
1000
800
600
400
200
0
0
–0.9
–150
–100
–50
0
50
100
150
–0.6
–0.3
0
0.3
0.6
0.9
CMR (µV/V)
INPUT OFFSET CURRENT (nA)
Figure 3. Typical Distribution for CMR (G = 1)
Figure 6. Typical Distribution of Input Offset Current
2400
15
10
5
2100
1800
1500
1200
900
600
300
0
V
= ±15V
S
0
V
= ±5V
S
–5
–10
–15
–15
–60
–40
–20
0
20
40
60
–10
–5
0
5
10
15
INPUT OFFSET VOLTAGE (µV)
OUTPUT VOLTAGE (V)
Figure 4. Typical Distribution of Input Offset Voltage
Figure 7. Input Common-Mode Range vs. Output Voltage, G = 1
3000
15
10
2500
2000
1500
1000
500
V
= ±15V
S
5
0
V
= ±5V
S
–5
–10
–15
0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
–15
–10
–5
0
5
10
15
INPUT BIAS CURRENT (nA)
OUTPUT VOLTAGE (V)
Figure 5. Typical Distribution of Input Bias Current
Figure 8. Input Common-Mode Range vs. Output Voltage, G = 100
Rev. B | Page 9 of 24
AD8221
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.45
180
160
140
120
100
80
GAIN = 1000
GAIN = 100
V
= ±15V
S
GAIN = 10
GAIN = 1
GAIN = 1000
V
= ±5V
S
60
40
0.40
–15
20
0.1
1
10
100
1k
10k
100k
1M
–10
–5
0
5
10
15
COMMON-MODE VOLTAGE (V)
FREQUENCY (Hz)
Figure 9. IBIAS vs. CMV
Figure 12. Positive PSRR vs. Frequency, RTI (G = 1 to 1000)
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
180
160
140
120
100
80
GAIN = 1000
GAIN = 100
GAIN = 10
GAIN = 1
60
40
0
0.01
20
0.1
0.1
1
10
1
10
100
1k
10k
100k
1M
WARM-UP TIME (min)
FREQUENCY (Hz)
Figure 10. Change in Input Offset Voltage vs. Warm-Up Time
Figure 13. Negative PSRR vs. Frequency, RTI (G = 1 to 1000)
5
100k
VS = ±15V
4
3
2
1
10k
1k
BEST AVAILABLE FET
INPUT IN-AMP GAIN = 1
INPUT OFFSET CURRENT
0
BEST AVAILABLE FET
INPUT IN-AMP GAIN = 1000
INPUT BIAS CURRENT
–1
–2
–3
–4
–5
AD8221 GAIN = 1
100
10
AD8221 GAIN = 1000
–40
–20
0
20
40
60
80
100
120
140
10
100
1k
10k
100k
1M
10M
TEMPERATURE (°C)
SOURCE RESISTANCE (Ω)
Figure 11. Input Bias Current and Offset Current vs. Temperature
Figure 14. Total Drift vs. Source Resistance
Rev. B | Page 10 of 24
AD8221
70
60
100
80
GAIN = 1000
50
60
GAIN = 100
GAIN = 10
GAIN = 1
40
40
30
20
20
0
10
–20
–40
–60
–80
–100
0
–10
–20
–30
100
1k
10k
100k
1M
10M
–40
–20
0
20
40
60
80
100
120
140
FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 15. Gain vs. Frequency
Figure 18. CMR vs. Temperature
160
+V
–0
S
GAIN = 1000
GAIN = 100
GAIN = 10
–0.4
–0.8
–1.2
–1.6
–2.0
–2.4
140
120
100
80
GAIN = 1
+2.4
+2.0
+1.6
+1.2
+0.8
+0.4
+0
60
40
0.1
–V
S
1
10
100
1k
10k
100k
1M
0
5
10
15
20
FREQUENCY (Hz)
SUPPLY VOLTAGE (±V)
Figure 16. CMRR vs. Frequency, RTI
Figure 19. Input Voltage Limit vs. Supply Voltage, G = 1
160
140
120
100
80
+V
S
–0
GAIN = 1000
–0.4
–0.8
–1.2
–1.6
–2.0
GAIN = 100
GAIN = 10
GAIN = 1
R
R
= 10kΩ
= 2kΩ
L
L
+2.0
+1.6
+1.2
+0.8
+0.4
+0
R
R
= 2kΩ
L
L
60
= 10kΩ
40
0.1
–V
S
1
10
100
1k
10k
100k
1M
0
5
10
SUPPLY VOLTAGE (±V)
15
20
FREQUENCY (Hz)
Figure 17. CMRR vs. Frequency, RTI, 1 kΩ Source Imbalance
Figure 20. Output Voltage Swing vs. Supply Voltage, G = 1
Rev. B | Page 11 of 24
AD8221
30
V
= ±15V
S
V
= ±15V
S
20
10
0
–10
–8
–6
–4
–2
0
2
4
6
8
10
1
10
100
1k
10k
OUTPUT VOLTAGE (V)
LOAD RESISTANCE (Ω)
Figure 24. Gain Nonlinearity, G = 100, RL = 10 kΩ
Figure 21. Output Voltage Swing vs. Load Resistance
+V –0
S
V
= ±15V
S
–1
–2
–3
SOURCING
+3
+2
+1
SINKING
–V +0
S
–10
–8
–6
–4
–2
0
2
4
6
8
10
0
1
2
3
4
5
6
7
8
9
10 11 12
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
Figure 22. Output Voltage Swing vs. Output Current, G = 1
Figure 25. Gain Nonlinearity, G = 1000, RL = 10 kΩ
1k
V
= ±15V
S
GAIN = 1
100
10
1
GAIN = 10
GAIN = 100
GAIN = 1000
GAIN = 1000
BW LIMIT
–10
–8
–6
–4
–2
0
2
4
6
8
10
1
10
100
1k
10k
100k
OUTPUT VOLTAGE (V)
FREQUENCY (Hz)
Figure 26. Voltage Noise Spectral Density vs. Frequency (G = 1 to 1000)
Figure 23. Gain Nonlinearity, G = 1, RL = 10 kΩ
Rev. B | Page 12 of 24
AD8221
2µV/DIV
1s/DIV
5pA/DIV
1s/DIV
Figure 27. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1)
Figure 30. 0.1 Hz to 10 Hz Current Noise
30
25
20
15
10
5
V
= ±15V
S
GAIN = 1
GAIN = 10, 100, 1000
0
1k
10k
100k
1M
0.1µV/DIV
1s/DIV
FREQUENCY (Hz)
Figure 28. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1000)
Figure 31. Large Signal Frequency Response
1k
100
10
5V/DIV
7.9µs TO 0.01%
8.5µs TO 0.001%
0.002%/DIV
1
10
100
1k
10k
20µs/DIV
FREQUENCY (Hz)
Figure 29. Current Noise Spectral Density vs. Frequency
Figure 32. Large Signal Pulse Response and Settling Time (G = 1), 0.002%/DIV
Rev. B | Page 13 of 24
AD8221
5V/DIV
4.9µs TO 0.01%
5.6µs TO 0.001%
0.002%/DIV
20mV/DIV
20µs/DIV
4µs/DIV
Figure 33. Large Signal Pulse Response and Settling Time (G = 10),
0.002%/DIV
Figure 36. Small Signal Response, G = 1, RL = 2 kΩ, CL = 100 pF
5V/DIV
10.3µs TO 0.01%
13.4µs TO 0.001%
0.002%/DIV
20mV/DIV
20µs/DIV
4µs/DIV
Figure 34. Large Signal Pulse Response and Settling Time (G = 100),
0.002%/DIV
Figure 37. Small Signal Response, G = 10, RL = 2 kΩ, CL = 100 pF
5V/DIV
83µs TO 0.01%
0.002%/DIV
112µs TO 0.001%
20mV/DIV
200µs/DIV
10µs/DIV
Figure 35. Large Signal Pulse Response and Settling Time (G = 1000),
0.002%/DIV
Figure 38. Small Signal Response, G = 100, RL = 2 kΩ, CL = 100 pF
Rev. B | Page 14 of 24
AD8221
1000
100
10
2
SETTLED TO 0.001%
SETTLED TO 0.01%
20mV/DIV
1
1
10
100
1000
100µs/DIV
GAIN
Figure 41. Settling Time vs. Gain for a 10 V Step
Figure 39. Small Signal Response, G = 1000, RL = 2 kΩ, CL = 100 pF
15
10
SETTLED TO 0.001%
SETTLED TO 0.01%
5
0
0
5
10
15
20
OUTPUT VOLTAGE STEP SIZE (V)
Figure 40. Settling Time vs. Step Size (G = 1)
Rev. B | Page 15 of 24
AD8221
THEORY OF OPERATION
V
I
I
B
A1
A2
I
COMPENSATION
I
COMPENSATION
B
B
10kΩ
C1
C2
+V
–V
S
10kΩ
10kΩ
OUTPUT
A3
+V
S
+V
S
+V
–V
R1 24.7kΩ
R2
+V
24.7kΩ
S
S
400Ω
+V
400Ω
S
S
Q2
–IN
Q1
+IN
REF
10kΩ
R
G
–V
–V
S
S
S
–V
–V
S
S
Figure 42. Simplified Schematic
The AD8221 is a monolithic instrumentation amplifier based
on the classic 3-op amp topology. Input transistors Q1 and Q2
are biased at a fixed current so that any differential input signal
forces the output voltages of A1 and A2 to change accordingly.
A signal applied to the input creates a current through RG, R1,
and R2, such that the outputs of A1 and A2 deliver the correct
voltage. Topologically, Q1, A1, R1 and Q2, A2, R2 can be
viewed as precision current feedback amplifiers. The amplified
differential and common-mode signals are applied to a
difference amplifier that rejects the common-mode voltage
but amplifies the differential voltage. The difference amplifier
employs innovations that result in low output offset voltage as
well as low output offset voltage drift. Laser-trimmed resistors
allow for a highly accurate in-amp with gain error typically less
than 20 ppm and CMRR that exceeds 90 dB (G = 1).
Because the input amplifiers employ a current feedback
architecture, the gain-bandwidth product of the AD8221
increases with gain, resulting in a system that does not suffer
from the expected bandwidth loss of voltage feedback
architectures at higher gains.
To maintain precision even at low input levels, special attention
was given to the design and layout of the AD8221, resulting in
an in-amp whose performance satisfies the most demanding
applications.
A unique pinout enables the AD8221 to meet a CMRR
specification of 80 dB at 10 kHz (G = 1) and 110 dB at 1 kHz
(G = 1000). The balanced pinout, shown in Figure 43, reduces
the parasitics that had, in the past, adversely affected CMRR
performance. In addition, the new pinout simplifies board
layout because associated traces are grouped together. For
example, the gain setting resistor pins are adjacent to the
inputs, and the reference pin is next to the output.
Using superbeta input transistors and an IB compensation
scheme, the AD8221 offers extremely high input impedance,
low IB, low IB drift, low IOS, low input bias current noise, and
extremely low voltage noise of 8 nꢀ/√Hz.
1
2
3
4
8
7
6
5
+V
V
–IN
S
R
G
OUT
The transfer function of the AD8221 is
R
REF
–V
G
49.4 kꢁ
G =1+
+IN
S
AD8221
RG
TOP VIEW
Users can easily and accurately set the gain using a single
standard resistor.
Figure 43. Pinout Diagram
Rev. B | Page 16 of 24
AD8221
Grounding
GAIN SELECTION
The output voltage of the AD8221 is developed with respect to
the potential on the reference terminal. Care should be taken to
tie REF to the appropriate local ground.
Placing a resistor across the RG terminals set the gain of
AD8221, which can be calculated by referring to Table 5 or
by using the gain equation.
In mixed-signal environments, low level analog signals need to
be isolated from the noisy digital environment. Many ADCs
have separate analog and digital ground pins. Although it is
convenient to tie both grounds to a single ground plane, the
current traveling through the ground wires and PC board may
cause hundreds of millivolts of error. Therefore, separate analog
and digital ground returns should be used to minimize the
current flow from sensitive points to the system ground. An
example layout is shown in Figure 44 and Figure 45.
49.4 kꢁ
RG =
G −1
Table 5. Gains Achieved Using 1% Resistors
1% Standard Table Value of RG (Ω)
Calculated Gain
49.9 k
12.4 k
5.49 k
2.61 k
1.00 k
499
1.990
4.984
9.998
19.93
50.40
100.0
249
199.4
100
495.0
49.9
991.0
The AD8221 defaults to G = 1 when no gain resistor is used.
Gain accuracy is determined by the absolute tolerance of RG.
The TC of the external gain resistor increases the gain drift of
the instrumentation amplifier. Gain error and gain drift are kept
to a minimum when the gain resistor is not used.
LAYOUT
Careful board layout maximizes system performance. Traces
from the gain setting resistor to the RG pins should be kept as
short as possible to minimize parasitic inductance. To ensure
the most accurate output, the trace from the REF pin should
either be connected to the local ground of the AD8221, as shown
in Figure 46, or connected to a voltage that is referenced to the
local ground of the AD8221.
Figure 44. Top Layer of the AD8221-EVAL
Common-Mode Rejection
One benefit of the high CMRR over frequency of the AD8221 is
that it has greater immunity to disturbances, such as line noise
and its associated harmonics, than do typical instrumentation
amplifiers. Typically, these amplifiers have CMRR fall-off at
200 Hz; common-mode filters are often used to compensate for
this shortcoming. The AD8221 is able to reject CMRR over a
greater frequency range, reducing the need for filtering.
A well implemented layout helps to maintain the high CMRR
over frequency of the AD8221. Input source impedance and
capacitance should be closely matched. In addition, source
resistance and capacitance should be placed as close to the
inputs as permissible.
Figure 45. Bottom Layer of the AD8221-EVAL
Rev. B | Page 17 of 24
AD8221
+V
S
REFERENCE TERMINAL
As shown in Figure 42, the reference terminal, REF, is at one
end of a 10 kꢁ resistor. The output of the instrumentation
amplifier is referenced to the voltage on the REF terminal; this
is useful when the output signal needs to be offset to a precise
midsupply level. For example, a voltage source can be tied to the
REF pin to level-shift the output so that the AD8221 can interface
with an ADC. The allowable reference voltage range is a function
of the gain, input, and supply voltage. The REF pin should not
exceed either +ꢀS or –ꢀS by more than 0.5 ꢀ.
AD8221
REF
REF
REF
–V
S
TRANSFORMER
+V
S
For best performance, source impedance to the REF terminal
should be kept low, because parasitic resistance can adversely
affect CMRR and gain accuracy.
AD8221
POWER SUPPLY REGULATION AND BYPASSING
A stable dc voltage should be used to power the instrumentation
amplifier. Noise on the supply pins can adversely affect
performance. Bypass capacitors should be used to decouple
the amplifier.
–V
S
THERMOCOUPLE
+V
S
A 0.1 μF capacitor should be placed close to each supply pin.
As shown in Figure 46, a 10 μF tantalum capacitor can be used
further away from the part. In most cases, it can be shared by
other precision integrated circuits.
C
R
1
fHIGH-PASS
=
2πRC
AD8221
+V
S
C
R
0.1µF
10µF
–V
S
+IN
–IN
CAPACITOR COUPLED
V
Figure 47. Creating an IBIAS Path
OUT
AD8221
LOAD
INPUT PROTECTION
REF
All terminals of the AD8221 are protected against ESD, 1 kꢀ
Human Body Model. In addition, the input structure allows for
dc overload conditions below the negative supply, −ꢀS. The
internal 400 Ω resistors limit current in the event of a negative
fault condition. However, in the case of a dc overload voltage
above the positive supply, +ꢀS, a large current flows directly
through the ESD diode to the positive rail. Therefore, an external
resistor should be used in series with the input to limit current
for voltages above +ꢀs. In either scenario, the AD8221 can
safely handle a continuous 6 mA current, I = ꢀIN/REXT for
positive overvoltage and I = ꢀIN/(400 Ω + REXT) for negative
overvoltage.
0.1µF
10µF
–V
S
Figure 46. Supply Decoupling, REF, and Output Referred to Local Ground
INPUT BIAS CURRENT RETURN PATH
The input bias current of the AD8221 must have a return path
to common. When the source, such as a thermocouple, cannot
provide a return current path, one should be created, as shown
in Figure 47.
For applications where the AD8221 encounters extreme
overload voltages, as in cardiac defibrillators, external series
resistors, and low leakage diode clamps, such as BAꢀ199Ls,
FJH1100s, or SP720s should be used.
Rev. B | Page 18 of 24
AD8221
CD affects the difference signal, and CC affects the common-
RF INTERFERENCE
mode signal. ꢀalues of R and CC should be chosen to minimize
RFI. Mismatch between the R × CC at the positive input and the
R × CC at the negative input degrades the CMRR of the AD8221.
By using a value of CD one magnitude larger than CC, the effect
of the mismatch is reduced, and therefore, performance is
improved.
RF rectification is often a problem when amplifiers are used in
applications where there are strong RF signals. The disturbance
can appear as a small dc offset voltage. High frequency signals
can be filtered with a low-pass RC network placed at the input
of the instrumentation amplifier, as shown in Figure 48. The
filter limits the input signal bandwidth according to the following
relationship:
PRECISION STRAIN GAGE
The low offset and high CMRR over frequency of the AD8221
make it an excellent candidate for bridge measurements. As
shown in Figure 49, the bridge can be directly connected to
the inputs of the amplifier.
1
FilterFreqDiff =
2πR(2CD +CC)
1
FilterFreqCM =
2πRCC
+5V
where CD ≥ 10CC.
10µF
0.1µF
+15V
350Ω
350Ω
350Ω
350Ω
+IN
–IN
+
0.1µF
10µF
R
AD8221
C
1nF
C
D
C
–
R
+IN
R1
+2.5V
4.02kΩ
V
OUT
C
10nF
1nF
AD8221
Figure 49. Precision Strain Gage
499Ω
R
REF
CONDITIONING 10 V SIGNALS FOR A +5 V
DIFFERENTIAL INPUT ADC
–IN
4.02kΩ
C
There is a need in many applications to condition 10 ꢀ signals.
However, many of today’s ADCs and digital ICs operate on
much lower, single-supply voltages. Furthermore, new ADCs
have differential inputs because they provide better common-
mode rejection, noise immunity, and performance at low supply
voltages. Interfacing a 10 ꢀ, single-ended instrumentation
amplifier to a +5 ꢀ, differential ADC can be a challenge.
Interfacing the instrumentation amplifier to the ADC requires
attenuation and a level shift. A solution is shown in Figure 50.
+12V
0.1µF
10µF
–15V
Figure 48. RFI Suppression
+2.5V
+12V
R3
1kΩ
0.1µF
+5V
10nF
+5V
R6
27.4Ω
+12V
10µF
0.1µF
AD8022
C1
470pF
(½)
0.1µF
+IN
–IN
AV
DV
DD
DD
VIN(+)
VIN(–)
0.1µF
–12V
AD8221
OP27
R1
C2
220µF
AD7723
10kΩ
REF
R5
+12V
499Ω
R2
10kΩ
0.1µF
AGND DGND REF1 REF2
0.1µF
10µF
0.1µF
R7
27.4Ω
–12V
AD8022
–12V
R4
(½)
1kΩ
220nF
10nF
0.1µF
–12V
2.5V
22µF
+5V
+V
V
OUT
IN
10µF
0.1µF
AD780
GND
Figure 50. Interfacing to a Differential Input ADC
Rev. B | Page 19 of 24
AD8221
In this topology, an OP27 sets the reference voltage of the
AD8221. The output signal of the instrumentation amplifier is
taken across the OUT pin and the REF pin. Two 1 kΩ resistors
and a 499 Ω resistor attenuate the 10 ꢀ signal to +4 ꢀ. An
optional capacitor, C1, can serve as an antialiasing filter. An
AD8022 is used to drive the ADC.
reduces the referred input noise of the amplifier to 8 nꢀ/√Hz.
Thus, smaller signals can be measured because the noise floor is
lower. DC offsets that would have been gained by 100 are
eliminated from the output of the AD8221 by the integrator
feedback network.
At low frequencies, the OP1177 forces the output of the AD8221 to
0 ꢀ. Once a signal exceeds fHIGH-PASS, the AD8221 outputs the
amplified input signal.
This topology has five benefits. In addition to level-shifting and
attenuation, very little noise is contributed to the system. Noise
from R1 and R2 is common to both of the inputs of the ADC
and is easily rejected. R5 adds a third of the dominant noise and
therefore makes a negligible contribution to the noise of the
system. The attenuator divides the noise from R3 and R4. Likewise,
its noise contribution is negligible. The fourth benefit of this
interface circuit is that the acquisition time of the AD8221 is
reduced by a factor of 2. With the help of the OP27, the AD8221
only needs to deliver one-half of the full swing; therefore, signals
can settle more quickly. Lastly, the AD8022 settles quickly,
which is helpful because the shorter the settling time, the
more bits that can be resolved when the ADC acquires data.
This configuration provides attenuation, a level-shift, and a
convenient interface with a differential input ADC while
maintaining performance.
+V
S
0.1µF
+IN
R
1
fHIGH-PASS
=
2πRC
AD8221
499Ω
R
REF
C
1µF
15.8kΩ
–IN
+V
S
0.1µF
0.1µF
–V
S
OP1177
AC-COUPLED INSTRUMENTATION AMPLIFIER
+V
–V
S
S
Measuring small signals that are in the noise or offset of the
amplifier can be a challenge. Figure 51 shows a circuit that can
improve the resolution of small ac signals. The large gain
10µF
10µF
0.1µF
–V
S
Figure 51. AC-Coupled Circuit
Rev. B | Page 20 of 24
AD8221
OUTLINE DIMENSIONS
3.20
3.00
2.80
8
1
5
4
5.15
4.90
4.65
3.20
3.00
2.80
PIN 1
0.65 BSC
0.95
0.85
0.75
1.10 MAX
0.80
0.60
0.40
8°
0°
0.15
0.00
0.38
0.22
0.23
0.08
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 52. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 53. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
Rev. B | Page 21 of 24
AD8221
ORDERING GUIDE
Temperature Range for
Specified Performance
Operating1
Temperature Range
Package
Option
Model
Package Description
Branding
AD8221AR
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
8-Lead SOIC_N
R-8
R-8
R-8
R-8
R-8
R-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
R-8
AD8221AR-REEL
AD8221AR-REEL7
AD8221ARZ2
AD8221ARZ-R72
AD8221ARZ-RL2
AD8221ARM
AD8221ARM-REEL
AD8221ARM REEL7
AD8221ARMZ2
AD8221ARMZ-R72
AD8221ARMZ-RL2
AD8221BR
AD8221BR-REEL
AD8221BR-REEL7
AD8221-EVAL
8-Lead SOIC_N, 13" Tape and Reel
8-Lead SOIC_N, 7" Tape and Reel
8-Lead SOIC_N
8-Lead SOIC_N, 7" Tape and Reel
8-Lead SOIC_N, 13" Tape and Reel
8-Lead MSOP
8-Lead MSOP, 13" Tape and Reel
8-Lead MSOP, 7" Tape and Reel
8-Lead MSOP
8-Lead MSOP, 7" Tape and Reel
8-Lead MSOP, 13" Tape and Reel
8-Lead SOIC_N
JLA
JLA
JLA
JLA#
JLA#
JLA#
8-Lead SOIC_N, 13" Tape and Reel
8-Lead SOIC_N, 7" Tape and Reel
Evaluation Board
R-8
R-8
1 See Typical Performance Characteristics for expected operation from 85°C to 125°C.
2 Z = RoHS Compliant Part, # denotes RoHS compliant product may be top or bottom marked.
Rev. B | Page 22 of 24
AD8221
NOTES
Rev. B | Page 23 of 24
AD8221
NOTES
©2003–2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03149–0–9/07(B)
Rev. B | Page 24 of 24
相关型号：
AD8221ARMZ-REEL7
INSTRUMENTATION AMPLIFIER, 60uV OFFSET-MAX, 0.825MHz BAND WIDTH, PDSO8, MO-187AA, MSOP-8
ADI
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