AD8223ARM-R7 [ADI]
Single Supply, Rail-to-Rail, Low Cost Instrumentation Amplifier; 单电源，轨到轨，低成本仪表放大器
| 型号： | AD8223ARM-R7 |
| 厂家： | 
ADI |
| 描述： | Single Supply, Rail-to-Rail, Low Cost Instrumentation Amplifier |
| 文件： | 总20页 (文件大小：420K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Single Supply, Rail-to-Rail, Low Cost
Instrumentation Amplifier
Preliminary Technical Data
AD8223
FEATURES
CONNECTION DIAGRAM
Gain set with 1 resistor per amplifier
Gain = 5 to 1000
Inputs
Voltage range to 150 mV below negative rail
25 nA maximum input bias current
30 nV/√Hz, RTI noise @ 1 kHz
Power supplies
1
2
3
4
8
7
6
5
–R
+R
G
G
–
+
–IN
+IN
+V
S
OUTPUT
REF
–V
S
AD8223
Figure 1. 8-Lead SOIC (R) and 8-Lead MSOP SOIC (RM) Packages
Dual supply: 2.5V to 12.5
Single supply: 3V to 25V
600 μA maximum supply current
APPLICATIONS
Low power medical instrumentation
Transducer interface
Thermocouple amplifiers
Industrial process controls
Difference amplifiers
Low power data acquisition
GENERAL DESCRIPTION
mode range and can amplify signals that have a common-mode
voltage 150 mV below ground. Although the design of the AD8223
is optimized to operate from a single supply, the AD8223 still
provides superior performance when operated from a dual
voltage supply ( 2.5 V to 12.5 V).
The AD8223 is an integrated single-supply instrumentation
amplifier that delivers rail-to-rail output swing on a single
supply (+3.0 V to +25 V supplies). The AD8223 offers superior
user flexibility by allowing single-gain set resistor program-
ming, and conforming to the 8-lead industry standard pinout
configuration.
Low power consumption (1.5 mW at 3 V), wide supply voltage
range, and rail-to-rail output swing make the AD8223 ideal for
battery-powered applications. The rail-to-rail output stage
maximizes the dynamic range when operating from low supply
voltages. The AD8223 replaces discrete instrumentation
amplifier designs and offers superior linearity, temperature
stability and reliability in a minimum of space.
With no external resistor, the AD8223 is configured for G = 5
and with an external resistor, the AD8223 can be programmed
for gains up to 1000.
The AD8223 holds errors to a minimum by providing superior
ac CMRR that increases with increasing gain. Line noise, as
well as line harmonics, is rejected because the CMRR remains
constant up to 200 Hz. The AD8223 has a wide input common-
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2008 Analog Devices, Inc. All rights reserved.
AD8223
Preliminary Technical Data
TABLE OF CONTENTS
Features .............................................................................................. 1
Input Voltage Range................................................................... 13
Reference Terminal .................................................................... 14
Input Protection ......................................................................... 14
RF Interference ........................................................................... 14
Ground Returns for Input Bias Currents ................................ 15
Applications Information.............................................................. 16
Basic Connection ....................................................................... 16
Differential Output .................................................................... 16
Output Buffering ........................................................................ 16
Cables........................................................................................... 16
A Single-Supply Data Acquisition System .............................. 17
Amplifying Signals with Low Common-Mode Voltage........ 17
Outline Dimensions....................................................................... 18
Ordering Guide .......................................................................... 19
Connection Diagram ....................................................................... 1
Applications....................................................................................... 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Single Supply................................................................................. 3
Dual Supply................................................................................... 5
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 13
Amplifier Architecture .............................................................. 13
Gain Selection............................................................................. 13
REVISION HISTORY
Rev. PrA | Page 2 of 20
Preliminary Technical Data
AD8223
SPECIFICATIONS
SINGLE SUPPLY
TA = 25°C, single supply, VS = +5 V, and RL = 10 kΩ, unless otherwise noted.
Table 1
AD8223A
Typ
AD8223B
Typ
Parameter
Conditions
Min
Max
Min
Max
Unit
COMMON MODE REJECTION RATIO
DC to 60 Hz with 1 kΩ Source
Imbalance
VCM = 0 V to 3 V
G = 5
G = 10
G = 100
G = 1000
74
80
88
88
86
92
100
100
dB
dB
dB
dB
NOISE
Voltage Noise, 1 kHz
G = 5
G = 1000
50
30
50
30
nV/√Hz
nV/√Hz
RTI, 0.1 Hz to 10 Hz
G = 5
G = 1000
Current Noise, 1 kHz
0.1 Hz to 10 Hz
VOLTAGE OFFSET
3.0
1.5
100
1.5
3.0
1.5
100
1.5
μV p-p
μV p-p
fA/√Hz
pA p-p
Total RTI Error =
VOSI + VOSO/G
Input Offset, VOSI
Average TC
Output Offset, VOSO
Average TC
400
5
1000
15
200
3
500
10
μV
μV/°C
μV
μV/°C
Offset Referred to Input vs.
Supply (PSR)
G = 5
G = 10
G = 100
G = 1000
80
86
90
90
90
96
100
100
dB
dB
dB
dB
INPUT CURRENT
Input Bias Current
Over Temperature
17
25
27.5
17
25
27.5
nA
nA
Average Temperature
Coefficient
25
25
pA/°C
Input Offset Current
Over Temperature
0.25
2
2.5
0.25
2
2.5
nA
nA
Average Temperature
Coefficient
5
5
pA/°C
DYNAMIC RESPONSE
Small Signal −3 dB Bandwidth
G = 5
G = 10
G = 100
G = 1000
Slew Rate
200
190
75
8
0.3
200
190
75
8
0.3
kHz
kHz
kHz
kHz
V/μs
Rev. PrA | Page 3 of 20
AD8223
Preliminary Technical Data
AD8223A
Typ
AD8223B
Typ
Parameter
Settling Time to 0.01%
G = 5
Conditions
Min
Max
Min
Max
Unit
Step size = 3.5 V
μs
μs
μs
G = 100
G = 1000
GAIN
G = 5 + (80 k/RG)
Gain Range
Gain Error1
G = 5
5
1000
5
1000
V/V
VOUT = 0.05 V to 4.5 V
0.03
0.10
0.10
0.10
0.15
0.03
0.10
0.10
0.10
0.1
0.5
0.5
0.5
%
%
%
%
G = 10
G = 100
G = 1000
1
1
1
Nonlinearity
G = 5 to 1000
Gain vs. Temperature
G = 5
VOUT = 0.05 V to 4.5 V
50
50
ppm
5
50
10
5
50
10
ppm/°C
ppm/°C
G > 51
INPUT
Input Impedance
Differential
Common-Mode
Input Voltage Range2
2||2
2||2
2||2
2||2
GΩ||pF
GΩ||pF
V
(−VS) −
0.15
(+VS) −
1.5
(−VS) −
0.15
(+VS) −
1.5
OUTPUT
Output Swing
RL = 10 kΩ to ground +0.01
(+VS) −
0.5
(+VS) −
0.2
+0.01
+0.01
(+VS) −
0.5
(+VS) −
0.2
V
V
RL = 100 kΩ to
ground
+0.01
REFERENCE INPUT
RIN
IIN
60
+50
20%
+60
+VS
60
+50
20%
+60
+VS
kΩ
μA
V
VIN+, VREF = 0
Voltage Range
Gain to Output
−VS
−VS
1
1
V
0.0002
0.0002
POWER SUPPLY
Operating Range
+3.0
-40
+25
550
+3.0
−40
+25
550
V
μA
Quiescent Current
TEMPERATURE RANGE
For Specified Performance
+85
+85
°C
1 Does not include effects of external resistor RG.
2 One input grounded. G = 1.
Rev. PrA | Page 4 of 20
Preliminary Technical Data
AD8223
DUAL SUPPLY
TA = 25°C, dual supply, VS = 12 V, and RL = 10 kꢀ, unless otherwise noted.
Table 2.
AD8223A
Typ
AD8223B
Typ
Parameter
Conditions
Min
Max
Min
Max
Unit
COMMON MODE REJECTION RATIO
DC to 60 Hz with 1 kΩ Source
Imbalance
VCM = −10 V to 10 V
G = 5
G = 10
G = 100
G = 1000
74
80
88
88
86
92
100
100
dB
dB
dB
dB
NOISE
Voltage Noise, 1 kHz
G = 5
G = 1000
50
30
50
30
nV/√Hz
nV/√Hz
RTI, 0.1 Hz to 10 Hz
G = 5
G = 1000
Current Noise, 1 kHz
0.1 Hz to 10 Hz
VOLTAGE OFFSET
3.0
1.5
100
1.5
3.0
1.5
100
1.5
μV p-p
μV p-p
fA/√Hz
pA p-p
Total RTI Error =
VOSI + VOSO/G
Input Offset, VOSI
Average TC
Output Offset, VOSO
Average TC
400
5
1000
15
200
3
500
10
μV
μV/°C
μV
μV/°C
Offset Referred to Input vs. Supply
(PSR)
G = 5
G = 10
G = 100
G = 1000
80
86
90
90
90
96
100
100
dB
dB
dB
dB
INPUT CURRENT
Input Bias Current
Over Temperature
17
25
27.5
17
25
27.5
nA
nA
Average Temperature
Coefficient
25
25
pA/°C
Input Offset Current
Over Temperature
0.25
2
2.5
0.25
2
2.5
nA
nA
Average Temperature
Coefficient
5
5
pA/°C
DYNAMIC RESPONSE
Small Signal −3 dB Bandwidth
G = 5
G = 10
G = 100
G = 1000
Slew Rate
Settling Time to 0.01%
G = 5
G = 100
G = 1000
200
190
75
8
0.3
200
190
75
8
0.3
kHz
kHz
kHz
kHz
V/μs
Step size = 10 V
30
30
140
30
30
140
μs
μs
μs
Rev. PrA | Page 5 of 20
AD8223
Preliminary Technical Data
AD8223A
Typ
AD8223B
Typ
Parameter
GAIN
Conditions
Min
Max
Min
Max
Unit
G = 5 + (80 k/RG)
Gain Range
Gain Error1
G = 5
G = 10
G = 100
G = 1000
Nonlinearity
5
1000
5
1000
V/V
VOUT = −10 V to +10 V
0.03
0.10
0.10
0.10
0.15
0.03
0.10
0.10
0.10
0.1
0.5
0.5
0.5
%
%
%
%
1
1
1
VOUT = −10 V to +10 V
G = 5 to 1000
50
50
ppm
Gain vs. Temperature
G = 5
5
10
5
10
ppm/°
C
ppm/°
C
G > 51
50
50
INPUT
Input Impedance
Differential
Common-Mode
Input Voltage Range2
2||2
2||2
2||2
2||2
GΩ||pF
GΩ||pF
V
(−VS) −
0.15
(+VS) −
1.5
(−VS) −
0.15
(+VS) −
1.5
OUTPUT
Output Swing
RL = 10 kΩ to ground
(−VS) +
0.2
(+VS) −
0.5
(+VS) −
0.2
(−VS) +
0.2
(−VS) +
0.1
(+VS) −
0.5
(+VS) −
0.2
V
V
RL = 100 kΩ to ground (−VS) +
0.1
REFERENCE INPUT
RIN
IIN
60
+50
20%
+60
+VS
60
+50
20%
+60
+VS
kΩ
μA
V
VIN+, VREF = 0
Voltage Range
Gain to Output
−VS
−VS
1
1
V
0.0002
0.0002
POWER SUPPLY
Operating Range
2.5
12.5
600
2.5
12.5
600
V
μA
Quiescent Current
TEMPERATURE RANGE
For Specified Performance
−40
+85
−40
+85
°C
1 Does not include effects of external resistor RG.
2 One input grounded. G = 1.
Rev. PrA | Page 6 of 20
Preliminary Technical Data
AD8223
ABSOLUTE MAXIMUM RATINGS
Table 3.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Parameter
Rating
Supply Voltage
12.5 V
Specification is for device in free air.
Internal Power Dissipation
Differential Input Voltage
Output Short-Circuit Duration
Storage Temperature Range (R, RM)
Operating Temperature Range (A)
Lead Temperature (Soldering 10 sec)
650 mW
6 V
Indefinite
−65°C to +125°C
−40°C to +85°C
+300°C
Table 4. Thermal Resistance
Package Type
8-Lead SOIC
8-Lead MSOP
θJA
Unit
°C/W
°C/W
155
200
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. PrA | Page 7 of 20
AD8223
Preliminary Technical Data
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C VS = 5 V, RL = 10 kꢀ, unless otherwise noted.
50
40
35
30
25
20
15
10
5
40
30
20
10
0
0
–9
–6
–3
0
3
6
9
–200
–150
–100
–50
0
50
100
150
200
CMRR, G = 100 (µV/V)
INPUT OFFSET VOLTAGE (µV)
Figure 2. Typical Distribution of Input Offset Voltage
Figure 5. Typical Distribution for CMRR (G = 100)
1000
100
10
80
70
60
50
40
30
20
10
0
G = 5
G = 10
G = 1000
BW LIMIT
G = 100
BW LIMIT
0
3
6
9
12
15
18
21
24
0.1
1
10
100
FREQUENCY (Hz)
1k
10k
100k
INPUT BIAS CURRENT (nA)
Figure 3. Typical Distribution of Input Bias Current
Figure 6. Voltage Noise Spectral Density vs. Frequency
30
25
20
15
10
5
80
60
40
20
0
0
–40
–20
0
20
40
–60 –40 –20
0
20
40
60
80
100 120 140
CMRR, G = 5 (µV/V)
TEMPERATURE (°C)
Figure 4. Typical Distribution for CMRR (G = 5)
Figure 7. IBIAS vs. Temperature
Rev. PrA | Page 8 of 20
Preliminary Technical Data
AD8223
1k
G = 1000
100
G = 5
10
1
10
100
FREQUENCY (Hz)
1k
0.5µV/DIV
1s/DIV
Figure 8. Current Noise Spectral Density vs. Frequency
Figure 11. 0.1 Hz to 10 Hz RTI and RTO Voltage Noise
120
110
100
90
18
16
14
12
10
8
G = 1000
G = 5
V
= ±5V
S
V
= ±2.5V
S
V
= ±12V
S
G = 100
G = 10
80
70
60
6
50
4
40
2
30
0
1
10
100
1k
10k
100k
–12 –10 –8
–6
–4
–2
0
2
4
6
8
10
FREQUENCY (Hz)
CMV (V)
Figure 12. CMRR vs. Frequency, 12 VS
Figure 9. IBIAS vs. CMV
120
110
100
90
G = 1000
0.71pA/DIV
1s/DIV
G = 5
G = 10
G = 100
80
70
60
50
40
30
1
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 13. CMRR vs. Frequency, VS = +5 V
Figure 10. 0.1 Hz to 10 Hz Current Noise (0.71 pA/Div)
Rev. PrA | Page 9 of 20
AD8223
Preliminary Technical Data
70
6
5
G = 1000
G = 100
60
V
= ±5V
S
4
50
3
40
2
V
= ±2.5V
S
30
1
V
= +5V
G = 10
G = 5
S
20
0
–1
–2
–3
–4
–5
–6
10
0
–10
–20
–30
100
1k
10k
100k
1M
–6 –5 –4 –3 –2 –1
0
1
2
3
4
5
6
FREQUENCY (Hz)
OUTPUT (V)
Figure 14. Gain vs. Frequency
Figure 17. Common-Mode Input vs. Maximum Output Voltage,
G = 100, Small Supplies
6
5
16
+V = +15V, –V = –5V
S
S
14
12
10
8
V
= ±12V
S
4
V
= ±5V
S
3
2
6
V
= ±2.5V
S
4
1
2
0
V
= +5V
S
0
–1
–2
–3
–4
–5
–6
–2
–4
–6
–8
–10
–12
–14
–6 –5 –4 –3 –2 –1
0
1
2
3
4
5
6
–14 –12 –10 –8 –6 –4 –2
0
2
4
6
8
10 12 14 16 18
OUTPUT (V)
OUTPUT (V)
Figure 15. Common-Mode Input vs. Maximum Output Voltage,
G = 5, Small Supplies
Figure 18. Common-Mode Input vs. Maximum Output Voltage,
G = 100, Large Supplies
16
140
+V = +15V, –V = –5V
S
S
14
12
10
8
120
V
= ±12V
S
G = 1000
100
6
G = 100
4
80
2
G = 10
0
60
–2
–4
–6
–8
–10
–12
–14
G = 5
40
20
0
–14 –12 –10 –8 –6 –4 –2
0
2
4
6
8
10 12 14 16
1
10
100
1k
10k
100k
OUTPUT (V)
FREQUENCY (Hz)
Figure 16. Common-Mode Input vs. Maximum Output Voltage,
G = 5, Large Supplies
Figure 19. Positive PSRR vs. Frequency, VS = 12 V
Rev. PrA | Page 10 of 20
Preliminary Technical Data
AD8223
140
120
G = 1000
100
80
60
40
20
0
5V/DIV
G = 100
G = 10
G = 5
0.1%/DIV
1
10
100
1k
10k
100k
100µs/DIV
FREQUENCY (Hz)
Figure 20. Positive PSRR vs. Frequency, VS = 5 V
Figure 23. Large Signal Response, G = 5
120
100
80
60
40
20
0
G = 1000
5V/DIV
G = 100
G = 10
G = 5
0.1%/DIV
1
10
100
1k
10k
100k
100µs/DIV
FREQUENCY (Hz)
Figure 21. Negative PSRR vs. Frequency, VS = 12 V
Figure 24. Large Signal Pulse Response, G = 100, CL = 100 pF
5V/DIV
0.1%/DIV
100µs/DIV
Figure 25. Large Signal Pulse Response, G = 1000, CL = 100 pF
Figure 22. Settling Time to 0.005% vs. Gain, for a 20 V Step at Output,
CL = 100 pF, VS = 12 V
Rev. PrA | Page 11 of 20
AD8223
Preliminary Technical Data
+V
S
G = 5
G = 10
–1
G = 100
–2
2
1
2
–V
S
0.01
0.1
1
10
20mV/DIV
10µs/DIV
I
(mA)
OUT
Figure 28. Output Voltage Swing vs. Output Current
Figure 26. Small Signal Pulse Response, G = 5, 10, 100; RL = 10 kΩ
2
20mV/DIV
100µs/DIV
Figure 27. Small Signal Pulse Response, G = 1000, RL = 25 kΩ, CL = 100 pF
Rev. PrA | Page 12 of 20
Preliminary Technical Data
AD8223
THEORY OF OPERATION
AMPLIFIER ARCHITECTURE
GAIN SELECTION
The AD8223 is an instrumentation amplifier based on a
classic 3-op amp approach, modified to assure operation
even at common-mode voltages at the negative supply rail.
The architecture allows lower voltage offsets, better CMRR,
and higher gain accuracy than competing instrumentation
amplifiers in its class.
Placing a resistor across the RG terminals sets the gain of the
AD8223, which can be calculated by referring to Table 5 or by
using the following gain equation:
80 kꢀ
RG
=
G − 5
POSITIVE SUPPLY
7
Table 5. Gains Achieved Using 1% Resistors
1% Standard Table
+
Value of RG (Ω)
26.7k
15.8k
5.36k
2.26k
1.78k
845
412
162
80.6
Desired Gain
Calculated Gain
INVERTING
–
2
8
10
20
40
7.99
10.1
19.9
40.4
49.9
99.7
199
499
998
4
8kΩ
8kΩ
10kΩ
10kΩ
50kΩ
1
–
OUT
6
GAIN
+
50kΩ
REF
5
8
50
7
4
100
200
500
1000
–
+
NON-
INVERTING
3
NEGATIVE SUPPLY
The AD8223 defaults to G = 5 when no gain resistor is used.
The tolerance and gain drift of the RG resistor should be added
to the specifications of the AD8223 to determine the total gain
accuracy of the system. When the gain resistor is not used,
gain error and gain drift are kept to a minimum.
Figure 29. Simplified Schematic
Figure 29 shows a simplified schematic of the AD8223. The
AD8223 has three stages. In the first stage, the input signal is
applied to PNP transistors. These PNP transistors act as voltage
buffers and allow input voltages below ground. The second
stage consists of a pair of 8 kꢀ resistors, the RG resistor, and a
pair of amplifiers. This stage allows the amplification of the
AD8223 to be set with a single external resistor. The third stage
is a differential amplifier composed of an op amp, two 10 kꢀ
resistors, and two 50 kꢀ resistors. This stage removes the
common mode signal and applies an additional gain of 5.
INPUT VOLTAGE RANGE
The 3-op amp architecture of the AD8223 applies gain and then
removes the common-mode voltage. Therefore, internal nodes
in the AD8223 experience a combination of both the gained
signal and the common-mode signal. This combined signal can
be limited by the voltage supplies even when the individual input
and output signals are not. To determine whether the signal can be
limited, refer to Figure 15 through Figure 18. Alternatively, use
the parameters in the Specifications section to verify that the
input and output are not limited and then use the following
formula to make sure the internal nodes are not limited:
The transfer function of the AD8223 is
V
OUT = G(VIN+ − VIN−) + VREF
where:
80 kꢀ
G = 5 +
RG
To check if it is limited by the internal nodes,
VDIFF ×Gain
−VS + 0.01 V < 0.6 + VCM
±
<+ VS − 0.1 V
10
If more common-mode range is required, a solution is to apply less
gain in the instrumentation amplifier and more in a later stage.
Rev. PrA | Page 13 of 20
AD8223
Preliminary Technical Data
REFERENCE TERMINAL
RF INTERFERENCE
The output voltage of the AD8223 is developed with respect to
the potential on the reference terminal. This is useful when the
output signal needs to be offset to a precise midsupply level. For
example, a voltage source can be tied to the REF pin to level-
shift the output so that the AD8223 can drive a single-supply
ADC. The REF pin is protected with ESD diodes and should
not exceed either +VS or −VS by more than 0.3 V.
RF rectification is often a problem when amplifiers are used in
applications where there are strong RF signals. The disturbance
can appear as a small dc offset voltage. High frequency signals
can be filtered with a low-pass, R-C network placed at the input
of the instrumentation amplifier, as shown in Figure 32. The
filter limits the input signal bandwidth according to the follow-
ing relationship:
1
For best performance, source impedance to the REF terminal
should be kept below 5 Ω. As shown in Figure 29, the reference
terminal, REF, is at one end of a 50 kꢀ resistor. Additional
impedance at the REF terminal adds to this resistor and results
in poorer CMRR performance.
FilterFreqDiff =
2π R(2CD + CC)
1
FilterFreqCM =
2π RCC
INCORRECT
CORRECT
where CD ≥ 10CC.
+15V
+
10µF
0.1µF
+IN
AD8223
AD8223
C
1nF
C
V
REF
V
R
REF
+
–
4.02kΩ
+
V
OUT
C
D
47nF
R1
499Ω
AD8223
OP2177
–
R
REF
–IN
4.02kΩ
C
1nF
C
Figure 30. Driving the Reference Pin
10µF
+
0.1µF
INPUT PROTECTION
–15V
Internal supply referenced clamping diodes allow the input,
reference, output, and gain terminals of the AD8223 to safely
withstand overvoltages of 0.3 V above or below the supplies.
This is true for all gains, and for power-on and power-off. This
last case is particularly important because the signal source and
amplifier may be powered separately.
Figure 32. RFI Suppression
Figure 32 shows an example where the differential filter
frequency is approximately 400 Hz, and the common-mode
filter frequency is approximately 40 kHz. The typical dc offset
shift over frequency is less than 1.5 μV and the circuit’s RF
signal rejection is better than 71 dB.
If the overvoltage is expected to exceed this value, the current
through these diodes should be limited to about 10 mA using
external current limiting resistors. This is shown in Figure 31.
The size of this resistor is defined by the supply voltage and the
required overvoltage protection.
The resistors were selected to be large enough to isolate the
circuit’s input from the capacitors, but not large enough to
significantly increase the circuit’s noise. Values of R and CC
should be chosen to minimize RFI. Mismatch between the R × CC
at the positive input and the R × CC at negative input degrades
the CMRR of the AD8223. Because of their higher accuracy and
stability, COG/NPO type ceramic capacitors are recommended
for the CC capacitors. The dielectric for the CD capacitor is not
as critical.
+V
S
1 = 10mA MAX
R
LIM
+
–
V
OVER
R
G
OUTPUT
AD8223
R
LIM
V
V
– V + 0.7V
S
OVER
OVER
R
=
LIM
10mA
–V
S
Figure 31. Input Protection
Rev. PrA | Page 14 of 20
Preliminary Technical Data
AD8223
INCORRECT
+V
CORRECT
+V
GROUND RETURNS FOR INPUT BIAS CURRENTS
S
S
Input bias currents are those dc currents that must flow to bias
the input transistors of an amplifier. These are usually transistor
base currents. When amplifying floating input sources such as
transformers or ac-coupled sources, there must be a direct dc
path into each input so that the bias current can flow. Figure 33
shows how a bias current path can be provided for the cases of
transformer coupling, capacitive ac-coupling and for a
thermocouple application.
AD8223
AD8223
REF
REF
REF
REF
–V
–V
S
S
TRANSFORMER
TRANSFORMER
In dc-coupled resistive bridge applications, providing this path
is generally not necessary as the bias current simply flows from
the bridge supply through the bridge and into the amplifier.
However, if the impedances that the two inputs see are large and
differ by a large amount (>10 kꢀ), the offset current of the
input stage causes dc errors proportional with the input offset
voltage of the amplifier.
+V
+V
S
S
AD8223
AD8223
REF
10MΩ
–V
–V
S
S
THERMOCOUPLE
THERMOCOUPLE
+V
+V
S
S
C
C
C
1
R
R
fHIGH-PASS
=
2πRC
AD8223
AD8223
C
REF
–V
–V
S
S
CAPACITIVELY COUPLED
CAPACITIVELY COUPLED
Figure 33. Creating an IBIAS Path
Rev. PrA | Page 15 of 20
AD8223
Preliminary Technical Data
APPLICATIONS INFORMATION
+V
+V
S
S
+2.5V TO +6V
+3V TO +12V
+
+
0.1µF
10µF
0.1µF
10µF
+
+
R
R
G
G
G
V
R
V
R
G
OUTPUT
V
OUTPUT
V
OUT
IN
G
IN
OUT
R
–
R
–
REF
REF
G
REF (INPUT)
REF (INPUT)
0.1µF
10µF
+
–2.5V TO –6V
–V
S
A. DUAL SUPPLY
B. SINGLE SUPPLY
Figure 34. Basic Connections
BASIC CONNECTION
OUTPUT BUFFERING
Figure 34 shows the basic connection circuit for the AD8223.
The +VS and −VS terminals are connected to the power supply.
The supply can be either bipolar (VS = 2.5 V to 12.5 V) or
single supply (−VS = 0 V, +VS = +3.0 V to +25 V). Power
supplies should be capacitively decoupled close to the device’s
power pins. For best results, use surface-mount 0.1 μF ceramic
chip capacitors and 10 μF electrolytic tantalum capacitors.
The AD8223 is designed to drive loads of 10 kꢀ or greater. If
the load is less than this value, the AD8223 output should be
buffered with a precision single-supply op amp such as the
OP113. This op amp can swing from 0 V to 4 V on its output
while driving a load as small as 600 ꢀ.
5V
0.1µF
5V
The input voltage, which can be either single-ended (tie either
−IN or +IN to ground) or differential, is amplified by the
programmed gain. The output signal appears as the voltage
difference between the output pin and the externally applied
voltage on the REF input.
0.1µF
+
AD8223
V
R
G
IN
+
–
OP113
V
OUT
REF
–
DIFFERENTIAL OUTPUT
Figure 36. Output Buffering
Figure 35 shows how to create a differential output in-amp. A
OP1177 op amp creates the inverted output. Because the op
amp drives the AD8223 reference pin, the AD8223 can still
ensure that the differential voltage is correct. Errors from the
op amp or mismatched resistors are common to both outputs
and are thus common mode. These common-mode errors
should be rejected by the next device in the signal chain.
CABLES
Receiving from a Cable
In many applications, shielded cables are used to minimize
noise; for best CMR over frequency, the shield should be
properly driven. Figure 37 shows an active guard drive that
is configured to improve ac common-mode rejection by
bootstrapping the capacitances of input cable shields, thus
minimizing the capacitance mismatch between the inputs.
+IN
+OUT
AD8223
+V
S
–INPUT
2
1
–IN
7
20kΩ
20kΩ
REF
R
V
G
G
REF
100Ω
2
6
V
AD8223
AD8031
OUT
R
–
+
5
2
8
3
OP1177
4
REFERENCE
+INPUT
–V
S
Figure 37. Common-Mode Shield Driver
–OUT
Figure 35. Differential Output Using Op Amp
Rev. PrA | Page 16 of 20
Preliminary Technical Data
AD8223
Driving a Cable
The bridge circuit is excited by a +5 V supply. The full-scale
output voltage from the bridge ( 10 mV) therefore has a
common-mode level of 2.5 V. The AD8223 removes the
common-mode component and amplifies the input signal by a
factor of 100 (RGAIN = 1.02 kꢀ). This results in an output signal
of 1 V. To prevent this signal from running into the AD8223
ground rail, the voltage on the REF pin has to be raised to at
least 1 V. In this example, the 2 V reference voltage from the
AD7776 ADC is used to bias the AD8223 output voltage to 2 V
1 V. This corresponds to the input range of the ADC.
All cables have a certain capacitance per unit length, which
varies widely with cable type. The capacitive load from the
cable may cause peaking in the AD8223’s output response. To
reduce the peaking, use a resistor between the AD8223 and the
cable. Because cable capacitance and desired output response
vary widely, this resistor is best determined empirically. A good
starting point is 50 Ω.
The AD8232 operates at a low enough frequency that
transmission line effects are rarely an issue; therefore, the
resistor need not match the characteristic impedance of
the cable.
AMPLIFYING SIGNALS WITH LOW COMMON-
MODE VOLTAGE
Because the common-mode input range of the AD8223 extends
0.1 V below ground, it is possible to measure small differential
signals that have low, or no, common-mode components. Figure 40
AD8223
(DIFF OUT)
shows a thermocouple application where one side of the J-type
thermocouple is grounded.
5V
0.1µF
AD8223
+
(SINGLE OUT)
R
J-TYPE
THERMOCOUPLE
G
V
AD8223
OUT
1.02kΩ
REF
–
2V
Figure 38. Driving a Cable
Figure 40. Amplifying Bipolar Signals with Low Common-Mode Voltage
Over a temperature range from −200°C to +200°C, the J-type
thermocouple delivers a voltage ranging from −7.890 mV
to 10.777 mV. A programmed gain on the AD8223 of 100
(RG = 845) and a voltage on the AD8223 REF pin of 2 V results
in the AD8223 output voltage ranging from 1.110 V to 3.077 V
relative to ground.
A SINGLE-SUPPLY DATA ACQUISITION SYSTEM
Interfacing bipolar signals to single-supply analog-to-digital
converters (ADCs) presents a challenge. The bipolar signal
must be mapped into the input range of the ADC. Figure 39
shows how this translation can be achieved.
5V
5V
5V
0.1µF
0.1µF
AD7776
+
R
G
±10mV
AD8223
–
A
IN
1.02kΩ
REF
REF
REF
OUT
IN
Figure 39. A Single Supply Data Acquisition System
Rev. PrA | Page 17 of 20
AD8223
Preliminary Technical Data
OUTLINE DIMENSIONS
3.20
3.00
2.80
8
1
5
4
5.15
4.90
4.65
3.20
3.00
2.80
PIN 1
0.65 BSC
0.95
0.85
0.75
1.10 MAX
0.80
0.60
0.40
8°
0°
0.15
0.00
0.38
0.22
0.23
0.08
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 41. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 42. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
Rev. PrA | Page 18 of 20
Preliminary Technical Data
AD8223
ORDERING GUIDE
Model
AD8223AR
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option
R-8
R-8
Branding
8-Lead SOIC_N
AD8223AR-RL
AD8223AR-R7
AD8223ARM
AD8223ARM-RL
AD8223ARM-R7
AD8223ARMZ1
AD8223ARMZ-RL1
AD8223ARMZ-R71
AD8223ARZ1
AD8223ARZ-RL1
AD8223ARZ-R71
AD8223BR
AD8223BR-RL
AD8223BR-R7
AD8223BRM
8-Lead SOIC_N,13" Tape and Reel
8-Lead SOIC_N, 7" Tape and Reel
8-Lead MSOP
8-Lead MSOP, 13" Tape and Reel
8-Lead MSOP, 7" Tape and Reel
8-Lead MSOP
8-Lead MSOP, 13" Tape and Reel
8-Lead MSOP, 7" Tape and Reel
8-Lead SOIC_N
8-Lead SOIC_N, 13" Tape and Reel
8-Lead SOIC_N, 7" Tape and Reel
8-Lead SOIC_N
8-Lead SOIC_N, 13" Tape and Reel
8-Lead SOIC_N, 7" Tape and Reel
8-Lead MSOP
8-Lead MSOP, 13" Tape and Reel
8-Lead MSOP, 7" Tape and Reel
8-Lead MSOP
8-Lead MSOP, 13" Tape and Reel
8-Lead MSOP, 7" Tape and Reel
8-Lead SOIC_N
8-Lead SOIC_N, 13" Tape and Reel
8-Lead SOIC_N, 7" Tape and Reel
R-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
R-8
R-8
R-8
R-8
R-8
Y0U
Y0U
Y0U
Y0Q
Y0Q
Y0Q
R-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
R-8
Y0V
Y0V
Y0V
Y0R
Y0R
Y0R
AD8223BRM-RL
AD8223BRM-R7
AD8223BRMZ1
AD8223BRMZ-RL1
AD8223BRMZ-R71
AD8223BRZ1
AD8223BRZ-RL1
AD8223BRZ-R71
R-8
R-8
1 Z = RoHS Compliant Part.
Rev. PrA | Page 19 of 20
AD8223
NOTES
Preliminary Technical Data
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR06925-0-1/08(PrA)
Rev. PrA | Page 20 of 20
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