AD8224ACPZ-WP [ADI]
Precision, Dual-Channel, JFET Input Rail-to-Rail Instrumentation Amplifier; 精密，双通道， JFET输入，轨到轨仪表放大器
| 型号： | AD8224ACPZ-WP |
| 厂家： | 
ADI |
| 描述： | Precision, Dual-Channel, JFET Input Rail-to-Rail Instrumentation Amplifier |
| 文件： | 总27页 (文件大小：1382K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Precision, Dual-Channel, JFET Input
Rail-to-Rail Instrumentation Amplifier
Preliminary Technical Data
AD8224
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Two channels in a small 4 mm × 4 mm LFCSP
Low input currents
16 15 14 13
10 pA maximum input bias current (B grade)
0.6 pA maximum input offset current (B grade)
High CMRR
100 dB CMRR (minimum), G = 10 (B grade)
80 dB CMRR (minimum) to 5 kHz, G = 1 (B grade)
Excellent ac specifications and low power
1.5 MHz bandwidth (G = 1)
AD8224
1
2
3
4
12
11
10
9
–IN1
RG1
RG1
+IN1
–IN2
RG2
RG2
+IN2
5
6
7
8
14 nV/√Hz input noise (1 kHz)
Slew rate 2 V/μs
750 μA quiescent supply current per amplifier (maximum)
Versatility
Figure 1. 4mm × 4 mm LFCSP
Rail-to-rail output
Table 1. In Amps and Difference Amplifiers by Category
Input voltage range to below negative supply rail
4 kV ESD protection
4.5 V to 36 V single supply
2.25 V to 18 V dual supply
Gain set with single resistor (G = 1 to 1000)
High
Perform. Cost
Low
High
Volt.
Mil
Low
Digital
Gain
Grade Power
AD82201
AD8221
AD8222
AD82241
AD85531 AD628 AD620 AD6271 AD85551
AD6231
AD629 AD621
AD524
AD85561
AD85571
AD526
APPLICATIONS
AD624
Medical instrumentation
Precision data acquisition
Transducer interface
Differential drive for
High resolution input ADCs
Remote sensors
1 Rail-to-rail output.
GENERAL DESCRIPTION
The AD8224 is the first single-supply junction field effect
transistor (JFET) input instrumentation amplifier available in
the space-saving 16-lead, 4 mm×4 mm LFCSP. It requires the
same board area as a typical single instrumentation amplifier,
yet doubles the channel density and offers a lower cost per
channel without compromising performance.
Designed to alleviate this problem, the AD8224 can operate on a
18 V dual supply, as well as on a single +5 V supply. The device’s
rail-to-rail output stage maximizes dynamic range on the low
voltage supplies common in portable applications. Its ability to run
on a single 5 V supply eliminates the need for higher voltage, dual
supplies. The AD8224 draws a maximum of 750 μA of quiescent
current per amplifier, making it ideal for battery-powered devices.
Designed to meet the needs of high performance, portable
instrumentation, the AD8224 has a minimum common-mode
rejection ratio (CMRR) of 86 dB at dc and a minimum CMRR
of 80 dB at 5 kHz for G = 1. Maximum input bias current is
10 pA and typically remains below 300 pA over the entire
industrial temperature range. Despite the JFET inputs, the
AD8224 typically has a noise corner of only 10 Hz.
In addition, the AD8224 can be configured as a single-channel,
differential output instrumentation amplifier. Differential
outputs provide high noise immunity, which can be useful when
the output signal must travel through a noisy environment, such
as with remote sensors. The configuration can also be used to
drive differential input ADCs.
With the proliferation of mixed-signal processing, the number of
power supplies required in each system has grown.
For a single-channel version, use the AD8220 device.
Rev. PrB
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
AD8224
Preliminary Technical Data
TABLE OF CONTENTS
Features .............................................................................................. 1
Layout .......................................................................................... 21
Solder Wash................................................................................. 22
Input Bias Current Return Path ............................................... 22
Input Protection ......................................................................... 22
RF Interference ........................................................................... 22
Common-Mode Input Voltage Range ..................................... 23
Applications..................................................................................... 24
Driving an Analog-to-Digital Converter ................................ 24
Differential Output .................................................................... 24
Driving a Differential Input ADC............................................ 25
Driving Cabling.......................................................................... 25
Outline Dimensions....................................................................... 26
Ordering Guide .......................................................................... 26
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History .......................... Error! Bookmark not defined.
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 9
Thermal Resistance ...................................................................... 9
ESD Caution.................................................................................. 9
Pin Configuration and Function Descriptions........................... 10
Typical Performance Characteristics ........................................... 11
Theory of Operation ...................................................................... 20
Gain Selection............................................................................. 20
Reference Terminal .................................................................... 21
Rev. PrB | Page 2 of 27
Preliminary Technical Data
AD8224
SPECIFICATIONS
VS+ = +15 V, VS− = −15 V, VREF = 0 V, TA = +25°C, G = 1, RL = 2 kΩ, unless otherwise noted.
Table 2. Single-Ended and Differential1 Output Configuration
A Grade
Typ
Parameter
Test Conditions
Min
Max
Unit
COMMON-MODE REJECTION RATIO (CMRR)
CMRR DC to 60 Hz with 1 kΩ Source Imbalance
VCM
=
10 V
G = 1
78
94
94
94
dB
dB
dB
dB
G = 10
G = 100
G = 1000
CMRR at 5 kHz
G = 1
VCM
=
10 V
74
84
84
84
dB
dB
dB
dB
G = 10
G = 100
G = 1000
NOISE
RTI noise = √(eni2 + (eno/G)2)
Voltage Noise, 1 kHz
Input Voltage Noise, eni
Output Voltage Noise, eno
RTI, 0.1 Hz to 10 Hz
G = 1
VIN+, VIN− = 0 V
VIN+, VIN− = 0 V
14
90
nV√Hz
nV√Hz
5
μV p-p
μV p-p
fA/√Hz
G = 1000
0.8
1
Current Noise
f = 1 kHz
VOLTAGE OFFSET
Input Offset, VOSI
Average TC
RTI VOS = (VOSI) + (VOSO/G)
250
10
μV
T = −40°C to +85°C
T = −40°C to +85°C
μV/°C
μV
Output Offset, VOSO
750
10
Average TC
μV/°C
Offset RTI vs. Supply (PSR)
G = 1
86
96
96
96
dB
dB
dB
dB
G = 10
G = 100
G = 1000
INPUT CURRENT (PER CHANNEL)
Input Bias Current
Over Temperature2
25
2
pA
pA
T = −40°C to +85°C
300
5
Input Offset Current
Over Temperature2
GAIN
pA
pA
T = −40°C to +85°C
G = 1 + (49.4 kΩ/RG)
Gain Range
Gain Error
G = 1
1
1000
V/V
VOUT
= 10 V
0.06
0.3
%
%
%
%
G = 10
G = 100
0.3
G = 1000
Gain Nonlinearity
G = 1
0.3
VOUT = −10 V to +10 V
RL = 10 kΩ
10
5
15
10
60
ppm
ppm
ppm
G = 10
RL = 10 kΩ
G = 100
RL = 10 kΩ
30
Rev. PrB | Page 3 of 27
AD8224
Preliminary Technical Data
A Grade
Parameter
Test Conditions
RL = 10 kΩ
RL = 2 kΩ
Min
Typ
400
10
Max
500
15
Unit
ppm
ppm
ppm
ppm
G = 1000
G = 1
G = 10
RL = 2 kΩ
10
15
G = 100
RL = 2 kΩ
50
75
Gain vs. Temperature
G = 1
3
10
ppm/°C
ppm/°C
G > 10
−50
INPUT
Impedance (Pin to Ground)3
Input Operating Voltage Range4
Over Temperature
OUTPUT
104||5
GΩ||pF
VS = 2.25 V to 18 V for dual supplies
T = −40°C to +85°C
−VS − 0.1
−VS − 0.1
+VS − 2
V
V
+VS − 2.1
Output Swing
Over Temperature
Output Swing
Over Temperature
Short-Circuit Current
REFERENCE INPUT
RIN
RL = 2 kΩ
−14.3
−14.3
−14.7
−14.6
+14.3
+14.1
+14.7
+14.6
V
V
T = −40°C to +85°C
RL = 10 kΩ
V
T = −40°C to +85°C
V
15
40
mA
kΩ
μA
V
IIN
VIN+, VIN− = 0 V
70
Voltage Range
Gain to Output
POWER SUPPLY (PER AMPLIFIER)
Operating Range
Quiescent Current
Over Temperature
TEMPERATURE RANGE
For Specified Performance
Operational6
−VS
+VS
1
0.0001
V/V
2.255
18
750
850
V
μA
μA
T = −40°C to +85°C
−40
−40
+85
°C
°C
+125
1 Refers to differential configuration shown in Figure 64.
2 Please refer to Figure 16 and Figure 17 for the relationship between input current and temperature.
3 Differential and common-mode input impedance can be calculated from the pin impedance: ZDIFF = 2(ZPIN); ZCM = ZPIN/2.
4 The AD8224 can operate up to a diode drop below the negative supply but the bias current increases sharply. The input voltage range reflects the maximum
allowable voltage where the input bias current is within the specification.
5 At this supply voltage, ensure that the input common-mode voltage is within the input voltage range specification.
6 The AD8224 is characterized from −40°C to +125°C. See the Typical Performance Characteristics section for expected operation in this temperature range.
Rev. PrB | Page 4 of 27
Preliminary Technical Data
AD8224
VS+ = +15 V, VS− = −15 V, VREF = 0 V, TA = +25°C, G = 1, RL = 2 kΩ, unless otherwise noted.
Table 3. Single-Ended Output Configuration—Dynamic Performance (Both Amplifiers)
A Grade
Typ
Parameter
DYNAMIC RESPONSE
Small Signal Bandwidth −3 dB
G = 1
Conditions
Min
Max
Unit
TBD
TBD
TBD
TBD
kHz
kHz
kHz
kHz
G = 10
G = 100
G =1000
Settling Time 0.01%
G = 1
G = 10
G = 100
G =1000
Settling Time 0.001%
G = 1
G = 10
10 V step
10 V step
TBD
TBD
TBD
TBD
ꢀs
ꢀs
ꢀs
ꢀs
TBD
TBD
TBD
TBD
ꢀs
ꢀs
ꢀs
ꢀs
G = 100
G =1000
Slew Rate
G = 1 to 100
TBD
V/ꢀs
Please fill in TBDs if you can.
VS+ = +15 V, VS− = −15 V, VREF = 0 V, TA = +25°C, G = 1, RL = 2 kΩ, unless otherwise noted.
Table 4. Differential Output Configuration1—Dynamic Performance
A Grade
Typ
Parameter
DYNAMIC RESPONSE
Small Signal Bandwidth−3 dB
G = 1
Conditions
Min
Max
Unit
TBD
TBD
TBD
TBD
kHz
kHz
kHz
kHz
G = 10
G = 100
G =1000
Settling Time 0.01%
G = 1
G = 10
G = 100
G =1000
Settling Time 0.001%
G = 1
G = 10
10 V step
10 V step
TBD
TBD
TBD
TBD
ꢀs
ꢀs
ꢀs
ꢀs
TBD
TBD
TBD
TBD
ꢀs
ꢀs
ꢀs
ꢀs
G = 100
G =1000
Slew Rate
G = 1 to 100
TBD
V/ꢀs
1 Refers to differential configuration shown in Figure 64.
Rev. PrB | Page 5 of 27
AD8224
Preliminary Technical Data
VS + = 5 V, VS− = 0 V, VREF = 2.5 V, TA = +25°C, G = 1, RL = 2 kΩ, unless otherwise noted.
Table 5. Single-Ended and Differential1 Output Configuration
A Grade
Parameter
Test Conditions
Min
Typ
Max
Unit
COMMON-MODE REJECTION RATIO (CMRR)
CMRR DC to 60 Hz with 1 kΩ Source Imbalance
G = 1
VCM = 0 to 2.5 V
78
94
94
94
dB
dB
dB
dB
G = 10
G = 100
G = 1000
CMRR at 5 kHz
G = 1
74
84
84
84
dB
dB
dB
dB
G = 10
G = 100
G = 1000
NOISE
RTI noise = √(eni2 + (eno/G)2)
Voltage Noise, 1 kHz
Input Voltage Noise, eni
Output Voltage Noise, eno
RTI, 0.1 Hz to 10 Hz
G = 1
VIN+, VIN− = 0 V, VREF = 0 V
VIN+, VIN− = 0 V, VREF = 0 V
14
90
nV√Hz
nV√Hz
5
0.8
1
μV p-p
μV p-p
fA/√Hz
G = 1000
Current Noise
VOLTAGE OFFSET
Input Offset, VOSI
Average TC
f = 1 kHz
RTI VOS = (VOSI) + (VOSO/G)
300
10
μV
μV/°C
μV
T = −40°C to +85°C
T = −40°C to +85°C
Output Offset, VOSO
Average TC
800
10
μV/°C
Offset RTI vs. Supply (PSR)
G = 1
86
96
96
96
dB
dB
dB
dB
G = 10
G = 100
G = 1000
INPUT CURRENT (PER CHANNEL)
Input Bias Current
Over Temperature2
Input Offset Current
Over Temperature2
GAIN
25
2
pA
pA
pA
pA
T = −40°C to +85°C
300
5
T = −40°C to +85°C
G = 1 + (49.4 kΩ/RG)
Gain Range
1
1000
V/V
VOUT = 0.3 V to 2.9 V for G = 1
VOUT = 0.3 V to 3.8 V for G > 1
Gain Error
G = 1
0.06
0.3
%
%
%
%
G = 10
G = 100
G = 1000
Nonlinearity
0.3
0.3
VOUT = 0.3 V to 2.9 V for G = 1
VOUT = 0.3 V to 3.8 V for G > 1
G = 1
RL = 10 kΩ
RL = 10 kΩ
RL = 10 kΩ
35
35
50
50
50
75
ppm
ppm
ppm
G = 10
G = 100
Rev. PrB | Page 6 of 27
Preliminary Technical Data
AD8224
A Grade
Typ
650
35
Parameter
Test Conditions
RL = 10 kΩ
RL = 2 kΩ
Min
Max
750
50
Unit
ppm
ppm
ppm
ppm
G = 1000
G = 1
RL = 2 kΩ
G = 10
35
50
RL = 2 kΩ
G = 100
50
75
Gain vs. Temperature
G = 1
3
10
ppm/°C
ppm/°C
G > 10
−50
INPUT
Impedance (Pin to Ground)3
Input Voltage Range4
Over Temperature
OUTPUT
104||6
GΩ||pF
V
−0.1
−0.1
+VS − 2
T = −40°C to +85°C
+VS − 2. V
Output Swing
Over Temperature
Output Swing
Over Temperature
Short-Circuit Current
REFERENCE INPUT
RIN
RL = 2 kΩ
0.25
0.3
4.75
4.70
4.85
4.80
V
V
T = −40°C to +85°C
RL = 10 kΩ
0.15
0.2
V
T = −40°C to +85°C
V
15
40
mA
kΩ
μA
V
VIN+, VIN− = 0 V
IIN
70
Voltage Range
Gain to Output
POWER SUPPLY (PER AMPLIFIER)
Operating Range
Quiescent Current
Over Temperature
TEMPERATURE RANGE
For Specified Performance
Operational5
−VS
+VS
1
0.0001
V/V
+4.5
+36
750
850
V
μA
μA
T = −40°C to +85°C
−40
−40
+85
°C
°C
+125
1 Refers to differential configuration shown in Figure 64.
2 Refer to Figure 16 and Figure 17 for the relationship between input current and temperature.
3 Differential and common-mode impedance can be calculated from the pin impedance: ZDIFF = 2(ZPIN); ZCM = ZPIN/2.
4 The AD8224 can operate up to a diode drop below the negative supply but the bias current increases sharply. The input voltage range reflects the maximum
allowable voltage where the input bias current is within the specification.
5 The AD8224 is characterized from −40°C to +125°C. See the Typical Performance Characteristics section for expected operation in that temperature range.
Rev. PrB | Page 7 of 27
AD8224
Preliminary Technical Data
VS + = 5 V, VS− = 0 V, VREF = 2.5 V, TA = +25°C, G = 1, RL = 2 kΩ, unless otherwise noted.
Table 6. Single-Ended Output Configuration—Dynamic Performance (Both Amplifiers)
A Grade
Parameter
DYNAMIC RESPONSE
Small Signal Bandwidth −3 dB
G = 1
Conditions
Min
Typ
Max
TBD
TBD
TBD
TBD
G = 10
G = 100
G =1000
Settling Time 0.01%
G = 1
G = 10
G = 100
G =1000
3 V Step
4 V Step
4 V Step
4 V Step
TBD
TBD
TBD
TBD
Settling Time 0.001%
G = 1
G = 10
3 V Step
4 V Step
4 V Step
4 V Step
TBD
TBD
TBD
TBD
G = 100
G =1000
Slew Rate
G = 1 to 100
TBD
VS + = 5 V, VS− = 0 V, VREF = 2.5 V, TA = +25°C, G = 1, RL = 2 kΩ, unless otherwise noted.
Table 7. Differential Output Configuration1—Dynamic Performance
A Grade
Typ
Parameter
DYNAMIC RESPONSE
Small Signal Bandwidth −3 dB
G = 1
Conditions
Min
Max
Unit
TBD
TBD
TBD
TBD
kHz
kHz
kHz
kHz
G = 10
G = 100
G =1000
Settling Time 0.01%
G = 1
G = 10
G = 100
G =1000
3 V Step
4 V Step
4 V Step
4 V Step
TBD
TBD
TBD
TBD
ꢀs
ꢀs
ꢀs
ꢀs
Settling Time 0.001%
G = 1
G = 10
3 V Step
4 V Step
4 V Step
4 V Step
TBD
TBD
TBD
TBD
ꢀs
ꢀs
ꢀs
ꢀs
G = 100
G =1000
Slew Rate
G = 1 to 100
TBD
V/ꢀs
1 Refers to differential configuration shown in Figure 64.
Rev. PrB | Page 8 of 27
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
AD8224
Maximum Power Dissipation
Table 8.
The maximum safe power dissipation for the AD8224 is limited
by the associated rise in junction temperature (TJ) on the die. At
approximately 130°C, which is the glass transition temperature,
the plastic changes its properties. Even temporarily exceeding
this temperature limit may change the stresses that the package
exerts on the die, permanently shifting the parametric performance
of the amplifiers. Exceeding a temperature of 130°C for an
extended period can result in a loss of functionality.
Parameter
Rating
Supply Voltage
Power Dissipation
18 V
See Figure 2
Indefinite1
Vs
Output Short Circuit Current
Input Voltage (Common Mode)
Differential Input Voltage
Storage Temperature
Operating Temperature Range2
Lead Temperature Range (Soldering 10 sec)
Junction Temperature
Vs
−65°C to +130°C
−40°C to +125°C
300°C
Figure 2 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the LFCSP on a 4-layer
JEDEC standard board.
130°C
Package Glass Transition Temperature
ESD (Human Body Model)
ESD (Charge Device Model)
130°C
4 kV
1 kV
4.0
3.5
3.0
ESD (Machine Model)
0.4 kV
1Assumes the load is referenced to mid-supply.
2Temperature for specified performance is −40°C to +85°C. For performance
to +125°C, see the Typical Performance Characteristics section.
θ
= 48°C/W WHEN THERMAL PAD
JA
IS SOLDERED TO BOARD
2.5
2.0
1.5
1.0
0.5
0
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions may affect device reliability.
θ
= 86°C/W WHEN THERMAL PAD
JA
IS NOT SOLDERED TO BOARD
THERMAL RESISTANCE
–60 –40 –20
0
20
40
60
80
100 120 140
Table 9.
AMBIENT TEMPERATURE (°C)
Thermal Pad
θJA
48
86
Unit
°C/W
°C/W
Figure 2. Maximum Power Dissipation
Soldered to Board
Not Soldered to Board
ESD CAUTION
The θJA values in Table 9 assume a 4-layer JEDEC standard
board. If the thermal pad is soldered to the board, then it is
also assumed it is connected to a plane. θJC at the exposed pad
is 4.4°C/W.
Rev. PrB | Page 9 of 27
AD8224
Preliminary Technical Data
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
12
11
–IN1 1
RG1 2
RG1 3
+IN1 4
–IN2
RG2
INDICATOR
AD8224
TOP VIEW
10 RG2
+IN2
9
Figure 3. Pin Configuration
Table 10. Pin Function Descriptions
Pin No
Mnemonic
−IN1
RG1
RG1
+IN1
+VS
Description
1
2
3
4
Negative Input In-Amp 1.
Gain Resistor In-Amp 1.
Gain Resistor In-Amp 1.
Positive Input In-Amp 1.
Positive Supply.
5
6
7
8
REF1
REF2
−VS
Reference Adjust In-Amp 1.
Reference Adjust In-Amp 2.
Negative Supply.
9
+IN2
RG2
RG2
−IN2
−VS
OUT2
OUT1
+VS
Positive Input In-Amp 2.
Gain Resistor In-Amp 2.
Gain Resistor In-Amp 2.
Negative Input In-Amp 2.
Negative Supply.
Output In-Amp 2.
Output In-Amp 1.
Positive Supply.
10
11
12
13
14
15
16
Rev. PrB | Page 10 of 27
Preliminary Technical Data
AD8224
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 4. Typical Distribution of CMRR (G = 1)
Figure 5. Typical Distribution of Input Offset Voltage
Figure 6. Typical Distribution of Output Offset Voltage
Figure 7. Typical Distribution of Input Bias Current
Figure 8. Typical Distribution of Input Offset Current
1000
100
10
GAIN = +100 BANDWIDTH ROLL-OFF
GAIN = +1
GAIN = +10
GAIN = 100/GAIN = +1000
GAIN = +1000 BANDWIDTH ROLL-OFF
1
1
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 9. Voltage Spectral Density vs. Frequency
Rev. PrB | Page 11 of 27
AD8224
Preliminary Technical Data
150
130
110
90
GAIN = +1000
BANDWIDTH
GAIN = +100
LIMITED
GAIN = +10
GAIN = +1
70
50
30
5µV/DIV
1s/DIV
10
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 10. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1)
Figure 13. Positive PSRR vs. Frequency, RTI
150
130
110
90
GAIN = +1000
GAIN = +1
70
GAIN = +10
50
GAIN = +100
30
1µV/DIV
1s/DIV
10
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 11. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1000)
Figure 14. Negative PSRR vs. Frequency, RTI
8
0.3
INPUT OFFSET
9
7
6
5
4
3
2
1
0
CURRENT ±15
0.2
INPUT OFFSET
CURRENT ±5
0.1
7
5
0
–15.1V
–5.1V
–0.1
–0.2
–0.3
–0.4
–0.5
3
INPUT BIAS
INPUT BIAS
CURRENT ±5
CURRENT ±15
1
–1
–16
–12
–8
–4
0
4
8
12
16
0.1
1
10
100
1k
COMMON-MODE VOLTAGE (V)
TIME (s)
Figure 15. Input Current vs. Common-Mode Voltage
Figure 12. Change in Input Offset Voltage vs. Warmup Time
Rev. PrB | Page 12 of 27
Preliminary Technical Data
AD8224
160
140
120
100
80
10n
1n
GAIN = +1000
GAIN = +100
I
BIAS
100p
10p
BANDWIDTH
LIMITED
GAIN = +1
GAIN = +10
I
OS
1p
60
0.1p
40
–50
–25
0
25
50
75
100
125
150
1
10
100
1k
10k
100k
TEMPERATURE (°C)
FREQUENCY (Hz)
Figure 16. Input Bias Current and Offset Current Temperature,
VS = 15 V, VREF = 0 V
Figure 19. CMRR vs. Frequency, 1 kΩ Source Imbalance
10
8
10n
1n
6
4
I
BIAS
2
100p
10p
1p
0
–2
–4
–6
–8
–10
I
OS
0.1p
–50
–25
0
25
50
75
100
125
150
–50
–30
–10
10
30
50
70
90
110
130
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 17. Input Bias Current and Offset Current vs. Temperature,
VS = +5 V, VREF = 2.5 V
Figure 20. Change in CMRR vs. Temperature, G = 1
160
70
60
GAIN = +1000
GAIN = +1000
140
50
40
GAIN = +100
120
GAIN = +100
GAIN = +10
GAIN = +1
30
GAIN = +10
20
BANDWIDTH
LIMITED
100
10
GAIN = +1
80
0
–10
–20
–30
–40
60
40
10
100
1k
10k
100k
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 18. CMRR vs. Frequency
Figure 21. Gain vs. Frequency
Rev. PrB | Page 13 of 27
AD8224
Preliminary Technical Data
R
= 2kΩ
LOAD
R
10kΩ
LOAD
R
2kΩ
LOAD
R
= 10kΩ
LOAD
V
±15V
–8 –6
V
±15V
–8 –6
S
S
–10
–4
–2
0
VIN (V)
2
4
6
8
10
–10
–4
–2
0
2
4
6
8
10
OUTPUT VOLTAGE (V)
Figure 22. Gain Nonlinearity, G = 1
Figure 25. Gain Nonlinearity, G = 1000
18
12
6
+13V
±15V SUPPLIES
–14.8V, +5.5V
–4.8V, +0.6V
+3V
+14.9V, +5.5V
+4.95V, +0.6V
R
= 2kΩ
LOAD
0
±5V SUPPLIES
–4.8V, –3.3V
–14.8V, –8.3V
+4.95V, –3.3V
+14.9V, –8.3V
R
10kΩ
LOAD
–6
–12
–18
–5.3V
–8 –6
–15.3V
–16
–12
–8
–4
0
4
8
12
16
–10
–4
–2
0
2
4
6
8
10
OUTPUT VOLTAGE (V)
VIN (V)
Figure 26. Input Common-Mode Voltage Range vs. Output Voltage,
G = 1, VREF = 0 V
Figure 23. Gain Nonlinearity, G = 10
4
+3V
3
R
2kΩ
2
LOAD
+0.1V, +1.7V
+0.1V, +0.5V
+4.9V, +1.7V
+4.9V, +0.5V
R
10kΩ
LOAD
+5V SINGLE SUPPLY,
V
= +2.5V
REF
1
0
–0.3V
–8 –6
–1
–1
0
1
2
3
4
5
6
–10
–4
–2
0
2
4
6
8
10
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
Figure 27. Input Common-Mode Voltage Range vs. Output Voltage,
G = 1, VS = +5 V, VREF = 2.5 V
Figure 24. Gain Nonlinearity, G = 100
Rev. PrB | Page 14 of 27
Preliminary Technical Data
AD8224
18
V +
S
–1
–2
–3
–4
+13V
+85°C
–40°C
±15V SUPPLIES
12
6
+25°C
+125°C
–14.9V, +5.4V
+3V
+14.9V, +5.4V
+4.9V, +0.5V
–4.9V, +0.4V
–4.9V, –4.1V
0
±5V SUPPLIES
–5.3V
+4
+3
+2
+1
+4.9V, –4.1V
+14.9V, –9V
–6
–12
–18
–14.8V, –9V
+125°C
–40°C
+85°C
+25°C
14
–15.3V
V
–
S
–16
–12
–8
–4
0
4
8
12
16
2
4
6
8
10
12
16
18
OUTPUT VOLTAGE (V)
DUAL SUPPLY VOLTAGE (±V)
Figure 28. Input Common-Mode Voltage Range vs. Output Voltage,
G = 100, VREF = 0 V
Figure 31. Output Voltage Swing vs. Supply Voltage, RL = 2 kΩ, G = 10,
REF = 0 V
V
4
V +
S
–0.2
–0.4
+125°C
+3V
+85°C
+25°C
3
–40°C
2
+0.1V, +1.7V
+4.9V, +1.7V
+5V SINGLE SUPPLY,
= +2.5V
1
0
V
REF
+0.4
+0.2
+125°C
+85°C
–40°C
10
+25°C
8
+0.1V, –0.5V
1
+4.9V, –0.5V
4
–0.3V
–1
–1
V –
S
0
2
3
5
6
2
4
6
12
14
16
18
OUTPUT VOLTAGE (V)
DUAL SUPPLY VOLTAGE (±V)
Figure 29. Input Common-Mode Voltage Range vs. Output Voltage,
G = 100, VS = +5 V, VREF = 2.5 V
Figure 32. Output Voltage Swing vs. Supply Voltage, RL = 10 kΩ, G = 10,
REF = 0 V
V
V +
S
15
10
5
–1
–2
–40°C
+25°C
+125°C
+85°C
–40°C
+25°C
+85°C
+125°C
+125°C
NOTES
1. THE AD8224 CAN OPERATE UP TO A V BELOW
THE NEGATIVE SUPPLY, BUT THE BIAS CURRENT
WILL INCREASE SHARPLY.
BE
0
–5
–10
–15
+1
+85°C
–40°C +25°C
+85°C
+125°C
+25°C
–40°C
V –
S
–1
2
4
6
8
10
12
14
16
18
100
1k
10k
VOLTAGE SUPPLY (V)
R
(Ω)
LOAD
Figure 30. Input Voltage Limit vs. Supply Voltage, G = 1, VREF =0 V
Figure 33. Output Voltage Swing vs. Load Resistance VS = 15 V, VREF = 0 V
Rev. PrB | Page 15 of 27
AD8224
Preliminary Technical Data
5
47pF
–40°C
NO LOAD
+85°C
100pF
+25°C
4
3
2
1
0
+125°C
+125°C
–40°C
+25°C
+85°C
1k
20mV/DIV
5µs/DIV
100
10k
R
(Ω)
LOAD
Figure 37. Small Signal Pulse Response for Various Capacitive Loads,
VS = 15 V, VREF = 0 V
Figure 34. Output Voltage Swing vs. Load Resistance VS = +5 V, VREF = 2.5 V
V +
S
–40°C
–1
–2
–3
–4
NO LO
+125°C
+85°C
+25°C
+4
+3
+2
+1
+25°C
+85°C
+125°C
10
–40°C
14 16
20mV/DIV
5µs/DIV
V
–
S
0
2
4
6
8
12
I
(mA)
OUT
Figure 35. Output Voltage Swing vs. Output Current, VS = 15 V, VREF = 0 V
Figure 38. Small Signal Pulse Response for Various Capacitive Loads,
VS = +5 V, VREF = 2.5 V
V +
S
35
GAIN = +10, +100, +1000
30
–1
+25°C
+85°C
GAIN = +1
25
+125°C
–2
+2
20
15
10
5
+25°C
+85°C
+1
+125°C
–40°C
V
–
S
0
100
0
2
4
6
8
10
12
14
16
1k
10k
100k
1M
10M
I
(mA)
OUT
FREQUENCY (Hz)
Figure 39. Output Voltage Swing vs. Large Signal Frequency Response
Figure 36. Output Voltage Swing vs. Output Current, VS = +5 V, VREF = 2.5 V
Rev. PrB | Page 16 of 27
Preliminary Technical Data
AD8224
5V/DIV
5V/DIV
5µs TO 0.01%
6µs TO 0.001%
58μs TO 0.01%
74μs TO 0.001%
0.002%/DIV
0.002%/DIV
200µs/DIV
20µs/DIV
Figure 40. Large Signal Pulse Response and Settle Time, G = 1,
RL = 10 kΩ, VS = 15 V, VREF = 0 V
Figure 43. Large Signal Pulse Response and Settle Time, G = 1000,
RL = 10 kΩ, VS = 15 V, VREF = 0 V
5V/DIV
4.3μs TO 0.01%
4.6μs TO 0.001%
0.002%/DIV
20mV/DIV
20µs/DIV
4µs/DIV
Figure 44. Small Signal Pulse Response, G = 1, RL = 2 kΩ, CL = 100 pF,
VS = 15 V, VREF = 0 V
Figure 41. Large Signal Pulse Response and Settle Time, G = 10,
RL = 10 kΩ, VS = 15 V, VREF = 0 V
5V/DIV
8.1μs TO 0.01%
9.6μs TO 0.001%
0.002%/DIV
20mV/DIV
20µs/DIV
4µs/DIV
Figure 45. Small Signal Pulse Response, G = 10, RL = 2 kΩ, CL = 100 pF,
VS = 15 V, VREF = 0 V.
Figure 42. Large Signal Pulse Response and Settle Time, G = 100,
RL = 10 kΩ, VS = 15 V, VREF = 0 V
Rev. PrB | Page 17 of 27
AD8224
Preliminary Technical Data
20mV/DIV
20mV/DIV
4µs/DIV
4µs/DIV
Figure 46. Small Signal Pulse Response, G = 100, RL = 2 kΩ, C L= 100 pF,
VS = 15 V, VREF =0 V
Figure 49. Small Signal Pulse Response, G = 10, RL = 2 kΩ, CL = 100 pF,
VS = +5 V, VREF = 2.5 V
20mV/DIV
20mV/DIV
40µs/DIV
4µs/DIV
Figure 47. Small Signal Pulse Response, G = 1000, RL = 2 kΩ, CL = 100 pF,
VS = 15 V, VREF = 0 V
Figure 50. Small Signal Pulse Response, G = 100, RL = 2 kΩ, CL = 100 pF,
VS = +5 V, VREF = 2.5 V
20mV/DIV
20mV/DIV
4µs/DIV
40µs/DIV
Figure 48. Small Signal Pulse Response, G = 1, RL = 2 kΩ, CL = 100 pF,
VS = +5 V, VREF = 2.5 V
Figure 51. Small Signal Pulse Response, G = 1000,RL = 2 kΩ, CL = 100 pF,
VS = +5 V, VREF = 2.5 V
Rev. PrB | Page 18 of 27
Preliminary Technical Data
AD8224
15
60
40
GAIN = +1000
GAIN = +100
GAIN = +10
10
20
SETTLED TO 0.001%
0
5
0
SETTLED TO 0.01%
GAIN = +1
–20
–40
0
5
10
15
20
100
1k
10k
100k
1M
10M
OUTPUT VOLTAGE STEP SIZE (V)
FREQUENCY (Hz)
Figure 52. Settling Time vs. Step Size (G = 1) 15 V, VREF = 0 V
Figure 55. Differential Output Configuration: Gain vs. Frequency
100
100
V
DIFF_OUT
CMR
= 20 log
OUT
90
80
70
60
50
40
30
20
10
0
V
CM_OUT
LIMITED BY
MEASUREMENT
SYSTEM
SETTLED TO 0.001%
10
SETTLED TO 0.01%
1
1
10
100
1000
1
10
100
1k
10k
100k
1M
GAIN (V/V)
FREQUENCY (Hz)
Figure 53. Settling Time vs. Gain for a 10 V Step, VS = 15 V, VREF = 0 V
Figure 56. Differential Output Configuration:
Common-Mode Output vs. Frequency
Figure 54 Channel Separation vs. Frequency, RL = 2 kΩ, Source Channel at G = 1
Rev. PrB | Page 19 of 27
AD8224
Preliminary Technical Data
THEORY OF OPERATION
+V
+V
+V
–V
+V
S
S
S
S
NODE A
NODE B
RG
20kꢀ
R2
24.7kꢀ
NODE F
+V
S
R1
24.7kꢀ
20kꢀ
–V
S
S
OUTPUT
A3
20kꢀ
+V
–V
+V
–V
S
S
S
–V
S
NODE E
+V
–V
NODE C
NODE D
S
+IN
J1
V
Q2 J2
–IN
Q1
C1
C2
REF
20kꢀ
A1
A2
V
PINCH
PINCH
S
S
I
VB
I
–V
S
Figure 57. Simplified Schematic
The AD8224 is a JFET input, monolithic instrumentation amplifier
based on the classic three op amp topology (see Figure 57). Input
Transistor J1 and Input Transistor J2 are biased at a fixed current so
that any input signal forces the output voltages of A1 and A2 to
change accordingly. The input signal creates a current through RG
that flows in R1 and R2 such that the outputs of A1 and A2 provide
the correct, gained signal. Topologically, J1, A1, R1 and J2, A2, R2
can be viewed as precision current feedback amplifiers with a gain
bandwidth of 1.5 MHz. The common-mode voltage and amplified
differential signal from A1 and A2 are applied to a difference
amplifier that rejects the common-mode voltage but amplifies the
differential signal. The difference amplifier employs 20 kΩ laser
trimmed resistors that result in an in-amp with gain error less than
0.04%. New trim techniques were developed to ensure that CMRR
exceeds 86 dB (G = 1).
The AD8224 has none of these problems; its input bias current
is limited to less than 10 μA and the output does not phase
reverse under overdrive fault conditions.
The AD8224 has extremely low load induced nonlinearity. All
amplifiers that comprise the AD8224 have rail-to-rail output
capability for enhanced dynamic range. The input of the AD8224
can amplify signals with wide common-mode voltages even
slightly lower than the negative supply rail. The AD8224 operates
over a wide supply voltage range. It can operate from either a
single +4.5 V to +36 V supply or a dual 2.25 V to 18 V. The
transfer function of the AD8224 is
49.4 kΩ
G = 1+
RG
Users can easily and accurately set the gain using a single,
standard resistor. Since the input amplifiers employ a current
feedback architecture, the AD8224 gain bandwidth product
increases with gain, resulting in a system that does not experience
as much bandwidth loss as voltage feedback architectures at
higher gains.
Using JFET transistors, the AD8224 offers extremely high input
impedance, extremely low bias currents of 10 pA maximum,
low offset current of 0.6 pA maximum, and no input bias
current noise. In addition, input offset is less than 125 μV and
drift is less than 5 μV/°C. Ease of use and robustness were
considered. A common problem for instrumentation amplifiers
is that at high gains, when the input is overdriven, an excessive
milliampere input bias current can result and the output can
undergo phase reversal. Overdriving the input at high gains
refers to when the input signal is within the supply voltages but
the amplifier cannot output the gained signal. For example, at a
gain of 100, driving the amplifier with 10 V on 15 V
constitutes overdriving the inputs since the amplifier cannot
output 100 V.
GAIN SELECTION
Placing a resistor across the RG terminals sets the gain of the
AD8224. This is calculated by referring to Table 11 or by using
the following gain equation.
49.4 kΩ
RG =
G −1
Rev. PrB | Page 20 of 27
Preliminary Technical Data
AD8224
LAYOUT
Table 11. Gains Achieved Using 1% Resistors
The AD8224 is a high precision device. To ensure optimum
performance at the PC board level, care must be taken in the
design of the board layout. The AD8224 pinout is arranged in a
logical manner to aid in this task.
1% Standard Table Value of RG (Ω)
Calculated Gain
49.9 k
12.4 k
5.49 k
2.61 k
1.00 k
499
249
100
49.9
1.990
4.984
9.998
19.93
50.40
100.0
199.4
495.0
991.0
Package Considerations
The AD8224 is available in a 16-lead, 4 mm × 4 mm LFCSP.
Blindly copying the footprint from another 4 mm × 4 mm
LFCSP part is not recommended; it may not have the same
thermal pad size and leads. Refer to the Outline Dimensions
section to verify that the PCB symbol has the correct dimensions.
Space between the leads and thermal pad should be kept as
wide as possible for the best bias current performance.
The AD8224 defaults to G = 1 when no gain resistor is used.
The tolerance and gain drift of the RG resistor should be added
to the AD8224’s specifications to determine the total gain
accuracy of the system. When the gain resistor is not used,
gain error and gain drift are kept to a minimum.
Thermal Pad
The AD8224’s 4 mm × 4 mm LFCSP comes with a thermal pad.
This pad is connected internally to +VS. The pad can either be
left unconnected or connected to the positive supply rail.
REFERENCE TERMINAL
The output voltage of the AD8224 is developed with respect to
the potential on the reference terminal. This is useful when the
output signal needs to be offset to a precise midsupply level. For
example, a voltage source can be tied to the REF1 or REF2 pin
to level-shift the output so that the AD8224 can drive a single-
supply ADC. Pin REFx is protected with ESD diodes and should
not exceed either +VS or −VS by more than 0.5 V.
To preserve maximum pin compatibility with future dual
instrumentation amplifiers, leave the pad unconnected. This
can be done by not soldering the paddle at all or by soldering
the part to a landing that is a not connected to any other net.
For high vibration applications, a landing is recommended.
Because the AD8224 dissipates little power, heat dissipation is
rarely an issue. If improved heat dissipation is desired (for example,
when driving heavy loads), connect the thermal pad to the
positive supply rail. For the best heat dissipation performance,
the positive supply rail should be a plane in the board. See
the section for thermal coefficients with and without the pad
soldered.
For best performance, source impedance to the REF terminal
should be kept below 1 ꢀ. As shown in Figure 57 the reference
terminal, REF, is at one end of a 20 kΩ resistor. Additional
impedance at the REF terminal adds to this 20 kΩ resistor and
results in amplification of the signal connected to the positive
input. The amplification from the additional RREF can be
computed by
Common-Mode Rejection over Frequency
The AD8224 has a higher CMRR over frequency than typical
in-amps, which gives it greater immunity to disturbances, such
as line noise and its associated harmonics. A well-implemented
layout is required to maintain this high performance. Input
source impedances should be matched closely. Source resistance
should be placed close to the inputs so that it interacts with as
little parasitic capacitance as possible.
2
(
20 kΩ + RREF
40 kΩ + RREF
)
Only the positive signal path is amplified; the negative path is
unaffected. This uneven amplification degrades the amplifier’s
CMRR.
INCORRECT
CORRECT
CORRECT
Parasitics at the RGx pins can also affect CMRR over frequency.
The PCB should be laid out so that the parasitic capacitances at
each pin match. Traces from the gain setting resistor to the RGx
pins should be kept short to minimize parasitic inductance.
AD8224
AD8224
AD8224
V
V
REF
REF
V
REF
Reference
+
+
Errors introduced at the reference terminal feed directly to the
output. Take care to tie the REFx pins to the appropriate local
ground.
AD8224
–
OP2177
–
Figure 58. Driving the Reference Pin
Rev. PrB | Page 21 of 27
AD8224
Preliminary Technical Data
Power Supplies
INPUT BIAS CURRENT RETURN PATH
A stable dc voltage should be used to power the instrumentation
amplifier. Noise on the supply pins can adversely affect
performance.
The input bias current of the AD8224 must have a return path
to common. When the source, such as a transformer, cannot
provide a return current path, one should be created, as shown
in Figure 60.
The AD8224 has two positive supply pins (Pin 5 and Pin 16)
and two negative supply pins (Pin 8 and Pin 13). While the part
functions with only one pin from each supply pair connected,
both pins should be connected for specified performance and
optimum reliability.
INPUT PROTECTION
All terminals of the AD8224 are protected against ESD. ESD
protection is guaranteed to 4 kV (human body model).In
addition, the input structure allows for dc overload conditions a
diode drop above the positive supply and a diode drop below
the negative supply. Voltages beyond a diode drop of the
supplies cause the ESD diodes to conduct and enable current to
flow through the diode. Therefore, an external resistor should
be used in series with each of the inputs to limit current for
voltages above +Vs. In either scenario, the AD8224 safely
handles a continuous 6 mA current at room temperature.
The AD8224 should be decoupled with 0.1 ꢁF bypass capacitors,
one for each supply. The positive supply decoupling capacitor
should be placed near Pin 16, and the negative supply
decoupling capacitor should be placed near Pin 8. Each supply
should also be decoupled with a 10 ꢁF tantalum capacitor. The
tantalum capacitor can be placed further away from the
AD8224 and can generally be shared by other precision integrated
circuits. Figure 59 shows an example layout.
For applications where the AD8224 encounters extreme
overload voltages, as in cardiac defibrillators, external series
resistors and low leakage diode clamps, such as BAV199L,
FJH1100, or SP720, should be used.
0.1µF
INCORRECT
+V
CORRECT
+V
S
S
16
15
14
13
AD8224
AD8224
AD8224
REF
REF
12
11
10
9
1
2
3
4
R
R
G
–V
S
–V
S
G
TRANSFORMER
TRANSFORMER
+V
+V
S
S
C
C
C
C
5
6
7
8
R
R
1
fHIGH-PASS
=
AD8224
2πRC
AD8224
REF
REF
0.1µF
–V
–V
S
S
CAPACITIVELY COUPLED
CAPACITIVELY COUPLED
Figure 60. Creating an IBIAS Path
Figure 59. Example Layout
RF INTERFERENCE
SOLDER WASH
The solder process can leave flux and other contaminants on
the board. When these contaminants are between the AD8224
leads and thermal pad, they can create leakage paths that are
larger than the AD8224’s bias currents. A thorough washing
process removes these contaminants and restores the device’s
excellent bias current performance.
RF rectification is often a problem in applications where there are
large RF signals. The problem appears as a small dc offset voltage.
The AD8224 by its nature has a 5 pF gate capacitance (CG) at its
inputs. Matched series resistors form a natural low-pass filter that
reduces rectification at high frequency (see Figure 61). The
relationship between external, matched series resistors and the
internal gate capacitance is expressed as follows:
Rev. PrB | Page 22 of 27
Preliminary Technical Data
AD8224
1
1
FilterFreqDIFF
=
FilterFreqCM =
2πRCG
2πR(CC + CG )
1
FilterFreqCM
=
2πRCG
Mismatched CC capacitors result in mismatched low-pass filters.
The imbalance causes the AD8224 to treat what would have
been a common-mode signal as a differential signal. To reduce
the effect of mismatched external CC capacitors, select a value of
CD greater than 10 times CC. This sets the differential filter
frequency lower than the common-mode frequency.
+15V
+15V
+
+
0.1µF
10µF
0.1µF
+IN
10µF
C
C
C
1nF
C
D
C
R
4.02kꢀ
+IN
V
OUT
R
R
10nF
1nF
AD8224
C
G
R
REF
V
OUT
AD8224
–IN
4.02kꢀ
–V
S
C
G
REF
–V
S
–IN
0.1µF
10µF
+
–15V
Figure 62. RFI Suppression
0.1µF
10µF
+
COMMON-MODE INPUT VOLTAGE RANGE
–15V
The three op amp architecture of the AD8224 applies gain and
then removes the common-mode voltage. Therefore, internal
nodes in the AD8224 experience a combination of both the
gained signal and the common-mode signal. This combined
signal can be limited by the voltage supplies even when the
individual input and output signals are not. Figure 26, Figure 27,
Figure 28, and Figure 29 show the allowable common-mode
input voltage ranges for various output voltages, supply voltages,
and gains.
Figure 61. RFI Filtering Without External Capacitors
To eliminate high frequency common-mode signals while using
smaller source resistors, a low-pass R-C network can be placed
at the input of the instrumentation amplifier (see Figure 62).
The filter limits the input signal bandwidth according to the
following relationship:
1
FilterFreqDIFF
=
2πR(2 CD +CC + CG )
Rev. PrB | Page 23 of 27
AD8224
Preliminary Technical Data
APPLICATIONS
DRIVING AN ANALOG-TO-DIGITAL CONVERTER
+IN
R
+
An instrumentation amplifier is often used in front of an analog-to-
digital converter to provide CMRR and additional conditioning
such as a voltage level shift and gain (see Figure 63). In this
example, a 2.7 nF capacitor and a 500 Ω resistor create an anti-
aliasing filter for the AD7685. The 2.7 nF capacitor also serves to
store and deliver necessary charge to the switched capacitor input
of the ADC. The 500 Ω series resistor reduces the burden of the
2.7 nF load from the amplifier. However, large source impedance in
front of the ADC can degrade total harmonic distortion (THD).
+OUT
AD8224
–
G
20kꢀ
–IN
–
33pF
AD8224
+
+IN2
REF2
–OUT
Figure 64. Differential Circuit Schematic
For applications where THD performance is critical, the series
resistor needs to be small. At worst, a small series resistor can load
the AD8224, potentially causing the output to overshoot or ring.
In such cases, a buffer amplifier, such as the AD8615, should be
used after the AD8224 to drive the ADC.
Setting the Common-Mode Voltage
The output common-mode voltage is set by the average of +IN2
and REF2. The transfer function is
V
CM_OUT = (V+OUT + V−OUT)/2 = (V+IN2 + VREF2)/2
+5V
+IN2 and REF2 have different properties that allow the
reference voltage to be easily set for a wide variety of applications.
+IN2 has high impedance but cannot swing to the supply rails
of the part. REF2 must be driven with a low impedance, but can
go 300 mV beyond the supply rails.
+
10µF
0.1µF
+IN
ADR435
+5V
4.7µF
500ꢀ
±50mV
1.07kꢀ
AD8224
AD7685
A common application sets the common-mode output voltage
to the midscale of a differential ADC. In this case, the ADC
reference voltage is sent to the +IN2 terminal, and ground is
connected to the REF2 terminal. This produces a common-
mode output voltage of half the ADC reference voltage.
REF
2.7nF
–IN
+2.5V
Figure 63. Driving an ADC in a Low Frequency Application
2-Channel Differential Output Using a Dual Op Amp
DIFFERENTIAL OUTPUT
Another differential output topology is shown in Figure 65.
Instead of a second in-amp, ½ of a dual OP2177 op amp creates
the inverted output. Because the OP2177 comes in an MSOP,
this configuration allows the creation of a dual channel,
precision differential output in-amp with little board area.
The differential configuration of the AD8224 has the same
excellent dc precision specifications as the single-ended output
configuration and is recommended for applications in the
frequency range of dc to 100 kHz.
The circuit configuration, outlined in Table 7, refers to the
configuration shown in Figure 64 only. The circuit includes an RC
filter that maintains the stability of the loop.
Errors from the op amp are common to both outputs and are
thus common mode. Errors from mismatched resistors also
create a common-mode dc offset. Because these errors are
common mode, they are likely to be rejected by the next device
in the signal chain.
The transfer function for the differential output is:
VDIFF_OUT = V+OUT − V−OUT = (V+IN − V−IN) × G
+IN
where:
+OUT
AD8224
49.4 kΩ
G =1 +
–IN
RG
4.99kꢀ
REF
V
REF
–
+
4.99kꢀ
OP2177
–OUT
Figure 65. Differential Output Using Op Amp
Rev. PrB | Page 24 of 27
Preliminary Technical Data
AD8224
+12V
+
10µF
0.1µF
+5V
100pF
NPO
5%
0.1µF
1kꢀ
+IN
–IN
806ꢀ
806ꢀ
VDD
+OUT
–OUT
IN+
IN–
AD8224
AD7688
GND REF
1000pF
(DIFF OUT)
1kꢀ
2.7nF
2.7nF
REF2
+IN2
100pF
NPO
5%
10µF
X5R
+12V
+5V REF
–12V
0.1µF
10µF
0.1µF
+
V
IN
V
+5V REF
OUT
0.1µF
ADR435
GND
Figure 66. Driving a Differential ADC
Reference
DRIVING A DIFFERENTIAL INPUT ADC
The ADR435 supplies a reference voltage to both the ADC and
the AD8224. Because REF2 on the AD8224 is grounded, the
common-mode output voltage is precisely half the reference
voltage, exactly where it needs to be for the ADC.
The AD8224 can be configured in differential output mode
to drive a differential analog-to-digital converter. Figure 66
illustrates several of the concepts.
First Antialiasing Filter
DRIVING CABLING
The 1 kꢀ resistor, 1000 pF capacitor, and 100 pF capacitors in
front of the in-amp form a 76 kHz filter. This is the first of two
antialiasing filters in the circuit and helps to reduce the noise of
the system. The 100 pF capacitors protect against common-
mode RFI signals. Note that they are 5% COG/NPO types.
These capacitors match well over time and temperature, which
keeps the system’s CMRR high over frequency.
All cables have a certain capacitance per unit length, which
varies widely with cable type. The capacitive load from the cable
may cause peaking in the AD8224 output response. To reduce
peaking, use a resistor between the AD8224 and the cable.
Because cable capacitance and desired output response vary
widely, this resistor is best determined empirically. A good
starting point is 50 ꢀ.
Second Antialiasing Filter
The AD8224 operates at a low enough frequency that
transmission line effects are rarely an issue; therefore, the
resistor need not match the characteristic impedance of
the cable.
An 806 ꢀ resistor and 2.7 nF capacitor are located between each
AD8224 output and ADC input. They create a 73 kHz low-pass
filter for another stage of antialiasing protection.
These four elements also isolate the ADC from loading the
AD8224. The 806 ꢀ resistor shields the AD8224 from the
ADC’s switched capacitor input which looks like a time varying
load. The 2.7 nF capacitor provides charge to the switched
capacitor front end of the ADC. If the application requires a
lower frequency antialiasing filter, increase the value of the
capacitor rather than the resistor.
AD8224
(DIFF OUT)
The 1 kꢀ resistors can also protect an ADC from overvoltages.
Because the AD8224 runs on wider supply voltages than a
typical ADC, there is a possibility of overdriving the ADC. This
is not an issue with a PulSAR® converter, such as the AD7688.
Its input can handle a 130 mA overdrive, which is much higher
than the short-circuit limit of the AD8224. However, other
converters have less robust inputs and may need the added
protection.
AD8224
(SINGLE OUT)
Figure 67. Driving a Cable
Rev. PrB | Page 25 of 27
AD8224
Preliminary Technical Data
OUTLINE DIMENSIONS
0.50
0.40
0.30
4.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
1
12
13
16
PIN 1
INDICATOR
2.65
2.50 SQ
2.35
3.75
BSC SQ
EXPOSED
PAD
4
8
5
0.65
BSC
9
0.25 MIN
TOP VIEW
1.95 BCS
BOTTOM VIEW
12° MAX
0.80 MAX
0.65 TYP
1.00
0.85
0.80
0.05 MAX
0.02 NOM
SEATING
PLANE
0.30
0.23
0.18
COPLANARITY
0.08
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VGGC.
Figure 68. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-16-13)
Dimensions are shown in millimeters
ORDERING GUIDE
Model
Temperature Range
−40°C to +85°C
Product Description
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
Evaluation Board
Package Option
CP-16-13
CP-16-13
CP-16-13
CP-16-13
AD8224ACPZ-R71
AD8224ACPZ-RL1
AD8224ACPZ-WP1
AD8224BCPZ-R71
AD8224BCPZ-RL1
AD8224BCPZ-WP1
AD8224-EVALZ
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
CP-16-13
CP-16-13
1 Z = Pb-free part.
Rev. PrB | Page 26 of 27
Preliminary Technical Data
NOTES
AD8224
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06286-0-12/06(PrB)
Rev. PrB | Page 27 of 27
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