AD8226BRZ-R7 [ADI]
Wide Supply Range, Rail-to-Rail Output Instrumentation Amplifier; 宽电源电压范围，轨到轨输出仪表放大器
| 型号： | AD8226BRZ-R7 |
| 厂家： | 
ADI |
| 描述： | Wide Supply Range, Rail-to-Rail Output Instrumentation Amplifier |
| 文件： | 总28页 (文件大小：686K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Wide Supply Range, Rail-to-Rail
Output Instrumentation Amplifier
AD8226
FEATURES
PIN CONFIGURATION
Gain set with 1 external resistor
Gain range: 1 to 1000
Input voltage goes below ground
Inputs protected beyond supplies
Very wide power supply range
Single supply: 2.2 V to 36 V
AD8226
1
2
3
4
8
7
6
5
–IN
+V
S
R
R
V
OUT
G
G
REF
–V
+IN
S
TOP VIEW
(Not to Scale)
Dual supplies: 1.3ꢀ V to 18 V
Bandwidth (G = 1): 1.ꢀ MHz
Figure 1.
CMRR (G = 1): 90 dB minimum for BR models
Input noise: 22 nV/√Hz
Typical supply current: 3ꢀ0 μA
Specified temperature: −40°C to +12ꢀ°C
8-lead SOIC and MSOP packages
Table 1. Instrumentation Amplifiers by Category1
General
Purpose
Zero
Drift
Military
Grade
Low
Power
High Speed
PGA
AD8220
AD8221
AD8222
AD8224
AD8228
AD8295
AD8231 AD620
AD8290 AD621
AD8293 AD524
AD8553 AD526
AD8556 AD624
AD8557
AD627
AD623
AD8223 AD8253
AD8226
AD8250
AD8251
APPLICATIONS
Industrial process controls
Bridge amplifiers
Medical instrumentation
Portable data acquisition
Multichannel systems
AD8227
1 Visit www.analog.com for the latest instrumentation amplifiers.
GENERAL DESCRIPTION
The AD8226 is a low cost, wide supply range instrumentation
amplifier that requires only one external resistor to set any gain
between 1 and 1000.
AD8226 can handle voltages beyond the rails. For example,
with a 5 V supply, the part is guaranteed to withstand 35 V
at the input with no damage. Minimum as well as maximum
input bias currents are specified to facilitate open wire detection.
The AD8226 is designed to work with a variety of signal
voltages. A wide input range and rail-to-rail output allow the
signal to make full use of the supply rails. Because the input
range also includes the ability to go below the negative supply,
small signals near ground can be amplified without requiring dual
supplies. The AD8226 operates on supplies ranging from 1.35 V
to 18 V for dual supplies and 2.2 V to 36 V for single supply.
The AD8226 is perfect for multichannel, space-constrained
industrial applications. Unlike other low cost, low power
instrumentation amplifiers, the AD8226 is designed with
a minimum gain of 1 and can easily handle 10 V signals.
With its MSOP package and 125°C temperature rating, the
AD8226 thrives in tightly packed, zero airflow designs.
The robust AD8226 inputs are designed to connect to real-
world sensors. In addition to its wide operating range, the
The AD8226 is available in 8-lead MSOP and SOIC packages,
and is fully specified for −40°C to +125°C operation.
For a device with a similar package and performance as the
AD8226 but with gain settable from 5 to 1000, consider using
the AD8227.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2009 Analog Devices, Inc. All rights reserved.
AD8226
TABLE OF CONTENTS
Features .............................................................................................. 1
Gain Selection............................................................................. 19
Reference Terminal .................................................................... 20
Input Voltage Range................................................................... 20
Layout .......................................................................................... 20
Input Bias Current Return Path ............................................... 21
Input Protection ......................................................................... 22
Radio Frequency Interference (RFI)........................................ 22
Applications Information.............................................................. 23
Differential Drive ....................................................................... 23
Precision Strain Gage................................................................. 24
Driving an ADC ......................................................................... 24
Outline Dimensions....................................................................... 25
Ordering Guide .......................................................................... 25
Applications....................................................................................... 1
Pin Configuration............................................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ............................................. 9
Theory of Operation ...................................................................... 19
Architecture................................................................................. 19
REVISION HISTORY
7/09—Rev. 0 to Rev. A
Added BRZ and BRM Models ..........................................Universal
Changes to Features Section............................................................ 1
Changes to Table 1............................................................................ 1
Changes to General Description Section ...................................... 1
Changes to Gain vs. Temperature Parameter, Output Parameter,
and Operating Range Parameter, Table 2 .........................................4
Changes to Common-Mode Rejection Ratio (CMRR) Parameter
and to Input Offset, VOSO, Average Temperature Coefficient
Parameter, Table 3 ........................................................................ 5
Changes to Gain vs. Temperature Parameter, Table 3 ................. 6
Changes to Gain Selection Section............................................... 19
Changes to Reference Terminal Section and Input Voltage
Range Section.............................................................................. 20
Changes to Ordering Guide .......................................................... 25
1/09—Revision 0: Initial Version
Rev. A | Page 2 of 28
AD8226
SPECIFICATIONS
+VS = +15 V, −VS = −15 V, VREF = 0 V, TA = 25°C, G = 1, RL = 10 kΩ, specifications referred to input, unless otherwise noted.
Table 2.
ARZ, ARMZ
Typ
BRZ, BRMZ
Typ
Parameter
Conditions
Min
Max
Min
Max
Unit
COMMON-MODE REJECTION RATIO (CMRR)
VCM = −10 V to +10 V
CMRR with DC to 60 Hz
G = 1
G = 10
80
90
dB
dB
dB
dB
100
105
105
105
110
110
G = 100
G = 1000
CMRR with DC at 5 kHz
G = 1
80
80
dB
dB
dB
dB
G = 10
90
90
G = 100
90
90
G = 1000
NOISE
100
100
Total noise: eN = √(eNI2 + (eNO/G)2)
1 kHz
Voltage Noise
Input Voltage Noise, eNI
Output Voltage Noise, eNO
RTI
22
24
22
24
nV/√Hz
nV/√Hz
120
125
120
125
f = 0.1 Hz to 10 Hz
G = 1
2
2
μV p-p
μV p-p
μV p-p
fA/√Hz
pA p-p
G = 10
0.5
0.4
100
3
0.5
0.4
100
3
G = 100 to 1000
Current Noise
f = 1 kHz
f = 0.1 Hz to 10 Hz
VOLTAGE OFFSET
Total offset voltage:
VOS = VOSI + (VOSO/G)
Input Offset, VOSI
Average Temperature Coefficient
Output Offset, VOSO
Average Temperature Coefficient
Offset RTI vs. Supply (PSR)
G = 1
VS = 5 V to 15 V
TA = −40°C to +125°C
VS = 5 V to 15 V
TA = −40°C to +125°C
VS = 5 V to 15 V
200
2
100
1
μV
0.5
2
0.5
1
μV/°C
μV
1000
10
500
5
μV/°C
80
90
dB
dB
dB
dB
G = 10
100
105
105
105
110
110
G = 100
G = 1000
INPUT CURRENT
Input Bias Current1
TA = +25°C
5
5
5
20
15
30
70
27
25
35
5
5
5
20
15
30
70
27
25
35
nA
TA = +125°C
nA
TA = −40°C
nA
Average Temperature Coefficient
Input Offset Current
TA = −40°C to +125°C
TA = +25°C
pA/°C
nA
1.5
1.5
2
0.5
0.5
0.5
TA = +125°C
nA
TA = −40°C
nA
Average Temperature Coefficient
TA = −40°C to +125°C
5
5
pA/°C
REFERENCE INPUT
RIN
100
7
100
7
kΩ
μA
V
IIN
Voltage Range
Reference Gain to Output
Reference Gain Error
DYNAMIC RESPONSE
Small-Signal −3 dB Bandwidth
G = 1
−VS
+VS
−VS
+VS
1
1
V/V
%
0.01
0.01
1500
160
20
1500
160
20
kHz
kHz
kHz
kHz
G = 10
G = 100
G = 1000
2
2
Rev. A | Page 3 of 28
AD8226
ARZ, ARMZ
Typ
BRZ, BRMZ
Typ
Parameter
Settling Time 0.01%
G = 1
Conditions
Min
Max
Min
Max
Unit
10 V step
25
25
μs
G = 10
15
15
μs
G = 100
40
40
μs
G = 1000
350
0.4
0.6
350
0.4
0.6
μs
Slew Rate
G = 1
V/μs
V/μs
G = 5 to 100
G = 1 + (49.4 kΩ/RG)
GAIN
Gain Range
Gain Error
G = 1
1
1000
1
1000
V/V
VOUT 10 V
0.04
0.3
0.01
0.1
%
%
G = 5 to 1000
Gain Nonlinearity
G = 1 to 10
G = 100
VOUT = −10 V to +10 V
RL ≥ 2 kΩ
10
10
ppm
ppm
ppm
RL ≥ 2 kΩ
75
75
G = 1000
Gain vs. Temperature2
RL ≥ 2 kΩ
750
750
G = 1
TA = −40°C to +85°C
TA = 85°C to 125°C
TA = −40°C to +125°C
VS = 1.35 V to +36 V
5
1
ppm/°C
ppm/°C
ppm/°C
5
2
G > 1
−100
−100
INPUT
Input Impedance
Differential
0.8||2
0.4||2
0.8||2
0.4||2
GΩ||pF
Common Mode
Input Operating Voltage Range3
GΩ||pF
TA = +25°C
−VS − 0.1
−VS − 0.05
−VS − 0.15
+VS − 40
+VS − 0.8
+VS − 0.6
+VS − 0.9
−VS + 40
−VS − 0.1
−VS − 0.05
−VS − 0.15
+VS − 40
+VS − 0.8
+VS − 0.6
+VS − 0.9
−VS + 40
V
V
V
V
TA = +125°C
TA = −40°C
Input Overvoltage Range
OUTPUT
TA = −40°C to +125°C
Output Swing
RL = 2 kΩ to Ground
TA = +25°C
TA = +125°C
TA = −40°C
−VS + 0.4
−VS + 0.4
−VS + 1.2
+VS − 0.7
+VS – 1.0
+VS – 1.1
−VS + 0.4
−VS + 0.4
−VS + 1.2
+VS − 0.7
+VS – 1.0
+VS – 1.1
V
V
V
RL = 10 kΩ to Ground
RL = 100 kΩ to Ground
TA = +25°C
TA = +125°C
TA = −40°C
−VS + 0.2
−VS + 0.3
−VS + 0.2
+VS − 0.2
+VS − 0.3
+VS − 0.2
−VS + 0.2
−VS + 0.3
−VS + 0.2
+VS − 0.2
+VS − 0.3
+VS − 0.2
V
V
V
TA = −40°C to +125°C
−VS + 0.1
1.35
+VS − 0.1
−VS + 0.1
1.35
+VS − 0.1
V
Short-Circuit Current
POWER SUPPLY
13
13
mA
Operating Range
Quiescent Current
Dual-supply operation
TA = +25°C
18
425
325
525
600
+125
18
425
325
525
600
+125
V
350
250
450
525
350
250
450
525
μA
μA
μA
μA
°C
TA = −40°C
TA = +85°C
TA = +125°C
TEMPERATURE RANGE
−40
−40
1 The input stage uses pnp transistors; therefore, input bias current always flows into the part.
2 The values specified for G > 1 do not include the effects of the external gain-setting resistor, RG.
3 Input voltage range of the AD8226 input stage. The input range depends on the common-mode voltage, the differential voltage, the gain, and the reference voltage.
See the Input Voltage Range section for more information.
Rev. A | Page 4 of 28
AD8226
+VS = 2.7 V, −VS = 0 V, VREF = 0 V, TA = 25°C, G = 1, RL = 10 kΩ, specifications referred to input, unless otherwise noted.
Table 3.
ARZ, ARMZ
BRZ, BRMZ
Typ
Parameter
Conditions
Min
Typ
Max
Min
Max
Unit
COMMON-MODE REJECTION RATIO (CMRR) VCM = 0 V to 1.7 V
CMRR with DC to 60 Hz
G = 1
80
90
dB
dB
dB
dB
G = 10
100
105
105
105
110
110
G = 100
G = 1000
CMRR with DC at 5 kHz
G = 1
80
80
dB
dB
dB
dB
G = 10
90
90
G = 100
90
90
G = 1000
100
100
NOISE
Total noise: eN = √(eNI2 + (eNO/G2))
Voltage Noise
1 kHz
Input Voltage Noise, eNI
22
24
22
24
nV/√Hz
nV/√Hz
Output Voltage Noise, eNO
120
125
120
125
RTI
f = 0.1 Hz to 10 Hz
G = 1
2.0
0.5
0.4
100
3
2.0
0.5
0.4
100
3
μV p-p
μV p-p
μV p-p
fA/√Hz
pA p-p
G = 10
G = 100 to 1000
Current Noise
f = 1 kHz
f = 0.1 Hz to 10 Hz
VOLTAGE OFFSET
Input Offset, VOSI
Total offset voltage: VOS = VOSI + (VOSO/G)
200
2
100
1
μV
Average Temperature Coefficient
TA = −40°C to +125°C
0.5
2
0.5
1
μV/°C
μV
Output Offset, VOSO
Average Temperature Coefficient
Offset RTI vs. Supply (PSR)
G = 1
1000
10
500
5
TA = −40°C to +125°C
VS = 0 V to 1.7 V
μV/°C
80
90
dB
dB
dB
dB
G = 10
100
105
105
105
110
110
G = 100
G = 1000
INPUT CURRENT
Input Bias Current1
TA = +25°C
5
5
5
20
15
30
70
27
25
35
5
5
5
20
15
30
70
27
25
35
nA
TA = +125°C
nA
TA = −40°C
nA
Average Temperature Coefficient
Input Offset Current
TA = −40°C to +125°C
TA = +25°C
pA/°C
nA
1.5
1.5
1
0.5
0.5
0.1
TA = +125°C
nA
TA = −40°C
nA
Average Temperature Coefficient
TA =−40°C to +125°C
5
5
pA/°C
REFERENCE INPUT
RIN
100
7
100
7
kΩ
μA
V
IIN
Voltage Range
Reference Gain to Output
Reference Gain Error
DYNAMIC RESPONSE
Small-Signal −3 dB Bandwidth
G = 1
−VS
+VS
−VS
+VS
1
1
V/V
%
0.01
0.01
1500
160
20
1500
160
20
kHz
kHz
kHz
kHz
G = 10
G = 100
G = 1000
2
2
Rev. A | Page 5 of 28
AD8226
ARZ, ARMZ
BRZ, BRMZ
Typ
Parameter
Settling Time 0.01%
G = 1
Conditions
Min
Typ
Max
Min
Max
Unit
2 V step
6
6
μs
G = 10
6
6
μs
G = 100
35
350
0.4
0.6
35
350
0.4
0.6
μs
G = 1000
μs
Slew Rate
G = 1
V/μs
V/μs
G = 5 to 100
G = 1 + (49.4 kΩ/RG)
GAIN
Gain Range
Gain Error
G = 1
1
1000
1
1000
V/V
VOUT = 0.8 V to 1.8 V
VOUT = 0.2 V to 2.5 V
0.04
0.3
0.01%
0.1%
%
%
G = 5 to 1000
Gain vs. Temperature2
G = 1
TA = −40°C to +85°C
5
1
2
ppm/°C
ppm/°C
ppm/°C
TA = +85°C to +125°C
TA = −40°C to +125°C
−VS = 0 V, +VS = 2.7 V to 36 V
5
G > 1
−100
INPUT
Input Impedance
Differential
0.8||2
0.4||2
0.8||2
0.4||2
GΩ||pF
Common Mode
Input Operating Voltage Range3
GΩ||pF
TA = +25°C
−0.1
+VS − 0.7 −0.1
+VS − 0.9 −0.15
+VS − 0.6 −0.05
−VS + 40 +VS − 40
+VS − 0.7
+VS − 0.9
+VS − 0.6
−VS + 40
V
V
V
TA = −40°C
−0.15
−0.05
+VS − 40
TA = +125°C
Input Overvoltage Range
OUTPUT
TA = −40°C to +125°C
Output Swing
RL = 10 kΩ to 1.35 V,
TA = −40°C to +125°C
0.1
+VS − 0.1 0.1
+VS − 0.1
V
Short-Circuit Current
POWER SUPPLY
13
13
mA
Operating Range
Quiescent Current
Single-supply operation
2.2
36
2.2
36
V
TA = +25°C, −VS = 0 V, +VS = 2.7 V
TA = −40°C, −VS = 0 V, +VS = 2.7 V
TA = +85°C, −VS = 0 V, +VS = 2.7 V
TA = +125°C, −VS = 0 V, +VS = 2.7 V
325
250
425
475
400
325
500
550
+125
325
250
425
475
400
325
500
550
+125
μA
μA
μA
μA
°C
TEMPERATURE RANGE
−40
−40
1 Input stage uses pnp transistors; therefore, input bias current always flows into the part.
2 The values specified for G > 1 do not include the effects of the external gain-setting resistor, RG.
3 Input voltage range of the AD8226 input stage. The input range depends on the common-mode voltage, the differential voltage, the gain, and the reference voltage.
See the Input Voltage Range section for more information.
Rev. A | Page 6 of 28
AD8226
ABSOLUTE MAXIMUM RATINGS
Table 4.
THERMAL RESISTANCE
θJA is specified for a device in free air.
Parameter
Rating
Supply Voltage
18 V
Table 5. Thermal Resistance
Package
Output Short-Circuit Current
Maximum Voltage at −IN or +IN
Minimum Voltage at −IN or +IN
REF Voltage
Indefinite
−VS + 40 V
+VS − 40 V
VS
θJA
Unit
°C/W
°C/W
8-Lead MSOP, 4-Layer JEDEC Board
8-Lead SOIC, 4-Layer JEDEC Board
135
121
Storage Temperature Range
Specified Temperature Range
Maximum Junction Temperature
ESD
−65°C to +150°C
−40°C to +125°C
140°C
ESD CAUTION
Human Body Model
Charge Device Model
Machine Model
1.5 kV
1.5 kV
100 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. A | Page 7 of 28
AD8226
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD8226
1
2
3
4
8
7
6
5
–IN
+V
S
R
R
V
OUT
G
G
REF
–V
+IN
S
TOP VIEW
(Not to Scale)
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic Description
1
2, 3
4
5
6
−IN
RG
Negative Input.
Gain-Setting Pins. Place a gain resistor between these two pins.
Positive Input.
Negative Supply.
Reference. This pin must be driven by low impedance.
Output.
Positive Supply.
+IN
−VS
REF
VOUT
+VS
7
8
Rev. A | Page 8 of 28
AD8226
TYPICAL PERFORMANCE CHARACTERISTICS
T = 25°C, VS = 15 V, RL = 10 kꢀ, unless otherwise noted.
N: 2203
MEAN: 35.7649
SD: 229.378
MEAN: 0.041
SD: 0.224
250
200
160
140
120
100
80
150
100
50
60
40
20
0
0
–1.2
–900
–600
–300
0
300
600
900
0
0.3
DRIFT (µV)
OSI
0.6
0.9
1.2
–0.9
–0.6
–0.3
V
@ ±15V (µV)
V
OSO
Figure 3. Typical Distribution of Output Offset Voltage
Figure 6. Typical Distribution of Input Offset Voltage Drift, G = 100
MEAN: –0.57
SD: 1.5762
MEAN: 21.5589
SD: 0.624
180
150
240
210
180
150
120
90
120
90
60
30
0
60
30
0
–9
–6
–3
0
3
6
9
18
26
20
22
24
V
DRIFT (µV)
POSITIVE I
CURRENT @ ±15V (nA)
OSO
BIAS
Figure 4. Typical Distribution of Output Offset Voltage Drift
Figure 7. Typical Distribution of Input Bias Current
350
MEAN: 0.003
SD: 0.075
MEAN: –3.67283
SD: 51.1
300
250
200
300
250
200
150
100
50
150
100
50
0
0
–400
0
200
400
–0.9
–0.6
–0.3
V
0
0.3
@ ±15V (nA)
OSI
0.6
0.9
–200
V
@ R PINS @ ±15V (µV)
OSI
G
Figure 5. Typical Distribution of Input Offset Voltage
Figure 8. Typical Distribution of Input Offset Current
Rev. A | Page 9 of 28
AD8226
2.5
2.0
1.5
1.0
0.5
0
2.5
2.0
1.5
1.0
0.5
0
+0.02V, +2.0V
V
= +1.35V
REF
+0.02V, +2.0V
+1.35V, +1.9V
V
= +1.35V
+1.35V, +1.9V
REF
+0.02V, +1.3V
+2.68V, +1.2V
+2.4V, +0.8V
+0.02V, +1.3V
+2.67V, +1.3V
V
= 0V
V
= 0V
REF
REF
+2.4V, +0.8V
+2.68V, +0.3V
+0.02V, +0.3V
+0.02V, +0.4V
+2.67V, +0.4V
–0.5
+1.35V, –0.4V
+0.02V, –0.4V
+1.35, –0.3V
1.5
+0.02V, –0.3V
–0.5
–0.5
–1.0
–0.5
2.0
2.0
0
0.5
1.0
1.5
2.5
3.0
0
0.5
1.0
2.5
3.0
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
Figure 9. Input Common-Mode Voltage vs. Output Voltage,
Single Supply, VS = +2.7 V, G = 1
Figure 12. Input Common-Mode Voltage vs. Output Voltage,
Single Supply, VS = +2.7 V, G = 100
5
5
+0.02V, +4.3V
+2.5V, +4.2V
+0.02V, +4.3V
+2.5V, +4.3V
V
= +1.35V
V
= +2.5V
REF
REF
4
3
4
3
+0.02V, +3.0V
+4.96V, +3.0V
+0.02V, +3.0V
+4.98V, +3.0V
V
= 0V
V
= 0V
REF
REF
2
2
+4.7V, +1.9V
+4.7V, +1.9V
1
+0.02V, +0.8V
1
+4.98V, +0.8V
+0.02V, +0.7V
+4.96V, +0.7V
0
0
+2.5V, –0.3.V
+0.02V, –0.3V
+0.02V, –0.4V
+2.5V, –0.4V
–1
–0.5
–1
–0.5
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
OUTPUT VOLTAGE (V)
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
OUTPUT VOLTAGE (V)
Figure 13. Input Common-Mode Voltage vs. Output Voltage,
Single Supply, VS = +5 V, G = 100
Figure 10. Input Common-Mode Voltage vs. Output Voltage,
Single Supply, VS = +5 V, G = 1
6
6
0V, +4.3V
0V, +4.2V
4
4
2
2
–4.97V, +1.8V
+4.96V, +1.8V
+4.96V, +1.7V
–4.96V, +1.7V
0
–2
–4
–6
0
–2
–4
–6
–4.97V, –3.0V
+4.96V, –0.3V
–4.96V, –3.1V
+4.96V, –3.1V
0V, –5.4V
0
0V, –5.3V
0
4
4
–6
–4
–2
2
6
–6
–4
–2
2
6
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
Figure 11. Input Common-Mode Voltage vs. Output Voltage,
Dual Supplies, VS = 5 V, G = 1
Figure 14. Input Common-Mode Voltage vs. Output Voltage,
Dual Supplies, VS = 5 V, G = 100
Rev. A | Page 10 of 28
AD8226
20
15
20
15
0V, +14.3V
0V, +11.3V
0V, +14.2V
0V, +11.2V
V
= ±15V
V = ±15V
S
S
10
10
+14.96V, +6.8V
+14.94V, +6.8V
+14.95V, +6.7V
+14.95V, +6.7V
5
5
–11.95V, +5.3V
+11.95V, +5.3V
= ±12V
–11.95V, +5.2V
+11.95V, +5.2V
0
0
V
S
V
S
= ±12V
–5
–5
+11.95V, –6.4V
+11.95V, –6.5V
–11.95V, –6.4V
–11.95V, –6.5V
0V, –12.4V
0V, –12.3V
–10
–15
–20
–10
–15
–20
+14.94V, –7.9V
+14.95V, –8.0V
–14.96V, –7.9V
–14.95V, –8.0V
0V, –15.4V
0
0V, –15.4V
0
5
10
5
10
–20
–15
–10
–5
15
20
–20
–15
–10
–5
15
20
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
Figure 15. Input Common-Mode Voltage vs. Output Voltage,
Dual Supplies, VS = 15 V, G = 1
Figure 18. Input Common-Mode Voltage vs. Output Voltage,
Dual Supplies, VS = 15 V, G = 100
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
0.6
0.5
0.4
0.3
2.75
2.50
0.6
0.5
0.4
0.3
V
G = 1
–V = 0V
IN
= 2.7V
V
= 2.7V
S
S
G = 100
–V = 0V
IN
2.25
2.00
1.75
1.50
1.25
1.00
0.75
V
OUT
V
OUT
0.2
0.2
0.1
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
I
IN
I
IN
0.50
0.25
0
–40 –35 –30 –25 –20 –15 –10 –5
0
5
10 15 20 25 30 35 40
–40 –35 –30 –25 –20 –15 –10 –5
0
5
10 15 20 25 30 35 40
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Figure 16. Input Overvoltage Performance, G = 1, VS = 2.7 V
Figure 19. Input Overvoltage Performance, G = 100, VS = 2.7 V
16
14
12
10
8
0.5
16
14
12
10
8
0.6
0.5
0.4
V
G = 1
–V = 0V
IN
= ±15V
V = ±15V
S
G = 100
–V = 0V
IN
S
0.4
0.3
V
V
I
OUT
OUT
0.3
0.2
0.1
0.2
6
6
4
4
0.1
2
0
2
0
I
IN
0
0
IN
–2
–2
–0.1
–0.1
–0.2
–0.3
–0.4
–0.5
–4
–4
–0.2
–6
–6
–8
–8
–0.3
–0.4
–0.5
–0.6
–10
–12
–14
–10
–12
–14
–16
–16
–40 –35 –30 –25 –20 –15 –10 –5
0
5
10 15 20 25 30 35 40
–40 –35 –30 –25 –20 –15 –10 –5
0
5
10 15 20 25 30 35 40
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Figure 17. Input Overvoltage Performance, G = 1, VS = 15 V
Figure 20. Input Overvoltage Performance, G = 100, VS = 15 V
Rev. A | Page 11 of 28
AD8226
30
29
28
160
140
120
100
GAIN = 1000
–0.15V
27
26
GAIN = 100
GAIN = 10
25
24
23
22
GAIN = 1
80
60
40
20
0
21
20
+4.22V
19
18
17
16
–0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0.1
1
10
100
1k
10k
100k
1M
COMMON-MODE VOLTAGE (V)
FREQUENCY (Hz)
Figure 21. Input Bias Current vs. Common-Mode Voltage, VS = +5 V
Figure 24. Negative PSRR vs. Frequency
50
70
60
V
= ±15V
S
GAIN = 1000
–15.13V
45
40
35
30
25
50
GAIN = 100
GAIN = 10
GAIN = 1
40
30
20
20
10
15
+14.18V
0
10
5
–10
–20
–30
0
–5
–16
–12
–8
–4
0
4
8
12
16
100
1k
10k
100k
1M
10M
COMMON-MODE VOLTAGE (V)
FREQUENCY (Hz)
Figure 22. Input Bias Current vs. Common-Mode Voltage, VS = 15 V
Figure 25. Gain vs. Frequency, VS = 15 V
160
70
60
V
= 2.7V
S
GAIN = 1000
GAIN = 1000
140
GAIN = 100
50
120
GAIN = 10
GAIN = 100
GAIN = 10
GAIN = 1
40
GAIN = 1
100
30
20
80
60
40
20
0
10
0
–10
–20
–30
0.1
1
10
100
1k
10k
100k
1M
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 23. Positive PSRR vs. Frequency, RTI
Figure 26. Gain vs. Frequency, 2.7 V Single Supply
Rev. A | Page 12 of 28
AD8226
160
35
30
25
20
15
10
5
150
V
V
= ±15V
= 0V
–IN BIAS CURRENT
+IN BIAS CURRENT
OFFSET CURRENT
S
GAIN = 1000
GAIN = 100
REF
140
120
100
80
125
100
75
50
25
0
BANDWIDTH
LIMITED
GAIN = 10
GAIN = 1
60
40
20
0
0.1
1
10
100
1k
10k
100k
–45 –30 –15
0
15 30 45 60 75 90 105 120 135
FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 27. CMRR vs. Frequency, RTI
Figure 30. Input Bias Current and Input Offset Current vs. Temperature
20
10
120
100
80
GAIN = 100
GAIN = 1000
GAIN = 1
BANDWIDTH
LIMITED
0
–0.6
ppm/°C
GAIN = 10
–10
–20
60
40
20
0
–0.3ppm/°C
–30
–0.4ppm/°C
–40
–50
–60
NORMALIZED AT 25°C
–70
–60 –40 –20
0
20
40
60
80
100 120 140
0.1
1
10
100
FREQUENCY (Hz)
1k
10k
100k
TEMPERATURE (°C)
Figure 31. Gain Error vs. Temperature, G = 1
Figure 28. CMRR vs. Frequency, RTI, 1 kΩ Source Imbalance
20
10
3.0
2.5
2.0
1.5
1.0
0.5
0
–0.35ppm/°C
0.2ppm/°C
0
–10
–20
–30
–40
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
REPRESENTATIVE DATA
NORMALIZED AT 25°C
–50
–30
–10
10
30
50
70
90
110
130
0
10 20 30 40 50 60 70 80 90 100 110 120
WARM-UP TIME (Seconds)
TEMPERATURE (°C)
Figure 32. CMRR vs. Temperature, G = 1
Figure 29. Change in Input Offset Voltage vs. Warm-Up Time
Rev. A | Page 13 of 28
AD8226
+V
S
15
10
5
–40°C
+25°C
+85°C
+105°C
+125°C
–0.2
–0.4
–0.6
–0.8
–40°C
+25°C
+85°C
+105°C
+125°C
0
–V
S
–5
–10
–15
–0.2
–0.4
–0.6
–0.8
2
4
6
8
10
12
14
16
18
100
1k
10k
100k
SUPPLY VOLTAGE (±V )
LOAD RESISTANCE (Ω)
S
Figure 33. Input Voltage Limit vs. Supply Voltage
Figure 36. Output Voltage Swing vs. Load Resistance
+V
S
+V
S
–0.1
–0.2
–0.3
–0.4
–0.2
–0.4
–0.6
–0.8
–40°C
+25°C
+85°C
+105°C
+125°C
–40°C
+25°C
+85°C
+105°C
+125°C
+0.8
+0.6
+0.4
+0.2
+0.4
+0.3
+0.2
+0.1
–V
–V
S
10µ
S
2
4
6
8
10
12
14
16
18
100µ
1M
10M
SUPPLY VOLTAGE (±V )
OUTPUT CURRENT (A)
S
Figure 34. Output Voltage Swing vs. Supply Voltage, RL = 10 kΩ
Figure 37. Output Voltage Swing vs. Output Current, G = 1
8
+V
S
G = 1
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
6
4
2
0
–40°C
+25°C
+85°C
+105°C
+125°C
+1.2
+1.0
+0.8
+0.6
+0.4
+0.2
–2
–4
–6
–8
–V
S
–10
–8
–6
–4
–2
0
2
4
6
8
10
2
4
6
8
10
12
14
16
18
OUTPUT VOLTAGE (V)
SUPPLY VOLTAGE (±V )
S
Figure 35. Output Voltage Swing vs. Supply Voltage, RL = 2 kΩ
Figure 38. Gain Nonlinearity, G = 1, RL ≥ 2 kΩ
Rev. A | Page 14 of 28
AD8226
8
6
1k
G = 10
4
2
GAIN = 1
0
100
–2
–4
–6
–8
GAIN = 10
GAIN = 100
GAIN = 1000
10
BANDWIDTH
LIMITED
10
–10
–8
–6
–4
–2
0
2
4
6
8
10
1
100
1k
10k
100k
OUTPUT VOLTAGE (V)
FREQUENCY (Hz)
Figure 39. Gain Nonlinearity, G = 10, RL ≥ 2 kΩ
Figure 42. Voltage Noise Spectral Density vs. Frequency
80
60
G = 100
GAIN = 1000, 200nV/DIV
40
20
GAIN = 1, 1µV/DIV
0
–20
–40
–60
–80
1s/DIV
–10
–8
–6
–4
–2
0
2
4
6
8
10
OUTPUT VOLTAGE (V)
Figure 40. Gain Nonlinearity, G = 100, RL ≥ 2 kΩ
Figure 43. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 1, G = 1000
800
600
1k
G = 1000
400
200
0
100
–200
–400
–600
–800
10
–10
–8
–6
–4
–2
0
2
4
6
8
10
1
10
100
1k
10k
OUTPUT VOLTAGE (V)
FREQUENCY (Hz)
Figure 41. Gain Nonlinearity, G = 1000, RL ≥ 2 kΩ
Figure 44. Current Noise Spectral Density vs. Frequency
Rev. A | Page 15 of 28
AD8226
5V/DIV
15.46μs TO 0.01%
17.68µs TO 0.001%
0.002%/DIV
40µs/DIV
1.5pA/DIV
1s/DIV
Figure 45. 0.1 Hz to 10 Hz Current Noise
Figure 48. Large-Signal Pulse Response and Settling Time,
G = 10, 10 V Step, VS = 15 V
30
V
S
= ±15V
27
24
21
18
15
12
9
5V/DIV
39.64μs TO 0.01%
58.04µs TO 0.001%
0.002%/DIV
6
V
S
= +5V
3
100µs/DIV
0
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 46. Large-Signal Frequency Response
Figure 49. Large-Signal Pulse Response and Settling Time,
G = 100, 10 V Step, VS = 15 V
5V/DIV
5V/DIV
349.6μs TO 0.01%
529.6µs TO 0.001%
25.38μs TO 0.01%
26.02µs TO 0.001%
0.002%/DIV
0.002%/DIV
400µs/DIV
40µs/DIV
Figure 47. Large-Signal Pulse Response and Settling Time,
G = 1, 10 V Step, VS = 15 V
Figure 50. Large-Signal Pulse Response and Settling Time,
G = 1000, 10 V Step, VS = 15 V
Rev. A | Page 16 of 28
AD8226
20mV/DIV
4µs/DIV
20mV/DIV
20µs/DIV
Figure 53. Small-Signal Response, G = 100, RL = 10 kΩ, CL = 100 pF
Figure 51. Small-Signal Response, G = 1, RL = 10 kΩ, CL = 100 pF
20mV/DIV
100µs/DIV
20mV/DIV
4µs/DIV
Figure 52. Small-Signal Response, G = 10, RL = 10 kΩ, CL = 100 pF
Figure 54. Small-Signal Response, G = 1000, RL = 10 kΩ, CL = 100 pF
Rev. A | Page 17 of 28
AD8226
340
330
320
310
300
290
NO LOAD
R
= 47pF
L
R
= 100pF
= 147pF
L
L
R
20mV/DIV
4µs/DIV
0
2
4
6
8
10
12
14
16
18
SUPPLY VOLTAGE (±V )
S
Figure 55. Small-Signal Response with Various Capacitive Loads,
G = 1, RL = ∞
Figure 57. Supply Current vs. Supply Voltage
60
50
40
30
SETTLED TO 0.001%
20
SETTLED TO 0.01%
10
0
2
4
6
8
10
12
14
16
18
20
STEP SIZE (V)
Figure 56. Settling Time vs. Step Size, VS = 15 V Dual Supplies
Rev. A | Page 18 of 28
AD8226
THEORY OF OPERATION
+V
–V
+V
–V
S
S
R
G
NODE 3
NODE 4
R3
50kΩ
S
S
R1
24.7kΩ
R2
24.7kΩ
+V
–V
S
R4
50kΩ
NODE 2
V
A3
OUT
+V
–V
NODE 1
R5
50kΩ
S
R6
50kΩ
S
ESD AND
OVERVOLTAGE
PROTECTION
ESD AND
OVERVOLTAGE
PROTECTION
REF
Q1
Q2
+IN
–IN
A1
A2
S
V
R
R
BIAS
B
B
–V
DIFFERENCE
AMPLIFIER STAGE
S
GAIN STAGE
Figure 58. Simplified Schematic
ARCHITECTURE
GAIN SELECTION
The AD8226 is based on the classic 3-op-amp topology. This
topology has two stages: a preamplifier to provide differential
amplification, followed by a difference amplifier to remove the
common-mode voltage. Figure 58 shows a simplified schematic
of the AD8226.
Placing a resistor across the RG terminals sets the gain of the
AD8226, which can be calculated by referring to Table 7 or by
using the following gain equation:
49.4 kΩ
RG =
G −1
The first stage works as follows: in order to maintain a constant
voltage across the bias resistor RB, A1 must keep Node 3 a con-
stant diode drop above the positive input voltage. Similarly, A2
keeps Node 4 at a constant diode drop above the negative input
voltage. Therefore, a replica of the differential input voltage is
placed across the gain-setting resistor, RG. The current that
flows across this resistance must also flow through the R1
and R2 resistors, creating a gained differential signal between
the A2 and A1 outputs. Note that, in addition to a gained
differential signal, the original common-mode signal, shifted
a diode drop up, is also still present.
Table 7. Gains Achieved Using 1% Resistors
1% Standard Table Value of RG (Ω)
Calculated Gain
49.9 k
12.4 k
5.49 k
2.61 k
1.00 k
499
1.990
4.984
9.998
19.93
50.40
100.0
249
199.4
100
495.0
49.9
991.0
The second stage is a difference amplifier, composed of A3 and
four 50 kꢀ resistors. The purpose of this stage is to remove the
common-mode signal from the amplified differential signal.
The AD8226 defaults to G = 1 when no gain resistor is used.
The tolerance and gain drift of the RG resistor should be added
to the AD8226 specifications to determine the total gain accu-
racy of the system. When the gain resistor is not used, gain
error and gain drift are minimal.
The transfer function of the AD8226 is
V
OUT = G(VIN+ − VIN−) + VREF
where:
49.4 kΩ
If a gain of 5 is required and minimal gain drift is important,
consider using the AD8227. The AD8227 has a default gain of 5
that is set with internal resistors. Because all resistors are internal,
the gain drift is extremely low (<5 ppm/°C maximum).
G =1 +
RG
Rev. A | Page 19 of 28
AD8226
REFERENCE TERMINAL
(VDIFF )(G)
VCM
VCM
−
+
> −V S + V−LIMIT
< +VS −V+LIMIT
(1)
(2)
2
The output voltage of the AD8226 is developed with respect to
the potential on the reference terminal. This is useful when the
output signal needs to be offset to a precise midsupply level. For
example, a voltage source can be tied to the REF pin to level-
shift the output so that the AD8226 can drive a single-supply
ADC. The REF pin is protected with ESD diodes and should
not exceed either +VS or −VS by more than 0.3 V.
(VDIFF )(G)
2
(VDIFF )(G)
+VCM +VREF
2
< +VS −VREF _ LIMIT
(3)
2
For the best performance, source impedance to the REF
terminal should be kept below 2 ꢀ. As shown in Figure 58,
the reference terminal, REF, is at one end of a 50 kΩ resistor.
Additional impedance at the REF terminal adds to this 50 kΩ
resistor and results in amplification of the signal connected to
the positive input. The amplification from the additional RREF
can be computed by 2(50 kΩ + RREF)/(100 kΩ + RREF).
Table 8. Input Voltage Range Constants for Various
Temperatures
Temperature
V−LIMIT
V+LIMIT
VREF_LIMIT
−40°C
+25°C
+85°C
+125°C
−0.55 V
−0.35 V
−0.15 V
−0.05 V
0.8 V
0.7 V
0.65 V
0.6 V
1.3 V
1.15 V
1.05 V
0.9 V
Only the positive signal path is amplified; the negative path
is unaffected. This uneven amplification degrades CMRR.
Performance Across Temperature
INCORRECT
CORRECT
The common-mode input range shifts upward with temper-
ature. At cold temperatures, the part requires extra headroom
from the positive supply, and operation near the negative supply
has more margin. Conversely, hot temperatures require less
headroom from the positive supply, but are the worst-case
conditions for input voltages near the negative supply.
AD8226
AD8226
REF
REF
V
V
+
Recommendation for Best Performance
OP1177
–
A typical part functions up to the boundaries described in this
section. However, for best performance, designing with a few
hundred millivolts extra margin is recommended. As signals
approach the boundary, internal transistors begin to saturate,
which can affect frequency and linearity performance.
Figure 59. Driving the Reference Pin
INPUT VOLTAGE RANGE
Figure 9 through Figure 15 and Figure 18 show the allowable
common-mode input voltage ranges for various output voltages
and supply voltages. The 3-op-amp architecture of the AD8226
applies gain in the first stage before removing common-mode
voltage with the difference amplifier stage. Internal nodes between
the first and second stages (Node 1 and Node 2 in Figure 58)
experience a combination of a gained signal, a common-mode
signal, and a diode drop. This combined signal can be limited
by the voltage supplies even when the individual input and
output signals are not limited.
If the application requirements exceed the boundaries, one
solution is to apply less gain with the AD8226, and then apply
additional gain later in the signal chain. Another option is to
use the pin-compatible AD8227.
LAYOUT
To ensure optimum performance of the AD8226 at the PCB
level, care must be taken in the design of the board layout.
The AD8226 pins are arranged in a logical manner to aid in
this task.
For most applications, Figure 9 through Figure 15 and Figure 18
provide sufficient information to achieve a good design. For
applications where a more detailed understanding is needed,
Equation 1 to Equation 3 can be used to understand how the
gain (G), common-mode input voltage (VCM), differential input
voltage (VDIFF), and reference voltage (VREF) interact. The values for
the constants, V−LIMIT, V+LIMIT, and VREF_LIMIT, are shown in Table 8.
These three formulas, along with the input and output range
specifications in Table 2 and Table 3, set the operating boundaries
of the part.
1
2
3
4
8
7
6
5
+V
V
–IN
S
R
G
OUT
R
REF
G
+IN
–V
S
AD8226
TOP VIEW
(Not to Scale)
Figure 60. Pinout Diagram
Rev. A | Page 20 of 28
AD8226
Common-Mode Rejection Ratio Over Frequency
INPUT BIAS CURRENT RETURN PATH
Poor layout can cause some of the common-mode signals to be
converted to differential signals before reaching the in-amp.
Such conversions occur when one input path has a frequency
response that is different from the other. To keep CMRR across
frequency high, the input source impedance and capacitance of
each path should be closely matched. Additional source resistance
in the input path (for example, for input protection) should be
placed close to the in-amp inputs, which minimizes their
interaction with parasitic capacitance from the PCB traces.
The input bias current of the AD8226 must have a return path
to ground. When the source, such as a thermocouple, cannot
provide a return current path, one should be created, as shown
in Figure 62.
INCORRECT
CORRECT
+V
+V
S
S
AD8226
AD8226
Parasitic capacitance at the gain-setting pins can also affect
CMRR over frequency. If the board design has a component
at the gain-setting pins (for example, a switch or jumper), the
part should be chosen so that the parasitic capacitance is as
small as possible.
REF
REF
REF
REF
–V
S
–V
S
TRANSFORMER
TRANSFORMER
Power Supplies
+V
+V
S
S
A stable dc voltage should be used to power the instrumentation
amplifier. Note that noise on the supply pins can adversely affect
performance. For more information, see the PSRR performance
curves in Figure 23 and Figure 24.
AD8226
AD8226
REF
A 0.1 μF capacitor should be placed as close as possible to each
supply pin. As shown in Figure 61, a 10 μF tantalum capacitor
can be used farther away from the part. In most cases, it can be
shared by other precision integrated circuits.
10MΩ
–V
–V
S
S
THERMOCOUPLE
THERMOCOUPLE
+V
S
+V
+V
S
S
C
C
C
0.1µF
10µF
R
R
1
fHIGH-PASS
=
+IN
–IN
AD8226
2πRC
AD8226
C
REF
V
OUT
AD8226
LOAD
REF
–V
S
–V
S
CAPACITIVELY COUPLED
CAPACITIVELY COUPLED
Figure 62. Creating an IBIAS Path
0.1µF
10µF
–V
S
Figure 61. Supply Decoupling, REF, and Output Referred to Local Ground
References
The output voltage of the AD8226 is developed with respect to
the potential on the reference terminal. Care should be taken to
tie REF to the appropriate local ground.
Rev. A | Page 21 of 28
AD8226
+V
S
INPUT PROTECTION
The AD8226 has very robust inputs and typically does not
need additional input protection. Input voltages can be up to
40 V from the opposite supply rail. For example, with a +5 V
positive supply and a −8 V negative supply, the part can safely
withstand voltages from −35 V to 32 V. Unlike some other
instrumentation amplifiers, the part can handle large differen-
tial input voltages even when the part is in high gain. Figure 16,
Figure 17, Figure 19, and Figure 20 show the behavior of the
part under overvoltage conditions.
0.1µF
+IN
10µF
C
1nF
C
R
4.02kΩ
V
C
D
10nF
OUT
R
G
AD8226
R
REF
–IN
4.02kΩ
C
C
1nF
0.1µF
10µF
The rest of the AD8226 terminals should be kept within the
supplies. All terminals of the AD8226 are protected against ESD.
–V
S
Figure 63. RFI Suppression
For applications where the AD8226 encounters voltages beyond
the allowed limits, external current-limiting resistors and low-
leakage diode clamps such as the BAV199L, the FJH1100s, or
the SP720 should be used.
CD affects the difference signal and CC affects the common-mode
signal. Values of R and CC should be chosen to minimize RFI.
Mismatch between the R × CC at the positive input and the R × CC
at the negative input degrades the CMRR of the AD8226. By using
a value of CD that is one magnitude larger than CC, the effect of
the mismatch is reduced and performance is improved.
RADIO FREQUENCY INTERFERENCE (RFI)
RF rectification is often a problem when amplifiers are used in
applications having strong RF signals. The disturbance can appear
as a small dc offset voltage. High frequency signals can be filtered
with a low-pass RC network placed at the input of the instru-
mentation amplifier, as shown in Figure 63. The filter limits the
input signal bandwidth according to the following relationship:
1
FilterFrequencyDIFF
FilterFrequencyCM
=
2πR(2CD +CC )
1
=
2πRCC
where CD ≥ 10 CC.
Rev. A | Page 22 of 28
AD8226
APPLICATIONS INFORMATION
Tips for Best Differential Output Performance
DIFFERENTIAL DRIVE
For best ac performance, an op amp with at least a 2 MHz gain
bandwidth and a 1 V/μs slew rate is recommended. Good choices
for op amps are the AD8641, AD8515, and AD820.
+IN
+OUT
AD8226
–IN
Keep trace lengths from the resistors to the inverting terminal
of the op amp as short as possible. Excessive capacitance at this
node can cause the circuit to be unstable. If capacitance cannot
be avoided, use lower value resistors.
REF
R
R
V
BIAS
–
+
OP AMP
For best linearity and ac performance, a minimum positive
supply voltage (+VS) is required. Table 9 shows the minimum
supply voltage required for optimum performance. In this mode,
–OUT
RECOMMENDED OP AMPS: AD8515, AD8641, AD820.
VCM_MAX indicates the maximum common-mode voltage expected
RECOMMENDED R VALUES: 5kΩ to 20kΩ.
at the input of the AD8226.
Figure 64. Differential Output Using an Op Amp
Figure 64 shows how to configure the AD8226 for differ-
ential output.
Table 9. Minimum Positive Supply Voltage
Temperature
Less than −10°C
−10°C to 25°C
More than 25°C
Equation
The differential output is set by the following equation:
+VS > (VCM_MAX + VBIAS)/2 + 1.4 V
+VS > (VCM_MAX + VBIAS)/2 + 1.25 V
+VS > (VCM_MAX + VBIAS)/2 + 1.1 V
V
DIFF_OUT = VOUT+ − VOUT− = Gain × (VIN+ − VIN−
The common-mode output is set by the following equation:
CM_OUT = (VOUT+ − VOUT−)/2= VBIAS
)
V
The advantage of this circuit is that the dc differential accuracy
depends on the AD8226, not on the op amp or the resistors. In
addition, this circuit takes advantage of the precise control that the
AD8226 has of its output voltage relative to the reference voltage.
Although the dc performance and resistor matching of the op amp
affect the dc common-mode output accuracy, such errors are
likely to be rejected by the next device in the signal chain and
therefore typically have little effect on overall system accuracy.
Rev. A | Page 23 of 28
AD8226
Option 1 shows the minimum configuration required to drive
a charge-sampling ADC. The capacitor provides charge to the
ADC sampling capacitor while the resistor shields the AD8226
from the capacitance. To keep the AD8226 stable, the RC time
constant of the resistor and capacitor needs to stay above 5 μs.
This circuit is mainly useful for lower frequency signals.
PRECISION STRAIN GAGE
The low offset and high CMRR over frequency of the AD8226
make it an excellent candidate for performing bridge measure-
ments. The bridge can be connected directly to the inputs of the
amplifier (see Figure 65).
5V
Option 2 shows a circuit for driving higher speed signals. It uses a
precision op amp (AD8616) with relatively high bandwidth and
output drive. This amplifier can drive a resistor and capacitor with
a much higher time constant and is therefore suited for higher
frequency applications.
10µF
0.1µF
350Ω
350Ω
350Ω
350Ω
+IN
–IN
+
R
AD8226
G
–
Option 3 is useful for applications where the AD8226 needs to
run off a large voltage supply but drive a single-supply ADC.
In normal operation, the AD8226 output stays within the ADC
range, and the AD8616 simply buffers it. However, in a fault
condition, the output of the AD8226 may go outside the supply
range of both the AD8616 and the ADC. This is not an issue in
the circuit, however, because the 10 kΩ resistor between the two
amplifiers limits the current into the AD8616 to a safe level.
2.5V
Figure 65. Precision Strain Gage
DRIVING AN ADC
Figure 66 shows several methods for driving an ADC. The
ADuC7026 microcontroller was chosen for this example because it
contains ADCs with an unbuffered, charge-sampling architecture
that is typical of most modern ADCs. This type of architecture
typically requires an RC buffer stage between the ADC and
amplifier to work correctly.
OPTION 1: DRIVING LOW FREQUENCY SIGNALS
3.3V
3.3V
AV
DD
100Ω
ADC0
AD8226
REF
100nF
ADuC7026
OPTION 2: DRIVING HIGH FREQUENCY SIGNALS
3.3V
3.3V
AD8226
10Ω
REF
ADC1
AD8616
10nF
OPTION 3: PROTECTING ADC FROM LARGE VOLTAGES
+15V
AD8226
–15V
3.3V
10kΩ
10Ω
REF
AD8616
ADC2
AGND
10nF
Figure 66. Driving an ADC
Rev. A | Page 24 of 28
AD8226
OUTLINE DIMENSIONS
3.20
3.00
2.80
8
1
5
4
5.15
4.90
4.65
3.20
3.00
2.80
PIN 1
0.65 BSC
0.95
0.85
0.75
1.10 MAX
0.80
0.60
0.40
8°
0°
0.15
0.00
0.38
0.22
0.23
0.08
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 67. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 68. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model
Temperature Range
−40°C to +125°C
Package Description
Package Option
Branding
Y18
Y18
AD8226ARMZ1
AD8226ARMZ-RL1
AD8226ARMZ-R71
AD8226ARZ1
AD8226ARZ-RL1
AD8226ARZ-R71
AD8226BRMZ1
AD8226BRMZ-RL1
AD8226BRMZ-R71
AD8226BRZ1
8-Lead MSOP
RM-8
RM-8
RM-8
R-8
R-8
R-8
RM-8
RM-8
RM-8
R-8
R-8
R-8
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
8-Lead MSOP, 13" Tape and Reel
8-Lead MSOP, 7" Tape and Reel
8-Lead SOIC_N
8-Lead SOIC_N, 13" Tape and Reel
8-Lead SOIC_N, 7" Tape and Reel
8-Lead MSOP
8-Lead MSOP, 13" Tape and Reel
8-Lead MSOP, 7" Tape and Reel
8-Lead SOIC_N
8-Lead SOIC_N, 13" Tape and Reel
8-Lead SOIC_N, 7" Tape and Reel
Y18
Y19
Y19
Y19
AD8226BRZ-RL1
AD8226BRZ-R71
1 Z = RoHS Compliant Part.
Rev. A | Page 25 of 28
AD8226
NOTES
Rev. A | Page 26 of 28
AD8226
NOTES
Rev. A | Page 27 of 28
AD8226
NOTES
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07036-0-7/09(A)
Rev. A | Page 28 of 28
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