AD8226 [ADI]
Wide Supply Range, Rail-to-Rail Output Instrumentation Amplifier; 宽电源电压范围，轨到轨输出仪表放大器
| 型号： | AD8226 |
| 厂家： | 
ADI |
| 描述： | Wide Supply Range, Rail-to-Rail Output Instrumentation Amplifier |
| 文件： | 总16页 (文件大小：415K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Wide Supply Range, Rail-to-Rail
Output Instrumentation Amplifier
AD8226
Preliminary Technical Data
FEATURES
PIN CONFIGURATION
Gain set with 1 external resistor
Gain r a n g e : 1 to 1000
AD8226
1
2
3
4
8
7
6
5
–IN
+V
S
R
R
V
OUT
G
G
Input voltage goes to ground
Input overdrive protection
V e r y w ide power supply range
Dual supply: 1.3 V t o 18 V
Single supply: 2.6 V to 36 V
Bandwidt h ( G = 1): 800 kHz
CMRR (G = 1): 78 dB minimum
Input noise: 22 nV/r t(Hz)
REF
–V
+IN
S
TOP VIEW
(Not to Scale)
Figure 1.
Typical s u p p l y c u r r e n t : 350 µA
SOIC-8 and MSOP-8 packages
APPLICATIONS
Industrial process controls
Bridge amplifiers
Medical instrumentation
Portable data acquisition
Multichannel systems
GENERAL DESCRIPTION
Th e A D 8 2 2 6 i s a l o w c o s t i n s t r u m e n t a t i o n a m p l i f i e r t h a t r e q u i r e s
only one external resistor to set any gain between 1 and 1000.
Table 1. Instrumentation Amplifiers by Category
General Z e r o
Purpose Drift
Military L o w
Grade P o w e r
High Speed
PGA
The AD8226 is designed to work with a very wide range of
volta ge s. It can operate on supplies ranging from 1.2 V to
18 V (2.4 V to 36 V s i ng l e s uppl y ) . The AD8226 comes with
rail-to-rail output and a wide input range that includes the
ability to go slightly below the negative supply. In addition, the
AD8226 inputs can withstand voltages beyond the rail.
AD82201 AD82311 AD620
AD6271
AD6231
AD82261
AD8250
AD8251
AD8253
AD8221
AD8222
AD8290
AD621
AD82931 AD524
AD82241 AD85531 AD526
AD8228
AD85561 AD624
AD85571
The AD8226 is perfect for multichannel, space-cons traine d
a p p l i c a t i o n s . Being a low power and low cost amplifier allows
multiple channels to be used.
1 R a i l -to-rail output.
The AD8226 has three grades. The A grade is the lower cost
version and is specifie d for temperatures f rom −40°C to +85°C.
The B grade is the higher performance version and is specified
from −40°C to +85°C. The C grade version is the higher
temperature version and is specified from −40°C to +105°C. All
models are operational from −40°C to +125°C; behavior a t
these temperatures is shown in the typical performance curves.
The AD8226 is available in MSOP and SOIC packages.
Rev. PrA
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2008 Analog Devices, Inc. All rights reserved.
AD8226
Preliminary Technical Data
TABLE OF CONTENTS
Features .............................................................................................. 1
A rchit e c tu re ...................................................................................9
Gain Selection................................................................................9
Input Prote c t ion ............................................................................9
Reference Terminal .................................................................... 10
Input Voltage Range ................................................................... 10
L ayout .......................................................................................... 10
Input Bias Current Return Path ............................................... 11
Radio Frequency Interference (RFI)........................................ 11
Outline Dimensi ons ....................................................................... 12
Ordering Guide .......................................................................... 13
Appl i c a t i o ns ....................................................................................... 1
Pin Configuration............................................................................. 1
General Description ......................................................................... 1
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
E S D C a u t i o n .................................................................................. 7
Pin Configuration and Function Descriptions ............................. 8
T he or y of Op e rat ion ........................................................................ 9
Rev. PrA | P a g e 2 of 16
Preliminary Technical Data
AD8226
SPECIFICATIONS
+VS = +15 V, −VS = −15 V, VREF = 0 V, TA = 25°C, G = 1, RL = 10 kΩ, unless otherwise noted.
Table 2.
A, C Grade
Typ
B Grade
Typ
Parameter
Conditions
Min
Max
Min
Max
Unit
COMMON-M O D E REJECTION RATIO
(CMRR)
CMRR DC to 60 Hz
G = 1
G = 10
G = 100
G = 1000
NOISE
VCM = –10 V to +10 V
76
90
105
105
86
dB
dB
dB
dB
100
105
105
Total Noise:
eN = √eNI2 + (eNO/G2)
Voltage Noise, 1 kHz
Input Voltage Noise, eNI
Output Voltage Noise, eNO
RTI
VIN+, VIN−, VREF = 0
f = 0.1 Hz to 10 Hz
22
120
22
120
nV/√Hz
nV/√Hz
G = 1
G = 10
G = 100 to 1000
Current Noise
3
3
µV p-p
µV p-p
µV p-p
fA/√Hz
pA p-p
0.8
0.6
100
3
0.8
0.6
100
3
f = 1 kHz
f = 0.1 Hz to 10 Hz
VOLTAGE OFFSET
Total offset voltage :
VOS = VO S I + (VO S O /G)
VS = 5 V to 15 V
TA = TMIN t o T MAX
TA = TMIN t o T MAX
VS = 5 V to 15 V
TA = TMIN t o T MAX
TA = TMIN t o T MAX
VS = 5 V to 15 V
Input Offset, VOSI
Over Temperature
Average temperature coefficient
Output Offset, VO SO
Over Temperature
Average temperature coefficient
Offset RTI vs. Supply (PSR)
G = 1
500
200
µV
µV
1500
15
750
7
µV
mV
µV/°C
2
2
80
90
dB
dB
dB
dB
G = 10
G = 100
G = 1000
100
105
105
105
105
105
INPUT CURRENT
Input Bias Current
Over Temperature
Average temperature coefficient
Input Offset Current
Over Temperature
Average temperature coefficient
REFERENCE INPUT
RIN
10
5
20
30
40
10
5
20
30
40
nA
nA
pA/°C
nA
nA
TA = TMIN t o T MAX
TA = TMIN t o T MAX
100
100
3
5
2
5
TA = TMIN t o T MAX
TA = TMIN t o T MAX
5
5
pA/°C
100
7
100
7
kΩ
µA
V
IIN
Voltage Range
−VS
+VS
−VS
+VS
Reference Gain to Output
Reference Gain Error
1
0.01
1
0.01
V/V
%
Rev. PrA | P a g e 3 of 16
AD8226
Preliminary Technical Data
A, C Grade
Typ
B Grade
Typ
Parameter
DYNAMIC RESPONSE
Small Signal –3 dB Bandwidth
G = 1
Conditions
Min
Max
Min
Max
Unit
1000
150
15
1000
150
15
kHz
kHz
kHz
kHz
G = 10
G = 100
G =1000
1.5
1.5
Settling Time 0.01%
G = 1
G = 10
G = 100
G = 1000
10 V step
22
22
50
600
0.5
1
22
22
50
600
0.5
1
µs
µs
µs
µs
V/µs
V/µs
Slew Rate
G = 1
G = 5 to 100
G = 1 + (49.4kΩ/RG)
GAIN
Gain Range
Gain Error
G = 1
G = 10
G = 100
1
1000
1
1000
V/V
VOUT 10 V
0.07
0.3
0.3
0.02
0.1
0.1
%
%
%
%
G = 1000
0.3
0.1
Gain Nonlinearity
G = 1
G = 100
G = 1000
G = 1-100
VOUT = –10 V to +10 V
RL = 10 kΩ
RL = 10 kΩ
RL = 10 kΩ
RL = 2kΩ
ppm
ppm
ppm
ppm
Gain vs. Temperature
G = 1
TA = TMIN t o T MAX
TA = TMIN t o T MAX
VS = 1.35 V to 36 V
2
10
–50
2
5
–50
ppm/°C
ppm/°C
G > 11
INPUT
Input Impedance
Differential
Common Mode
Input Operating Voltage Range2
2||2
2||2
2||2
2||2
GΩ||pF
GΩ||pF
V
V
V
V
TA = 25°C
TA = –40°C
TA = 105°C
TA = TMIN t o T MAX
VS = 1.35 V to 36 V
RL = 10 kΩ to ground
TA = TMIN t o T MAX
RL = 100 kΩ to ground
TA = TMIN t o T MAX
−VS − 0.1
−VS − 0.15
−VS − 0.05
+VS −40
+VS − 0.7 −VS − 0.1
+VS − 0.9 −VS − 0.15
+VS − 0.6 −VS − 0.05
+VS − 0.7
+VS − 0.9
+VS − 0.6
−VS +40
Input Overvoltage Range
OUTPUT
Output Swing
−VS +40
+VS −40
−VS + 0.2
−VS + 0.3
−VS + 0.1
−VS + 0.1
+VS − 0.2 −VS + 0.2
+VS − 0.3 −VS + 0.3
+VS − 0.1 −VS + 0.1
+VS − 0.1 −VS + 0.1
−VS + 0.2
+VS − 0.3
−VS + 0.1
−VS + 0.1
13
V
Over Temperature
Output Swing
Over Temperature
Short-Circuit Current
POWER SUPPLY
V
V
V
mA
13
Operating Range
Dual supply operation
TA = TMIN t o T MAX
1.3
18
1.3
18
V
µA
µA
Quiescent Current
Over Temperature
TEMPERATURE RANGE
Specified Performance: TM I N to TM A X
350
400
+85
350
400
A and B grades
C grade
–40
–40
–40
−40
−40
+85
°C
°C
+105
+125
Operational
+125
1 Does not include the effects of external resistor RG
2 Input voltage range of the AD8226 input stage. Input range depends on common mode voltage, differential voltage, gain, and reference voltage. Se e t he Input
V o l t a g e R a n g e section in the Theory of Operation for more information.
Rev. PrA | P a g e 4 of 16
Preliminary Technical Data
AD8226
+VS = 2.7 V, –VS = 0 V, VREF = 0 V, TA = 25°C, G = 1, RL = 10 kΩ, unless otherwise noted.
Table 3.
A,C Grade
B Grade
Typ
Parameter
Conditions
Min
Typ
Max
Min
Max
Unit
COMMON-M O D E REJECTION RATIO
(CMRR)
CMRR DC to 60 Hz
G = 1
G = 10
G = 100
G = 1000
VCM = 0 V to 1.7 V
76
90
105
105
86
dB
dB
dB
dB
100
105
105
Total Noise:
NOISE
eN = √eNI2 + (eNO/G2)
Voltage Noise, 1 kHz
Input Voltage Noise, eNI
Output Voltage Noise, eNO
RTI
VIN+, VIN−, VREF= 0
22
120
22
120
nV/√Hz
nV/√Hz
f = 0.1 Hz to 10 Hz
G = 1
G = 10
3
3
µV p-p
µV p-p
µV p-p
fA/√Hz
pA p-p
0.8
0.6
100
3
0.8
0.6
100
3
G = 100 to 1000
Current Noise
f = 1 kHz
f = 0.1 Hz to 10 Hz
VOLTAGE OFFSET
Total offset voltage :
VOS = VO S I + (VO S O /G)
VS = 0 V to 1.7 V
TA = TMIN t o T MAX
TA = TMIN t o T MAX
VS = 0 V to 1.7 V
TA = TMIN t o T MAX
TA = TMIN t o T MAX
VS = 0 V to 1.7 V
Input Offset, VOSI
Over Temperature
Average TC
Output Offset, VO SO
Over Temperature
Average TC
Offset RTI vs. Supply (PSR)
G = 1
G = 10
300
150
µV
µV
µV/°C
µV
mV
0.1
2
4
1200
0.1
2
2
750
15
7
µV/°C
80
90
dB
dB
dB
dB
100
105
105
105
105
105
G = 100
G = 1000
INPUT CURRENT
Input Bias Current
Over Temperature
Average TC
Input Offset Current
Over Temperature
Average TC
10
5
20
30
40
10
5
20
30
40
nA
nA
pA/°C
nA
nA
TA = TMIN t o T MAX
TA = TMIN t o T MAX
100
100
3
5
2
5
TA = TMIN t o T MAX
TA = TMIN t o T MAX
5
5
pA/°C
REFERENCE INPUT
RIN
IIN
Voltage Range
Reference Gain to Output
Reference Gain Error
DYNAMIC RESPONSE
Small Signal –3 dB Bandwidth
G = 1
100
7
100
7
kΩ
µA
V
V/V
%
−VS
+VS
−VS
+VS
1
1
0.01
0.01
1000
150
15
1000
150
15
kHz
kHz
kHz
kHz
G = 10
G = 100
G =1000
1.5
1.5
Rev. PrA | P a g e 5 of 16
AD8226
Preliminary Technical Data
A,C Grade
B Grade
Parameter
Settling Time 0.01%
G = 1
G = 1 0
G = 100
G = 1000
Slew Rate
Conditions
Min
Typ
Max
Min
Typ
Max
Unit
2 V step
22
22
50
600
0.5
1
22
22
50
600
0.5
1
µs
µs
µs
µs
V/µs
V/µs
G = 1
G = 5 to 100
G = 1 + (49.4 kΩ/RG)
GAIN
Gain Range
Gain Error
G = 1
G = 10
G = 100
1
1000
1
1000
V/V
VOUT = 0 V to 1.7 V
0.07
0.3
0.3
0.02
0.1
0.1
%
%
%
%
G = 1000
0.3
0.1
Gain Nonlinearity
G = 1
G = 100
G = 1000
G = 1-100
VOUT = 0 V to 1.7 V
RL = 10 kΩ
RL = 10 kΩ
RL = 10 kΩ
RL = 2 kΩ
ppm
ppm
ppm
ppm
Gain vs. Temperature
G = 1
G > 11
TA = TMIN t o T MAX
TA = TMIN t o T MAX
2
10
−50
2
5
–50
ppm/°C
ppm/°C
INPUT
−VS = 0V; +VS = 2.7 V to 36 V
Input Impedance
Differential
Common Mode
Input Operating Voltage Range2
2||2
2||2
2||2
2||2
GΩ||pF
GΩ||pF
TA = 25°C
TA = –40°C
TA = 105°C
TA = TMIN t o T MAX
− 0.1
+VS − 0.7
+VS − 0.9
+VS − 0.6
−VS +40
− 0.1
+VS − 0.7
+VS − 0.9
+VS − 0.6
−VS +40
V
V
V
− 0.15
− 0.05
+VS −40
− 0.15
− 0.05
+VS −40
Input Overvoltage Range
OUTPUT
Output Swing
Over Temperature
Output Swing
Over Temperature
Short-Circuit Current
POWER SUPPLY
−VS = 0V; +VS = 2.7 V to 36 V
RL = 10 kΩ to opposite supply
TA = TMIN t o T MAX
RL = 100 kΩ to opposite supply
TA = TMIN t o T MAX
0.2
0.3
0.1
0.1
+VS − 0.2
+VS − 0.3
+VS − 0.1
+VS − 0.1
0.2
0.3
0.1
0.1
−VS + 0.2
+VS − 0.3
−VS + 0.1
−VS + 0.1
V
V
V
V
13
13
mA
Operating Range
Single supply operation
TA = TMIN t o T MAX
2.6
36
2.6
36
350
V
µA
µA
Quiescent Current
Over Temperature
TEMPERATURE RANGE
Specified Performance: TM I N to TM A X
300
350
300
A and B grades
C grade
–40
–40
–40
+85
–40
–40
+85
°C
°C
+105
+125
Operational
+125
1 Does not include the effects of external resistor RG
2 Input voltage range of the AD8226 input stage. Input range depends on common mode voltage, differential voltage, gain, and reference voltage. Se e t he Input
V o l t a g e R a n g e section in the Theory of Operation for more information.
Rev. PrA | P a g e 6 of 16
Preliminary Technical Data
AD8226
ABSOLUTE MAXIMUM RATINGS
Table 4.
THERMAL RESISTANCE
θJA is specified for a device in free air.
Parameter
Rating
Supply Voltage
18 V
Table 5.
Package
Output Short-Circuit Current
Maximum Voltage at −IN or +IN
Minimum Voltage at −IN or +IN
R E F V o lt a g e
Indefinite
−Vs + 40V
+Vs − 40V
V s
θJA
Unit
°C/W
°C/W
8-Lead MSOP, 4-Layer JEDEC Board
8-L e a d S O I C , 4-Layer JEDEC Board
135
121
Differential Input Voltage
Storage Temperature Range
Operating Temperature Range1
Maximum Junction Temperature
ESD
40V
−65°C to +150°C
−40°C to +125°C
140°C
ESD CAUTION
Human Body Model
Charge Device Model
2 kV
1 kV
1 Temperature range for specified performance is either −40°C to +85 °C or
− 4 0 ° C t o + 105°C, depending on grade.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. PrA | P a g e 7 of 16
AD8226
Preliminary Technical Data
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD8226
1
2
3
4
8
7
6
5
–IN
+V
S
R
R
V
OUT
G
G
REF
–V
+IN
S
TOP VIEW
(Not to Scale)
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
P in N o .
Mnemonic Description
1
2, 3
4
5
6
−IN
RG
Negative Input.
Gain Setting Pins. Place gain resistor between these two pins.
Positive Input.
Negative Supply.
Reference. Must be driven by low impedance.
Output.
Positive Supply.
+IN
−VS
REF
VOUT
+VS
7
8
Rev. PrA | P a g e 8 of 16
Preliminary Technical Data
AD8226
THEORY OF OPERATION
+V
–V
+V
–V
S
S
R
G
NODE 3
NODE 4
R3
50kΩ
S
S
R1
2.47kΩ
R2
2.47kΩ
+V
–V
S
R4
50kΩ
NODE 2
OUT
REF
A3
+V
–V
NODE 1
R5
50kΩ
S
+V
–V
+V
–V
S
S
R6
50kΩ
S
Q1
Q2
+IN
–IN
A1
A2
S
S
S
U
R
R
B
B
B
DIFFERENCE
AMPLIFIER STAGE
GAIN STAGE
Figure 3. Simplified Schematic
ARCHITECTURE
GAIN SELECTION
The AD8226 is based on the classic three op amp top olog y. T his
topology has two stages: a preamplifier to provide differential
amplification, followed by a difference amplifier to remove the
common-mode voltage. Fig u re 3 shows a simplified schematic of
the AD8226.
Placing a resistor across the RG terminals sets the gain of the
AD8226, which can be calculated by referring to Table 7 or by
using the following gain equ a t i o n :
49.4 kΩ
RG =
G −1
The first stage works as follows: in ord e r to maintain a constant
voltage across the Bias Resistor RB, Amplifier A1 must keep
Node 3 a constant diode drop above the positive input voltage.
Similarly, Amplifier A2 keeps Node 4 at a constant diode drop
above the negative input voltage. Therefore a replica of the
differential input voltage is placed across the gain setting
resistor, RG. The current that flows across this resistance must
also flow through the R1 and R2 resistors, creating a gained
differential signal between the A2 and A1 outputs. Note that, in
addition to a gained differential signal, the original common-
mode signal, shifted a diode drop down, is also still present.
Table 7. Gains Achieved Using 1% Resistors
1% Standard Table Value of RG (Ω)
Calculated Gain
49.9 k
12.4 k
5.49 k
2.61 k
1.00 k
499
1.990
4.984
9.998
19.93
50.40
100.0
249
199.4
100
495.0
49.9
991.0
The second stage is a difference amplifier, composed of A3 and
four 50 kΩ resistors. The purpose of this stage is to remove the
com m on-mode signal from the amplified differential signal.
The AD8226 defaults to G = 1 when no gain resistor is used.
The tolerance and gain drift of the RG resistor should be added
to the AD8226’s specifications to determine the total gain
accuracy of the system. When the gain resistor is not used,
gain error and gain drift are minimal.
Because the input amplifiers employ a current feedback
architecture, the gain-bandwidth product of the AD8226
increases with gain, resulting in a system that does not suffer
from the expected bandwidth loss of voltage feedback
architectures at higher gains.
INPUT PROTECTION
The transfer function of the AD8226 is
The input terminals of the AD8226 have input protection that
allows the i nput voltage to go beyond the rails without
damaging the part. Maximum voltage is –Vs+40 V and
minimum voltage is +Vs-40 V. For example: with 15 V
supplies, the part can withstand input voltages of 25 V; with a
5 V single supply, maximum input voltage is 40 V and
minimum input voltage is 35 V.
VOUT = G(VIN+ − VIN−) + VREF
where
49.4 kΩ
G =1+
RG
Rev. PrA | P a g e 9 of 16
AD8226
Preliminary Technical Data
(VDIFF )(GAIN)
REFERENCE TERMINAL
+VCM +VREF
2
The output voltage of the AD8226 is developed with respect to
the potential on the reference terminal. This is useful when the
output signal needs to be offset to a precise midsupply level. For
e x a m p l e, a voltage source can be tied to the REF pin to level-
shift the output so that the AD8226 can drive a single-supply
ADC. The REF pin is protected with ESD diodes and should
not exceed either +VS or − V S by more than 0.3 V.
<
+VS −1.6V
2
The com m on-mode input range shifts upwards with temper-
a t u r e . At cold temperatures, the part requires an extra 200 mV
of he a d ro om f rom the positive supply, and operation near the
negative supply has more margin. C onve rs e ly, hot temperatures
r e q u i r e l e s s h e a d r o o m f r o m t h e p o s itive supply, but are the worst-
case conditions for input voltages near the negative supply.
For the best performance, source impedance to the REF
terminal should be kept below 2 Ω. As shown in Fig u re 3, the
reference terminal, REF, is at one end of a 50 kΩ resistor.
Additional impedance at the REF terminal adds to this 50 kΩ
resistor and results in amplification of the signal connected to
the positive input. The amplification from the additional RREF
LAYOUT
To ensure optimum performance of the AD8226 at the PCB
level, care must be taken in the design of the board layout.
The AD8226 pins are arranged in a logical manner to aid in
this task.
can be computed by 2(50 kΩ + RREF)/100 kΩ + RREF
.
1
2
3
4
8
7
6
5
+V
–IN
Only the positive signal path is amplified; the negative path
is unaffected. This uneven amplification degrades CMRR.
S
R
G
V
OUT
R
REF
–V
G
INCORRECT
CORRECT
+IN
S
AD8226
TOP VIEW
(Not to Scale)
AD8226
AD8226
Figure 5. Pinout Diagram
REF
REF
V
Common-Mode Rejection Ratio over Frequency
V
+
Poor layout can cause some of the common-mode signals to be
converted to differential signals before re a chi ng the in-a m p .
Such conversions occur when one input path has a frequency
response t h a t i s d i f f e r e n t f r o m t h e o t h e r. To k e e p C M R R a c r o s s
fre q u e n c y h i g h , i nput source impedance and capacitance of each
path should be closely matched. Additional source resistance in
t h e in p u t p a t h ( f o r e x a m p le , f o r i n p u t p r o t e c t i o n ) s h o u l d b e p l a c e d
close to the in-amp inputs, which minimizes their interaction
with parasitic capacitance from the PCB traces.
OP1177
–
Figure 4. Driving the Reference Pin
INPUT VOLTAGE RANGE
The three op amp architecture of the AD8226 applies gain in
the first stage before removing c om m on-m o d e volta ge in the
difference amplifier stage. In addition, the input transistors in
the first stage shift the common mode voltage up one diode
drop (about 650 mV.) Therefore, internal nodes between the
first and second stages (nodes 1 and 2 in Fig u re 3) experience a
combinat ion of gained signal, c om m on-mode signal, and
650 mV. This combined signal can be limited by the voltage
supplies even when the individual input and output signals are
not. Fig u re X X through Fig u re X X show the allowable
com m on-mode input voltage range s for v a riou s output v olta ge s
and supply voltages.
Parasitic capacitance at the gain setting pins can also affect
CMRR over frequency. If the board design has a component
at the gain setting pins (for example, a switch or jumper), the
part should be chosen so that the parasitic capacitance is as
small as possible.
Power Supplies
A stable dc voltage should be used to power the instrumenta-
tion amplifier. Noise on the supply pins can adversely affect
p e r form ance.
The following formulas can also be used to understand how the
reference voltage (VREF), common mode input voltage (VCM),
and differential input voltage (VDIFF) interact. These two
formulas, along with the input range specifications in Table 1
and Table 3, set the boundaries where the part operates with
best performance.
A 0.1 µF capacitor should be placed as close as possible to each
s upp ly pi n . As shown in Fig u re 6, a 10 µF tantalum capacitor
can be used farther away from the part. In most cases, it can be
shared by other precision integrated circuits.
(VDIFF )(GAIN)
−VS − 0.4 V <
+ VCM < + VS − 0.9 V
Rev. PrA | P a g e 10 of 16
Preliminary Technical Data
AD8226
+V
S
R A D I O FR E Q U E NC Y INTERFERENCE (RFI)
RF rectification is often a problem when amplifiers are used in
a p p l i c a t i o n s h a v i n g s t r o n g R F s i g n a l s . T h e d i s t u r b a n c e c a n a p p e a r
a s a s m a l l d c o f f s e t v o l t a g e . H i g h f r e q u e n c y s i g n a l s c a n b e f i l t e r e d
with a low-pass RC network placed at the input of the instru-
mentation amplifier, as shown in Fig u re 8. The f i l t e r l i m i t s t h e
i n p u t s i g n a l b a n d w i d t h , a c c o r d i n g t o t h e f o l l o w i n g r e l a t i o n s h i p :
0.1µF
10µF
+IN
–IN
V
OUT
AD8226
LOAD
REF
1
FilterFrequencyDIFF
=
2πR(2C
D
+ C )
C
0.1µF
10µF
1
–V
S
FilterFrequencyCM
where CD ≥ 10 CC.
=
2πRC
C
Figure 6. Supply Decoupling, REF, and Output Referred to Local Ground
References
+V
S
The output voltage of the AD8226 is developed with respect to
the potential on the reference terminal. Care should be taken to
tie REF to the appropriate local ground.
0.1µF
10µF
C
1nF
C
INPUT BIAS CURRENT RETURN PATH
R
+IN
–IN
4.02kΩ
The input bias current of the AD8226 must have a return path
to g rou nd . When the source, such as a thermocou ple , cann ot
provide a return current path, one should be created, as shown
in Fig u re 7.
V
C
D
10nF
OUT
R
G
AD8226
R
REF
4.02kΩ
C
C
1nF
INCORRECT
+V
CORRECT
+V
0.1µF
10µF
S
S
–V
S
Figure 8. RFI Suppression
AD8226
AD8226
CD a f f e c t s t h e d i f f e r e n c e s i g n a l , a n d C C a f f e c t s t h e c o m m o n -m o d e
signal. Values of R and CC should be chosen to minimize RFI.
M i s m a t c h b e t w e e n t h e R × C C a t t h e p o s i t i v e i n p u t a n d t h e R × C C
at t h e n e g at ive i nput d e g r a d e s t h e C MR R o f t h e A D 8 2 2 6. By using
a value of CD one magnitude larger than CC, the effect of the
mismatch is reduced, and performance is improved.
REF
REF
REF
REF
–V
–V
S
S
TRANSFORMER
TRANSFORMER
+V
+V
S
S
AD8226
AD8226
REF
10MΩ
–V
–V
S
S
THERMOCOUPLE
THERMOCOUPLE
+V
+V
S
S
C
C
C
R
R
1
fHIGH-PASS
=
AD8226
2πRC
AD8226
C
REF
–V
–V
S
S
CAPACITIVELY COUPLED
CAPACITIVELY COUPLED
Figure 7. Creating an IB I A S Path
Rev. PrA | P a g e 11 of 16
AD8226
Preliminary Technical Data
OUTLINE DIMENSIONS
3.20
3.00
2.80
8
1
5
4
5.15
4.90
4.65
3.20
3.00
2.80
PIN 1
0.65 BSC
0.95
0.85
0.75
1.10 MAX
0.80
0.60
0.40
8°
0°
0.15
0.00
0.38
0.22
0.23
0.08
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 9. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-A A
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 10. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
Rev. PrA | P a g e 12 of 16
Preliminary Technical Data
AD8226
ORDERING GUIDE
Model
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
Package Description
PackageOption
RM-8
RM-8
RM-8
R-8
R-8
R-8
RM-8
RM-8
RM-8
R-8
R-8
R-8
RM-8
RM-8
RM-8
R-8
Branding
Y16
Y16
AD8226ARMZ1
AD8226ARMZ-RL1
AD8226ARMZ-R71
AD8226ARZ1
AD8226ARZ-RL1
AD8226ARZ-R71
AD8226BRMZ1
AD8226BRMZ-RL1
AD8226BRMZ-R71
AD8226BRZ1
8-Lead MSOP
8-Lead MSOP, 13" Tape and Reel
8-Lead MSOP, 7" Tape and Reel
8-L e a d SOIC_N
8-L e a d SOIC_N, 13" Tape and Reel
8-L e a d SOIC_N, 7" Tape and Reel
8-Lead MSOP
8-Lead MSOP, 13" Tape and Reel
8-Lead MSOP, 7" Tape and Reel
8-L e a d SOIC_N
8-L e a d SOIC_N, 13" Tape and Reel
8-L e a d SOIC_N, 7" Tape and Reel
8-Lead MSOP
8-Lead MSOP, 13" Tape and Reel
8-Lead MSOP, 7" Tape and Reel
8-L e a d SOIC_N
8-L e a d SOIC_N, 13" Tape and Reel
8-L e a d SOIC_N, 7" Tape and Reel
Y16
Y1M
Y1M
Y1M
AD8226BRZ-RL1
AD8226ARZ-R71
AD8226CRMZ1
AD8226CRMZ-RL1
AD8226CRMZ-R71
AD8226CRZ1
Y1Y
Y1Y
Y1Y
AD8226CRZ-RL1
AD8226CRZ-R71
R-8
R-8
1 Z = RoHS Compliant Part.
Rev. PrA | P a g e 13 of 16
AD8226
NOTES
Preliminary Technical Data
Rev. PrA | P a g e 14 of 16
Preliminary Technical Data
NOTES
AD8226
Rev. PrA | P a g e 15 of 16
AD8226
NOTES
Preliminary Technical Data
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR07036-0-10/08(PrA)
Rev. PrA | Page 16 of 16
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