AD824ARZ-14 [ADI]
Single Supply, Rail-to-Rail Low Power, FET-Input Op Amp; 单电源，轨到轨，低功耗， FET输入运算放大器
| 型号： | AD824ARZ-14 |
| 厂家： | 
ADI |
| 描述： | Single Supply, Rail-to-Rail Low Power, FET-Input Op Amp |
| 文件： | 总16页 (文件大小：1372K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Single Supply, Rail-to-Rail
Low Power, FET-Input Op Amp
AD824
PIN CONFIGURATIONS
FEATURES
Single Supply Operation: 3 V to 30 V
Very Low Input Bias Current: 2 pA
Wide Input Voltage Range
Rail-to-Rail Output Swing
Low Supply Current: 500 ꢀA/Amp
Wide Bandwidth: 2 MHz
Slew Rate: 2 V/ꢀs
16-Lead Epoxy SOIC
(R Suffix)
14-Lead Epoxy SOIC
(R Suffix)
OUT D
–IN D
OUT A
–IN A
+IN A
V+
1
2
3
4
5
6
7
8
16
15
OUT A
–IN A
+IN A
V+
1
2
3
4
5
6
7
14
13
12
11
10
9
OUT D
–IN D
+IN D
V–
14 +IN D
No Phase Reversal
AD824
13
12
V–
AD824
TOP VIEW
+IN B
–IN B
OUT B
+IN C
APPLICATIONS
(Not to Scale)
+IN C
–IN C
OUT C
+IN B
–IN B
OUT B
Photo Diode Preamplifier
Battery Powered Instrumentation
Power Supply Control and Protection
Medical Instrumentation
Remote Sensors
11 –IN C
OUT C
NC
10
9
8
NC
NC = NO CONNECT
Low Voltage Strain Gage Amplifiers
DAC Output Amplifier
GENERAL DESCRIPTION
The FET input combined with laser trimming provides an input
that has extremely low bias currents with guaranteed offsets
below 1 mV. This enables high accuracy designs even with
high source impedances. Precision is combined with low
noise, making the AD824 ideal for use in battery powered
medical equipment.
The AD824 is a quad, FET input, single supply amplifier, fea-
turing rail-to-rail outputs. The combination of FET inputs and
rail-to-rail outputs makes the AD824 useful in a wide variety of
low voltage applications where low input current is a primary
consideration.
The AD824 is guaranteed to operate from a 3 V single supply
up to ±15 V dual supplies. AD824AR-3V Parametric Perfor-
mance at 3 V is fully guaranteed.
Applications for the AD824 include portable medical equipment,
photo diode preamplifiers and high impedance transducer
amplifiers.
Fabricated on ADI’s complementary bipolar process, the AD824
has a unique input stage that allows the input voltage to safely
extend beyond the negative supply and to the positive supply
without any phase inversion or latchup. The output voltage
swings to within 15 mV of the supplies. Capacitive loads to
350 pF can be handled without oscillation.
The ability of the output to swing rail-to-rail enables designers
to build multistage filters in single supply systems and maintain
high signal-to-noise ratios.
The AD824 is specified over the extended industrial (–40∞C to
+85∞C) temperature range and is available in narrow 14-lead
and 16-lead SOIC packages.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
AD824–SPECIFICATIONS
ELECTRICAL SPECIFICATIONS (@ VS = 5.0 V, VCM = 0 V, VOUT = 0.2 V, TA = 25ꢁC unless otherwise noted)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage AD824A
VOS
IB
0.1
1.0
1.5
12
4000
10
mV
mV
pA
pA
pA
pA
V
dB
dB
dB
WʈpF
TMIN to TMAX
Input Bias Current
Input Offset Current
2
300
2
T
MIN to TMAX
TMIN to TMAX
CM = 0 V to 2 V
IOS
300
Input Voltage Range
Common-Mode Rejection Ratio
–0.2
66
60
3.0
CMRR
AVO
V
80
74
VCM = 0 V to 3 V
TMIN to TMAX
60
Input Impedance
Large Signal Voltage Gain
1013ʈ3.3
VO = 0.2 V to 4.0 V
RL = 2 kW
20
50
250
180
40
V/mV
V/mV
V/mV
V/mV
mV/∞C
RL = 10 kW
RL = 100 kW
100
1000
400
2
TMIN to TMAX, RL = 100 kW
Offset Voltage Drift
DVOS/DT
OUTPUT CHARACTERISTICS
Output Voltage High
VOH
ISOURCE = 20 mA
4.975
4.97
4.80
4.75
4.988
4.985
4.85
4.82
15
V
V
V
V
mV
mV
mV
mV
mA
mA
W
TMIN to TMAX
I
T
SOURCE = 2.5 mA
MIN to TMAX
ISINK = 20 mA
MIN to TMAX
SINK = 2.5 mA
Output Voltage Low
VOL
25
30
150
200
T
I
20
120
140
±12
±10
100
TMIN to TMAX
Sink/Source
TMIN to TMAX
f = 1 MHz, AV = 1
Short Circuit Limit
ISC
Open-Loop Impedance
ZOUT
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
ISY
VS = 2.7 V to 12 V
70
66
80
dB
dB
mA
TMIN to TMAX
Supply Current/Amplifier
TMIN to TMAX
500
600
DYNAMIC PERFORMANCE
Slew Rate
Full-Power Bandwidth
Settling Time
Gain Bandwidth Product
Phase Margin
Channel Separation
SR
BWP
tS
GBP
fo
CS
RL = 10 kW, AV = 1
2
V/ms
kHz
ms
MHz
Degrees
dB
1% Distortion, VO = 4 V p-p
VOUT = 0.2 V to 4.5 V, to 0.01%
150
2.5
2
50
–123
No Load
f = 1 kHz, RL = 2 kW
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
Total Harmonic Distortion
en p-p
en
in
0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
2
16
0.8
0.005
mV p-p
nV/÷Hz
fA/÷Hz
%
THD
f = 10 kHz, RL = 0, AV = +1
–2–
REV. C
AD824
ELECTRICAL SPECIFICATIONS (@ VS = ꢂ15.0 V, VOUT = 0 V, TA = 25ꢁC unless otherwise noted)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage AD824A
VOS
IB
0.5
0.6
4
500
25
3
2.5
4.0
35
mV
mV
pA
pA
pA
pA
pA
V
TMIN to TMAX
VCM = 0 V
TMIN to TMAX
Input Bias Current
4000
IB
IOS
VCM = –10 V
Input Offset Current
20
13
TMIN to TMAX
500
Input Voltage Range
Common-Mode Rejection Ratio
–15
70
66
CMRR
AVO
VCM = –15 V to 13 V
TMIN to TMAX
80
dB
dB
WʈpF
Input Impedance
Large Signal Voltage Gain
1013ʈ3.3
Vo = –10 V to +10 V;
RL = 2 kW
12
50
300
200
50
V/mV
V/mV
V/mV
V/mV
mV/∞C
RL = 10 kW
RL = 100 kW
200
2000
1000
2
TMIN to TMAX, RL = 100 kW
Offset Voltage Drift
DVOS/DT
OUTPUT CHARACTERISTICS
Output Voltage High
VOH
ISOURCE = 20 mA
MIN to TMAX
SOURCE = 2.5 mA
14.975
14.970
14.80
14.988
14.985
14.85
V
V
V
T
I
TMIN to TMAX
14.75
14.82
V
Output Voltage Low
VOL
ISINK = 20 mA
–14.985 –14.975
V
V
V
V
mA
W
T
MIN to TMAX
–14.98
–14.88
–14.86
±20
–14.97
–14.85
–14.8
ISINK = 2.5 mA
MIN to TMAX
T
Short Circuit Limit
Open-Loop Impedance
ISC
ZOUT
Sink/Source, TMIN to TMAX
f = 1 MHz, AV = 1
±8
100
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
ISY
VS = 2.7 V to 15 V
70
68
80
dB
dB
mA
mA
TMIN to TMAX
Supply Current/Amplifier
VO = 0 V
TMIN to TMAX
560
625
675
DYNAMIC PERFORMANCE
Slew Rate
Full-Power Bandwidth
Settling Time
Gain Bandwidth Product
Phase Margin
SR
BWP
tS
GBP
fo
CS
RL = 10 kW, AV = 1
2
33
6
2
50
–123
V/ms
kHz
ms
MHz
Degrees
dB
1% Distortion, VO = 20 V p-p
VOUT = 0 V to 10 V, to 0.01%
Channel Separation
f = 1 kHz, RL =2 kW
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
Total Harmonic Distortion
en p-p
en
in
0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
f =10 kHz, VO = 3 V rms,
RL = 10 kW
2
16
1.1
mV p-p
nV/÷Hz
fA/÷Hz
THD
0.005
%
–3–
REV. C
AD824–SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
(@ VS = 3.0 V, VCM = 0 V, VOUT = 0.2 V, TA = 25ꢁC unless otherwise noted)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage AD824A -3 V
VOS
IB
0.2
1.0
1.5
12
4000
10
mV
mV
pA
pA
pA
pA
V
TMIN to TMAX
TMIN to TMAX
TMIN to TMAX
Input Bias Current
Input Offset Current
2
250
2
IOS
250
Input Voltage Range
0
1
Common-Mode Rejection Ratio
CMRR
AVO
VCM = 0 V to 1 V
TMIN to TMAX
58
56
74
dB
dB
WʈpF
Input Impedance
Large Signal Voltage Gain
1013ʈ3.3
VO = 0.2 V to 2.0 V
RL = 2 kW
10
30
180
90
20
65
500
250
2
V/mV
V/mV
V/mV
V/mV
mV/∞C
RL = 10 kW
RL = 100 kW
TMIN to TMAX, RL = 100 kW
Offset Voltage Drift
DVOS/DT
OUTPUT CHARACTERISTICS
Output Voltage High
VOH
ISOURCE = 20 mA
2.975
2.97
2.8
2.988
2.985
2.85
2.82
15
V
V
V
V
mV
mV
mV
mV
mA
mA
W
TMIN to TMAX
ISOURCE = 2.5 mA
MIN to TMAX
T
2.75
Output Voltage Low
VOL
ISINK = 20 mA
TMIN to TMAX
25
30
150
200
20
I
T
SINK = 2.5 mA
MIN to TMAX
120
140
±8
±6
100
Short Circuit Limit
ISC
ISC
ZOUT
Sink/Source
Sink/Source, TMIN to TMAX
f = 1 MHz, AV = 1
Open-Loop Impedance
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
ISY
VS = 2.7 V to 12 V,
TMIN to TMAX
VO = 0.2 V, TMIN to TMAX
70
66
dB
dB
mA
Supply Current/Amplifier
500
600
DYNAMIC PERFORMANCE
Slew Rate
Full-Power Bandwidth
Settling Time
Gain Bandwidth Product
Phase Margin
SR
BWP
tS
GBP
fo
CS
RL =10 kW, AV = 1
2
300
2
2
50
–123
V/ms
kHz
ms
MHz
Degrees
dB
1% Distortion, VO = 2 V p-p
VOUT = 0.2 V to 2.5 V, to 0.01%
Channel Separation
f = 1 kHz, RL = 2 kW
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
Total Harmonic Distortion
en p-p
en
in
0.1 Hz to 10 Hz
f = 1 kHz
2
16
0.8
0.01
mV p-p
nV/÷Hz
fA/÷Hz
%
THD
f = 10 kHz, RL = 0, AV = +1
–4–
REV. C
AD824
(@ V = 5.0 V, VCM = 0 V, TA = 25ꢁC unless otherwise noted)
WAFER TEST LIMITS
S
Parameter
Symbol
Conditions
Limit
Unit
Offset Voltage
Input Bias Current
VOS
IB
1.0
12
mV max
pA max
Input Offset Current
IOS
20
pA
Input Voltage Range
VCM
CMRR
PSRR
AVO
VOH
VOL
ISY
–0.2 to 3.0
66
70
15
4.975
25
600
V min
dB min
mV/V
V/mV min
V min
mV max
mA max
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Large Signal Voltage Gain
Output Voltage High
Output Voltage Low
VCM = 0 V to 2 V
V = + 2.7 V to +12 V
RL = 2 kW
ISOURCE = 20 mA
ISINK = 20 mA
Supply Current/Amplifier
VO = 0 V, RL = •
NOTE
Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for
standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
ABSOLUTE MAXIMUM RATINGS1
V
CC
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . –VS – 0.2 V to +VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ±30 V
Output Short Circuit Duration to GND . . . . . . . . . Indefinite
Storage Temperature Range
R-14, R-16 Packages . . . . . . . . . . . . . . . . –65∞C to +150∞C
Operating Temperature Range
AD824A . . . . . . . . . . . . . . . . . . . . . . . . . . . –40∞C to +85∞C
Junction Temperature Range
R-14, R-16 Packages . . . . . . . . . . . . . . . . –65∞C to +150∞C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300∞C
I5
I6
Q18
Q29
R1
J1
R2
R9
Q21 Q27
Q4
Q6
C3
Q5
J2
Q20
Q23
Q19
Q22
+IN
R7
Q7
C2
C4
R13
–IN
R15
V
OUT
2
Q24 Q25
Package Type
qJA
qJC
Unit
Q8
C1
14-Lead SOIC (R)
16-Lead SOIC (R)
120
92
36
27
∞C/W
∞C/W
Q2
Q3
Q31
Q28
NOTES
Q26
R12
I1
R14
I2
R17
1 Absolute maximum ratings apply to packaged parts unless otherwise noted.
2 qJA is specified for the worst case conditions, i.e., qJA is specified for device in socket
for P-DIP packages; qJA is specified for device soldered in circuit board for SOIC
package.
I3
V
I4
EE
Figure 1. Simplified Schematic of 1/4 AD824
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Option
Model
AD824AR-14
AD824AR-14-3V –40∞C to +85∞C 14-Pin SOIC
AD824AR-16
–40∞C to +85∞C 14-Pin SOIC
R-14
R-14
R-16
–40∞C to +85∞C 16-Pin SOIC
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD824 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. C
–5–
AD824–Typical Performance Characteristics
V
=
15V
V
= 5V
S
80
60
40
20
0
S
80
60
40
20
0
NO LOAD
NO LOAD
45
45
90
90
135
180
135
180
100
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
10M
100
90
100
90
10
10
0%
0%
50mV
1µs
50mV
1µs
TPC 1. Open-Loop Gain/Phase and Small Signal
Response, VS = ±15 V, No Load
TPC 3. Open-Loop Gain/Phase and Small Signal
Response, VS = 5 V, No Load
V
=
15V
V
= 5V
= 220pF
S
L
80
60
40
20
0
60
40
20
S
L
C
= 100pF
C
45
90
45
135
180
90
0
135
180
–20
100
1k
10k
100k
1M
10M
1k
10k
100k
1M
10M
100
90
100
90
10
10
0%
0%
50mV
1µs
50mV
1µs
TPC 2. Open-Loop Gain/Phase and Small Signal
Response, VS = ±15 V, CL = 100 pF
TPC 4. Open-Loop Gain/Phase and Small Signal
Response, VS = 5 V, CL = 220 pF
–6–
REV. C
AD824
V
= 3V
60
40
20
S
NO LOAD
t
µs
9.950
100
90
45
90
135
180
0
10
0%
–20
5V
2µs
1k
10k
100k
1M
10M
t
µs
10.810
100
90
100
90
10
10
0%
0%
50mV
1µs
5V
2µs
TPC 5. Open-Loop Gain/Phase and Small Signal
Response, VS = 3 V, No Load
TPC 7. Slew Rate, RL = 10k
V
= 3V
= 220pF
60
40
20
S
L
C
100
90
45
V
OUT
90
10
135
180
0%
0
100µs
5V
–20
TPC 8. Phase Reversal with Inputs Exceeding Supply by 1 V
1k
10k
100k
1M
10M
0.8
0.7
0.6
100
90
0.5
SOURCE
0.4
0.3
0.2
10
0%
SINK
0.1
50mV
1µs
0
1ꢀ
5ꢀ
10ꢀ
50ꢀ 100ꢀ
500ꢀ
1m
5m
10m
LOAD CURRENT – A
TPC 6. Open-Loop Gain/Phase and Small Signal
Response, VS = 3 V, CL = 220 pF
TPC 9. Output Voltage to Supply Rail vs. Sink and Source
Load Currents
REV. C
–7–
AD824
14
12
10
8
COUNT = 60
3V
V
S
15V
60
40
20
6
4
2
5
10
15
20
FREQUENCY – kHz
0
–2.5 –2.0 –1.5 –1.0 –0.5
0
0.5 1.0 1.5 2.0
2.5
OFFSET VOLTAGE DRIFT
TPC 10. Voltage Noise Density
TPC 13. TC VOS Distribution, –55∞C to +125∞C, VS = 5, 0
150
0.1
V
= 5, 0
S
R
A
= 0
= +1
L
V
125
100
75
V
= +3
= +5
S
0.010
0.001
V
S
50
25
V
= 15
S
0
0.0001
–25
20
100
1k
FREQUENCY – Hz
10k 20k
–60 –40 –20
0
20
40
60
80 100 120
140
TEMPERATURE –
C
TPC 11. Total Harmonic Distortion
TPC 14. Input Offset Current vs. Temperature
280
240
200
160
120
80
100k
V
= 5, 0
COUNT = 860
S
10k
1k
100
10
1
40
0
–0.5 –0.4 –0.3 –0.2 –0.1
0
0.1 0.2 0.3 0.4 0.5
20
40
60
80
100
C
120
140
OFFSET VOLTAGE – mV
TEMPERATURE –
TPC 12. Input Offset Distribution, VS = 5, 0
TPC 15. Input Bias Current vs. Temperature
–8–
REV. C
AD824
120
100
80
60
40
20
0
1k
100
10
1
10
100
1k
10k
100k
1M
10M
1
10
100
1k
10k
100k
FREQUENCY – Hz
FREQUENCY – Hz
TPC 16. Common-Mode Rejection vs. Frequency
TPC 19. Input Voltage Noise Spectral Density vs.
Frequency
–40
–60
120
100
80
60
40
20
0
–80
–100
–120
100
1k
10k
FREQUENCY – Hz
100k
10
100
1k
10k
100k
1M
10M
FREQUENCY – Hz
TPC 17. THD vs. Frequency, 3 V rms
TPC 20. Power Supply Rejection vs. Frequency
100
80
60
40
20
100
80
60
40
20
0
30
25
20
15
10
5
15V
3, 0V
0
–20
–20
0
10
100
1k
10k
100k
1M
10M
1k
3k
10k
30k
100k
300k
1M
FREQUENCY – Hz
INPUT FREQUENCY – Hz
TPC 18. Open-Loop Gain and Phase vs. Frequency
TPC 21. Large Signal Frequency Response
REV. C
–9–
AD824
–80
–90
–100
–110
–120
–130
–140
5V
5µs
100
90
1 TO 4
1 TO 2
10
1 TO 3
0%
10
100
1k
FREQUENCY – Hz
10k
100k
TPC 22. Crosstalk vs. Frequency
TPC 25. Large Signal Response
10k
1k
100
10
1
2750
2500
2250
2000
1750
1500
1250
1000
V
= 15V
S
V
= 3, 0
S
.1
.01
10
100
1k
10k
100k
1M
10M
–60 –40 –20
0
20
40
60
80 100 120
140
FREQUENCY – Hz
TEMPERATURE –
C
TPC 23. Output Impedance vs. Frequency, Gain = +1
TPC 26. Supply Current vs. Temperature
1000
100
10
V
V
=
15V
S
S
= 3, 0
20mV
500ns
100
90
V
– V
S
OL
V
– V
OH
S
10
0%
0
0.01
0.10
1.0
10.0
LOAD CURRENT – mA
TPC 24. Small Signal Response, Unity Gain Follower,
TPC 27. Output Saturation Voltage
10kʈ100 pF Load
–10–
REV. C
AD824
APPLICATION NOTES
A current-limiting resistor should be used in series with the
input of the AD824 if there is a possibility of the input voltage
exceeding the positive supply by more than 300 mV or if an
input voltage will be applied to the AD824 when ±VS = 0. The
amplifier will be damaged if left in that condition for more than
10 seconds. A 1 kW resistor allows the amplifier to withstand up
to 10 V of continuous overvoltage and increases the input volt-
age noise by a negligible amount.
INPUT CHARACTERISTICS
In the AD824, n-channel JFETs are used to provide a low
offset, low noise, high impedance input stage. Minimum input
common-mode voltage extends from 0.2 V below –VS to 1 V less
than +VS. Driving the input voltage closer to the positive rail will
cause a loss of amplifier bandwidth.
The AD824 does not exhibit phase reversal for input voltages
up to and including +VS. Figure 2a shows the response of an
AD824 voltage follower to a 0 V to 5 V (+VS) square wave input.
The input and output are superimposed. The output tracks the
input up to +VS without phase reversal. The reduced bandwidth
above a 4 V input causes the rounding of the output wave form.
For input voltages greater than +VS, a resistor in series with
the AD824’s noninverting input will prevent phase reversal at
the expense of greater input voltage noise. This is illustrated in
Figure 2b.
Input voltages less than –VS are a completely different story.
The amplifier can safely withstand input voltages 20 V below
the minus supply voltage as long as the total voltage from the
positive supply to the input terminal is less than 36 V. In addition,
the input stage typically maintains picoamp level input currents
across that input voltage range.
OUTPUT CHARACTERISTICS
The AD824’s unique bipolar rail-to-rail output stage swings
within 15 mV of the positive and negative supply voltages. The
AD824’s approximate output saturation resistance is 100 W for
both sourcing and sinking. This can be used to estimate output
saturation voltage when driving heavier current loads. For
instance, the saturation voltage will be 0.5 V from either supply
with a 5 mA current load.
1V
2µs
100
90
For load resistances over 20 kW, the AD824’s input error
voltage is virtually unchanged until the output voltage is driven
to 180 mV of either supply.
10
GND
0%
1V
1V
If the AD824’s output is overdriven so as to saturate either of
the output devices, the amplifier will recover within 2 ms of its
input returning to the amplifier’s linear operating region.
(a)
Direct capacitive loads will interact with the amplifier’s effective
output impedance to form an additional pole in the amplifier’s
feedback loop, which can cause excessive peaking on the pulse
response or loss of stability. Worst case is when the amplifier is
used as a unity gain follower. TPC 4 and 6 show the AD824’s
pulse response as a unity gain follower driving 220 pF. Configu-
rations with less loop gain, and as a result less loop bandwidth,
will be much less sensitive to capacitance load effects. Noise
gain is the inverse of the feedback attenuation factor provided
by the feedback network in use.
10µs
1V
100
90
+V
S
10
GND 0%
1V
(b)
Figure 3 shows a method for extending capacitance load drive
capability for a unity gain follower. With these component val-
ues, the circuit will drive 5,000 pF with a 10% overshoot.
+5V
R
P
V
IN
V
OUT
+V
S
0.01ꢀF
8
100ꢃ
1/4
V
IN
Figure 2. (a) Response with RP = 0; VIN from 0 to +VS
(b) VIN = 0 to + VS + 200 m V
VOUT = 0 to + VS
AD824
V
OUT
0.01ꢀF
4
C
L
–V
S
RP = 49.9 kW
20pF
Since the input stage uses n-channel JFETs, input current
during normal operation is positive; the current flows out from
the input terminals. If the input voltage is driven more positive
than +VS – 0.4 V, the input current will reverse direction as
internal device junctions become forward biased. This is
illustrated in TPC 8.
20kꢃ
Figure 3. Extending Unity Gain Follower Capacitive Load
Capability Beyond 350 pF
REV. C
–11–
AD824
APPLICATIONS
Table I. AD824 In Amp Performance
VS = 3 V, 0 V VS = ꢂ5 V
74 dB 80 dB
Single Supply Voltage-to-Frequency Converter
The circuit shown in Figure 4 uses the AD824 to drive a low
power timer, which produces a stable pulse of width t1. The
positive going output pulse is integrated by R1-C1 and used as
one input to the AD824, which is connected as a differential
integrator. The other input (nonloading) is the unknown voltage,
VIN. The AD824 output drives the timer trigger input, closing
the overall feedback loop.
Parameters
CMRR
Common-Mode
Voltage Range
3 dB BW, G = 10
G = 100
–0.2 V to +2 V –5.2 V to +4 V
180 kHz
18 kHz
180 kHz
18 kHz
tSETTLING
2 V Step (VS = 0 V, 3 V)
5 V (VS = ±5 V)
Noise @ f = 1 kHz, G = 10
2 ms
10V
U4
5 ms
270 nV/÷Hz
2.2 mV/÷Hz
REF02
C5
270 nV/÷Hz
0.1ꢀF
2
V
= 5V
G = 100 2.2 mV/÷Hz
REF
6
5
CMOS
R
10kꢃ
**
OUT2
OUT1
3
SCALE
74HCO4
C3
0.1ꢀF
5µs
4
U3B
U3A
2
4
3
1
100
90
U2
CMOS 555
0.01ꢀF, 2%
4
8
R2
U1
R3*
C1
R
V+
499kꢃ, 1%
116kꢃ
6
THR
OUT
3
5
1/4
2
7
TR
10
AD824
R1
CV
0%
DIS
499kꢃ, 1%
C6
390pF
5%
1V
GND
0VTO 2.5V
1
C4
FULL SCALE
(NPO)
C2
0.1ꢀF
Figure 5a. Pulse Response of In Amp to a 500 mV p-p
Input Signal; VS = 5 V, 0 V; Gain = 10
0.01ꢀF, 2%
NOTES
=V /(VREF ꢄ t1), t1 = 1.1 ꢄ R3 ꢄ C6
f
OUT
IN
= 25kHz f AS SHOWN.
S
R1
R2
R3
R4
R5
R6
OHMTEK
* = 1% METAL FILM, <50ppm/ꢁC TC
** = 10%, 20T FILM, <100ppm/ꢁC TC
PART # 1043
V
90kꢃ
9kꢃ
1kꢃ
1kꢃ
9kꢃ
90kꢃ
REF
t1 = 33ꢀs FOR f
= 20kHz @V = 2.0V
IN
OUT
G = 10
G = 100
G = 100
G = 10
Figure 4. Single Supply Voltage-to-Frequency Converter
+V
S
Typical AD824 bias currents of 2 pA allow megaohm-range
source impedances with negligible dc errors. Linearity errors on
the order of 0.01% full scale can be achieved with this circuit.
This performance is obtained with a 5 V single supply, which
delivers less than 3 mA to the entire circuit.
0.1ꢀF
2
3
6
1/4
1
1/4
AD824
7
AD824
R
P
V
V
5
OUT
IN1
11
1kꢃ
R
P
Single Supply Programmable Gain Instrumentation Amplifier
The AD824 can be configured as a single supply instrumenta-
tion amplifier that is able to operate from single supplies down
to 5 V or dual supplies up to ±15 V. AD824 FET inputs’ 2 pA
bias currents minimize offset errors caused by high unbalanced
source impedances.
V
IN2
1kꢃ
R6
R4 + R5
(G = 10)V
= (V
IN1
–V ) (1+
IN2
) +V
REF
OUT
R5 + R6
R4
(G = 100)V
= (V
IN1
–V ) (1+
IN2
) +V
REF
OUT
FOR R1 = R6, R2 = R5 AND R3 = R4
An array of precision thin-film resistors sets the in amp gain to
be either 10 or 100. These resistors are laser-trimmed to ratio
match to 0.01% and have a maximum differential TC of 5 ppm/∞C.
Figure 5b. A Single Supply Programmable
Instrumentation Amplifier
–12–
REV. C
AD824
3 Volt, Single Supply Stereo Headphone Driver
The AD824 exhibits good current drive and THD+N perfor-
mance, even at 3 V single supplies. At 1 kHz, total harmonic
distortion plus noise (THD+N) equals –62 dB (0.079%) for a
300 mV p-p output signal. This is comparable to other single
supply op amps that consume more power and cannot run on 3 V
power supplies.
of 4.5 V can be used to drive an A/D converter front end. The
other half of the AD824 is configured as a unity-gain inverter
and generates the other bridge input of –4.5 V. Resistors R1 and
R2 provide a constant current for bridge excitation. The AD620
low power instrumentation amplifier is used to condition the
differential output voltage of the bridge. The gain of the AD620
is programmed using an external resistor RG and determined by:
In Figure 6, each channel’s input signal is coupled via a 1 mF
Mylar capacitor. Resistor dividers set the dc voltage at the
noninverting inputs so that the output voltage is midway between
the power supplies (1.5 V). The gain is 1.5. Each half of the
AD824 can then be used to drive a headphone channel. A 5 Hz
high-pass filter is realized by the 500 mF capacitors and the
headphones, which can be modeled as 32 ohm load resistors to
ground. This ensures that all signals in the audio frequency
range (20 Hz–20 kHz) are delivered to the headphones.
49.4 kW
RG
G =
+ 1
A 3.3 V/5 V Precision Sample-and-Hold Amplifier
In battery-powered applications, low supply voltage operational
amplifiers are required for low power consumption. Also, low
supply voltage applications limit the signal range in precision
analog circuitry. Circuits like the sample-and-hold circuit shown
in Figure 8, illustrate techniques for designing precision analog
circuitry in low supply voltage applications. To maintain high
signal-to-noise ratios (SNRs) in a low supply voltage application
requires the use of rail-to-rail, input/output operational amplifi-
ers. This design highlights the ability of the AD824 to operate
rail-to-rail from a single 3 V/5 V supply, with the advantages of
high input impedance. The AD824, a quad JFET-input op amp,
is well suited to S/H circuits due to its low input bias currents
(3 pA, typical) and high input impedances (3 ¥ 1013 W, typical).
The AD824 also exhibits very low supply currents so the total
supply current in this circuit is less than 2.5 mA.
3V
0.1ꢀF
0.1ꢀF
95.3kꢃ
1ꢀF
CHANNEL 1
1/4
MYLAR
47.5kꢃ AD824
500ꢀF
95.3kꢃ
L
4.99kꢃ
10kꢃ
10kꢃ
HEADPHONES
32ꢃ IMPEDANCE
3.3/5V
R1
3.3/5V
R
0.1ꢀF
4.99kꢃ
AD824A
50kꢃ
3
4
1
1/4
47.5kꢃ
1ꢀF
A1
FALSE GROUND (FG)
AD824
2
R2
50kꢃ
500ꢀF
CHANNEL 2
11
R4
2kꢃ
MYLAR
3.3/5V
13
Figure 6. 3 Volt Single Supply Stereo Headphone Driver
ADG513
FG
15
14
Low Dropout Bipolar Bridge Driver
R5
16
9
The AD824 can be used for driving a 350 ohm Wheatstone
bridge. Figure 7 shows one half of the AD824 being used to
buffer the AD589—a 1.235 V low power reference. The output
2kꢃ
11
10
AD824B
CH
500pF
5
7
2
3
A2
+V
S
6
1
8
10
9
\
49.9kꢃ
+1.235V
8
R1
A3
+
–
20ꢃ
V
OUT
7
4
6
5
1/4
TO A/D CONVERTER
REFERENCE INPUT
AD824C
AD824
AD589
C
AD824D
10kꢃ
26.4kꢃ, 1%
350ꢃ
FG
14
500pF
+V
S
12
1%
A4
SAMPLE/
HOLD
FG
350ꢃ
3
2
13
7
6
AD824
R
G
350ꢃ
350ꢃ
5
Figure 8. 3.3 V/5.5 V Precision Sample and Hold
4
10kꢃ
V
In many single supply applications, the use of a false ground
generator is required. In this circuit, R1 and R2 divide the
supply voltage symmetrically, creating the false ground voltage
at one-half the supply. Amplifier A1 then buffers this voltage
creating a low impedance output drive. The S/H circuit is con-
figured in an inverting topology centered around this false
ground level.
REF
–V
S
1%
10kꢃ
1/4
1%
+V
+5V
–5V
S
–4.5V
AD824
1ꢀF
1ꢀF
0.1ꢀF
GND
0.1ꢀF
–V
R2
20ꢃ
–V
S
S
Figure 7. Low Dropout Bipolar Bridge Driver
REV. C
–13–
AD824
A design consideration in sample-and-hold circuits is voltage
droop at the output caused by op amp bias and switch leakage
currents. By choosing a JFET op amp and a low leakage CMOS
switch, this design minimizes droop rate error to better than
0.1 mV/ms in this circuit. Higher values of CH will yield a lower
droop rate. For best performance, CH and C2 should be poly-
styrene, polypropylene or Teflon capacitors. These types of
capacitors exhibit low leakage and low dielectric absorption. Addi-
tionally, 1% metal film resistors were used throughout the design.
less than 2 mV over the entire 0 V to 3.3 V/5 V signal range.
Another method of reducing pedestal error is to reduce the pulse
amplitude applied to the control pins. In order to control the
ADG513, only 2.4 V are required for the “ON” state and
0.8 V for the “OFF” state. If possible, use an input control
signal whose amplitude ranges from 0.8 V to 2.4 V instead of a
full range 0 V to 3.3 V/5 V for minimum pedestal error.
Other circuit features include an acquisition time of less than
3 ms to 1%; reducing CH and C2 will speed up the acquisition
time further, but an increased pedestal error will result. Settling
time is less than 300 ns to 1%, and the sample-mode signal BW
is 80 kHz.
In the sample mode, SW1 and SW4 are closed, and the output
is VOUT = –VIN. The purpose of SW4, which operates in parallel
with SW1, is to reduce the pedestal, or hold step, error by
injecting the same amount of charge into the noninverting input
of A3 that SW1 injects into the inverting input of A3. This
creates a common-mode voltage across the inputs of A3 and is
then rejected by the CMR of A3; otherwise, the charge injection
from SW1 would create a differential voltage step error that
would appear at VOUT. The pedestal error for this circuit is
The ADG513 was chosen for its ability to work with 3 V/5 V
supplies and for having normallyopen and normallyclosed preci-
sion CMOS switches on a dielectrically isolated process. SW2 is
not required in this circuit; however, it was used in parallel with
SW3 to provide a lower RON analog switch.
–14–
REV. C
AD824
* AD824 SPICE Macro-model
9/94, Rev. A *
G15 98
(9,98) 1E-6
*
* OUTPUT STAGE
*
ES 26
(18,98) 1
RS 26
500
IB1 98
2.404E-3
IB2 23
2.404E-3
D10 21
DY
D11 98
DY
C16 20
2E-12
C17 24
2E-12
DQ197
DQ
Q2 20
22 NPN
Q3 24
22 PNP
DQ224
DQ
Q5 25
97 PNP 20
Q6 25
51 NPN 20
VP 96
0
18
ARG/ADI
*
* Copyright 1994 by Analog Devices, Inc.
*
98
22
21
98
98
23
25
25
20
21
23
51
20
24
97
52
0
* Refer to “README.DOC” file for License Statement.
Use of this model indicates your acceptance with
the terms and provisions in the License Statement. *
* Node assignments
*
noninverting input
| inverting input
| | positive supply
*
*
*
| |
| |
| |
|
|
|
negative supply
|
|
*
output
|
*
.SUBCKT AD824
1 2 99 50 25
*
* INPUT STAGE & POLE AT 3.1 MHz
*
R3
5
99
99
2
1.193E3
R4
6
1.193E3
CIN 1
4E-12
C2
5
6
19.229E-12
I1 4 50
IOS 1
1E-12
108E-6
2
EOS 7
1
5
6
POLY(1) (12,98) 100E-6 1
J1 4 2
JX
J2 4 7
VN 51
0
JX
EP 96
(99,0) 1
EN 52
(50,0) 1
R25 30
5E6
R26 30
5E6
FSY1
0 VP 1
FSY2
50VN 1
DC125
DX
DC250
DX
*
*
* GAIN STAGE & DOMINANT POLE
*
EREF
0 (30,0) 1
0
98
98
25
9
99
50
99
0
R5
2.205E6
C3
9
9
54E-12
G1 98
(6,5) 0.838E-3
V1
-1
8
98
10
10
9
99
25
V2 98
-1
D1
DX
D2
DX
*
9
* MODELS USED
*
8
.MODEL JX NJF(BETA=3.2526E-3 VTO=-2.000 IS=2E-12) .MODEL
NPN NPN(BF=120 VAF=150 VAR=15 RB=2E3
+ RE=4 RC=550 IS=1E-16)
.MODEL PNP PNP(BF=120 VAF=150 VAR=15 RB=2E3 + RE=4
RC=750 IS=1E-16)
* COMMON-MODE GAIN NETWORK WITH ZERO AT 1 kHz *
R21 11
1E6
R22 12
100
C14 11
159E-12
E13 11
12
98
12
98
.MODEL DX D(IS=1E-15)
.MODEL DY D()
.MODEL DQ D(IS=1E-16)
.ENDS AD824
POLY(2) (2,98) (1,98) 0 0.5 0.5
*
* POLE AT 10 MHz
*
R23 18
1E6
98
98
C15 18
15.9E-15
REV. C
–15–
AD824
OUTLINE DIMENSIONS
14-Lead Standard Small Outline Package [SOIC]
16-Lead Standard Small Outline Package [SOIC]
Narrow Body
(R-14)
Dimensions shown in millimeters and (inches)
Wide Body
(R-16)
Dimensions shown in millimeters and (inches)
8.75 (0.3445)
8.55 (0.3366)
10.50 (0.4134)
10.10 (0.3976)
14
1
8
7
16
1
9
8
4.00 (0.1575)
3.80 (0.1496)
6.20 (0.2441)
5.80 (0.2283)
7.60 (0.2992)
7.40 (0.2913)
10.65 (0.4193)
10.00 (0.3937)
1.75 (0.0689)
1.35 (0.0531)
1.27 (0.0500)
BSC
0.50 (0.0197)
0.25 (0.0098)
؋
45؇ 0.25 (0.0098)
0.10 (0.0039)
8؇
0؇
1.27 (0.0500)
0.75 (0.0295)
0.25 (0.0098)
2.65 (0.1043)
2.35 (0.0925)
0.51 (0.0201)
0.33 (0.0130)
BSC
SEATING
PLANE
؋
45؇ 1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.19 (0.0075)
COPLANARITY
0.10
0.30 (0.0118)
0.10 (0.0039)
COMPLIANT TO JEDEC STANDARDS MS-012AB
8؇
0؇
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
0.51 (0.0201)
0.33 (0.0130)
SEATING
PLANE
1.27 (0.0500)
0.40 (0.0157)
0.32 (0.0126)
0.23 (0.0091)
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MS-013AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Revision History
Location
Page
2/03–Data Sheet changed from REV. B to REV. C.
Deleted N Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
Edits to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Edits to Figure 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Edits to Figure 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1/02–Data Sheet changed from REV. A to REV. B.
Edits to ELECTRICAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2, 3
Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Deleted DICE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
–16–
REV. C
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