AD826ANZ [ADI]
High-Speed, Low-Power Dual Operational Amplifier; 高速，低功耗双路运算放大器
| 型号： | AD826ANZ |
| 厂家： | 
ADI |
| 描述： | High-Speed, Low-Power Dual Operational Amplifier |
| 文件： | 总15页 (文件大小：731K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High-Speed, Low-Power
Dual Operational Amplifier
a
AD826
FEATURES
CONNECTION DIAGRAM
8-Lead Plastic Mini-DIP and SO Package
High Speed:
50 MHz Unity Gain Bandwidth
350 V/ꢀs Slew Rate
70 ns Settling Time to 0.01%
Low Power:
7.5 mA Max Power Supply Current Per Amp
Easy to Use:
Drives Unlimited Capacitive Loads
50 mA Min Output Current Per Amplifier
Specified for +5 V, ꢁ5 V and ꢁ15 V Operation
2.0 V p-p Output Swing into a 150 ꢂ Load
(VS = +5 V)
8
OUT1
1
2
3
V+
7
OUT2
–IN2
+IN2
–IN1
+IN1
6
5
V–
4
AD826
Good Video Performance
Differential Gain & Phase Error of 0.07% & 0.11ꢃ
Excellent DC Performance:
2.0 mV Max Input Offset Voltage
The AD826 features high output current drive capability of
50 mA min per amp, and is able to drive unlimited capacitive
loads. With a low power supply current of 15 mA max for both
amplifiers, the AD826 is a true general purpose operational
amplifier.
APPLICATIONS
Unity Gain ADC/DAC Buffer
Cable Drivers
8- and 10-Bit Data Acquisition Systems
Video Line Driver
Active Filters
The AD826 is ideal for power sensitive applications such as video
cameras and portable instrumentation. The AD826 can operate
from a single +5 V supply, while still achieving 25 MHz of band-
width. Furthermore the AD826 is fully specified from a single
+5 V to 15 V power supplies.
PRODUCT DESCRIPTION
The AD826 is a dual, high speed voltage feedback op amp. It
is ideal for use in applications which require unity gain stability
and high output drive capability, such as buffering and cable
driving. The 50 MHz bandwidth and 350 V/µs slew rate make
the AD826 useful in many high speed applications including:
video, CATV, copiers, LCDs, image scanners and fax machines.
The AD826 excels as an ADC/DAC buffer or active filter in
data acquisition systems and achieves a settling time of 70 ns
to 0.01%, with a low input offset voltage of 2 mV max. The
AD826 is available in small 8-lead plastic mini-DIP and SO
packages.
1kꢂ
ꢄV
S
500ns
5V
3.3ꢀF
100
90
C
= 100pF
L
0.01ꢀF
V
IN 1kꢂ
50ꢂ
2
HP PULSE
GENERATOR
TEKTRONIX
P6201 FET
PROBE
TEKTRONIX
7A24 FET
PREAMP
1/2
AD826
1
V
OUT
3
10
C
= 1000pF
L
0.01ꢀF
3.3ꢀF
0%
C
L
5V
–V
S
Driving a Large Capacitive Load
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: © Analog Devices, Inc.,
781/461-3113
2010
(@ T = +25ꢃC, unless otherwise noted)
AD826–SPECIFICATIONS
A
Parameter
Conditions
VS
Min Typ Max
Unit
DYNAMIC PERFORMANCE
Unity Gain Bandwidth
5 V
30
45
25
10
25
10
35
50
29
20
55
20
MHz
MHz
MHz
MHz
MHz
MHz
15 V
0, +5 V
5 V
15 V
0, +5 V
Bandwidth for 0.1 dB Flatness
Full Power Bandwidth1
Gain = +1
VOUT = 5 V p-p
R
V
R
R
LOAD = 500 Ω
OUT = 20 V p-p
LOAD = 1 kΩ
LOAD = 1 kΩ
5 V
15.9
MHz
15 V
5 V
15 V
0, +5 V
5 V
15 V
5 V
5.6
250
350
200
45
45
70
MHz
V/µs
V/µs
V/µs
ns
ns
ns
Slew Rate
200
300
150
Gain = –1
Settling Time to 0.1%
to 0.01%
–2.5 V to +2.5 V
0 V–10 V Step, AV = –1
–2.5 V to +2.5 V
0 V–10 V Step, AV = –1
15 V
70
ns
NOISE/HARMONIC PERFORMANCE
Total Harmonic Distortion
Input Voltage Noise
Input Current Noise
Differential Gain Error
(R1 = 150 Ω)
FC = 1 MHz
f = 10 kHz
f = 10 kHz
NTSC
15 V
5 V, 15 V
5 V, 15 V
15 V
5 V
0, +5 V
–78
15
1.5
0.07 0.1
0.12 0.15
0.15
dB
nV/√Hz
pA/√Hz
%
%
%
Gain = +2
Differential Phase Error
(R1 = 150 Ω)
NTSC
Gain = +2
15 V
5 V
0, +5 V
0.11 0.15
0.12 0.15
0.15
Degrees
Degrees
Degrees
DC PERFORMANCE
Input Offset Voltage
5 V to 15 V
5 V, 15 V
5 V, 15 V
5 V
0.5
2
3
mV
mV
µV/°C
µA
T
MIN to TMAX
Offset Drift
Input Bias Current
10
3.3
6.6
10
4.4
300
500
TMIN
TMAX
µA
µA
nA
nA
nA/°C
Input Offset Current
25
0.3
4
TMIN to TMAX
Offset Current Drift
Open-Loop Gain
VOUT
= 2.5 V
R
T
R
LOAD = 500 Ω
MIN to TMAX
LOAD = 150 Ω
2
1.5
1.5
V/mV
V/mV
V/mV
3
VOUT
=
10 V
15 V
15 V
R
T
LOAD = 1 kΩ
3.5
2
6
5
V/mV
V/mV
MIN to TMAX
VOUT
= 7.5 V
RLOAD = 150 Ω (50 mA Output)
2
4
V/mV
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
300
1.5
+3.8 +4.3
–2.7 –3.4
kΩ
pF
V
Input Common-Mode Voltage Range
5 V
V
15 V
+13
–12
+14.3
–13.4
V
V
0, +5 V
+3.8 +4.3
+1.2 +0.9
V
V
Common-Mode Rejection Ratio
VCM
VCM
TMIN to TMAX
=
=
2.5 V, TMIN–TMAX
12 V
5 V
15 V
15 V
80
86
80
100
120
100
dB
dB
dB
REV. C
–2–
AD826
Parameter
Conditions
VS
5 V
5 V
15 V
Min
Typ
Max Unit
OUTPUT CHARACTERISTICS
Output Voltage Swing
RLOAD = 500 Ω
RLOAD = 150 Ω
RLOAD = 1 kΩ
RLOAD = 500 Ω
RLOAD = 500 Ω
3.3
3.2
13.3
12.8
+1.5,
+3.5
50
3.8
3.6
13.7
13.4
V
V
V
V
15 V
0, +5 V
V
Output Current
15 V
5 V
0, +5 V
15 V
mA
mA
mA
mA
Ω
50
30
Short-Circuit Current
Output Resistance
90
8
Open Loop
MATCHING CHARACTERISTICS
Dynamic
Crosstalk
Gain Flatness Match
Slew Rate Match
f = 5 MHz
G = +1, f = 40 MHz
G = –1
15 V
15 V
15 V
–80
0.2
10
dB
dB
V/µs
DC
Input Offset Voltage Match
Input Bias Current Match
Open-Loop Gain Match
TMIN–TMAX
5 V to 15 V
5 V to 15 V
0.5
2
0.8
mV
µA
TMIN–TMAX
0.06
VO = 10 V, RLOAD = 1 kΩ,
TMIN–TMAX
= 12 V, TMIN–TMAX
5 V to 15 V, TMIN–TMAX
15 V
15 V
0.15
80
80
0.01
100
100
mV/V
dB
dB
Common-Mode Rejection Ratio Match VCM
Power Supply Rejection Ratio Match
POWER SUPPLY
Operating Range
Dual Supply
Single Supply
2.5
+5
18
V
+36
7.5
7.5
7.5
7.5
V
Quiescent Current/Amplifier
5 V
6.6
mA
mA
mA
mA
dB
TMIN to TMAX
5 V
15 V
15 V
TMIN to TMAX
VS = 5 V to 15 V, TMIN to TMAX
6.8
86
Power Supply Rejection Ratio
75
NOTES
1Full power bandwidth = slew rate/2 π VPEAK
.
ESD SUSCEPTIBILITY
Specifications subject to change without notice.
ESD (electrostatic discharge) sensitive device. Electrostatic charges
as high as 4000 volts, which readily accumulate on the human
body and on test equipment, can discharge without detection.
Although the AD826 features proprietary ESD protection cir-
cuitry, permanent damage may still occur on these devices
if they are subjected to high energy electrostatic discharges.
Therefore, proper ESD precautions are recommended to avoid
any performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Power Dissipation2
Plastic (N) . . . . . . . . . . . . . . . . . . . . . See Derating Curves
Small Outline (R) . . . . . . . . . . . . . . . . See Derating Curves
Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . VS
18 V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . .
6 V
2.0
Output Short Circuit Duration . . . . . . . See Derating Curves
Storage Temperature Range (N, R) . . . . . . . –65°C to +125°C
Operating Temperature Range . . . . . . . . . . –40°C to +85°C
Lead Temperature Range (Soldering 10 seconds) . . . +300°C
T
J
= +150ꢃC
8-LEAD MINI-DIP PACKAGE
1.5
1.0
0.5
0
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability .
2Specification is for device in free air: 8-lead plastic package, θJA = 100°C/watt;
8-lead SOIC package, θJA = 155°C/watt.
8-LEAD SOIC PACKAGE
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
AMBIENT TEMPERATURE –
ꢃC
Maximum Power Dissipation vs. Temperature for Different
Package Types
REV. C
–3–
AD826 – Typical Characteristics
7.7
20
15
7.2
6.7
6.2
5.7
+V
CM
CM
+85ꢃC
+25ꢃC
10
5
–V
–40ꢃC
0
0
5
10
SUPPLY VOLTAGE – ꢁVolts
15
20
0
5
10
SUPPLY VOLTAGE – ꢁVolts
15
20
Figure 1. Common-Mode Voltage Range vs. Supply
Figure 4. Quiescent Supply Current per Amp vs. Supply
Voltage for Various Temperatures
20
15
400
350
300
250
200
R
= 500V
L
10
5
R
= 150V
L
0
0
5
10
15
20
0
5
10
SUPPLY VOLTAGE – ꢁVolts
15
20
SUPPLY VOLTAGE – ꢁVolts
Figure 2. Output Voltage Swing vs. Supply
Figure 5. Slew Rate vs. Supply Voltage
30
25
100
10
V
= ꢁ15V
S
20
15
10
5
1
0.1
0.01
V
= ꢁ5V
S
0
10
100
1k
10k
1k
10k
100k
1M
10M
100M
LOAD RESISTANCE – ꢂ
FREQUENCY – Hz
Figure 3. Output Voltage Swing vs. Load Resistance
Figure 6. Closed-Loop Output Impedance vs. Frequency
–4–
REV. C
AD826
7
100
+100
PHASE ꢁ5V OR
ꢁ15V SUPPLIES
6
5
80
60
40
20
0
+80
+60
+40
+20
0
GAIN ꢁ15V SUPPLIES
4
3
2
1
GAIN ꢁ5V SUPPLIES
RL = 1kꢂ
10k
–20
–60 –40 –20
0
20
40
60
80
100 120 140
1k
100k
1M
10M
100M
1G
TEMPERATURE –
ꢃC
FREQUENCY – Hz
Figure 7. Input Bias Current vs. Temperature
Figure 10. Open-Loop Gain and Phase Margin
vs. Frequency
130
7
ꢁ15V
6
110
SOURCE CURRENT
5
90
ꢁ5V
SINK CURRENT
4
3
2
70
50
30
1
100
–60 –40 –20
0
20
40
60
80
100 120 140
1k
10k
LOAD RESISTANCE – ꢂ
TEMPERATURE –
ꢃC
Figure 8. Short Circuit Current vs. Temperature
Figure 11. Open-Loop Gain vs. Load Resistance
100
100
90
80
70
60
50
40
30
20
10
80
60
40
20
80
PHASE MARGIN
POSITIVE
SUPPLY
NEGATIVE
SUPPLY
60
GAIN BANDWIDTH
40
20
–60 –40 –20
0
20
40
60
80
100 120 140
100
1k
10k
100k
1M
10M
100M
TEMPERATURE –
ꢃC
FREQUENCY – Hz
Figure 9. Unity Gain Bandwidth and Phase Margin
vs. Temperature
Figure 12. Power Supply Rejection vs. Frequency
REV. C
–5–
AD826
–40
–50
–60
–70
–80
–90
–100
140
V
= 1V p-p
IN
GAIN = +2
120
100
80
2
ND HARMONIC
3
RD HARMONIC
1M
60
100
1k
10k
100k
10M
1k
10k
100k
1M
10M
FREQUENCY – Hz
FREQUENCY – Hz
Figure 13. Common-Mode Rejection vs. Frequency
Figure 16. Harmonic Distortion vs. Frequency
30
50
40
30
20
10
0
R
= 1kꢂ
L
20
10
0
R
= 150ꢂ
L
100k
1M
10M
100M
3
10
100
1k
10k
100k
1M
10M
FREQUENCY – Hz
FREQUENCY – Hz
Figure 14. Large Signal Frequency Response
Figure 17. Input Voltage Noise Spectral Density
380
10
0.1%
8
6
4
360
340
320
300
1%
1%
0.01%
2
0
–2
–4
–6
–8
–10
0.01%
0.1%
0
20
40
60
80
100
120
140
160
–60 –40 –20
0
20
40
60
80
100 120 140
SETTLING TIME – ns
TEMPERATURE –
ꢃC
Figure 15. Output Swing and Error vs. Settling Time
Figure 18. Slew Rate vs. Temperature
–6–
REV. C
AD826
5
4
5
4
0.1dB
1kꢂ
0.1dB
FLATNESS
ꢁ15V 3pF 16MHz
781ꢂ
V
FLATNESS
S
V
C
C
1kꢂ
S
ꢁ15V
ꢁ5V
ꢄ5V
55MHz
20MHz
20MHz
VIN
3
3
2
VOUT
VOUT
150ꢂ
CC
VIN
ꢁ5V
ꢄ5V
4pF 14MHz
6pF 12MHz
2
V
S
= ꢁ15V
1
1
V
= ꢁ15V
S
0
0
V
= ꢁ5V
= ꢄ5V
S
–1
–2
–3
–4
–5
–1
–2
–3
–4
–5
V
= ꢁ5V
S
V
= ꢄ5V
S
V
S
100k
1M
10M
FREQUENCY – Hz
100M
100k
1M
10M
100M
FREQUENCY – HZ
Figure 22. Closed-Loop Gain vs. Frequency, Gain = –1
Figure 19. Closed-Loop Gain vs. Frequency
1.0
0.8
0.6
0.4
0.2
0.13
0.10
0.07
DIFF GAIN
0.13
V
= ꢁ15V
S
0
–0.2
–0.4
–0.6
–0.8
–1.0
0.12
0.11
0.10
V
= ꢁ5V
S
DIFF PHASE
V
= +5V
S
100k
1M
10M
100M
ꢁ5
ꢁ10
SUPPLY VOLTAGE – Volts
ꢁ15
FREQUENCY – Hz
Figure 20. Differential Gain and Phase vs. Supply Voltage
Figure 23. Gain Flatness Matching vs. Supply, G = +1
ꢄV
V
OUT
S
–30
–40
–50
0.1ꢀF
1ꢀF
8
5
6
3
2
1
7
1/2
AD826
1/2
AD826
–60
V
IN
ꢁ5V
4
R
= 150ꢂ
L
–70
–80
0.1ꢀF
1ꢀF
R
R
L
L
ꢁ15V
L
–90
R
= 1kꢂ
–V
S
–100
R
= 150ꢂ FOR ꢁV = 5V, 1kꢂ FOR ꢁV = 15V
S S
L
–110
10k
100k
1M
FREQUENCY – Hz
10M
100M
USE GROUND PLANE
PINOUT SHOWN IS FOR MINIDIP PACKAGE
Figure 24. Crosstalk Test Circuit
Figure 21. Crosstalk vs. Frequency
REV. C
–7–
AD826
1kꢂ
ꢄV
S
3.3ꢀF
0.01ꢀF
V
TEKTRONIX
P6201 FET
PROBE
TEKTRONIX
7A24
PREAMP
OUT
1/2
AD826
R
IN
100ꢂ
PULSE (LS)
OR
V
IN
FUNCTION (SS)
GENERATOR
50ꢂ
0.01ꢀF
3.3ꢀF
R
L
–V
S
Figure 25. Noninverting Amplifier Configuration
50ns
200mV
50ns
5V
100
90
100
90
10
10
0%
0%
200mV
5V
Figure 26. Noninverting Large Signal Pulse Response,
Figure 28. Noninverting Small Signal Pulse Response,
RL = 1 kΩ
RL = 1 kΩ
5V
50ns
200mV
50ns
100
90
100
90
10
10
0%
0%
5V
200mV
Figure 27. Noninverting Large Signal Pulse Response,
RL = 150 Ω
Figure 29. Noninverting Small Signal Pulse Response,
RL = 150 Ω
–8–
REV. C
AD826
1kꢂ
ꢄV
S
3.3ꢀF
0.01ꢀF
R
IN
1kꢂ
PULSE (LS)
OR FUNCTION (SS)
GENERATOR
V
IN
TEKTRONIX
7A24
PREAMP
TEKTRONIX
P6201 FET
PROBE
1/2
AD826
50ꢂ
V
OUT
0.01ꢀF
3.3ꢀF
R
L
–V
S
Figure 30. Inverting Amplifier Configuration
5V
200mV
50ns
50ns
100
90
100
90
10
10
0%
0%
200mV
5V
Figure 31. Inverting Large Signal Pulse Response,
Figure 33. Inverting Small Signal Pulse Response,
RL = 1 kΩ
RL = 1 kΩ
5V
200mV
50ns
50ns
100
90
100
90
10
10
0%
0%
5V
200mV
Figure 32. Inverting Large Signal Pulse Response,
Figure 34. Inverting Small Signal Pulse Response,
RL = 150 Ω
RL = 150 Ω
REV. C
–9–
AD826
THEORY OF OPERATION
The AD826 is a low cost, wide band, high performance dual
operational amplifier which can drive heavy capacitive and
resistive loads. It also achieves a constant slew rate, bandwidth
and settling time over its entire specified temperature range.
For high performance circuits, it is recommended that a
“balancing” resistor be used to reduce the offset errors caused
by bias current flowing through the input and feedback resistors.
The balancing resistor equals the parallel combination of RIN
and RF and thus provides a matched impedance at each input
terminal. The offset voltage error will then be reduced by more
than an order of magnitude.
The AD826 (Figure 35) consists of a degenerated NPN
differential pair driving matched PNPs in a folded-cascode gain
stage. The output buffer stage employs emitter followers in a
class AB amplifier which delivers the necessary current to the
load while maintaining low levels of distortion.
APPLYING THE AD826
The AD826 is a breakthrough dual amp that delivers precision
and speed at low cost with low power consumption. The AD826
offers excellent static and dynamic matching characteristics,
combined with the ability to drive heavy resistive and capacitive
loads. As with all high frequency circuits, care should be taken
to maintain overall device performance as well as their matching.
The following items are presented as general design considerations.
+V
S
C
F
OUTPUT
Circuit Board Layout
Input and output runs should be laid out so as to physically
isolate them from remaining runs. In addition, the feedback
resistor of each amplifier should be placed away from the
feedback resistor of the other amplifier, since this greatly
reduces inter-amp coupling.
–IN
+IN
Choosing Feedback and Gain Resistors
In order to prevent the stray capacitance present at each
amplifier’s summing junction from limiting its performance,
the feedback resistors should be ≤1 kΩ. Since the summing
junction capacitance may cause peaking, a small capacitor
(1 pF–5pF) maybe paralleled with RF to neutralize this effect.
Finally, sockets should be avoided, because of their tendency to
increase interlead capacitance.
–V
S
NULL1
NULL8
Figure 35. Simplified Schematic
The capacitor, CF, in the output stage mitigates the effect of
capacitive loads. With low capacitive loads, the gain from the
compensation node to the output is very close to unity. In this
case, CF is bootstrapped and does not contribute to the overall
compensation capacitance of the device. As the capacitive load
is increased, a pole is formed with the output impedance of the
output stage. This reduces the gain, and therefore, CF is
incompletely bootstrapped. Effectively, some fraction of CF
contributes to the overall compensation capacitance, reducing
the unity gain bandwidth. As the load capacitance is further
increased, the bandwidth continues to fall, maintaining the
stability of the amplifier.
Power Supply Considerations
To ensure the proper operation of the AD826, connect the
positive supply before the negative supply. Also, proper power
supply decoupling is critical to preserve the integrity of high
frequency signals. In carefully laid out designs, decoupling
capacitors should be placed in close proximity to the supply
pins, while their lead lengths should be kept to a minimum.
These measures greatly reduce undesired inductive effects on
the amplifier’s response.
Though two 0.1 μF capacitors will typically be effective in
decoupling the supplies, several capacitors of different values
can be paralleled to cover a wider frequency range.
INPUT CONSIDERATIONS
An input protection resistor (RIN in Figure 25) is required in
circuits where the input to the AD826 will be subjected to
transient or continuous overload voltages exceeding the 6 ꢀ
maximum differential limit. This resistor provides protection
for the input transistors by limiting their maximum base current.
-10-
Rev. C
AD826
ꢁSINGLE SUPPLY OPERATION
R3 and C2 reduce the effect of the power supply changes on the
An exciting feature of the AD826 is its ability to perform well in a
single supply configuration (see Figure 37). The AD826 is ideally
suited for applications that require low power dissipation and high
output current and those which need to drive large capacitive
loads, such as high speed buffering and instrumentation.
1
output by low-pass filtering with a corner at
.
2πR3C2
The values for RL and CL were chosen to demonstrate the
AD826’s exceptional output drive capability. In this configura-
tion, the output is centered around 2.5 V. In order to eliminate
the static dc current associated with this level, C3 was inserted
in series with RL.
Referring to Figure 36, careful consideration should be given to
the proper selection of component values. The choices for this
particular circuit are: (R1 + R3)ʈR2 combine with C1 to form a
low frequency corner of approximately 30 Hz.
ꢄV
S
500mV
100
90
R3
1kꢂ
3.3ꢀF
C2
0.1ꢀF
0.01ꢀF
R1
9kꢂ
10
C
C
OUT
1/2
AD826
C1
1ꢀF
0%
V
OUT
V
R
150ꢂ
IN
L
L
500mV
100ns
200pF
R2
10kꢂ
C3
0.1ꢀF
Figure 37. Single Supply Pulse Response, G = +1,
RL = 150 Ω, CL = 200 pF
Figure 36. Single Supply Amplifier Configuration
1kꢂ
PARALLEL AMPS PROVIDE 100 mA TO LOAD
ꢄV
1ꢀF
S
By taking advantage of the superior matching characteristics of
the AD826, enhanced performance can easily be achieved by
employing the circuit in Figure 38. Here, two identical cells are
paralleled to obtain even higher load driving capability than that
of a single amplifier (100 mA min guaranteed). R1 and R2 are
included to limit current flow between amplifier outputs that
would arise in the presence of any residual mismatch.
0.1ꢀF
1kꢂ
R1
5ꢂ
1/2
AD826
V
V
OUT
IN
R
L
R2
5ꢂ
1/2
AD826
1kꢂ
0.1ꢀF
1ꢀF
–V
S
1kꢂ
Figure 38. Parallel Amp Configuration
REV. C
–11–
AD826
SINGLE-ENDED TO DIFFERENTIAL LINE DRIVER
Outstanding CMRR (> 80 dB @ 5 MHz), high bandwidth, wide
supply voltage range, and the ability to drive heavy loads, make
the AD826 an ideal choice for many line driving applications.
In this application, the AD830 high speed video difference
amp serves as the differential line receiver on the end of a back
terminated, 50 ft., twisted-pair transmission line (see Figure 40).
The overall system is configured in a gain of +1 and has a –3 dB
bandwidth of 14 MHz. Figure 39 is the pulse response with a
2 V p-p, 1 MHz signal input.
2V
200ns
100
90
10
0%
2V
Figure 39. Pulse Response
ꢄ15V
0.01ꢀF
ꢄ15V
0.01ꢀF
0.1ꢀF
50 FEET TWISTED PAIR
0.1ꢀF
Z = 72ꢂ
I
N
2.2ꢀF
36ꢂ
1/2
AD826
1.05kꢂ
5pF
36ꢂ
36ꢂ
V
OUT
BNC
AD830
1.05kꢂ
1.05kꢂ
1.05kꢂ
5pF
36ꢂ
1/2
AD826
0.01ꢀF
0.1ꢀF
0.01ꢀF
–15V
–15V
0.1ꢀF
2.2ꢀF
Figure 40. Differential Line Driver
1.1kꢂ
LOW DISTORTION LINE DRIVER
The AD826 can quickly be turned into a powerful, low distor-
tion line driver (see Figure 41). In this arrangement the AD826
can comfortably drive a 75 Ω back-terminated cable, with a
5 MHz, 2 V p-p input; all of this while achieving the harmonic
distortion performance outlined in the following table.
ꢄV
1ꢀF
S
1kꢂ
0.1ꢀF
1/2
AD826
Configuration
2nd Harmonic
–78.5 dBm
R
7.5ꢂ
C
1. No Load
1kꢂ
2. 150 Ω RL Only
3. 150 Ω RL 7.5 Ω RC
–63.8 dBm
1kꢂ
–70.4 dBm
R
L
75ꢂ
1/2
AD826
In this application one half of the AD826 operates at a gain of
2.1 and supplies the current to the load, while the other pro-
vides the overall system gain of 2. This is important for two
reasons: the first is to keep the bandwidth of both amplifiers the
same, and the second is to preserve the AD826’s ability to oper-
ate from low supply voltages. RC varies with the load and must
be chosen to satisfy the following equation:
75ꢂ
1ꢀF
75ꢂ
0.1ꢀF
Figure 41. Low Distortion Amplifier
RC = MRL
where M is defined by [(M+ 1) GS = GD] and GD = Driver’s Gain,
GS = System Gain.
–12–
REV. C
AD826
1kꢂ
ꢄV
HIGH PERFORMANCE ADC BUFFER
Figure 42 is a schematic of a 12-bit high speed analog-to-digital
converter. The AD826 dual op amp takes a single ended input
and drives the AD872 A/D converter differentially, thus reduc-
ing 2nd harmonic distortion. Figure 43 is a FFT of a 1 MHz
input, sampled at 10 MHz with a THD of –78 dB. The AD826
can be used to amplify low level signals so that the entire range
of the converter is used. The ability of the AD826 to perform on
S
0.1ꢀF
1kꢂ
1/2
AD826
V
INA
50ꢂ
COAX
CABLE
V
IN
AD872
12-BIT
10MSPS
ADC
a
5 volt supply or even with a single 5 volts combined with its
500mV
p-p MAX
52.5ꢂ
rapid settling time and ability to deliver high current to compli-
cated loads make it a very good flash A/D converter buffer as
well as a very useful general purpose building block.
1/2
AD826
V
INB
1kꢂ
ꢄV
0.1ꢀF
ꢄ5V
S
100ꢀF
25V
–V
COMMON
S
100ꢀF
25V
1kꢂ
–V
–5V
S
Figure 42. A Differential Input Buffer for High
Bandwidth ADCs
Figure 43. FFT, Buffered A/D Converter
REV. C
–13–
AD826
OUTLINE DIMENSIONS
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
8
1
5
4
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.210 (5.33)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
PLANE
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 44. 8-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body (N-8)
Dimensions shown in inches and (millimeters)
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 45. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-8)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model1
AD826AN
AD826ANZ
AD826AR
AD826AR-REEL
AD826AR-REEL7
AD826ARZ
AD826ARZ-REEL
AD826ARZ-REEL7
Temperature Range
Package Description
8-Lead PDIP
8-Lead PDIP
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
Package Option
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
N-8
N-8
R-8
R-8
R-8
R-8
R-8
R-8
1 Z = RoHS Compliant Part.
-14-
Rev. C
AD826
REVISION HISTORY
Changed Power Supply Bypassing Section to Power Supply
Considerations Section...................................................................10
Changes to Power Supply Considerations Section ....................10
Updated Outline Dimensions........................................................14
Changes to Ordering Guide...........................................................14
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08950-0-4/10(C)
Rev. C
-15-
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