AD829AR-EBZ [ADI]
High Speed, Low Noise Video Op Amp; 高速，低噪声视频运算放大器
| 型号： | AD829AR-EBZ |
| 厂家： | 
ADI |
| 描述： | High Speed, Low Noise Video Op Amp |
| 文件： | 总20页 (文件大小：385K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Speed, Low Noise
Video Op Amp
Data Sheet
AD829
FEATURES
CONNECTION DIAGRAM
OFFSET NULL
1
2
3
4
8
7
6
5
OFFSET NULL
High speed
120 MHz bandwidth, gain = −1
230 V/µs slew rate
90 ns settling time to 0.1%
Ideal for video applications
0.02% differential gain
AD829
–IN
+IN
+V
S
OUTPUT
TOP VIEW
(Not to Scale)
–V
C
COMP
S
Figure 1. 8-Lead PDIP (N), CERDIP (Q), and SOIC (R)
0.04° differential phase
Low noise
3
2
1
20 19
1.7 nV/√Hz input voltage noise
1.5 pA/√Hz input current noise
Excellent dc precision
1 mV maximum input offset voltage (over temperature)
0.3 µV/°C input offset drift
Flexible operation
18 NC
+V
4
5
6
7
8
NC
–IN
NC
+IN
NC
17
16 NC
AD829
TOP VIEW
(Not to Scale)
OUTPUT
15
14 NC
9
10 11 12 13
Specified for 5 V to 15 V operation
3 V output swing into a 150 Ω load
External compensation for gains 1 to 20
5 mA supply current
NC = NO CONNECT
Figure 2. 20-Terminal LCC
Operating as a traditional voltage feedback amplifier, the AD829
provides many of the advantages that a transimpedance amplifier
offer. A bandwidth >50 MHz can be maintained for a range of
gains through the replacement of the external compensation
capacitor. The AD829 and the transimpedance amplifier are both
unity-gain stable and provide similar voltage noise performance
(1.7 nV/√Hz); however, the current noise of the AD829
(1.5 pA/√Hz) is less than 10% of the noise of transimpedance
amplifiers. The inputs of the AD829 are symmetrical.
Available in tape and reel in accordance with EIA-481A standard
GENERAL DESCRIPTION
The " % is a low noise (1.7 nV/√Hz), high speed op amp with
custom compensation that provides the user with gains of 1 to 20
while maintaining a bandwidth >50 MHz. Its 0.04° differential
phase and 0.02% differential gain performance at 3.58 MHz and
4.43 MHz, driving reverse-terminated 50 Ω or 75 Ω cables, makes
it ideally suited for professional video applications. The AD829
achieves its 230 V/µs uncompensated slew rate and 750 MHz
gain bandwidth while requiring only 5 mA of current from
power supplies.
PRODUCT HIGHLIGHTS
1. The input voltage noise of 2 nV/√Hz, current noise of
1.5 pA/√Hz, and 50 MHz bandwidth for gains of 1 to 20
make the AD829 an ideal preamp.
The external compensation pin of the AD829 gives it
2. A differential phase error of 0.04 and a 0.02% differential
gain error, at the 3.58 MHz NTSC, 4.43 MHz PAL, and
SECAM color subcarrier frequencies, make the op amp an
outstanding video performer for driving reverse-terminated
50 Ω and 75 Ω cables to 1 V (at their terminated end).
3. The AD829 can drive heavy capacitive loads.
4. Performance is fully specified for operation from 5 V
to 15 V supplies.
5. The AD829 is available in PDIP, CERDIP, and small outline
packages. Chips and MIL-STD-883B parts are also available.
The 8-lead SOIC is available for the extended temperature
range (−40°C to +125°C).
exceptional versatility. For example, compensation can be
selected to optimize the bandwidth for a given load and power
supply voltage. As a gain-of-2 line driver, the −3 dB bandwidth
can be increased to 95 MHz at the expense of 1 dB of peaking.
Its output can also be clamped at its external compensation pin.
The AD829 exhibits excellent dc performance. It offers a minimum
open-loop gain of 30 V/mV into loads as low as 500 Ω, a low input
voltage noise of 1.7 nV/√Hz, and a low input offset voltage of 1 mV
maximum. Common-mode rejection and power supply rejection
ratios are both 120 dB.
This op amp is also useful in multichannel, high speed data
conversion where its fast (90 ns to 0.1%) settling time is important.
In such applications, the AD829 serves as an input buffer for 8-bit to
10-bit ADCs and as an output I/V converter for high speed DACs.
Rev. I
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2011 Analog Devices, Inc. All rights reserved.
AD829
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Test Circuits..................................................................................... 11
Theory of Operation ...................................................................... 12
Externally Compensating the AD829...................................... 12
Shunt Compensation ................................................................. 12
Current Feedback Compensation ............................................ 13
Low Error Video Line Driver ................................................... 15
General Description......................................................................... 1
Connection Diagram ....................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Characteristics .............................................................. 5
Metallization Photo...................................................................... 5
ESD Caution.................................................................................. 5
Typical Performance Characteristics ............................................. 6
High Gain Video Bandwidth, 3-Op-Amp Instrumentation
Amplifier ..................................................................................... 16
Outline Dimensions....................................................................... 17
Ordering Guide .......................................................................... 19
REVISION HISTORY
10/11—Rev. H to Rev. I
Change to Table 2 ............................................................................. 5
2/03—Rev. E to Rev. F
Renumbered Figures .........................................................Universal
Changes to Product Highlights .......................................................1
Changes to Specifications.................................................................2
Changes to Absolute Maximum Ratings........................................4
Changes to Ordering Guide.............................................................4
Updated Outline Dimensions....................................................... 13
4/09—Rev. G to Rev. H
Changes to Features.......................................................................... 1
Changes to Quiescent Current Parameter, Table 1 ...................... 4
Changes to Table 2 ............................................................................ 5
Added Thermal Characteristics Section and Table 3 .................. 5
Updated Outline Dimensions ....................................................... 17
Changes to Ordering Guide .......................................................... 19
4/04—Rev. F to Rev. G
Added Figure 1; Renumbered Sequentially .................................. 4
Changes to Ordering Guide ............................................................ 5
Updated Table I............................................................................... 11
Updated Figure 15 .......................................................................... 12
Updated Figure 16 .......................................................................... 13
Updated Outline Dimensions ....................................................... 14
Rev. I | Page 2 of 20
Data Sheet
AD829
SPECIFICATIONS
TA = 25°C and VS = 15 V dc, unless otherwise noted.
Table 1.
AD829JR
Min Typ
AD829AR
Max Min Typ
AD829AQ/AD829S
Parameter
Conditions
VS
Max Min Typ
Max
Unit
INPUT OFFSET VOLTAGE
tMIN to tMAX
±5 V,
0.2
±
0.2
±
0.±
0.5
mV
±±5 V
±
±
0.5
7
mV
µV/°C
Offset Voltage Drift
±5 V,
±±5 V
0.3
3.3
0.3
3.3
0.3
3.3
INPUT BIAS CURRENT
±5 V,
7
7
µA
±±5 V
tMIN to tMAX
8.2
9.5
9.5
µA
nA
INPUT OFFSET CURRENT
±5 V,
50
500
50
500
50
500
±±5 V
tMIN to tMAX
500
500
500
nA
Offset Current Drift
OPEN-LOOP GAIN
± 5 V,
±±5 V
0.5
65
40
0.5
65
40
0.5
65
40
nA/°C
VO = ±2.5 V,
RL = 500 Ω
RL = ±50 Ω
tMIN to tMAX
VO = ±±0 V,
RL = ± kΩ
RL = 500 Ω
tMIN to tMAX
±5 V
30
20
30
30
V/mV
V/mV
V/mV
V/mV
20
50
20
50
±±5 V 50
±00
85
±00
85
±00
85
V/mV
V/mV
20
20
20
DYNAMIC PERFORMANCE
Gain Bandwidth Product
±5 V
±±5 V
±5 V
600
750
25
600
750
25
600
750
25
MHz
MHz
MHz
Full Power Bandwidth±, 2
VO = 2 V p-p,
RL = 500 Ω
VO = 20 V p-p, ±±5 V
RL = ± kΩ
3.6
3.6
3.6
MHz
Slew Rate2
RL = 500 Ω
RL = ± kΩ
AV = –±9
±5 V
±±5 V
±50
230
±50
230
±50
230
V/µs
V/µs
Settling Time to 0.±%
−2.5 V to
+2.5 V
±0 V step
CL = ±0 pF
RL = ± kΩ
±5 V
65
90
65
90
65
90
ns
ns
±±5 V
±±5 V
Phase Margin2
60
60
60
Degrees
%
DIFFERENTIAL GAIN ERROR3
DIFFERENTIAL PHASE ERROR3
COMMON-MODE REJECTION
RL = ±00 Ω,
CCOMP = 30 pF
±±5 V
±±5 V
±5 V
0.02
0.02
0.02
RL = ±00 Ω,
CCOMP = 30 pF
0.04
0.04
0.04
Degrees
VCM = ±2.5 V
VCM = ±±2 V
tMIN to tMAX
±00
±20
±20
±00
±00
96
±20
±20
±00
±00
96
±20
±20
dB
dB
dB
dB
±±5 V ±00
96
98
POWER SUPPLY REJECTION
VS = ±4.5 V
to ±±8 V
±20
98
±20
98
±20
tMIN to tMAX
f = ± kHz
f = ± kHz
94
±±5 V
94
94
dB
INPUT VOLTAGE NOISE
INPUT CURRENT NOISE
±.7
±.5
2
±.7
±.5
2
±.7
±.5
2
nV/√Hz
pA/√Hz
±±5 V
Rev. I | Page 3 of 20
AD829
Data Sheet
AD829JR
Min Typ
AD829AR
Max Min Typ
AD829AQ/AD829S
Max Min Typ Max
Parameter
Conditions
VS
Unit
INPUT COMMON-MODE
VOLTAGE RANGE
±5 V
+4.3
+4.3
+4.3
V
−3.8
+±4.3
−3.8
+±4.3
−3.8
+±4.3
V
V
±±5 V
−±3.8
−±3.8
−±3.8
V
OUTPUT VOLTAGE SWING
RL = 500 Ω
RL = ±50 Ω
RL = 50 Ω
RL = ± kΩ
RL = 500 Ω
±5 V
±5 V
±5 V
±3.0 ±3.6
±2.5 ±3.0
±±.4
±3.0 ±3.6
±2.5 ±3.0
±±.4
±±2 ±±3.3
±±0 ±±2.2
32
±3.0 ±3.6
±2.5 ±3.0
±±.4
±±2 ±±3.3
±±0 ±±2.2
32
V
V
V
V
V
mA
±±5 V ±±2 ±±3.3
±±5 V ±±0 ±±2.2
±5 V,
Short-Circuit Current
32
±±5 V
INPUT CHARACTERISTICS
Input Resistance
(Differential)
Input Capacitance
(Differential)4
±3
5
±3
5
±3
5
kΩ
pF
Input Capacitance
(Common Mode)
±.5
2
±.5
2
±.5
2
pF
CLOSED-LOOP OUTPUT
RESISTANCE
AV = +±,
f = ± kHz
mΩ
POWER SUPPLY
Operating Range
Quiescent Current
±4.5
±±8
6.5
8.0
6.8
8.3
±4.5
5
±±8
6.5
8.0
6.8
9.0
±4.5
5
±±8
6.5
8.7
6.8
9.0
V
±5 V
5
mA
mA
mA
mA
tMIN to tMAX
tMIN to tMAX
±±5 V
5.3
46
5.3
46
5.3
46
TRANSISTOR COUNT
Number of
transistors
± Full power bandwidth = slew rate/2 π VPEAK
.
2 Tested at gain = 20, CCOMP = 0 pF.
3 3.58 MHz (NTSC) and 4.43 MHz (PAL and SECAM).
4 Differential input capacitance consists of ±.5 pF package capacitance plus 3.5 pF from the input differential pair.
Rev. I | Page 4 of 20
Data Sheet
AD829
ABSOLUTE MAXIMUM RATINGS
METALLIZATION PHOTO
Table 2.
OFFSET NULL
1
OFFSET NULL
8
Parameter
Rating
+V
7
S
Supply Voltage
Internal Power Dissipation±
±±8 V
8-Lead PDIP (N)
8-Lead SOIC (R)
8-Lead CERDIP (Q)
20-Terminal LCC (E)
Differential Input Voltage2
Output Short-Circuit Duration
Storage Temperature Range
8-Lead CERDIP (Q) and 20-Terminal LCC (E)
8-Lead PDIP (N) and 8-Lead SOIC (R)
Operating Temperature Range
AD829J
±.3 W
0.9 W
±.3 W
0.8 W
±6 V
–IN
2
OUTPUT
6
0.054
(1.37)
COMP
C
Indefinite
5
+IN
3
−65°C to +±50°C
−65°C to +±25°C
–V
4
S
0.067 (1.70)
0°C to 70°C
SUBSTRATE CONNECTED TO +V
S
AD829A
AD829S
−40°C to +±25°C
−55°C to +±25°C
300°C
Figure 3. Metallization Photo; Contact Factory for Latest Dimensions,
Dimensions Shown in Inches and (Millimeters)
Lead Temperature (Soldering, 60 sec)
2.5
± Maximum internal power dissipation is specified so that TJ does not exceed
±50°C at an ambient temperature of 25°C.
2 If the differential voltage exceeds 6 V, external series protection resistors
should be added to limit the input current.
PDIP
2.0
1.5
1.0
0.5
0
LCC
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
CERDIP
SOIC
THERMAL CHARACTERISTICS
–55 –45 –35 –25 –15 –5
5
15 25 35 45 55 65 75 85 95 105 115 125
AMBIENT TEMPERATURE (°C)
Table 3.
Package Type
8-Lead PDIP (N)
8-Lead CERDIP (Q)
20-Lead LCC (E)
8-Lead SOIC (R)
θJA
Unit
°C/W
°C/W
°C/W
°C/W
Figure 4. Maximum Power Dissipation vs. Temperature
±00 (derates at 8.7 mW/°C)
±±0 (derates at 8.7 mW/°C)
77
ESD CAUTION
±25 (derates at 6 mW/°C)
Rev. I | Page 5 of 20
AD829
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
20
6.0
5.5
5.0
4.5
4.0
15
+V
OUT
10
5
–V
OUT
0
0
5
10
SUPPLY VOLTAGE (±V)
15
20
0
5
10
15
20
SUPPLY VOLTAGE (±V)
Figure 5. Input Common-Mode Range vs. Supply Voltage
Figure 8. Quiescent Current vs. Supply Voltage
20
–5
–4
–3
–2
15
10
5
+V
OUT
V
= ±5V, ±15V
S
–V
OUT
R
= 1kΩ
L
0
0
5
10
SUPPLY VOLTAGE (±V)
15
20
–60 –40 –20
0
20
40
60
80
100 120 140
TEMPERATURE (°C)
Figure 6. Output Voltage Swing vs. Supply Voltage
Figure 9. Input Bias Current vs. Temperature
30
25
20
15
10
5
100
10
±15V
SUPPLIES
A
C
= 20
V
= 0pF
COMP
1
0.1
A
C
= 1
V
= 68pF
COMP
0.01
±5V
SUPPLIES
0
10
0.001
100
1k
10k
1k
10k
100k
1M
10M
100M
LOAD RESISTANCE (Ω)
FREQUENCY (Hz)
Figure 7. Output Voltage Swing vs. Resistive Load
Figure 10. Closed-Loop Output Impedance vs. Frequency
Rev. I | Page 6 of 20
Data Sheet
AD829
7
120
100
80
60
40
20
0
100
PHASE
80
60
40
20
0
GAIN
6
5
4
3
±15V
SUPPLIES
1kΩ LOAD
V
= ±15V
S
GAIN
±5V
V
= ±5V
SUPPLIES
500Ω LOAD
S
C
= 0pF
COMP
–20
100M
–60 –40 –20
0
20
40
60
80
100 120 140
100
1k
10k
100k
1M
10M
TEMPERATURE (°C)
FREQUENCY (Hz)
Figure 14. Open-Loop Gain and Phase vs. Frequency
Figure 11. Quiescent Current vs. Temperature
105
100
95
40
35
30
25
20
15
NEGATIVE
CURRENT LIMIT
V
= ±15V
S
POSITIVE
CURRENT LIMIT
V
= ±5V
S
90
85
80
V
= ±5V
S
75
10
100
1k
10k
–60 –40 –20
0
20
40
60
80
100 120 140
LOAD RESISTANCE (Ω)
AMBIENT TEMPERATURE (°C)
Figure 15. Open-Loop Gain vs. Resistive Load
Figure 12. Short-Circuit Current Limit vs. Ambient Temperature
120
100
80
65
V
A
C
= ±15V
= +20
S
+SUPPLY
V
= 0pF
COMP
60
55
50
45
–SUPPLY
60
40
C
= 0pF
COMP
20
1k
10k
100k
1M
10M
100M
–60 –40 –20
0
20
40
60
80
100 120 140
FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 16. Power Supply Rejection Ratio (PSRR) vs. Frequency
Figure 13. –3 dB Bandwidth vs. Temperature
Rev. I | Page 7 of 20
AD829
Data Sheet
–70
–75
120
100
80
V
= 3V RMS
= –1
IN
A
C
C
V
= 30pF
COMP
= 100pF
L
–80
–85
R
= 500Ω
L
–90
60
–95
–100
–105
–110
40
R
= 2kΩ
L
C
= 0pF
COMP
20
1k
100
300
1k
3k
10k
30k
100k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 17. Common-Mode Rejection Ratio (CMRR) vs. Frequency
Figure 20. Total Harmonic Distortion (THD) vs. Frequency
30
–20
–30
–40
–50
–60
–70
V
= 2.25V RMS
= –1
= 250Ω
= 0pF
IN
V
= ±15V
= 1kΩ
= +20
S
A
R
C
C
THIRD HARMONIC
V
R
A
C
L
V
25
20
15
10
5
L
L
= 0pF
COMP
= 30pF
COMP
V
= ±5V
= 500Ω
= +20
S
R
A
C
L
V
SECOND HARMONIC
= 0pF
COMP
0
1
10
INPUT FREQUENCY (MHz)
100
0
500k
1.0M
1.5M
2.0M
FREQUENCY (Hz)
Figure 21. Second and Third THD vs. Frequency
Figure 18. Large Signal Frequency Response
5
4
3
2
1
0
10
8
6
4
2
1%
1%
0.1%
0.1%
ERROR
A
C
= –19
0
V
= 0pF
COMP
–2
–4
–6
–8
–10
10
100
1k
10k
100k
1M
10M
0
20
40
60
80
100
120
140
160
SETTLING TIME (ns)
FREQUENCY (Hz)
Figure 22. Input Voltage Noise Spectral Density
Figure 19. Output Swing and Error vs. Settling Time
Rev. I | Page 8 of 20
Data Sheet
AD829
400
A
= +20
V
20mV
20ns
SLEW RATE 10% TO 90%
350
300
250
200
150
100
100%
90
RISE
FALL
V
= ±15V
S
RISE
FALL
10
0%
V
= ±5V
40
S
–60 –40 –20
0
20
60
80
100 120 140
TEMPERATURE (°C)
Figure 23. Slew Rate vs. Temperature
Figure 26. Gain-of-2 Follower Small Signal Pulse Response (See Figure 32)
0.03
0.02
2V
50ns
100%
90
0.01
DIFFERENTIAL GAIN
0.043°
DIFFERENTIAL PHASE
0.05
10
0%
0.04
0.03
±5
±10
SUPPLY VOLTAGE (V)
±15
Figure 24. Differential Phase and Gain vs. Supply Voltage
Figure 27. Gain-of-20 Follower Large Signal Pulse Response (See Figure 33)
200mV
50ns
50mV
20ns
100%
90
90
10
10
0%
0%
Figure 25. Gain-to-2 Follower Large Signal Pulse Response (See Figure 32)
Figure 28. Gain-of-20 Follower Small Signal Pulse Response (See Figure 33)
Rev. I | Page 9 of 20
AD829
Data Sheet
200mV
50ns
20mV
20ns
100%
90
100%
90
10
10
0%
0%
Figure 29. Unity-Gain Inverter Large Signal Pulse Response (See Figure 34)
Figure 30. Unity-Gain Inverter Small Signal Pulse Response (See Figure 34)
Rev. I | Page ±0 of 20
Data Sheet
AD829
TEST CIRCUITS
C
COMP
(EXTERNAL)
+V
7
S
0.1µF
5
2
–
6
AD829
4
3
+
8
1
0.1µF
OFFSET
NULL
ADJUST
–V
S
Figure 31. Offset Null and External Shunt Compensation Connections
+15V
C
COMP
15pF
0.1µF
50Ω
CABLE
7
50Ω
CABLE
HP8130A
5ns RISE TIME
3
2
+
5
TEKTRONIX
TYPE 7A24
PREAMP
50Ω
6
AD829
50Ω
–
50Ω
4
5pF
300kΩ
300kΩ
0.1µF
–15V
Figure 32. Follower Connection, Gain = 2
+15V
0.1µF
50Ω
CABLE
45Ω
100Ω
FET
PROBE
HP8130A
5ns RISE TIME
7
2
3
–
6
AD829
TEKTRONIX
TYPE 7A24
PREAMP
5Ω
+
4
1pF
2kΩ
0.1µF
–15V
C
= 0pF
105kΩ
COMP
Figure 33. Follower Connection, Gain = 20
5pF
300Ω
+15V
50Ω
CABLE
0.1µF
300Ω
50Ω
CABLE
HP8130A
5ns RISE TIME
7
2
3
–
TEKTRONIX
TYPE 7A24
PREAMP
50Ω
6
AD829
50Ω
5
C
+
COMP
15pF
50Ω
4
0.1µF
–15V
Figure 34. Unity-Gain Inverter Connection
Rev. I | Page ±± of 20
AD829
Data Sheet
THEORY OF OPERATION
The AD829 is fabricated on the Analog Devices, Inc., proprietary
complementary bipolar (CB) process, which provides PNP and
NPN transistors with similar fTs of 600 MHz. As shown in
Figure 35, the AD829 input stage consists of an NPN differential
pair in which each transistor operates at a 600 µA collector current.
This gives the input devices a high transconductance, which in
turn gives the AD829 a low noise figure of 2 nV/√Hz at 1 kHz.
An RC network in the output stage (see Figure 35) completely
removes the effect of capacitive loading when the amplifier
compensates for closed-loop gains of 10 or higher. At low
frequencies, and with low capacitive loads, the gain from the
compensation node to the output is very close to unity. In this case,
C is bootstrapped and does not contribute to the compensation
capacitance of the device. As the capacitive load increases, a pole
forms with the output impedance of the output stage, which
reduces the gain, and subsequently, C is incompletely
+V
S
bootstrapped. Therefore, some fraction of C contributes to the
compensation capacitance, and the unity-gain bandwidth falls.
As the load capacitance is further increased, the bandwidth
continues to fall, and the amplifier remains stable.
15Ω
15Ω
OUTPUT
R
500Ω
C
12.5pF
+IN
–IN
EXTERNALLY COMPENSATING THE AD829
The AD829 is stable with no external compensation for noise
gains greater than 20. For lower gains, two different methods of
frequency compensating the amplifier can be used to achieve
closed-loop stability: shunt and current feedback compensation.
1.2mA
–V
S
C
OFFSET NULL
COMP
SHUNT COMPENSATION
Figure 36 and Figure 37 show that shunt compensation has an
external compensation capacitor, CCOMP, connected between the
compensation pin and ground. This external capacitor is tied in
parallel with approximately 3 pF of internal capacitance at the
compensation node. In addition, a small capacitance, CLEAD, in
parallel with resistor R2, compensates for the capacitance at the
inverting input of the amplifier.
Figure 35. Simplified Schematic
The input stage drives a folded cascode that consists of a fast pair of
PNP transistors. These PNPs drive a current mirror that provides a
differential-input-to-single-ended-output conversion. The high
speed PNPs are also used in the current-amplifying output stage,
which provides a high current gain of 40,000. Even under heavy
loading conditions, the high fTs of the NPN and PNPs, produced
using the CB process, permit cascading two stages of emitter
followers while maintaining 60 phase margin at closed-loop
bandwidths greater than 50 MHz.
C
LEAD
R2
+V
7
S
50Ω
COAX
CABLE
0.1µF
R1
Two stages of complementary emitter followers also effectively
buffer the high impedance compensation node (at the CCOMP pin)
from the output so that the AD829 can maintain a high dc open-
loop gain, even into low load impedances (92 dB into a 150 Ω
load and 100 dB into a 1 kΩ load). Laser trimming and PTAT
biasing ensure low offset voltage and low offset voltage drift,
enabling the user to eliminate ac coupling in many applications.
V
2
3
–
IN
V
6
OUT
AD829
50Ω
5
+
1kΩ
C
COMP
4
0.1µF
–V
S
Figure 36. Inverting Amplifier Connection Using External Shunt
Compensation
For added flexibility, the AD829 provides access to the internal
frequency compensation node. This allows users to customize the
frequency response characteristics for a particular application.
+V
S
50Ω
CABLE
0.1µF
7
V
3
2
+
IN
V
6
OUT
AD829
50Ω
5
1kΩ
Unity-gain stability requires a compensation capacitance of 68 pF
(Pin 5 to ground), which yields a small signal bandwidth of
66 MHz and slew rate of 16 V/µs. The slew rate and gain
bandwidth product varies inversely with compensation
capacitance. Table 4 and Figure 37 show the optimum
compensation capacitance and the resulting slew rate for
a desired noise gain.
R2
–
C
4
COMP
C
LEAD
0.1µF
–V
S
R1
Figure 37. Noninverting Amplifier Connection Using External Shunt
Compensation
For gains between 1 and 20, choose CCOMP to keep the small signal
bandwidth relatively constant. The minimum gain that will still
provide stability depends on the value of the external
compensation capacitance.
Table 4 gives the recommended CCOMP and CLEAD values, as well
as the corresponding slew rates and bandwidth. The capacitor
values were selected to provide a small signal frequency response
with <1 dB of peaking and <10% overshoot. For Table 4, 15 V
Rev. I | Page ±2 of 20
Data Sheet
AD829
supply voltages should be used. Figure 38 is a graphical extension
of Table 4, which shows the slew rate/gain trade-off for lower
closed-loop gains, when using the shunt compensation scheme.
CCOMP is the compensation capacitance.
re is the inverse of the transconductance of the input transistors.
kT/q approximately equals 26 mV at 27°C.
100
10
1
1k
Because both fT and slew rate are functions of the same variables,
the dynamic behavior of an amplifier is limited. Because
2I
CCOMP
Slew Rate =
C
SLEW RATE
COMP
then
100
Slew Rate
fT
kT
q
= 4 π
This shows that the slew rate is only 0.314 V/µs for every mega-
hertz of bandwidth. The only way to increase the slew rate is to
increase the fT, and that is difficult because of process limitations.
Unfortunately, an amplifier with a bandwidth of 10 MHz can
only slew at 3.1 V/µs, which is barely enough to provide a full
power bandwidth of 50 kHz.
V
= ±15V
S
10
100
1
10
NOISE GAIN
Figure 38. Value of CCOMP and Slew Rate vs. Noise Gain
CURRENT FEEDBACK COMPENSATION
The AD829 is especially suited to a form of current feedback
compensation that allows for the enhancement of both the full
power bandwidth and the slew rate of the amplifier. The voltage
gain from the inverting input pin to the compensation pin is
large; therefore, if a capacitance is inserted between these pins,
the bandwidth of the amplifier becomes a function of its feed-
back resistor and the capacitance. The slew rate of the amplifier
is now a function of its internal bias (2I) and the compensation
capacitance.
Bipolar, nondegenerated, single-pole, and internally
compensated amplifiers have their bandwidths defined as
1
I
kT
fT
=
=
2 π re CCOMP
2 π
CCOMP
q
where:
fT is the unity-gain bandwidth of the amplifier.
I is the collector current of the input transistor.
Table 4. Component Selection for Shunt Compensation
Follower Gain Inverter Gain R1 (Ω) R2 (Ω) CLEAD (pF) CCOMP (pF) Slew Rate (V/µs) −3 dB Small Signal Bandwidth (MHz)
±
2
5
±0
20
25
±00
Open
± k
±00
± k
2.0 k
2.05 k
2 k
0
5
±
0
0
0
0
68
25
7
3
0
±6
38
90
±30
230
230
230
66
7±
76
65
55
39
7.5
−±
−4
−9
−±9
−24
−99
5±±
226
±05
±05
20
2.49
2 k
0
0
Rev. I | Page ±3 of 20
AD829
Data Sheet
Because the closed-loop bandwidth is a function of RF and
Figure 42 is an oscilloscope photo of the pulse response of a unity-
gain inverter that has been configured to provide a small signal
bandwidth of 53 MHz and a subsequent slew rate of 180 V/µs;
RF = 3 kΩ and CCOMP = 1 pF. Figure 43 shows the excellent pulse
response as a unity-gain inverter, this using component values
of RF = 1 kΩ and CCOMP = 4 pF.
CCOMP (see Figure 39), it is independent of the amplifier closed-
loop gain, as shown in Figure 41. To preserve stability, the time
constant of RF and CCOMP needs to provide a bandwidth of
<65 MHz. For example, with CCOMP = 15 pF and RF = 1 kΩ, the
small signal bandwidth of the AD829 is 10 MHz. Figure 40
shows that the slew rate is in excess of 60 V/µs. As shown in
Figure 41, the closed-loop bandwidth is constant for gains of
−1 to −4; this is a property of the current feedback amplifiers.
5V
200ns
100%
90
R
C
F
COMP
0.1µF
+V
S
50Ω
COAX
CABLE
7
R1
V
2
–
IN
5
V
6
OUT
AD829
C1*
10
R
50Ω
IN4148
L
3
+
4
1kΩ
0%
0.1µF
–V
S
*RECOMMENDED VALUE
C
SHOULD NEVER EXCEED
COMP
15pF FOR THIS CONNECTION
Figure 42. Large Signal Pulse Response of the Inverting Amplifier Using
Current Feedback Compensation, CCOMP = 1 pF, RF = 3 kΩ, R1 = 3 kΩ
OF C
FOR C1
COMP
<7pF
≥7pF
0pF
15pF
Figure 39. Inverting Amplifier Connection Using Current Feedback
Compensation
10ns
100%
90
5V
200ns
100%
90
10
0%
10
20mV
0%
Figure 43. Small Signal Pulse Response of Inverting Amplified Using Current
Feedback Compensation, CCOMP = 4 pF, RF = 1 kΩ, R1 = 1 kΩ
Figure 40. Large Signal Pulse Response of Inverting Amplifier Using Current
Feedback Compensation, CCOMP = 15 pF, C1 = 15 pF RF = 1 kΩ, R1 = 1 kΩ
15
GAIN = –4
12
–3dB @ 8.2MHz
9
GAIN = –2
6
–3dB @ 9.6MHz
3
GAIN = –1
0
–3dB @ 10.2MHz
–3
–6
V
V
R
R
C
= –30dBm
= ±15V
= 1kΩ
IN
S
–9
–12
–15
L
= 1kΩ
F
= 15pF
COMP
C1 = 15pF
100k
1M
10M
FREQUENCY (Hz)
100M
Figure 41. Closed-Loop Gain vs. Frequency for the Circuit of Figure 38
Rev. I | Page ±4 of 20
Data Sheet
AD829
+15V
Figure 44 and Figure 45 show the closed-loop frequency
response of the AD829 for different closed-loop gains and
different supply voltages.
0.1µF
50Ω
COAX
CABLE
50Ω
7
COAX
CABLE
V
3
2
+
IN
15
50Ω
2kΩ
2kΩ
6
V
AD829
OUT
GAIN = –4
12
50Ω
C
= 2pF
5
–
COMP
50kΩ
9
6
4
3pF
COMP
GAIN = –2
= 3pF
C
–15V
C
COMP
0.1µF
3
GAIN = –1
= 4pF
0
C
COMP
–3
–6
–9
–12
–15
Figure 46. Noninverting Amplifier Connection Using Current Feedback
Compensation
V
R
R
= ±15V
= 1kΩ
= 1kΩ
S
L
+15V
F
V
= –30dBm
IN
0.1µF
1
10
100
50Ω
COAX
CABLE
7
FREQUENCY (MHz)
V
3
2
+
IN
75Ω
Figure 44. Closed-Loop Frequency Response for the Inverting Amplifier Using
Current Feedback Compensation
6
V
AD829
OUT
75Ω
75Ω
4
–
5
–17
–20
–23
0.1µF
300Ω
300Ω
30pF
COMP
OPTIONAL
–15V
C
2pF TO 7pF
FLATNESS
TRIM
±5V
–26
±15V
Figure 47. Video Line Driver with a Flatness over Frequency Adjustment
–29
–32
–35
–38
LOW ERROR VIDEO LINE DRIVER
The buffer circuit shown in Figure 47 drives a back-terminated
75 Ω video line to standard video levels (1 V p-p), with 0.1 dB
gain flatness to 30 MHz and with only 0.04° and 0.02% differential
phase and gain at the 4.43 MHz PAL color subcarrier frequency.
This level of performance, which meets the requirements for
high definition video displays and test equipment, is achieved
using only 5 mA quiescent current.
V
R
R
= –20dBm
= 1kΩ
= 1kΩ
IN
–41
–44
–47
L
F
GAIN = –1
C
= 4pF
COMP
1
10
100
FREQUENCY (MHz)
Figure 45. Closed-Loop Frequency Response vs. Supply for the Inverting
Amplifier Using Current Feedback Compensation
When a noninverting amplifier configuration using a current
feedback compensation is needed, the circuit shown in Figure 46 is
recommended. This circuit provides a slew rate twice that of the
shunt compensated noninverting amplifier of Figure 47 at the
expense of gain flatness. Nonetheless, this circuit delivers 95 MHz
bandwidth with 1 dB flatness into a back-terminated cable,
with a differential gain error of only 0.01% and a differential
phase error of only 0.015 at 4.43 MHz.
Rev. I | Page ±5 of 20
AD829
Data Sheet
The input amplifiers operate at a gain of 20, while the output
op amp runs at a gain of 5. In this circuit, the main bandwidth
limitation is the gain/bandwidth product of the output amplifier.
Extra care should be taken while breadboarding this circuit
because even a couple of extra picofarads of stray capacitance at the
compensation pins of A1 and A2 will degrade circuit bandwidth.
HIGH GAIN VIDEO BANDWIDTH, 3-OP-AMP
INSTRUMENTATION AMPLIFIER
Figure 48 shows a 3-op-amp instrumentation amplifier circuit
that provides a gain of 100 at video bandwidths. At a circuit gain of
100, the small signal bandwidth equals 18 MHz into a FET probe.
Small signal bandwidth equals 6.6 MHz with a 50 Ω load. The
0.1% settling time is 300 ns.
3pF
5
(G = 20)
2pF TO 8pF
SETTLING TIME
AC CMR ADJUST
+V
3
2
IN
A1
AD829
6
1kΩ
2kΩ
1pF
200Ω
200Ω
2
A3
AD848
R
210Ω
G
6
1pF
2kΩ
3
INPUT
FREQUENCY CMRR
(G = 5)
5
2kΩ
3pF
100Hz
1MHz
10MHz
64.6dB
44.7dB
23.9dB
970Ω
2
3
DC CMR
ADJUST
A2
AD829
6
+V
+15V
COMM
–15V
PIN 7
S
50Ω
10µF
10µF
0.1µF
0.1µF
1µF
1µF
0.1µF
0.1µF
+V
IN
(G = 20)
5
EACH
AMPLIFIER
3pF
4000Ω
CIRCUIT GAIN =
+ 1 5
R
G
–V
PIN 4
S
Figure 48. High Gain Video Bandwidth, 3-Op-Amp In-Amp Circuit
Rev. I | Page ±6 of 20
Data Sheet
AD829
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 49. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-8)
Dimensions shown in millimeters and (inches)
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
8
1
5
4
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.210 (5.33)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
PLANE
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 50. 8-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-8)
Dimensions shown in inches and (millimeters)
Rev. I | Page ±7 of 20
AD829
Data Sheet
0.005 (0.13)
MIN
0.055 (1.40)
MAX
8
5
0.310 (7.87)
0.220 (5.59)
1
4
0.100 (2.54) BSC
0.405 (10.29) MAX
0.320 (8.13)
0.290 (7.37)
0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
MAX
0.150 (3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
0.023 (0.58)
0.014 (0.36)
15°
0°
0.070 (1.78)
0.030 (0.76)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 51. 8-Lead Ceramic Dual In-Line [CERDIP]
(Q-8)
Dimensions shown in inches and (millimeters)
0.200 (5.08)
0.075 (1.91)
REF
REF
0.100 (2.54)
0.064 (1.63)
0.100 (2.54) REF
0.095 (2.41)
0.015 (0.38)
MIN
0.075 (1.90)
3
19
18
20
4
8
0.028 (0.71)
0.022 (0.56)
1
0.358 (9.09)
0.342 (8.69)
SQ
0.358
0.011 (0.28)
0.007 (0.18)
R TYP
(9.09)
MAX
SQ
BOTTOM
VIEW
0.050 (1.27)
BSC
14
0.075 (1.91)
13
9
REF
45° TYP
0.088 (2.24)
0.054 (1.37)
0.055 (1.40)
0.045 (1.14)
0.150 (3.81)
BSC
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 52. 20-Terminal Ceramic Leadless Chip Carrier [LCC]
(E-20-1)
Dimensions shown in inches and (millimeters)
Rev. I | Page ±8 of 20
Data Sheet
AD829
ORDERING GUIDE
Model±
AD829AR
AD829AR-REEL
AD829AR-REEL7
AD829ARZ
AD829ARZ-REEL
AD829ARZ-REEL7
AD829JN
Temperature Range
−40°C to +±25°C
−40°C to +±25°C
−40°C to +±25°C
−40°C to +±25°C
−40°C to +±25°C
−40°C to +±25°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
−40°C to +±25°C
−55°C to +±25°C
−55°C to +±25°C
−55°C to +±25°C
−55°C to +±25°C
−55°C to +±25°C
Package Description
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead PDIP
Package Option
R-8
R-8
R-8
R-8
R-8
R-8
N-8
N-8
R-8
R-8
R-8
R-8
R-8
AD829JNZ
AD829JR
8-Lead PDIP
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead CERDIP
8-Lead CERDIP
8-Lead CERDIP
8-Lead CERDIP
20-Lead LCC
AD829JR-REEL
AD829JR-REEL7
AD829JRZ
AD829JRZ-REEL
AD829JRZ-REEL7
AD829AQ
R-8
Q-8
Q-8
Q-8
Q-8
E-20-±
E-20-±
AD829SQ
AD829SQ/883B
5962-93±290±MPA
AD829SE/883B
5962-93±290±M2A
AD829JCHIPS
AD829SCHIPS
AD829AR-EBZ
20-Lead LCC
Die
Die
Evaluation Board
± Z = RoHS Compliant Part.
Rev. I | Page ±9 of 20
AD829
NOTES
Data Sheet
©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00880-0-10/11(I)
Rev. I | Page 20 of 20
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