AD8307-EB [ADI]
Low Cost DC-500 MHz, 92 dB Logarithmic Amplifier; 低成本DC - 500 MHz的92分贝对数放大器
| 型号： | AD8307-EB |
| 厂家： | 
ADI |
| 描述： | Low Cost DC-500 MHz, 92 dB Logarithmic Amplifier |
| 文件： | 总20页 (文件大小：397K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Cost DC-500 MHz, 92 dB
Logarithmic Amplifier
a
AD8307
FEATURES
FUNCTIO NAL BLO CK D IAGRAM
Com plete Multistage Logarithm ic Am plifier
92 dB Dynam ic Range: –75 dBm to +17 dBm
to –90 dBm Using Matching Netw ork
Single Supply of 2.7 V Min at 7.5 m A Typical
DC-500 MHz Operation, ؎1 dB Linearity
Slope of 25 m V/ dB, Intercept of –84 dBm
Highly Stable Scaling Over Tem perature
Fully Differential DC-Coupled Signal Path
100 ns Pow er-Up Tim e, 150 A Sleep Current
AD8307
BANDGAP REFERENCE
AND BIASING
VPS
ENB
INT
SUPPLY
7.5mA
ENABLE
INT. ADJ
SIX 14.3dB 900MHz
AMPLIFIER STAGES
INP
1.15k⍀
+INPUT
–INPUT
MIRROR
INM
2A
/dB
3
OUT
OUTPUT
2
NINE DETECTOR CELLS
SPACED 14.3dB
12.5k⍀
APPLICATIONS
COMMON
COM
COM
Conversion of Signal Level to Decibel Form
Transm itter Antenna Pow er Measurem ent
Receiver Signal Strength Indication (RSSI)
Low Cost Radar and Sonar Signal Processing
Netw ork and Spectrum Analyzers (to 120 dB)
Signal Level Determ ination Dow n to 20 Hz
True Decibel AC Mode for Multim eters
OFS
INPUT-OFFSET
COMPENSATION LOOP
OFS. ADJ.
T he output is a voltage scaled 25 mV/dB, generated by a current
of nominally 2 µA/dB through an internal 12.5 kΩ resistor. T his
voltage varies from 0.25 V at an input of –74 dBm (that is, the
ac intercept is at –84 dBm, a 20 µV rms sine input), up to 2.5 V
for an input of +16 dBm. This slope and intercept can be trimmed
using external adjustments. Using a 2.7 V supply, the output
scaling may be lowered, for example to 15 mV/dB, to permit
utilization of the full dynamic range.
P RO D UCT D ESCRIP TIO N
The AD8307 is the first logarithmic amplifier in an 8-lead (SO-8)
package. It is a complete 500 MHz monolithic demodulating
logarithmic amplifier based on the progressive compression
(successive detection) technique, providing a dynamic range of
92 dB to ±3 dB law-conformance and 88 dB to a tight ±1 dB
error bound at all frequencies up to 100 MHz. It is extremely
stable and easy to use, requiring no significant external compo-
nents. A single supply voltage of 2.7 V to 5.5 V at 7.5 mA is
needed, corresponding to an unprecedented power consumption
of only 22.5 mW at 3 V. A fast-acting CMOS-compatible con-
trol pin can disable the AD8307 to a standby current of under
150 µA.
T he AD8307 exhibits excellent supply insensitivity and tem-
perature stability of the scaling parameters. T he unique combi-
nation of low cost, small size, low power consumption, high
accuracy and stability, very high dynamic range, and a frequency
range encompassing audio through IF to UHF, make this prod-
uct useful in numerous applications requiring the reduction of a
signal to its decibel equivalent.
Each of the cascaded amplifier/limiter cells has a small-signal
gain of 14.3 dB, with a –3 dB bandwidth of 900 MHz. T he
input is fully differential and at a moderately high impedance
(1.1 kΩ in parallel with about 1.4 pF). T he AD8307 provides a
basic dynamic range extending from approximately –75 dBm
(where dBm refers to a 50 Ω source, that is, a sine amplitude of
about ±56 µV) up to +17 dBm (a sine amplitude of ±2.2 V).
A simple input-matching network can lower this range to –88 dBm
to +3 dBm. T he logarithmic linearity is typically within ±0.3 dB
up to 100 MHz over the central portion of this range, and is
degraded only slightly at 500 MHz. T here is no minimum
frequency limit; the AD8307 may be used at audio frequencies
(20 Hz) or even lower.
T he AD8307 is available in the industrial temperature range of
–40°C to +85°C, and in 8-lead SOIC and PDIP packages.
REV. A
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 781/ 329-4700
Fax: 781/ 326-8703
World Wide Web Site: http:/ / w w w .analog.com
© Analog Devices, Inc., 1999
(V = +5 V, T = 25؇C, R ≥ 1 M⍀, unless otherwise noted)
AD8307–SPECIFICATIONS
S
A
L
P aram eter
Conditions
Min
Typ
Max
Units
GENERAL CHARACT ERIST ICS
Input Range (±1 dB Error)
Logarithmic Conformance
Expressed in dBm re 50 Ω
f ≤ 100 MHz, Central 80 dB
f = 500 MHz, Central 75 dB
Unadjusted1
–72
16
±1
dBm
dB
dB
mV/dB
mV/dB
µV
±0.3
±0.5
25
Logarithmic Slope
vs. T emperature
Logarithmic Intercept
23
23
27
27
Sine Amplitude; Unadjusted2
20
Equivalent Sine Power in 50 Ω
–87
–88
–84
–77
–76
dBm
dBm
nV/√Hz
dBm
kΩ
vs. T emperature
Input Noise Spectral Density
Operating Noise Floor
Output Resistance
Inputs Shorted
RSOURCE = 50 Ω/2
Pin 4 to Ground
1.5
–78
12.5
3.5
10
15
Internal Load Capacitance
Response T ime
pF
Small Signal, 10%-90%,
0 mV–100 mV, CL = 2 pF
Large Signal, 10%-90%,
0 V–2.4 V, CL = 2 pF
400
ns
500
ns
Upper Usable Frequency3
Lower Usable Frequency
500
10
MHz
Hz
Input AC-Coupled
–3 dB
AMPLIFIER CELL CHARACT ERIST ICS
Cell Bandwidth
Cell Gain
900
14.3
MHz
dB
INPUT CHARACT ERIST ICS
DC Common-Mode Voltage
Common-Mode Range
Inputs AC-Coupled
Either Input (Small Signal)
RSOURCE ≤ 50 Ω
Drift
Differential
Either Pin to Ground
Either Input
3.2
1.6
50
0.8
1.1
1.4
10
V
V
µV
µV/°C
kΩ
pF
–0.3
VS – 1
500
DC Input Offset Voltage4
Incremental Input Resistance
Input Capacitance
Bias Current
25
µA
POWER INT ERFACES
Supply Voltage
Supply Current
Disabled
2.7
5.5
10
750
V
mA
µA
VENB ≥ 2 V
VENB ≤ 1 V
8
150
NOT ES
1T his may be adjusted downward by adding a shunt resistor from the Output to Ground. A 50 k Ω resistor will reduce the nominal slope to 20 mV/dB.
2T his may be adjusted in either direction by a voltage applied to Pin 5, with a scale factor of 8 dB/V.
3See Application on 900 MHz operation.
4Normally nulled automatically by internal offset correction loop. May be manually nulled by a voltage applied between Pin 3 and Ground; see APPLICAT IONS.
Specifications subject to change without notice.
–2–
REV. A
AD8307
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. T his is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may effect device reliability.
ABSO LUTE MAXIMUM RATINGS*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.5 V
Input Voltage (Pins 1, 8) . . . . . . . . . . . . . . . . . . . . . . VSUPPLY
Storage T emperature Range, N, R . . . . . . . . –65°C to +125°C
Ambient T emperature Range, Rated Performance Industrial,
AD8307AN, AD8307AR . . . . . . . . . . . . . –40°C to +85°C
Lead T emperature Range (Soldering 10 sec) . . . . . . . +300°C
O RD ERING GUID E
Model
Tem perature Range
P ackage D escriptions
P ackage O ptions
AD8307AR
AD8307AN
AD8307AR-REEL
AD8307AR-REEL7
AD8307-EB
–40°C to +85°C
–40°C to +85°C
SOIC
SO-8
N-8
Plastic DIP
13" REEL
7" REEL
Evaluation Board
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8307 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. T herefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
P IN CO NFIGURATIO N
P IN FUNCTIO N D ESCRIP TIO NS
Nam e Function
P in
1
2
3
4
8
7
6
5
INP
INM
COM
OFS
1
INM
Signal Input, Minus Polarity; Normally at
POS/2.
AD8307
TOP VIEW
(Not to Scale)
VPS
ENB
INT
V
2
3
COM
OFS
Common Pin (Usually Grounded).
Offset Adjustment; External Capacitor
Connection.
OUT
4
OUT
Logarithmic (RSSI) Output Voltage; ROUT
12.5 kΩ.
=
5
6
INT
ENB
Intercept Adjustment; ±6 dB (See T ext).
CMOS-compatible Chip Enable; Active when
“HI.”
7
8
VPS
INP
Positive Supply, 2.7 V–5.5 V.
Signal Input, Plus Polarity; Normally at VPOS
/
2. Note: Due to the symmetrical nature of the
response, there is no special significance to the
sign of the two input pins. DC resistance from
INP to INM = 1.1 kΩ.
REV. A
–3–
AD8307–Typical Performance Characteristics
3
2
8
7
6
5
4
3
2
1
0
1
TEMPERATURE ERROR @ +85؇C
TEMPERATURE ERROR @ +25؇C
0
–1
–2
–3
TEMPERATURE ERROR @ –40؇C
–80
–60
–40
–20
0
20
1.0
1.2
1.7
1.8
2.0
1.1
1.3
1.4
V
1.5
1.6
1.9
INPUT LEVEL – dBm
– Volts
ENB
Figure 1. Supply Current vs. VENB Voltage (5 V)
Figure 4. Log Conform ance vs. Input Level (dBm ) at 25 °C,
85°C, –40°C
3
8
7
6
5
4
3
2
1
0
INPUT FREQUENCY 10MHz
2
INPUT FREQUENCY 100MHz
1
0
INPUT FREQUENCY 300MHz
INPUT FREQUENCY 500MHz
1.2
1.3
1.5
1.6
1.7
1.8
1.9
–80
–60
–40
–20
0
20
1.0
1.1
1.4
V
2.0
– Volts
INPUT LEVEL – dBm
ENB
Figure 2. Supply Current vs. VENB Voltage (3 V)
Figure 5. VOUT vs. Input Level (dBm ) at Various Frequencies
3
2
1.5
1.0
1
0.5
FREQUENCY INPUT = 300MHz
CFO VALUE = 0.01F
0
0
CFO VALUE = 1F
–1
–0.5
CFO VALUE = 0.1F
FREQUENCY INPUT = 100MHz
–2
–1.0
–3
–80
– 1.5
–60
–40
–20
0
20
– 80
– 60
– 40
– 20
0
20
INPUT LEVEL – dBm
INPUT LEVEL – dBm
Figure 3. Log Conform ance vs. Input Level (dBm ) @
100 MHz, 300 MHz
Figure 6. Log Conform ance vs. CFO Values at 1 kHz Input
Frequency
REV. A
–4–
AD8307
3
2
3.0
2.5
2.0
1.5
1.0
0.5
0
INT P = 3.0V
IN
10MHz, INT = –96.52dBm
100MHz
1
INT P = 4.0V
10MHz, INT = –87.71dBm
IN
+ INPUT
0
–1
–2
–3
NO CONNECT ON INT
10MHz, INT = –82.90dBm
– INPUT
–80
–60
–40
–20
0
20
–80 –70 –60 –50 –40 –30 –20 –10
0
10
20
INPUT LEVEL – dBm
INPUT LEVEL – dBm
Figure 7. VOUT vs. Input Level at 5 V Supply; Showing
Intercept Adjustm ent
Figure 10. Log Conform ance vs. Input Level at 100 MHz;
Showing Response to Alternative Inputs
3
3.0
INT VOLTAGE
INT = 1.0V, INT = –86dBm
2.5
2
500MHz
2.0
1
0
INT VOLTAGE
INT NO CONNECT, INT = –71dBm
1.5
1.0
–1
100MHz
0.5
–2
–3
INT VOLTAGE
INT = 2.0V, INT = –78dBm
0
–80
–90
–70
–50
–30
–10
10
–70 –60
–50 –40
–30 –20
–10
0
10
INPUT LEVEL – dBm
INPUT LEVEL – dBm
Figure 8. VOUT vs. Input Level at 3 V Supply Using AD820
as Buffer, Gain = +2; Showing Intercept Adjustm ent
Figure 11. Log Conform ance vs. Input at 100 MHz, 500 MHz;
Input Driven Differentially Using Transform er
3
2.5
2.0
2
500MHz
1
1.5
100MHz @ –40؇C
0
100MHz
1.0
0.5
0
100MHz @ +25؇C
–1
10MHz
–2
–3
100MHz @ +85؇C
–70
–60
–50
–40
–30
–20
–10
0
10
20
–80
–60
–40
–20
0
20
INPUT LEVEL – dBm
INPUT LEVEL – dBm
Figure 9. VOUT vs. Input Level at Three Tem peratures
(–40°C, +25°C, +85°C)
Figure 12. Log Conform ance vs. Input Level at 3 V Supply
Using AD820 as Buffer, Gain = +2
REV. A
–5–
AD8307
2V
V
CH 1
OUT
Ch1 500mV
Ch1 200mV
V
OUT
CH 1
CH 1 GND
V
ENB
INPUT SIGNAL
CH 2
CH 2
CH 2 GND
GND
Ch2 1.00V
200ns
Ch2 2.00V
500ns
Figure 16. VOUT Rise Tim e
Figure 13. Power-Up Response Tim e
Ch1 500mV
Ch1 200mV
V
CH 1
OUT
2.5V
INPUT SIGNAL
CH 2
CH 2 GND
V
ENB
CH 2
V
OUT
CH 1
CH 1 GND
GND
Ch2 1.00V
200ns
Ch2 2.00V
500ns
Figure 17. Large Signal Response Tim e
Figure 14. Power-Down Response Tim e
HP8648B
EXT TRIG
OUT
10MHz REF CLK
PULSE MODE IN
TRIG
OUT
SIGNAL
GENERATOR
PULSE
MODULATION
MODE
HP8112A
PULSE
GENERATOR
VPS = +5.0V
HP8648B
SIGNAL
HP8112A
PULSE
SYNCH OUT
0.1F
VPS = +5.0V
0.1F
GENERATOR
GENERATOR
1nF
RF OUT
OUT
RF OUT
1nF
NC
NC
INP VPS ENB INT
AD8307
52.3⍀
INP VSP ENB INT
AD8307
52.3⍀
INM COM OFS OUT
INM COM OFS OUT
TEK744A
SCOPE
NC
TRIG
TEK744A
SCOPE
TEK P6139A
10x PROBE
NC
1nF
TEK P6204
FET PROBE
TRIG
1nF
NC = NO CONNECT
NC = NO CONNECT
Figure 18. Test Setup For VOUT Pulse Response
Figure 15. Test Setup For Power-Up/Power-Down
Response Tim e
REV. A
–6–
AD8307
LO G AMP TH EO RY
continue indefinitely in both directions. T he dotted line shows
that the effect of adding an offset voltage VSHIFT to the output is
to lower the effective intercept voltage VX. Exactly the same
alteration could be achieved raising the gain (or signal level)
ahead of the log amp by the factor VSHIFT /VY. For example, if
VY is 500 mV per decade (that is, 25 mV/dB, as for the AD8307),
an offset of +150 mV added to the output will appear to lower
the intercept by two tenths of a decade, or 6 dB. Adding an
offset to the output is thus indistinguishable from applying an
input level that is 6 dB higher.
Logarithmic amplifiers perform a more complex operation than
that of classical linear amplifiers, and their circuitry is signifi-
cantly different. A good grasp of what log amps do, and how
they do it, will avoid many pitfalls in their application. T he
essential purpose of a log amp is not to amplify, though amplifi-
cation is utilized to achieve the function. Rather, it is to com-
press a signal of wide dynamic range to its decibel equivalent. It
is thus a measurement device. A better term might be logarith-
mic converter, since its basic function is the conversion of a
signal from one domain of representation to another, via a precise
nonlinear transformation.
T he log amp function described by Equation 1 differs from that
of a linear amplifier in that the incremental gain ∂VOUT /∂VIN is a
very strong function of the instantaneous value of VIN, as is
apparent by calculating the derivative. For the case where the
logarithmic base is e, we have:
Logarithmic compression leads to situations that may be con-
fusing or paradoxical. For example, a voltage offset added to
the output of a log amp is equivalent to a gain increase ahead of
its input. In the usual case where all the variables are voltages,
and regardless of the particular structure, the relationship between
the variables can be expressed as:
∂V
VY
OUT
=
(2)
∂VIN
VIN
VOUT = VY log (VIN /VX)
where:
VOUT is the output voltage,
(1)
T hat is, the incremental gain is inversely proportional to the
instantaneous value of the input voltage. T his remains true for
any logarithmic base, which is chosen as 10 for all decibel-
related purposes. It follows that a perfect log amp would be
required to have infinite gain under classical small-signal (zero-
amplitude) conditions. Less ideally, this result indicates that,
whatever means are used to implement a log amp, accurate
response under small-signal conditions (that is, at the lower end
of the dynamic range) demands the provision of a very high
gain-bandwidth product. A further consequence of this high
gain is that, in the absence of an input signal, even very small
amounts of thermal noise at the input of a log amp will cause a
finite output for zero input, resulting in the response line curving
away from the ideal shown in Figure 19 toward a finite baseline,
which can be either above or below the intercept. Note that the
value given for this intercept may be an extrapolated value, in
which case the output may not cross zero, or even reach it, as is
the case for the AD8307.
VY is called the slope voltage; the logarithm is usually taken
to base-ten (in which case VY is also the volts-per-decade),
VIN is the input voltage,
and
VX is called the intercept voltage.
All log amps implicitly require two references, here VX and VY,
which determine the scaling of the circuit. T he absolute accu-
racy of a log amp cannot be any better than the accuracy of its
scaling references. Equation 1 is mathematically incomplete in
representing the behavior of a demodulating log amp such as
the AD8307, where VIN has an alternating sign. However, the
basic principles are unaffected, and we can safely use this as our
starting point in the analyses of log amp scaling which follow.
While Equation 1 is fundamentally correct, a simpler formula is
appropriate for specifying the calibration attributes of a log amp
like the AD8307, which demodulates a sine wave input:
V
OUT
5V
Y
4V
VOUT = VSLOPE (PIN – P0)
where:
(3)
Y
V
SHIFT
3V
2V
V
Y
Y
Y
LOWER INTERCEPT
VOUT is the demodulated and filtered baseband (video or
RSSI) output,
VSLOPE is the logarithmic slope, now expressed in volts/dB
(typically between 15 and 30 mV/dB),
LOG V
IN
PIN is the input power, expressed in decibels relative to some
reference power level,
V
= 0
OUT
–2
= 10 V
X
2
4
= 10 V
IN X
+80dBc
V
V
= V
X
0dBc
V
= 10 V
V
IN
IN
IN
X
–40dBc
+40dBc
and
–2V
P0 is the logarithmic intercept, expressed in decibels relative
Y
to the same reference level.
Figure 19. Ideal Log Am p Function
T he most widely used reference in RF systems is decibels above
1 mW in 50 Ω, written dBm. Note that the quantity (PIN – P0) is
just dB. T he logarithmic function disappears from the formula
because the conversion has already been implicitly performed in
stating the input in decibels. T his is strictly a concession to popu-
lar convention: log amps manifestly do not respond to power
(tacitly, power absorbed at the input), but, rather, to input
Figure 19 shows the input/output relationship of an ideal log
amp, conforming to Equation 1. T he horizontal scale is loga-
rithmic and spans a wide dynamic range, shown here as over
120 dB, or six decades. T he output passes through zero (the
log-intercept) at the unique value VIN = VX and would ideally
become negative for inputs below the intercept. In the ideal
case, the straight line describing VOUT for all values of VIN would
REV. A
–7–
AD8307
voltage. T he use of dBV (decibels with respect to 1 V rms) would
be more precise, though still incomplete, since waveform is
involved, too. Since most users think about and specify RF
signals in terms of power—even more specifically, in dBm re 50 Ω
—we will use this convention in specifying the performance of
the AD8307.
in the case of the AD8307, VY is traceable to an on-chip band-
gap reference, while VX is derived from the thermal voltage kT /q
and later temperature-corrected.
Let the input of an N-cell cascade be VIN, and the final output
VOUT . For small signals, the overall gain is simply AN. A six-
stage system in which A = 5 (14 dB) has an overall gain of
15,625 (84 dB). T he importance of a very high small-signal gain
in implementing the logarithmic function has been noted; how-
ever, this parameter is of only incidental interest in the design of
log amps.
P r ogr essive Com pr ession
Most high speed high dynamic range log amps use a cascade of
nonlinear amplifier cells (Figure 20) to generate the logarithmic
function from a series of contiguous segments, a type of piece-
wise-linear technique. T his basic topology immediately opens
up the possibility of enormous gain-bandwidth products. For
example, the AD8307 employs six cells in its main signal path,
each having a small-signal gain of 14.3 dB (×5.2) and a –3 dB
bandwidth of about 900 MHz; the overall gain is about 20,000
(86 dB) and the overall bandwidth of the chain is some 500 MHz,
resulting in the incredible gain-bandwidth product (GBW) of
10,000 GH z, about a million times that of a typical op amp.
T his very high GBW is an essential prerequisite to accurate
operation under small-signal conditions and at high frequencies.
Equation 2 reminds us, however, that the incremental gain will
decrease rapidly as VIN increases. T he AD8307 continues to
exhibit an essentially logarithmic response down to inputs as
small as 50 µV at 500 MHz.
From here onward, rather than considering gain, we will analyze
the overall nonlinear behavior of the cascade in response to a
simple dc input, corresponding to the VIN of Equation 1. For
very small inputs, the output from the first cell is V1 = AVIN
;
from the second, V2 = A2 VIN, and so on, up to VN = AN VIN. At
a certain value of VIN, the input to the Nth cell, VN–1, is exactly
equal to the knee voltage EK. T hus, VOUT = AEK and since there
are N–1 cells of gain A ahead of this node, we can calculate that
VIN = EK /AN–1. T his unique situation corresponds to the lin-log
transition, labeled 1 on Figure 22. Below this input, the cascade
of gain cells is acting as a simple linear amplifier, while for higher
values of VIN, it enters into a series of segments which lie on a
logarithmic approximation (dotted line).
STAGE 1
STAGE 2
STAGE N –1
STAGE N
V
OUT
V
(4A-3) E
(3A-2) E
(2A-1) E
AE
V
A
A
A
A
X
W
K
K
K
Figure 20. Cascade of Nonlinear Gain Cells
(A-1) E
K
T o develop the theory, we will first consider a slightly different
scheme to that employed in the AD8307, but which is simpler
to explain and mathematically more straightforward to analyze.
T his approach is based on a nonlinear amplifier unit, which we
may call an A/1 cell, having the transfer characteristic shown in
Figure 21. T he local small-signal gain ∂VOUT /∂VIN is A, main-
tained for all inputs up to the knee voltage EK, above which the
incremental gain drops to unity. The function is symmetrical: the
same drop in gain occurs for instantaneous values of VIN less
than –EK. T he large-signal gain has a value of A for inputs in the
range –EK ≤ VIN ≤ +EK, but falls asymptotically toward unity for
very large inputs. In logarithmic amplifiers based on this ampli-
fier function, both the slope voltage and the intercept voltage
must be traceable to the one reference voltage, EK. T herefore, in
this fundamental analysis, the calibration accuracy of the log amp
is dependent solely on this voltage. In practice, it is possible to
separate the basic references used to determine VY and VX and
RATIO
OF A
K
LOG V
IN
0
N–1
N–2
N–3
N–4
/A
E
/A
E
/A
E
/A
E
K
K
K
K
Figure 22. The First Three Transitions
Continuing this analysis, we find that the next transition occurs
when the input to the (N–1) stage just reaches EK; that is, when
VIN = EK /AN–2. T he output of this stage is then exactly AEK,
and it is easily demonstrated (from the function shown in Figure
21) that the output of the final stage is (2A–1) EK (labeled ➁ on
Figure 22). Thus, the output has changed by an amount (A–1)EK
for a change in VIN from EK /AN–1 to EK /AN–2, that is, a ratio
change of A. At the next critical point, labeled ➂, we find the
input is again A times larger and VOUT has increased to (3A–2)EK,
that is, by another linear increment of (A–1)EK. Further analysis
shows that right up to the point where the input to the first cell
is above the knee voltage, VOUT changes by (A–1)EK for a ratio
change of A in VIN. T his can be expressed as a certain fraction
of a decade, which is simply log10(A). For example, when A = 5
a transition in the piecewise linear output function occurs at
regular intervals of 0.7 decade (that is, log10(A), or 14 dB divided
by 20 dB). T his insight allows us to immediately write the Volts
per Decade scaling parameter, which is also the Scaling Voltage
VY, when using base-10 logarithms, as:
AE
K
SLOPE = 1
A/1
SLOPE = A
0
E
INPUT
K
A −1 EK
(
=
)
(
Linear Change in VOUT
Decades Change in VIN
VY
=
(4)
log10
A
)
Figure 21. The A/1 Am plifier Function
REV. A
–8–
AD8307
Note that only two design parameters are involved in determin-
ing VY, namely, the cell gain A and the knee voltage EK, while
N, the number of stages, is unimportant in setting the slope of
the overall function. For A = 5 and EK = 100 mV, the slope
would be a rather awkward 572.3 mV per decade (28.6 mV/dB).
A well designed log amp will have rational scaling parameters.
A EK
log10
VY
=
(6)
A
(
)
Preference for the A/0 style of log amp, over one using A/1 cells,
stems from several considerations. T he first is that an A/0 cell
can be very simple. In the AD8307 it is based on a bipolar-
transistor differential pair, having resistive loads RL and an
emitter current source, IE. T his will exhibit an equivalent knee-
voltage of EK = 2 kT /q and a small signal gain of A = IERL /EK.
T he large signal transfer function is the hyperbolic tangent (see
dotted line in Figure 23). T his function is very precise, and the
deviation from an ideal A/0 form is not detrimental. In fact, the
rounded shoulders of the tanh function beneficially result in a
lower ripple in the logarithmic conformance than that obtained
using an ideal A/0 function.
T he intercept voltage can be determined by using two pairs of
transition points on the output function (consider Figure 22).
T he result is:
EK
VX
=
(5)
N +1/ A−1
(
)
)
A(
For the case under consideration, using N = 6, we calculate
VZ = 4.28 µV. However, we need to be careful about the inter-
pretation of this parameter, since it was earlier defined as the
input voltage at which the output passes through zero (see Fig-
ure 19). But clearly, in the absence of noise and offsets, the
output of the amplifier chain shown in Figure 21 can be zero
when, and only when, VIN = 0. T his anomaly is due to the finite
gain of the cascaded amplifier, which results in a failure to maintain
the logarithmic approximation below the lin-log transition (point ➀
in Figure 22). Closer analysis shows that the voltage given by
Equation 5 represents the extrapolated, rather than actual,
intercept.
An amplifier built of these cells is entirely differential in struc-
ture and can thus be rendered very insensitive to disturbances
on the supply lines and, with careful design, to temperature
variations. T he output of each gain cell has an associated
transconductance (gm) cell, which converts the differential out-
put voltage of the cell to a pair of differential currents, which are
summed simply by connecting the outputs of all the gm (detec-
tor) stages in parallel. T he total current is then converted back
to a voltage by a transresistance stage, to generate the logarith-
mic output. T his scheme is depicted, in single-sided form, in
Figure 24.
D em odulating Log Am ps
Log amps based on a cascade of A/1 cells are useful in baseband
applications, because they do not demodulate their input signal.
However, baseband and demodulating log amps alike can be
made using a different type of amplifier stage, which we will call
an A/0 cell. Its function differs from that of the A/1 cell in that
the gain above the knee voltage EK falls to zero, as shown by the
solid line in Figure 23. T his is also known as the limiter func-
tion, and a chain of N such cells is often used to generate a
hard-limited output, in recovering the signal in FM and PM
modes.
2
3
4
AV
A V
A V
A V
IN
IN
IN
IN
A/0
A/0
A/0
A/0
V
V
LIM
IN
g
g
g
g
g
m
m
m
m
m
I
OUT
Figure 24. Log Am p Using A/0 Stages and Auxiliary Sum -
m ing Cells
T he chief advantage of this approach is that the slope voltage
may now be decoupled from the knee-voltage EK = 2 kT /q,
which is inherently PT AT . By contrast, the simple summation
of the cell outputs would result in a very high temperature coef-
ficient of the slope voltage given by Equation 6. T o do this, the
detector stages are biased with currents (not shown in the Fig-
ure) which are rendered stable with temperature. T hese are
derived either from the supply voltage (as in the AD606 and
AD608) or from an internal bandgap reference (as in the AD640
and AD8307). T his topology affords complete control over the
magnitude and temperature behavior of the logarithmic slope,
decoupling it completely from EK.
SLOPE = 0
AE
K
TANH
A/0
SLOPE = A
0
E
K
INPUT
Figure 23. A/0 Am plifier Functions (Ideal and Tanh)
The AD640, AD606, AD608, AD8307 and various other Analog
Devices communications products incorporating a logarithmic
IF amplifier all use this technique. It will be apparent that the
output of the last stage can no longer provide the logarithmic
output, since this remains unchanged for all inputs above the
limiting threshold, which occurs at VIN = EK /AN–1. Instead, the
logarithmic output is now generated by summing the outputs of
all the stages. T he full analysis for this type of log amp is only
slightly more complicated than that of the previous case. It is
readily shown that, for practical purpose, the intercept voltage
VX is identical to that given in Equation 5, while the slope
voltage is:
A further step is yet needed to achieve the demodulation response,
required when the log amp is to convert an alternating input
into a quasi-dc baseband output. T his is achieved by altering the
gm cells used for summation purposes to also implement the
rectification function. Early discrete log amps based on the
progressive compression technique used half-wave rectifiers.
T his made post-detection filtering difficult. T he AD640 was the
first commercial monolithic log amp to use a full-wave rectifier,
a practice followed in all subsequent Analog Devices types.
REV. A
–9–
AD8307
We can model these detectors as being essentially linear gm cells,
but producing an output current independent of the sign of the
voltage applied to the input of each cell. T hat is, they imple-
ment the absolute-value function. Since the output from the
later A/0 stages closely approximates an amplitude-symmetric
square wave for even moderate input levels (most stages of the
amplifier chain operate in a limiting mode), the current output
from each detector is almost constant over each period of the
input. Somewhat earlier detectors stages produce a waveform
having only very brief dropouts, while the detectors nearest the
input produce a low level almost-sinusoidal waveform at twice
the input frequency. T hese aspects of the detector system result
in a signal that is easily filtered, resulting in low residual ripple
on the output.
O ffset Contr ol
In a monolithic log amp, direct-coupling between the stages is
used for several reasons. First, this avoids the use of coupling
capacitors, which may typically have a chip area equal to that of
a basic gain cell, thus considerably increasing die size. Second,
the capacitor values predetermine the lowest frequency at which
the log amp can operate; for moderate values, this may be as
high as 30 MHz, limiting the application range. T hird, the para-
sitic (back-plate) capacitance lowers the bandwidth of the cell,
further limiting the applications.
But the very high dc gain of a direct-coupled amplifier raises a
practical issue. An offset voltage in the early stages of the chain
is indistinguishable from a ‘real’ signal. If it were as high as, say,
400 µV, it would be 18 dB larger than the smallest ac signal
(50 µV), potentially reducing the dynamic range by this amount.
T his problem is averted by using a global feedback path from
the last stage to the first, which corrects this offset in a similar
fashion to the dc negative feedback applied around an op amp.
T he high frequency components of the signal must, of course,
be removed, to prevent a reduction of the HF gain in the for-
ward path.
Inter cept Calibr ation
All monolithic log amps from Analog Devices include accurate
means to position the intercept voltage VX (or equivalent power
for a demodulating log amp). Using the scheme shown in Figure
24, the basic value of the intercept level departs considerably
from that predicted by the simpler analyses given earlier. How-
ever, the intrinsic intercept voltage is still proportional to EK,
which is PT AT (Equation 5). Recalling that the addition of an
offset to the output produces an effect which is indistinguishable
from a change in the position of the intercept, we can cancel the
left-right motion of VX resulting from the temperature variation of
EK by adding an offset having the required temperature behavior.
In the AD8307, this is achieved by an on-chip filter, providing
sufficient suppression of HF feedback to allow operation above
1 MHz. T o extend the range below this frequency, an external
capacitor may be added. T his permits the high pass corner to be
lowered to audio frequencies using a capacitor of modest value.
Note that this capacitor has no effect on the minimum signal
frequency for input levels above the offset voltage: this extends
down to dc (for a signal applied directly to the input pins). T he
offset voltage will vary from part to part; some will exhibit essen-
tially stable offsets of under 100 µV, without the benefit of an
offset adjustment.
T he precise temperature-shaping of the intercept-positioning
offset results in a log amp having stable scaling parameters,
making it a true measurement device, for example, as a cali-
brated Received Signal Strength Indicator (RSSI). In this appli-
cation, one is more interested in the value of the output for an
input waveform which is invariably sinusoidal. T he input level
may alternatively be stated as an equivalent power, in dBm, but
here we must step carefully. It is essential to know the load
impedance in which this power is presumed to be measured.
Extension of Range
T he theoretical dynamic range for the basic log amp shown in
Figure 24 is AN. For A = 5.2 (14.3 dB) and N = 6, it is 20,000
or 86 dB. T he actual lower end of the dynamic range is largely
determined by the thermal noise floor, measured at the input of
the chain of amplifiers. T he upper end of the range is extended
upward by the addition of top-end detectors. T he input signal is
applied to a tapped attenuator, and progressively smaller signals
are applied to three passive rectifying gm cells whose outputs are
summed with those of the main detectors. With care in design,
the extension to the dynamic range can be seamless over the full
frequency range. For the AD8307 it amounts to a further 27 dB.
In RF practice, it is generally safe to assume a reference imped-
ance of 50 Ω, in which 0 dBm (1 mW) corresponds to a sinusoi-
dal amplitude of 316.2 mV (223.6 mV rms). T he intercept may
likewise be specified in dBm. For the AD8307, it is positioned
at –84 dBm, corresponding to a sine amplitude of 20 µV. It is
important to bear in mind that log amps do not respond to
power, but to the voltage applied to their input.
T he AD8307 presents a nominal input impedance much higher
than 50 Ω (typically 1.1 kΩ at low frequencies). A simple input
matching network can considerably improve the sensitivity of
this type of log amp. T his will increase the voltage applied to the
input and thus alter the intercept. For a 50 Ω match, the voltage
gain is 4.8 and the whole dynamic range moves down by 13.6 dB
(see Figure 33). Note that the effective intercept is a function of
waveform. For example, a square-wave input will read 6 dB
higher than a sine wave of the same amplitude, and a Gaussian
noise input 0.5 dB higher than a sine wave of the same rms
value.
T he total dynamic range is thus theoretically 113 dB. T he speci-
fied range of 90 dB (–74 dBm to +16 dBm) is that for high
accuracy, calibrated operation, and includes the low end degra-
dation due to thermal noise, and the top end reduction due to
voltage limitations. T he additional stages are not, however,
redundant, but are needed to maintain accurate logarithmic
conformance over the central region of the dynamic range, and
in extending the usable range considerably beyond the specified
range. In applications where log-conformance is less demand-
ing, the AD8307 can provide over 95 dB of range.
REV. A
–10–
AD8307
P RO D UCT O VERVIEW
junction capacitances associated with them, due to active
devices or ESD protection; these may be neither accurate nor
stable. Component numbering in each of these interface dia-
grams is local.
T he AD8307 comprises six main amplifier/limiter stages, each
having a gain of 14.3 dB and small signal bandwidth of 900 MHz;
the overall gain is 86 dB with a –3 dB bandwidth of 500 MHz.
T hese six cells, and their associated gm-styled full-wave detec-
tors, handle the lower two-thirds of the dynamic range. T hree
top-end detectors, placed at 14.3 dB taps on a passive attenua-
tor, handle the upper third of the 90 dB range. Biasing for these
cells is provided by two references: one determines their gain;
the other is a bandgap circuit that determines the logarithmic
slope and stabilizes it against supply- and temperature-variations.
T he AD8307 may be enabled/disabled by a CMOS-compatible
level at ENB (Pin 6). T he first amplifier stage provides a low
voltage noise spectral density (1.5 nV/√Hz).
Enable Inter face
T he chip-enable interface is shown in Figure 26. T he currents
in the diode-connected transistors control the turn-on and turn-
off states of the bandgap reference and the bias generator, and
are a maximum of 100 µA when Pin 6 is taken to 5 V, under
worst case conditions. Left unconnected, or at a voltage below
1 V, the AD8307 will be disabled and consume a sleep current
of under 50 µA; tied to the supply, or a voltage above 2 V, it will
be fully enabled. T he internal bias circuitry is very fast (typically
<100 ns for either OFF or ON), and in practice the latency
period before the log amp exhibits its full dynamic range is more
likely to be limited by factors relating to the use of ac coupling
at the input or the settling of the offset-control loop (see follow-
ing sections).
T he differential current-mode outputs of the nine detectors are
summed and then converted to single-sided form in the output
stage, nominally scaled 2 µA/dB. T he logarithmic output voltage
is developed by applying this current to an on-chip 12.5 kΩ
resistor, resulting in a logarithmic slope of 25 mV/dB (i.e.,
500 mV/decade) at OUT . T his voltage is not buffered, allowing
the use of a variety of special output interfaces, including the
addition of post-demodulation filtering. T he last detector stage
includes a modification to temperature-stabilize the log intercept,
which is accurately positioned to make optimal use of the full
output voltage range available. T he intercept may be adjusted
using the pin INT , which adds or subtracts a small current to
the signal current.
AD8307
40k⍀
ENB
TO BIAS
STAGES
COM
Figure 26. Enable Interface
AD8307
VPS
VPS
ENB
BAND GAP REFERENCE
SUPPLY
7.5mA
ENABLE
INT. ADJ
AND BIASING
S
125⍀
SIX 14.3dB 900MHz
AMPLIFIER STAGES
INT
6k⍀
INP
1.1k⍀
COM
+INPUT
–INPUT
MIRROR
2k⍀
6k⍀
C
P
INM
2A
/dB
3
OUT
Q1
INP
INM
OUTPUT
2
NINE DETECTOR CELLS
SPACED 14.3dB
12.5k⍀
TOP-END
DETECTORS
4k⍀
C
D
~3k⍀
COMMON
COM
COM
Q2
OFS
INPUT– OFFSET
COMPENSATION LOOP
OFS. ADJ.
TYP +2.2V FOR
+3V SUPPLY,
+3.2V AT +5V
C
M
COM
I
E
COM
2.4mA
S
Figure 25. Main Features of the AD8307
T he last gain stage also includes an offset-sensing cell. T his
generates a bipolarity output current when the main signal path
has an imbalance due to accumulated dc offsets. T his current is
integrated by an on-chip capacitor (which may be increased in
value by an off-chip component, at OFS). T he resulting voltage
is used to null the offset at the output of the first stage. Since it
does not involve the signal input connections, whose ac coupling
capacitors otherwise introduce a second pole in the feedback
path, the stability of the offset correction loop is assured.
COM
Figure 27. Signal Input Interface
Input Inter face
Figure 27 shows the essentials of the signal input interface. CP
and CM are the parasitic capacitances to ground; CD is the dif-
ferential input capacitance, mostly due to Q1 and Q2. In most
applications both input pins are ac-coupled. T he switches S
close when Enable is asserted. When disabled, the inputs float,
bias current IE is shut off, and the coupling capacitors remain
charged. If the log amp is disabled for long periods, small leak-
age currents will discharge these capacitors. If they are poorly
matched, charging currents at power-up can generate a transient
input voltage which may block the lower reaches of the dynamic
range until it has become much less than the signal.
T he AD8307 is built on an advanced dielectrically-isolated
complementary bipolar process. Most resistors are thin-film
types having a low temperature coefficient of resistance (T CR)
and high linearity under large signal conditions. T heir absolute
tolerance will typically be within ±20%. Similarly, the capacitors
have a typical tolerance of ±15% and essentially zero tempera-
ture or voltage sensitivity. Most interfaces have additional small
REV. A
–11–
AD8307
In most applications, the signal will be single-sided, and may be
applied to either Pin 1 or Pin 8, with the other pin ac-coupled to
ground. Under these conditions, the largest input signal that can
be handled by the AD8307 is +10 dBm (sine amplitude of ±1 V)
when operating from a 3 V supply; a +16 dBm may be handled
using a 5 V supply. T he full 16 dBm may be achieved for sup-
plies down to 2.7 V, using a fully balanced drive. For frequencies
above about 10 MHz, this is most easily achieved using a matching
network (see below). Using such a network, having an inductor
at the input, the input transient noted above is eliminated. Occa-
sionally, it may be desirable to use the dc-coupled potential of
the AD8307. T he main challenge here is to present signals to
the log amp at the elevated common-mode input level, requiring
the use of low noise, low offset buffer amplifiers. Using dual
supplies of ±3 V, the input pins may operate at ground potential.
T he offset feedback is limited to a range ±400 µV; signals larger
than this override the offset control loop, which only impacts
performance for very small inputs. An external capacitor re-
duces the high pass corner to arbitrarily low frequencies; using
1 µF this corner is below 10 Hz. All ADI log amps use an offset-
nulling loop; the AD8307 differs in using this single-sided form.
O utput Inter face
T he outputs from the nine detectors are differential currents,
having an average value that is dependent on the signal input
level, plus a fluctuation at twice the input frequency. T he cur-
rents are summed at nodes LGP and LGN in Figure 29. Fur-
ther currents are added at these nodes, to position the intercept,
by slightly raising the output for zero input, and to provide
temperature compensation. Since the AD8307 is not laser-
trimmed, there is a small uncertainty in both the log slope and
the log intercept. T hese scaling parameters may be adjusted (see
below).
O ffset Inter face
T he input-referred dc offsets in the signal path are nulled via the
interface associated with Pin 3, shown in Figure 28. Q1 and Q2
are the first stage input transistors, with their corresponding
load resistors (125 Ω). Q3 and Q4 generate small currents,
which can introduce a dc offset into the signal path. When the
voltage on OFS is at about 1.5 V, these currents are equal, and
nominally 16 µA. When OFS is taken to ground, Q4 is off and
the effect of the current in Q3 is to generate an offset voltage of
16 µA × 125 Ω = 2 mV. Since the first stage gain is ×5, this is
equivalent to a input offset (INP to INM) of 400 µV. When
OFS is taken to its most positive value, the input-referred offset
is reversed, to –400 µV. If true dc-coupling is needed, down to
very small inputs, this automatic loop must be disabled, and the
residual offset eliminated using a manual adjustment, as explained
in the next section.
For zero-signal conditions, all the detector output currents are
equal. For a finite input, of either polarity, their difference is
converted by the output interface to a single-sided unipolar
current nominally scaled 2 µA/dB (40 µA/decade), at the output
pin OUT . An on-chip 12.5 kΩ resistor, R1, converts this cur-
rent to a voltage of 25 mV/dB. C1 and C2 are effectively in
shunt with R1 and form a low-pass filter pole, with a corner
frequency of about 5 MHz. T he pulse response settles to within
1% of the final value within 300 ns. T his integral low-pass filter
provides adequate smoothing in many IF applications. At
10.7 MHz, the 2f ripple is 12.5 mV in amplitude, equivalent to
±0.5 dB, and only 0.5 mV (±0.02 dB) at f = 50 MHz. A filter
capacitor CFLT added from OUT to ground will lower this cor-
ner frequency. Using 1 µF, the ripple is maintained to less than
±0.5 dB down to input frequencies of 100 Hz. Note that COFS
(above) should also be increased in low frequency applications,
In normal operation, however, using an ac-coupled input signal,
the OFS pin should be left open. Any residual input-offset volt-
age is then automatically nulled by the action of the feedback
loop. T he gm cell, which is gated off when the chip is disabled,
converts any output offset (sensed at a point near the end of the
cascade of amplifiers) to a current. T his is integrated by the on-
and will typically be made equal to CFLT
.
It may be desirable to increase the speed of the output response,
with the penalty of increased ripple. One way to do this is sim-
ply by connecting a shunt load resistor from OUT to ground,
which raises the low pass corner frequency. T his also alters the
logarithmic slope, for example to 7.5 mV/dB using a 5.36 kΩ
resistor, while reducing the 10%-90% rise time to 25 ns. T he
ripple amplitude for 50 MHz input remains 0.5 mV, but this is
now equivalent to ±0.07 dB. If a negative supply is available,
the output pin may be connected directly to the summing
node of an external op amp connected as an inverting-mode
transresistance stage.
chip capacitor CHP, plus any added external capacitance COFS
,
so as to generate an error voltage, which is applied back to the
input stage in the polarity needed to null the output offset. From
a small-signal perspective, this feedback alters the response of
the amplifier, which, rather than behaving as a fully dc-coupled
system, now exhibits a zero in its ac transfer function, resulting
in a closed-loop high-pass corner at about 700 kHz.
VPS
125⍀
INPUT
STAGE
VPS
MAIN GAIN
TO LAST
1.25k⍀ 1.25k⍀
1.25k⍀ 1.25k⍀
3pF
FROM ALL
8.25k⍀
60k⍀
STAGES
DETECTOR
LGP
LGM
Q1
400mV
16A AT
BALANCE
S
DETECTORS
Q2
g
m
INT
2A/dB
0-220A
AVERAGE
ERROR
CURRENT
OFS
BIAS, 1.2V
Q3
36k⍀
Q4
25mV/dB
OUT
C
C
HP
OFS
48k⍀
C2
1pF
BIAS
COM
C1
2.5pF
R1
12.5k⍀
C
FLT
60A
Figure 28. Offset Interface and Offset-Nulling Path
COM
Figure 29. Sim plified Output Interface
REV. A
–12–
AD8307
USING TH E AD 8307
Figure 31 shows the output versus the input level, in dBm when
driven from a terminated 50 Ω generator, for sine inputs at
10 MHz, 100 MHz and 500 MHz; Figure 32 shows the typical
logarithmic conformance under the same conditions. Note that
+10 dBm corresponds to a sine amplitude of 1 V, equivalent to
an rms power of 10 mW in a 50 Ω termination. But if the termi-
nation resistor is omitted, the input power is negligible. T he use
of dBm to define input level therefore needs to be considered
carefully in connection with the AD8307.
T he AD8307 has very high gain and a bandwidth from dc to
over 1 GHz, at which frequency the gain of the main path is still
over 60 dB. Consequently, it is susceptible to all signals within
this very broad frequency range that find their way to the input
terminals. It is important to remember that these are quite indis-
tinguishable from the “wanted” signal, and will have the effect
of raising the apparent noise floor (that is, lowering the useful
dynamic range). For example, while the signal of interest may
be an IF of 50 MHz, any of the following could easily be larger
than the IF signal at the lower extremities of its dynamic range:
60 Hz hum, picked up due to poor grounding techniques; spuri-
ous coupling from a digital clock source on the same PC board;
local radio stations; etc.
3
2.5
10MHz
2
Careful shielding is essential. A ground plane should be used to
provide a low impedance connection to the common pin COM,
for the decoupling capacitor(s) used at VPS, and as the output
ground. It is inadvisable to assume that the ground plane is an
equipotential, however, and neither of the inputs should be ac-
coupled directly to the ground plane, but kept separate from it,
being returned instead to the low associated with the source.
T his may mean isolating the low side of an input connector with
a small resistance to the ground plane.
1.5
100MHz
1
500MHz
0.5
0
–80 –70 –60 –50 –40 –30 –20 –10
0
10
20
Basic Connections
INPUT LEVEL – dBm
Figure 30 shows the simple connections suitable for many appli-
cations. T he inputs are ac-coupled by C1 and C2, which should
have the same value, say, CC. T he coupling time-constant is RIN
CC/2, thus forming a high pass corner with a 3 dB attenuation at
fHP = 1/(p RIN CC ). In high frequency applications, fHP should
be as large as possible, in order to minimize the coupling of
unwanted low frequency signals. Conversely, in low frequency
applications, a simple RC network forming a low-pass filter
should be added at the input for the same reason. For the case
where the generator is not terminated, the signal range should
be expressed in terms of the voltage response, and extends from
–85 dBV to +6 dBV.
Figure 31. Log Response at 10 MHz, 100 MHz and 500 MHz
5
4
3
2
500MHz
1
0
10MHz
–1
–2
–3
–4
–5
100MHz
0.1F
4.7⍀
V , 2.7V – 5.5V
P
AT 8mA
C1 = C
C
NC
–80 –70 –60 –50
–30
INPUT LEVEL – dBm
–10
0
10
20
–40
–20
INP VPS ENB INT
R
INϷ
INPUT
–75dBm TO
+16dBm
R
AD8307
Figure 32. Logarithm ic Law Conform ance at 10 MHz,
100 MHz and 500 MHz
T
1.1k⍀
INM COM OFS OUT
OUTPUT
25mV/dB
NC
Input Matching
C2 = C
C
Where higher sensitivity is required, an input matching network
is valuable. Using a transformer to achieve the impedance trans-
formation also eliminates the need for coupling capacitors,
lowers the offset voltage generated directly at the input, and
balances the drives to INP and INM. T he choice of turns ratio
will depend somewhat on the frequency. At frequencies below
50 MHz, the reactance of the input capacitance is much higher
than the real part of the input impedance. In this frequency
range, a turns ratio of about 1:4.8 will lower the input imped-
ance to 50 Ω while raising the input voltage, and thus lowering
the effect of the short circuit noise voltage by the same factor.
T here will be a small contribution from the input noise current,
so the total noise will be reduced by a somewhat smaller factor.
T he intercept will also be lowered by the turns ratio; for a
50 Ω match, it will be reduced by 20 log10 (4.8) or 13.6 dB.
NC = NO CONNECT
Figure 30. Basic Connections
Where it is necessary to terminate the source at a low imped-
ance, the resistor RT should be added, with allowance for the
shunting effect of the basic 1.1 kΩ input resistance (RIN) of the
AD8307. For example, to terminate a 50 Ω source a 52.3 Ω 1%
tolerance resistor should be used. T his may be placed on the
input side or the log-amp side of the coupling capacitors; in the
former case, smaller capacitors can be used for a given fre-
quency range; in the latter case, the effective RIN is lowered
directly at the log-amp inputs.
REV. A
–13–
AD8307
Nar r ow-Band Matching
Table I. Narrow-Band Matching Values
T ransformer coupling is useful in broadband applications. How-
ever, a magnetically-coupled transformer may not be convenient
in some situations. At high frequencies, it is often preferable to
use a narrow-band matching network, as shown in Figure 33.
T his has several advantages. T he same voltage gain is achieved,
providing increased sensitivity, but now a measure of selectively
is also introduced. T he component count is low: two capacitors
and an inexpensive chip inductor. Further, by making these
capacitors unequal the amplitudes at INP and INM may be
equalized when driving from a single-sided source; that is, the
network also serves as a balun. Figure 34 shows the response for
a center frequency of 100 MHz; note the very high attenuation
at low frequencies. T he high-frequency attenuation is due to the
input capacitance of the log amp.
FC
MH z
ZIN
Ω
C1
pF
C2
pF
LM
nH
Voltage
Gain (dB)
10
45
44
46
50
57
57
50
54
160
82
150
75
27
13
8.2
6.8
5.6
3.3
3300
1600
680
330
220
150
100
39
13.3
13.4
13.4
13.4
13.2
12.8
12.3
10.9
20
50
30
100
150
200
250
500
15
10
7.5
6.2
3.9
10
103
102
99
98
101
95
100
51
22
11
7.5
5.6
4.3
2.2
91
5600
2700
1000
430
260
180
130
47
10.4
10.4
10.6
10.5
10.3
10.3
9.9
20
43
50
18
100
150
200
250
500
9.1
6.2
4.7
3.9
2.0
0.1F
4.7⍀
92
114
V , 2.7V – 5.5V
P
AT 8mA
6.8
C1
50⍀ INPUT
–88dBm TO
+3dBm
NC
Slope and Inter cept Adjustm ents
Where higher calibration accuracy is needed, the adjustments
shown in Figure 35 can be used, either singly or in combination.
T he log slope is lowered to 20 mV/dB by shunting the nominally
12.5 kΩ on-chip load resistor (see Figure 29) with 50 kΩ,
adjusted by VR1. T he calibration range is ±10% (18 mV/dB to
22 mV/dB), including full allowance for the variability in the
value of the internal load. T he adjustment may be made by
alternately applying two input levels, provided by an accurate
signal generator, spaced over the central portion of the log amp’s
dynamic range, for example –60 dBm and 0 dBm. An AM-
modulated signal, at the center of the dynamic range, can also
be used. For a modulation depth M, expressed as a fraction, the
decibel range between the peaks and troughs over one cycle of
the modulation period is given by:
INP VPS ENB INT
AD8307
L
M
Z
= 50⍀
IN
INM COM OFS OUT
OUTPUT
25mV/dB
NC
C2
NC = NO CONNECT
Figure 33. High Frequency Input Matching Network
14
13
12
11
GAIN
10
9
8
7
6
5
4
1+ M
∆ dB = 20 log10
(7)
1− M
For example, using an rms signal level of –40 dBm with a 70%
modulation depth (M = 0.7), the decibel range is 15 dB, as the
signal varies from –47.5 dBm to –32.5 dBm.
3
INPUT
2
1
0
T he log intercept is adjustable over a ±3 dB range, which is
sufficient to absorb the worst-case intercept error in the AD8307
plus some system-level errors. For greater range, set RS to zero.
VR2 is adjusted while applying an accurately known CW signal
near the lower end of the dynamic range, in order to minimize
the effect of any residual uncertainty in the slope. For example,
to position the intercept to –80 dBm, a test level of –65 dBm
may be applied and VR2 adjusted to produce a dc output of
15 dB above zero at 25 mV/dB, which is +0.3 V.
–1
60
70
80
90
100
110
120
130
140
150
FREQUENCY – MHz
Figure 34. Response of 100 MHz Matching Network
T able I provides solutions for a variety of center frequencies FC
and matching impedances ZIN of nominally 50 Ω and 100 Ω.
T he unequal capacitor values were chosen to provide a well-
balanced differential drive, and also to allow better centering of
the frequency response peak when using standard value compo-
nents; this generally results in a ZIN that is not exact. T he full
AD8307 HF input impedance and the inductor losses were
included in the modeling.
0.1F
4.7⍀
V , 2.7V – 5.5V
P
VR2
AT 8mA
R
50k⍀
S
C1 = C
C
؎3dB
INP VPS ENB INT
AD8307
INPUT
–75dBm TO
+16dBm
FOR V = 3V, R = 20k⍀
P
P
S
V
= 5V, R = 51k⍀
S
INM COM OFS OUT
C2 = C
C
20mV/dB
؎10%
NC
32.4k⍀
VR1
NC = NO CONNECT
50k⍀
Figure 35. Slope and Intercept Adjustm ents
REV. A
–14–
AD8307
0.1F
AP P LICATIO NS
4.7⍀
V
, 2.7–5.5V
P
T he AD8307 is a highly versatile and easily applied log amp
requiring very few external components. Most applications of
this product can be accommodated using the simple connec-
tions shown in the preceding section. A few examples of more
specialized applications are provided here.
VR2
50k⍀
(SEE FIGURE 36)
AD8031
R
S
2N3904
؎3dB
25mV/dB
INP VPS ENB INT
R
T
INPUT
–75dBm TO
+16dBm
(OPTIONAL)
AD8307
R2
3.01k⍀
Buffer ed O utput
INM COM OFS OUT
T he output may be buffered, and the slope optionally increased,
using an op amp. If the single-supply capability is to be pre-
served, a suitable component is the AD8031. Like the AD8307,
it is capable of operating from a 2.7 V supply and features a rail-
to-rail output capability; it is available in a 5-pin version and in
dual form as the 8-pin AD8032. Figure 36 shows how the slope
may be increased to 50 mV/dB (1 V per decade), requiring a 5 V
supply (90 dB times 50 mV is a 4.5 V swing). VR1 provides a
±10% slope adjustment; VR2 provides a ±3 dB intercept range.
With R2 = 4.99 kΩ, the slope is adjustable to 25 mV/dB, allow-
ing the use of a 2.7 V supply. Setting R2 to 80.6 kΩ, it is raised
to 100 mV/dB, providing direct reading in decibels on a digital
voltmeter. Since a 90 dB range now corresponds to a 9 V swing,
a supply of at least this amount is needed for the op amp.
OUTPUT
50⍀
MIN
10mV/dB ؎18%
VR1
NC
R1
2k⍀
5k⍀
6.34k⍀
COM
NC = NO CONNECT
Figure 37. Cable-Driving Log Am p
In Figure 38, the capacitor values were chosen for operation in
the audio field, providing a corner frequency of 10 Hz, an attenua-
tion of 80 dB/decade above this frequency, and a 1% settling
time of 150 ms (0.1% in 175 ms). T he residual ripple is 4 mV
(±0.02 dB) when the input to the AD8307 is at 20 Hz. T his
filter may easily be adapted to other frequencies, by proportional
scaling of C5–C7 (e.g., for 100 kHz use 100 pF). Placed ahead
of a digital multimeter, the convenient slope scaling of 100 mV/dB
requires only a repositioning of the decimal point to read directly
in decibels. The supply voltage for the filter must be large enough
to support the dynamic range; a minimum of 9 V is needed for
most applications; 12 V is recommended.
0.1F
4.7⍀
V , 2.7V – 5.5V
P
VR2
50k⍀
FOR V = 3V, R = 20k⍀
R
P
P
S
S
V
= 5V, R = 51k⍀
S
؎3dB
OUTPUT
50mV/dB
؎10%
0.1F
4.7⍀
INP VPS ENB INT
AD8307
INPUT
–75dBm TO
+16dBm
AD8031
R2
V
OP AMP IS AD8032
P
30.1k⍀
VR1
SCALE C1 – C8 AS NEEDED
(SEE TEXT). NOTE POLARITIES
IF TANTALUM CAPACITORS
ARE USED.
R1
50k⍀
2k⍀
INM COM OFS OUT
422⍀
INPUT
5mV TO
160V rms
20mV/dB
VR1
INT ؎4dB
NC
C1
10F
C8
1F
OUTPUT
100mV/dB
R1
20k⍀
50k⍀
NC
C1
32.4k⍀
7.32k⍀
INP VPS ENB INT
COM
C5
1F
100k⍀
34k⍀
NC = NO CONNECT
C3
2.5nF
AD8307
INM COM OFS OUT
93k⍀
Figure 36. Log Am p with Buffered Output
34k⍀
C1 is optional; it lowers the corner frequency of the low-pass
output filter. A value of 0.1 µF should be used for applications
in which the output is measured on a voltmeter or other low
speed device. On the other hand, when C1 is omitted the 10%-
90% response time is under 200 ns, and is typically 300 ns to
99% of final value. T o achieve faster response times, it is neces-
sary to lower the load resistance at the output of the AD8307,
then restore the scale using a higher gain in the op amp. Using
8.33 kΩ, the basic slope is 10 mV/dB; this can be restored to
25 mV/dB using a buffer gain of 2.5. T he overall 10%-90%
response time is under 100 ns. Figure 37 shows how the output
current capability can be augmented to drive a 50 Ω load; RT
optionally provides reverse termination, which halves the slope
to 12.5 mV/dB.
VR2
50k⍀
SLOPE C6
C7
1F
C2
10F
C4
1F
75k⍀
80.6k⍀
1F
32.4k⍀
COM
Figure 38. Log Am p with Four-Pole Low-Pass Filter
Figure 38 also shows the use of an input attenuator which may
optionally be employed here, or in any other of these applica-
tions, to produce a useful wide-range ac voltmeter with direct-
decibel scaling. T he basic range of –73 dBm to +17 dBm (that
is, 50 µV rms to 1.6 V rms, for sine excitations) is shifted, for
illustrative purposes, to 5 mV to 160 V rms (at which point the
power in R1 is 512 mW). Because the basic input resistance of
the AD8307 is not precise, VR1 is used to center the signal
range at its input, doubling as a ±4 dB intercept adjustment.
T he low frequency response extends to 15 Hz; a higher corner
frequency can be selected as needed, by scaling C1 and C2. T he
shunt capacitor C3 is used to lower the high frequency band-
width to about 100 kHz, and thus lower the susceptibility to
spurious signals. Other values should be chosen as needed for
the coupling and filter capacitors.
Four -P ole Filter
In low frequency applications, for example, audio down to 20 Hz,
it is useful to employ the buffer amplifier as a multipole low-pass
filter, in order to achieve low output ripple while maintaining a
rapid response time to changes in signal level.
REV. A
–15–
AD8307
1 W to 1 kW 50 ⍀ P ower Meter
T he AD603 has a very low input referred noise: 1.3 nV/√Hz at
its 100-Ω input, or 0.9 nV/√Hz when matched to 50 Ω, equivalent
to 0.4 µV rms, or –115 dBm, in a 200 kHz bandwidth. It is also
capable of handling inputs in excess of 1.4 V rms, or +16 dBm.
It is thus able to cope with a dynamic range of over 130 dB in
this particular bandwidth.
T he front-end adaptation shown in Figure 39 provides the mea-
surement of power being delivered from a transmitter final am-
plifier to an antenna. T he range has been set to cover the power
range –30 dBm (7.07 mV rms, or 1 µW) to +60 dBm (223 V rms,
or 1 kW). A nominal voltage attenuation ratio of 158:1 (44 dB) is
used; thus the intercept is moved from –84 dBm to –40 dBm and
the AD8307, scaled 0.25 V/decade of power, will now read 1.5 V
for a power level of 100 mW, 2.0 V at 10 W and 2.5 V at 1 kW.
Now, if the gain control voltage for the X-AMP is derived from
the output of the AD8307, the effect will be to raise the gain of
this front-end stage when the signal is small and lower it when it
is large, but without altering the fundamental logarithmic nature
of the response. T his gain range is 40 dB, which, combined with
the 90 dB range of the AD8307, again corresponds to a 130 dB
range.
T he general expression is:
P (dBm) = 40 (VOUT – 1)
T he required attenuation could be implemented using a capaci-
tive divider, providing a very low input capacitance, but it is
difficult to ensure accurate values of small capacitors. A better
approach is to use a resistive divider, taking the required precau-
tions to minimize spurious coupling into the AD8307 by placing
it in a shielded box, with the input resistor passing through a
hole in this box, as indicated in the figure. T he coupling capaci-
tors shown here are suitable for f ≥ 10 MHz. A capacitor may be
added across the input pins of the AD8307 to reduce the re-
sponse to spurious HF signals which, as already noted, extends
to over 1 GHz.
V
, +5V
P
50⍀
INPUT
–105dBm
TO
R1
187k⍀
R2
28k⍀
BANDPASS
FILTER*
4.7⍀
0.1F
0.65V
GPOS
+15dBm
NC
VPOS
VOUT
R3
330⍀
INP VPS ENB INT
L1
750nH
GNEG
VINP
R4
464⍀
AD8307
AD603
INM COM OFS OUT
VNEG
FDBK
C1
150pF
VR1
5k⍀
INT
0.3V
TO
2.3V
NC
COMM
1nF
؎8dB
T he mismatch caused by the loading of this resistor will be
trivial; only 0.05% of the power delivered to the load will be
absorbed by the measurement system, a maximum of 500 mW
at 1 kW. T he post-demodulation filtering and slope-calibration
arrangements should be chosen from other applications described
here, to meet the particular system requirements. T he 1 nF
capacitor lowers the risk of HF signals entering the AD8307 via
the load.
R7
80.6k⍀
R6
20k⍀
V
, –5V
N
0.15V TO 1.15V
* E.G., MURATA SFE10.7MS2G-A
NC = NO CONNECT
R5
100k⍀
OUTPUT
10mV/dB
Figure 40. 120 dB Measurem ent System
Figure 40 shows how these two parts can work together to pro-
vide state-of-the-art IF measurements in applications such as
spectrum/ network analyzers and other high dynamic range
instrumentation. T o understand the operation, note first that
the AD8307 is used to generate an output of about 0.3 V to
2.3 V. T his 2 V span is divided by 2 in R5/R6/R7 to provide the
1 V span needed by the AD603 to vary its gain by 40 dB. Note
that an increase in the positive voltage applied at GNEG (Pin 2)
lowers the gain. T his feedback network is tapped to provide a
convenient 10 mV/dB scaling at the output node, which may be
buffered if necessary.
TO
ANTENNA
100k⍀
0.1F
V
1/2W
P
22⍀
+5V
51pF
NC
LEAD-
THROUGH
CAPACITORS,
1nF
VR1
2k⍀
INT ؎3dB
INP VPS ENB INT
AD8307
INM COM OFS OUT
50⍀ INPUT
FROM P.A.
1W TO
1kW
604⍀
2k⍀
NC
V
OUT
The center of the voltage range fed back to the AD603 is 650 mV
and the ±20 dB gain range is centered by R1/R2. Note that the
intercept calibration of this system benefits from the use of a
well regulated 5 V supply. T o absorb the insertion loss of the
filter and center the full dynamic range, the intercept is adjusted
by varying the maximum gain of the AD603, using VR1.
Figure 41 shows the AD8307 output over the range –120 dBm
to +20 dBm and the deviation from an ideal logarithmic re-
sponse. T he dotted line shows the increase in the noise floor
that results when the filter is omitted; the decibel difference is
about 10log10(50/0.2) or 24 dB, assuming a 50 MHz band-
width from the AD603. An L-C filter may be used in place of
the ceramic filter used in this example.
OUTPUT
51pF
1nF
NC = NO CONNECT
Figure 39. 1 µW to 1 kW 50-Ω Power Meter
Measur em ent System with 120 dB D ynam ic Range
T he dynamic range of the AD8307 can be extended further—
from 90 dB to over 120 dB—by the addition of an X-AMP™
such as the AD603. T his type of variable gain amplifier exhibits
a very exact exponential gain control characteristic, which is
another way of stating that the gain varies by a constant number
of decibels for a given change in the control voltage. For the
AD603, this scaling factor is 40 dB/V, or 25 mV/dB. It will be
apparent that this property of a linear-in-dB response is charac-
teristic of log amps; indeed, the AD8307 exhibits the same
scaling factor.
X-AMP is a trademark of Analog Devices, Inc.
REV. A
–16–
AD8307
2.50
2.25
2.00
1.75
1.50
is 125 ms. (See also Figure 38 for a more elaborate filter). Finally,
to improve the law-conformance at very low signal levels and at
low frequencies, C4 has been added to the offset compensation
loop.
WITHOUT
FILTER
2
+5V
1
4.7⍀
0.1F
0
1.25
1.00
C1
10F
R1
5k⍀
–1
–2
ERROR
(WITH FILTER)
V
NC
IN
0.75
0.50
FOR SLOPE AND
INTERCEPT ADJUSTMENTS
SEE FIGURE 35
0.5mV
TO 20V
SINE
INP VPS ENB INT
AD8307
C3
750pF
WITH FILTER
AMPLITUDE
INM COM OFS OUT
0.25
0
V
OUT
–20
INPUT LEVEL – dBm
0
20
–100
–80
–60
–40
25mV/dB
R2
5k⍀
C2
10F
C4
C5
1F
1F
NC = NO CONNECT
Figure 41. Results for 120 dB Measurem ent System
Figure 42. Connections for Low Frequency Operation
O per ation at Low Fr equencies
T he AD8307 provides excellent logarithmic conformance at
signal frequencies that may be arbitrarily low, depending only
on the values used for the input coupling capacitors. It may also
be desirable to add a low-pass input filter in order to desensitize
the log amp to HF signals. Figure 42 shows a simple arrange-
ment, providing coupling with an attenuation of 20 dB; the
intercept is shifted up by this attenuation, from –84 dBm to
–64 dBm, and the input range is now 0.5 mV to 20 V (sine
amplitude).
D C-Coupled Applications
It may occasionally be necessary to provide response to dc in-
puts. Since the AD8307 is internally dc-coupled, there is no
fundamental reason why this is precluded. However, there is a
practical constraint, which is that its inputs must be positioned
about 2 V above the COM potential for proper biasing of the
first stage. If it happens that the source is a differential signal at
this level, it may be directly connected to the input. For ex-
ample, a microwave detector can be ac-coupled at its RF input
and its baseband load then automatically provided by the “float-
ing” RIN and CIN of the AD8307, at about VP/2.
A high pass 3 dB corner frequency of nominally 3 Hz is set by
the 10 µF coupling capacitors C1 and C2, which are preferably
tantalum electrolytics (note the polarity) and a low pass 3 dB
corner frequency of 200 kHz (set by C3 and the effective resis-
tance at the input of 1 kΩ). T he –1% amplitude error points
occur at 20 Hz and 30 kHz. T hese are readily altered to suit
other applications by simple scaling. When C3 is zero, the low
pass corner is at 200 MHz. Note that the lower end of the dy-
namic range is improved by this capacitor, which provides es-
sentially an HF short circuit at the input, thus significantly
lowering the wideband noise; the noise reduction is about 2 dB
compared to the case when the AD8307 is driven from a 50 Ω
source.
Usually, the source will be a single-sided ground-referenced
signal, and it will thus be necessary to provide a negative supply
for the AD8307. T his can be achieved as shown in Figure 43.
T he output is now referenced to this negative supply, and it is
necessary to provide an output interface that performs a differ-
ential-to-single-sided conversion. T his is the purpose of the
AD830. T he slope may be arranged to be 20 mV/dB, when the
output ideally runs from zero, for a dc input of 10 µV, to +2.2 V
for an input of 4 V. T he AD8307 is fundamentally insensitive to
the sign of the input signal, but with this biasing scheme, the
maximum negative input is constrained to about –1.5 V. T he
transfer function after trimming and with R7 = 0, is
T o ensure that the output is free of post-demodulation ripple, it
is necessary to lower the low-pass filter time-constant. T his is
provided by C5; with the value shown, the output time-constant
VOUT = (0.4 V) log10 (VIN /10 µV)
R1
4.7⍀
+5V FOR 20mV/dB
+10V FOR 50mV/dB
+5V
+15V FOR 100mV/dB
C1
0.1F
VR2
50k⍀
V
OUT
–5V
R2
3.3k⍀
R5
*
VP
NC VN
INT
INP VPS ENB INT
V
IN
AD830
AD8307
INM COM OFS OUT
C2
1F
R7
* 51k⍀ FOR
20mV/dB
5k FOR
X1 X2 Y1 Y2
TEMP
R7,R8:
SEE TEXT
100mV/dB
20mV/dB
R6
32.4k⍀
AD589
VR1
2k⍀
C3
0.1F
R8
Q1
2N3904
R9
250⍀
VR3
50k⍀
R3
1k⍀
–5V
NC = NO CONNECT
–2V
Figure 43. Connections for DC-Coupled Applications
REV. A
–17–
AD8307
T he intercept can be raised, for example, to 100 µV, with the
rationale that the dc precision does not warrant operation in the
first decade (from 10 µV–100 µV). Likewise, the slope can be
raised to 50 mV/dB, using R7 = 3 kΩ, R8 = 2 kΩ, or to 100 mV/
dB, to simplify decibel measurements on a DVM, using R7 =
8 kΩ, R8 = 2 kΩ, which raises the maximum output to +11 V,
thus requiring a +15 V supply for the AD830. T he output may
be made to swing in a negative direction by simply reversing
Pins 1 and 2. Low-pass filtering capacitor C3 sets the output
rise time to about 1 ms.
requires adjusting the output to 0.68 V; for the 100 mV/dB
scaling, this becomes 3.4 V. If a 100 µV intercept is preferred
(usefully lowering the maximum output voltage), these become
0.28 V and 1.4 V respectively.
Finally, the slope must be adjusted. T his can be performed by
applying a low frequency square wave to the main input, having
precisely determined upper and lower voltage levels, provided
by a programmable waveform generator. A suitable choice is a
100 Hz square wave with levels of 10 mV and 1 V. T he output
will be a low-pass filtered square wave, and its amplitude should
be 0.8 V, for 20 mV/dB scaling, or 4 V for 100 mV/dB scaling.
6.0
5.5
5.0
4.5
O per ation Above 500 MH z
T he AD8307 is not intended for use above 500 MHz. However,
it does provide useful performance at higher frequencies.
Figure 45 shows a plot of the logarithmic output of the AD8307
for an input frequency of 900 MHz. T he device shows good
logarithmic conformance from –50 dBm to –10 dBm. T here is a
“bump” in the transfer function at –5 dBm, but if this is accept-
able, the device is usable over a 60 dB dynamic range (–50 dBm
to +10 dBm).
1.0
0.5
0
4.0
3.5
3.0
2.5
–0.5
–1.0
2.0
1.5
1.0
0.5
0
2
1.8
1.6
1.4
1.2
1
1m
10m
100m
1
10
10
100
V
IN
Figure 44. Ideal Output and Law-Conform ance Error for
the DC-Coupled AD8307 at 50 m V/dB
Figure 44 shows the output and the law-conformance error in
the absence of noise and input offset, for the 50 mV/dB option.
Note in passing that the error ripple for dc excitation is about
twice that for the more usual sinusoidal excitation. In practice,
both the noise and the internal offset voltage will degrade the
accuracy in the first decade of the dynamic range. T he latter is
now manually nulled, by VR1, using a simple method that en-
sures very low residual offsets.
0.8
0.6
0.4
0.2
0
–60
–50
–40
–30
P
–20
– dBm
–10
0
10
IN
Figure 45. Output vs. Input Level for a 900 MHz Input Signal
A temporary ac signal, typically a sine wave of 100 mV in ampli-
tude at a frequency of about 100 Hz, is applied via the capacitor
at node TEMP; this has the effect of disturbing the offset-nulling
voltage. T he output voltage is then viewed on an oscilloscope
and VR1 is adjusted until the peaks of the (frequency-doubled)
waveform are exactly equal in amplitude. T his procedure can
provide an input null down to about 10 µV; the temperature
drift is very low, though not specified since the AD8307 is not
principally designed to operate as a baseband log amp, and in ac
modes this offset is continuously and automatically nulled.
Evaluation Boar d
An evaluation board, carefully laid out and tested to demon-
strate the specified high speed performance of the AD8307 is
available. Figure 46 shows the schematic of the evaluation board.
For ordering information, please refer to the Ordering Guide.
Figures 47 and 49 show the component-side and solder-side
silkscreens of the evaluation board. T he component-side and
solder-side layouts are shown in Figures 48 and 50.
For connection to external instruments, side-launched SMA
type connectors are provided. Space is also provided on the
board for the installation of SMB or SMC type connectors.
When using the top-mount SMA connector, it is recommended
that the stripline on the outside 1/8" of the board edge be re-
moved (i.e., scraped using a blade) as this unused stripline acts
as an open stub, which could degrade the overall performance of
the evaluation board/device combination at high frequencies.
Next, it is necessary to set the intercept. T his is the purpose of
VR2, which should be adjusted after VR1. T he simplest method
is to short the input and adjust VR2 for an output of 0.3 V,
corresponding to the noise floor. For more exacting applica-
tions, a temporary sinusoidal test voltage of 1 mV in amplitude,
at about 1 MHz, should be applied, which may require the use
of a temporary onboard input attenuator. For 20 mV/dB scaling,
a 10 µV dc intercept (which is 6 dB below the ac intercept)
REV. A
–18–
AD8307
+V
S
C4
0.1F
C3
10F
A
B
LK1
R2
50k⍀
INPUT
C2
0.1F
LK2
INP VPS ENB INT
R1
52.3⍀
AD8307
INM COM OFS OUT
C1
0.1F
LOG
OUTPUT
LK4
LK3
LK5
R3
C5
12.5k⍀
0.1F
C6
1nF
Figure 49. Solder Side Silkscreen
Figure 46. Evaluation Board Schem atic
Figure 50. Board Layout (Solder Side)
Link and Tr im O ptions
Figure 47. Com ponent Side Silkscreen
T here are a number of link options and trim potentiometers on
the evaluation board which should be set for the required oper-
ating setup before using the board. T he functions of these link
options and trim potentiometers are described in detail in
T able II.
Figure 48. Board Layout (Com ponent Side)
REV. A
–19–
AD8307
Table II. Evaluation Board Link O ptions
Function
Link No.
D efault P osition
LK1
A
Power Up/Power Down. When this link is in position B, the ENB pin is connected to ground,
putting the AD8307 in power-down mode. Placing this link in position A connects the ENB
pin to the positive supply, thereby putting the AD8307 in normal operating mode.
LK2
LK3
LK4
Open
Open
Open
Intercept Adjust. When Pin LK2 is left open, the AD8307 has a nominal logarithmic
intercept of –84 dBm. Putting LK2 in place connects the wiper of potentiometer R2 to Pin 5
(INT). By varying the voltage on INT, the position of the intercept can be adjusted. The inter-
cept varies by about 8 dB/V.
Slope Adjust. When this link is open, the nominal slope of the output is 25 mV/dB. Putting this
link in place connects a ground referenced 12.5 kΩ load resistor (R3) to the logarithmic out-
put. The parallel combination of this resistor and an internal 12.5 kΩ resistor reduces the
logarithmic slope to 12.5 mV/dB. R3 may be adjusted for other scaling factors.
Corner Frequency of Low-Pass Demodulating Filter. When this link is open, the corner fre-
quency of the low pass post demodulation filter has a nominal value of 4 MHz. This is set by
an on-chip load impedance of 12.5 kΩ and an on-chip load capacitance of 3.5 pF. The load
capacitance (e.g., of an oscilloscope probe) must be added to this capacitance, and will lower
the internal video bandwidth, to a nominal 1 MHz for a total of 13.5 pF. Putting LK4 in place
connects an external load capacitance (C5) of 0.1 µF to the output, reducing the corner fre-
quency of the low-pass filter to about 125 Hz. For large values of C5, the corner frequency can
be calculated using the equation, f ≈ 12.7 Hz/C5 (µF).
LK5
Open
Offset Control Loop. When this link is open, the internal offset control loop gives the circuit an
overall high pass corner frequency of about 1 MHz. With LK5 link in place, a 1 nF capacitor
(C6) is connected to the OFS pin, reducing the high pass corner frequency to allow accurate
operation down to 10 kHz. To reduce the minimum operational frequency even further, a
larger capacitor can replace C6 (e.g., a 1 µF capacitor allows operation down to 10 Hz). Note
that that external capacitor C6 has no effect on the minimum signal frequency for input levels
that exceed the offset voltage (typically 400 µV). The range for such signals extends down to dc
(for signals applied directly to the input pins).
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
8-Lead P lastic D IP
(N-8)
8-Lead SO IC
(SO -8)
0.430 (10.92)
0.348 (8.84)
0.1968 (5.00)
0.1890 (4.80)
8
5
8
1
5
4
0.280 (7.11)
0.240 (6.10)
0.1574 (4.00)
0.1497 (3.80)
0.2440 (6.20)
0.2284 (5.80)
1
4
0.325 (8.25)
0.300 (7.62)
0.060 (1.52)
0.015 (0.38)
PIN 1
PIN 1
0.0688 (1.75)
0.0532 (1.35)
0.0196 (0.50)
0.0099 (0.25)
0.195 (4.95)
0.115 (2.93)
؋
45؇ 0.210 (5.33)
MAX
0.0098 (0.25)
0.0040 (0.10)
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
8؇
0؇
SEATING
PLANE
0.0500
(1.27)
BSC
0.100
(2.54)
BSC
0.0192 (0.49)
0.0138 (0.35)
0.022 (0.558)
0.014 (0.356)
0.070 (1.77)
0.045 (1.15)
SEATING
PLANE
0.0098 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
–20–
REV. A
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