AD8313 [ADI]
0.1 GHz-2.5 GHz, 70 dB Logarithmic Detector/Controller; 0.1千兆赫， 2.5千兆赫， 70分贝对数检测器/控制器
| 型号： | AD8313 |
| 厂家： | 
ADI |
| 描述： | 0.1 GHz-2.5 GHz, 70 dB Logarithmic Detector/Controller |
| 文件： | 总16页 (文件大小：264K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
0.1 GHz–2.5 GHz, 70 dB
Logarithmic Detector/Controller
a
AD8313
FUNCTIONAL BLOCK DIAGRAM
NINE DETECTOR CELLS
FEATURES
Wide Bandwidth: 0.1 GHz to 2.5 GHz Min
High Dynamic Range: 70 dB to ؎3.0 dB
High Accuracy: ؎1.0 dB over 65 dB Range (@ 1.9 GHz)
Fast Response: 40 ns Full-Scale Typical
Controller Mode with Error Output
Scaling Stable Over Supply and Temperature
Wide Supply Range: +2.7 V to +5.5 V
Low Power: 40 mW at 3 V
+
+
+
+
+
IvV
VOUT
VPOS
C
INT
INHI
LP
8dB
8dB
8dB
8dB
VvI
VSET
INLO
EIGHT 8dB 3.5GHz AMPLIFIER STAGES
Power-Down Feature: 60 W at 3 V
Complete and Easy to Use
INTERCEPT
CONTROL
COMM
PWDN
AD8313
APPLICATIONS
RF Transmitter Power Amplifier Setpoint
Control and Level Monitoring
VPOS
SLOPE
CONTROL
BAND-GAP
REFERENCE
GAIN
BIAS
Logarithmic Amplifier for RSSI Measurement
Cellular Base Stations, Radio Link, Radar
PRODUCT DESCRIPTION
When used as a log amp, the scaling is determined by a separate
feedback interface (a transconductance stage) that sets the slope
to approximately 18 mV/dB; used as a controller, this stage
accepts the setpoint input. The logarithmic intercept is posi-
tioned to nearly –100 dBm, and the output runs from about
0.45 V dc at –73 dBm input to 1.75 V dc at 0 dBm input. The
scale and intercept are supply and temperature stable.
The AD8313 is a complete multistage demodulating logarith-
mic amplifier, capable of accurately converting an RF signal at
its differential input to an equivalent decibel-scaled value at its
dc output. The AD8313 maintains a high degree of log con-
formance for signal frequencies from 0.1 GHz to 2.5 GHz and
is useful over the range of 10 MHz to 3.5 GHz. The nominal
input dynamic range is –65 dBm to 0 dBm (re: 50 Ω), and the
sensitivity can be increased by 6 dB or more with a narrow band
input impedance matching network or balun. Application is
straightforward, requiring only a single supply of 2.7 V–5.5 V
and the addition of a suitable input and supply decoupling.
Operating on a 3 V supply, its 13.7 mA consumption (for TA =
+25°C) amounts to only 41 mW. A power-down feature is
provided; the input is taken high to initiate a low current
(20 µA) sleep mode, with a threshold at half the supply voltage.
The AD8313 is fabricated on Analog Devices’ advanced
25 GHz silicon bipolar IC process and is available in a 8-lead
µSOIC package. The operating temperature range is –40°C to
+85°C. An evaluation board is available.
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
5
FREQUENCY = 1.9GHz
4
3
2
The AD8313 uses a cascade of eight amplifier/limiter cells,
each having a nominal gain of 8 dB and a –3 dB bandwidth of
3.5 GHz, for a total midband gain of 64 dB. At each amplifier
output, a detector (rectifier) cell is used to convert the RF signal
to baseband form; a ninth detector cell is placed directly at the
input of the AD8313. The current-mode outputs of these cells
are summed to generate a piecewise linear approximation to the
logarithmic function, and converted to a low impedance voltage-
mode output by a transresistance stage, which also acts as a low-
pass filter.
1
0
–1
–2
–3
–4
–5
0
–80
–70
–60
–50
–40
–30
–20
–10
INPUT AMPLITUDE – dBm
Figure 1. Typical Logarithmic Response and Error vs.
Input Amplitude
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1999
(@ T = +25؇C, V = +5.0 V1, R ≥ 10 k⍀ unless otherwise noted)
AD8313–SPECIFICATIONS
A
S
L
Parameter
Conditions
Min2
Typ
Max2
Units
SIGNAL INPUT INTERFACE
Specified Frequency Range
DC Common-Mode Voltage
Input Bias Currents
0.1
2.5
GHz
V
VPOS – 0.75
10
900ʈ1.1
µA
Input Impedance
fRF < 100 MHz3
ΩʈpF4
LOG (RSSI) MODE
100 MHz5
Sinusoidal, input termination configuration shown in Figure 27.
Nominal Conditions
±3 dB Dynamic Range6
Range Center
53.5
65
dB
dBm
dB
–31.5
56
±1 dB Dynamic Range
Slope
Intercept
17
–96
19
–88
21
–80
mV/dB
dBm
+2.7 V ≤ VS ≤ +5.5 V, –40°C ≤ T ≤ +85°C
±3 dB Dynamic Range
Range Center
±1 dB Dynamic Range
51
64
–31
55
dB
dBm
dB
Slope
Intercept
Temperature Sensitivity
16
–99
19
–89
–0.022
22
–75
mV/dB
dBm
dB/°C
PIN = –10 dBm
900 MHz5
Nominal Conditions
±3 dB Dynamic Range
Range Center
±1 dB Dynamic Range
Slope
60
69
–32.5
62
18
–93
dB
dBm
dB
mV/dB
dBm
15.5
–105
20.5
–81
Intercept
+2.7 V ≤ VS ≤ +5.5 V, –40°C ≤ T ≤ +85°C
±3 dB Dynamic Range
Range Center
±1 dB Dynamic Range
55.5
68.5
–32.75
61
dB
dBm
dB
Slope
Intercept
Temperature Sensitivity
15
–110
18
–95
–0.019
21
–80
mV/dB
dBm
dB/°C
PIN = –10 dBm
1.9 GHz7
Nominal Conditions
±3 dB Dynamic Range
Range Center
±1 dB Dynamic Range
Slope
52
73
–36.5
62
17.5
–100
dB
dBm
dB
mV/dB
dBm
15
–115
20.5
–85
Intercept
+2.7 V ≤ VS ≤ +5.5 V, –40°C ≤ T ≤ +85°C
±3 dB Dynamic Range
Range Center
±1 dB Dynamic Range
Slope
Intercept
Temperature Sensitivity
50
73
36.5
60
17.5
–101
–0.019
dB
dBm
dB
mV/dB
dBm
dB/°C
14
–125
21.5
–78
PIN = –10 dBm
2.5 GHz7
Nominal Conditions
±3 dB Dynamic Range
Range Center
±1 dB Dynamic Range
Slope
48
66
–34
46
20
dB
dBm
dB
mV/dB
dBm
16
–111
25
–72
Intercept
–92
+2.7 V ≤ VS ≤ +5.5 V, –40°C ≤ T ≤ +85°C
±3 dB Dynamic Range
Range Center
±1 dB Dynamic Range
Slope
Intercept
Temperature Sensitivity
47
68
–34.5
46
20
–92
–0.040
dB
dBm
dB
mV/dB
dBm
dB/°C
14.5
–128
25
–56
PIN = –10 dBm
–2–
REV. B
AD8313
Parameter
Conditions
Min2
Typ
Max2
Units
3.5 GHz5
±3 dB Dynamic Range
±1 dB Dynamic Range
Slope
43
35
24
–65
dB
dB
mV/dB
dBm
Intercept
CONTROL MODE
Controller Sensitivity
Low Frequency Gain
Open-Loop Corner Frequency
Open-Loop Slew Rate
VSET Delay Time
f = 900 MHz
23
84
700
2.5
150
V/dB
dB
Hz
V/µs
ns
VSET to VOUT8
VSET to VOUT8
f = 900 MHz
VOUT INTERFACE
Current Drive Capability
Source Current
400
10
50
VPOS – 0.1
2.0
1.3
µA
Sink Current
mA
mV
V
µV/√Hz
µV/√Hz
ns
Minimum Output Voltage
Maximum Output Voltage
Output Noise Spectral Density
Open Loop
Open Loop
P
IN = –60 dBm, fSPOT = 100 Hz
PIN = –60 dBm, fSPOT = 10 MHz
IN = –60 dBm to –57 dBm, 10% to 90%
Small Signal Response Time
Large Signal Response Time
P
40
110
60
160
PIN = No Signal to 0 dBm, Settled to 0.5 dB
ns
VSET INTERFACE
Input Voltage Range
Input Impedance
0
VPOS
V
ΩʈpF
18kʈ1
POWER-DOWN INTERFACE
PWDN Threshold
VPOS/2
V
Power-Up Response Time
Time delay following HI to LO transition
until device meets full specifications.
PWDN = 0 V
1.8
5
<1
µs
µA
µA
PWDN Input Bias Current
PWDN = VS
POWER SUPPLY
Operating Range
Powered Up Current
+2.7
+5.5
15.5
18.5
18.5
150
50
V
13.7
mA
mA
mA
µA
µA
+4.5 V ≤ VS ≤ +5.5 V, –40°C ≤ T ≤ +85°C
+2.7 V ≤ VS ≤ +3.3 V, –40°C ≤ T ≤ +85°C
+4.5 V ≤ VS ≤ +5.5 V, –40°C ≤ T ≤ +85°C
+2.7 V ≤ VS ≤ +3.3 V, –40°C ≤ T ≤ +85°C
Powered Down Current
50
20
NOTES
1Except where otherwise noted, performance at VS = +3.0 V is equivalent to +5.0 V operation.
2Minimum and maximum specified limits on parameters that are guaranteed but not tested are six sigma values.
3Input impedance shown over frequency range in Figure 24.
4Double slashes (ʈ) denote “in parallel with.”
5Linear regression calculation for error curve taken from –40 dBm to –10 dBm for all parameters.
6Dynamic range refers to range over which the linearity error remains within the stated bound.
7Linear regression calculation for error curve taken from –60 dBm to –5 dBm for 3 dB dynamic range. All other regressions taken from –40 dBm to –10 dBm.
8AC response shown in Figure 10.
Specifications subject to change without notice.
REV. B
–3–
AD8313
ABSOLUTE MAXIMUM RATINGS*
PIN FUNCTION DESCRIPTIONS
Supply Voltage VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
VOUT, VSET, PWDN . . . . . . . . . . . . . . . . . . . . . . 0 V, VPOS
Input Power Differential (re: 50 Ω, 5.5 V) . . . . . . . . . +25 dBm
Input Power Single-Ended (re: 50 Ω, 5.5 V) . . . . . . . +19 dBm
Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . . 200 mW
θJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200°C/W
Maximum Junction Temperature . . . . . . . . . . . . . . . . +125°C
Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300°C
Pin
Name
Description
1, 4
VPOS
Positive supply voltage (VPOS), +2.7 V to
+5.5 V.
Noninverting Input. This input should be
ac coupled.
Inverting Input. This input should be ac
coupled.
Connect pin to ground for normal operat-
ing mode. Connect pin to supply for power-
down mode.
2
3
5
INHI
INLO
PWDN
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may effect device reliability.
6
7
COMM Device Common.
VSET
Setpoint input for operation in controller
mode. To operate in RSSI mode, short
VSET and VOUT.
PIN CONFIGURATION
8
VOUT
Logarithmic/Error Output.
1
2
3
4
8
7
6
5
VPOS
INHI
VOUT
VSET
AD8313
TOP VIEW
(Not to Scale)
COMM
PWDN
INLO
VPOS
ORDERING GUIDE
Package
Temperature
Range
Package
Option
Brand
Code
Model
AD8313ARM
AD8313ARM-REEL
AD8313ARM-REEL7
AD8313-EVAL
Descriptions
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
8-Lead µSOIC
RM-08
RM-08
RM-08
J1A
J1A
J1A
13” Tape and Reel
7” Tape and Reel
Evaluation Board
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8313 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy [>250 V HBM] electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. B
Typical Performance Characteristics–
AD8313
2.0
5
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
V
= +5V
V
= +5V
S
S
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
4
INPUT MATCH SHOWN IN FIGURE 27
INPUT MATCH SHOWN IN FIGURE 27
3
2
100MHz
1
–40؇C
1.9GHz
2.5GHz
0
+25؇C
+85؇C
–1
–2
–3
–4
–5
900MHz
SLOPE AND INTERCEPT NORMALIZED AT +25؇C
AND APPLIED TO –40؇C AND +85؇C
0
–70
–60
–50
–40
–30
–20
–10
0
10
–70
–60
–50
–40
–30
–20
–10
0
10
INPUT AMPLITUDE – dBm
INPUT AMPLITUDE – dBm
Figure 2. VOUT vs. Input Amplitude
Figure 5. VOUT and Log Conformance vs. Input Amplitude
at 900 MHz; –40°C, +25°C and +85°C
6
4
2
0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
5
V
= +5V
S
V
= +5V
S
4
INPUT MATCH SHOWN IN FIGURE 27
INPUT MATCH SHOWN IN FIGURE 27
3
900MHz
100MHz
–40؇C
2
1
+25؇C
+85؇C
900MHz
0
–1
–2
–3
–4
–5
2.5GHz
100MHz
–2
–4
–6
1.9GHz
2.5GHz
1.9GHz
SLOPE AND INTERCEPT NORMALIZED AT +25؇C
AND APPLIED TO –40؇C AND +85؇C
0
0
–70
–60
–50
–40
–30
–20
–10
10
–70
–60
–50
–40
–30
–20
–10
0
10
INPUT AMPLITUDE – dBm
INPUT AMPLITUDE – dBm
Figure 3. Log Conformance vs. Input Amplitude
Figure 6. VOUT and Log Conformance vs. Input Amplitude
at 1.9 GHz; –40°C, +25°C and +85°C
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
5
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
5
V
= +5V
S
V
= +5V
S
INPUT MATCH SHOWN IN FIGURE 27
4
4
INPUT MATCH SHOWN IN FIGURE 27
3
3
–40؇C
2
2
–40؇C
1
1
+25؇C
+85؇C
0
0
+25؇C
–1
–2
–3
–4
–5
–1
–2
–3
–4
–5
SLOPE AND INTERCEPT
NORMALIZED AT +25؇C AND
APPLIED TO –40؇C AND +85؇C
SLOPE AND INTERCEPT NORMALIZED AT +25؇C
AND APPLIED TO –40؇C AND +85؇C
+85؇C
0
0
–70
–60
–50
–40
–30
–20
–10
0
10
–70
–60
–50
–40
–30
–20
–10
0
10
INPUT AMPLITUDE – dBm
INPUT AMPLITUDE – dBm
Figure 7. VOUT and Log Conformance vs. Input Amplitude
at 2.5 GHz; –40°C, +25°C and +85°C
Figure 4. VOUT and Log Conformance vs. Input Amplitude
at 100 MHz; –40°C, +25°C and +85°C
REV. B
–5–
AD8313
–70
–80
22
21
20
19
18
17
V
= +5V
PS
V
= +5V
PS
INPUT MATCH SHOWN IN FIGURE 27
INPUT MATCH SHOWN IN FIGURE 27
+85؇C
+25؇C
+85؇C
–90
–40؇C
+25؇C
–100
–110
–40؇C
16
0
0
500
1000
1500
2000
2500
500
1000
1500
2000
2500
FREQUENCY – MHz
FREQUENCY – MHz
Figure 8. VOUT Slope vs. Frequency; –40°C, +25°C and
+85°C
Figure 11. VOUT Intercept vs. Frequency; –40°C, +25°C and
+85°C
–70
–75
24
23
SPECIFIED OPERATING RANGE
22
SPECIFIED OPERATING RANGE
–80
21
2.5GHz
–85
100MHz
20
100MHz
2.5GHz
900MHz
–90
–95
19
18
900MHz
1.9GHz
17
16
1.9GHz
–100
–105
–110
15
14
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE – V
SUPPLY VOLTAGE – V
Figure 9. VOUT Slope vs. Supply Voltage
Figure 12. VOUT Intercept vs. Supply Voltage
REF LEVEL = 92dB
10
SCALE: 10dB/DIV
2GHz RF INPUT
V
= +5.5V
S
INPUT MATCH SHOWN
IN FIGURE 27
RF INPUT
–70dBm
–60dBm
–55dBm
–50dBm
1
–45dBm
–40dBm
–35dBm
–30dBm
0.1
100
100
1k
10k
100k
1M
1k
10k
100k
1M
10M
FREQUENCY – Hz
FREQUENCY – Hz
Figure 10. AC Response from VSET to VOUT
Figure 13. VOUT Noise Spectral Density
–6–
REV. B
AD8313
100.00
10.00
CH. 1 & CH. 2: 200mV/DIV
AVERAGE: 50 SAMPLES
V
= +5.5V
= +2.7V
S
13.7mA
CH. 1
CH. 2
V
S
PULSED RF
100MHz, –45dBm
CH. 1 GND
CH. 2 GND
1.00
0.10
0.01
V
= +3V
V
= +5V
POS
POS
40A
HORIZONTAL: 50ns/DIV
20A
0
1
2
3
4
5
PWDN VOLTAGE – V
Figure 17. Response Time, No Signal to –45 dBm
Figure 14. Typical Supply Current vs. PWDN Voltage
AVERAGE: 50 SAMPLES
CH. 1 & CH. 2: 500mV/DIV
CH. 1 & CH. 2: 1V/DIV
CH. 3: 5V/DIV
V
= +5.5V
= +2.7V
V
S
@
= +5.5V
S
OUT
CH. 1
CH. 2
V
CH. 1 GND
CH. 2 GND
V
S
CH. 1 GND
V
S
@
= +2.7V
OUT
V
PULSED RF
100MHz, 0dBm
CH. 2 GND
PWDN
CH. 3 GND
HORIZONTAL: 50ns/DIV
HORIZONTAL: 1s/DIV
Figure 18. Response Time, No Signal to +0 dBm
Figure 15. PWDN Response Time
HP8648B
TRIG
OUT
EXT TRIG
OUT
10MHz REF OUTPUT
PULSE MODE IN
SIGNAL
GENERATOR
PULSE
HP8112A
PULSE
GENERATOR
HP8112A
PULSE
GENERATOR
HP8648B
SIGNAL
MODULATION
MODE
10MHz REF OUTPUT
PIN = 0dBm
EXT TRIG
OUT
GENERATOR
RF OUT
RF OUT
–6dB
RF
TEK
TDS784C
SCOPE
10⍀
SPLITTER
TEK P6205
FET PROBE
1
2
3
4
8
7
6
5
VPOS VOUT
AD8313
+V
S
–6dB
0.1F
54.9⍀
TRIG
TEK
10⍀
TEK P6205
FET PROBE
0.01F
1
2
3
4
8
7
6
5
TDS784C
SCOPE
VPOS
VOUT
VSET
+V
S
INHI
VSET
INLO COMM
PWDN
TRIG
0.1F
54.9⍀
AD8313
INHI
0.01F
0603 SIZE SURFACE
MOUNT COMPONENTS ON
A LOW LEAKAGE PC BOARD
0.01F
0603 SIZE SURFACE
MOUNT COMPONENTS ON
A LOW LEAKAGE PC BOARD
0.01F
10⍀
INLO COMM
PWDN
+V
VPOS
S
0.1F
10⍀
+V
VPOS
S
0.1F
Figure 16. Test Setup for PWDN Response Time
Figure 19. Test Setup for RSSI-Mode Pulse Response
REV. B
–7–
AD8313
CIRCUIT DESCRIPTION
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
5
The AD8313 is essentially an 8-stage logarithmic amplifier,
specifically designed for use in RF measurement and power
amplifier control applications at frequencies up to 2.5 GHz. A
block diagram is shown in Figure 20. (For a full treatment of
log-amp theory and design principles, consult the AD8307
data sheet).
SLOPE = 18mV/dB
4
3
2
1
0
NINE DETECTOR CELLS
–1
–2
–3
–4
–5
+
+
+
+
+
IvV
VOUT
VPOS
C
INT
INTERCEPT = –100dBm
INHI
LP
8dB
8dB
8dB
8dB
VvI
VSET
INLO
0
EIGHT 8dB 3.5GHz AMPLIFIER STAGES
–90
–80
–70
–60
–50
–40
–30
–20
–10
INPUT AMPLITUDE – dBm
INTERCEPT
CONTROL
COMM
PWDN
AD8313
Figure 21. Typical RSSI Response and Error vs. Input
Power at 1.9 GHz
VPOS
SLOPE
CONTROL
BAND-GAP
REFERENCE
GAIN
BIAS
The fluctuating current output generated by the detector cells,
with a fundamental component at twice the signal frequency, is
filtered first by a low-pass section inside each cell, and also by
the output stage. The output stage converts these currents to a
voltage, VOUT, at pin VOUT (Pin 8), which can swing “rail-to-
rail.” The filter exhibits a two-pole response with a corner at
approximately 12 MHz and full-scale rise time (10%–90%) of
40 ns. The residual output ripple at an input frequency of
100 MHz has an amplitude of under 1 mV. The output can
drive a small resistive load: it can source currents of up to
400 µA, and sink up to 10 mA. The output is stable with any
capacitive load, though settling time may be impaired. The low
frequency incremental output impedance is approximately 0.2 Ω.
Figure 20. Block Diagram
A fully-differential design is used, and the inputs INHI and INLO
(Pins 2 and 3) are internally biased to approximately 0.75 V
below the supply voltage, and present a low frequency imped-
ance of nominally 900 Ω in parallel with 1.1 pF. The noise
spectral density referred to the input is 0.6 nV/√Hz, equivalent
to a voltage of 35 µV rms in a 3.5 GHz bandwidth, or a noise
power of –76 dBm re: 50 Ω. This sets the lower limit to the
dynamic range; the Applications section shows how to increase
the sensitivity by the use of a matching network or input trans-
former. However, the low end accuracy of the AD8313 is enhanced
by specially shaping the demodulation transfer characteristic to
partially compensate for errors due to internal noise.
In addition to its use as an RF power measurement device (that
is, as a logarithmic amplifier) the AD8313 may also be used in
controller applications, by breaking the feedback path from
VOUT to the VSET (Pin 7), which determines the slope of the
output (nominally 18 mV/dB). This pin becomes the setpoint
input in controller modes. In this mode, the voltage VOUT re-
mains close to ground (typically under 50 mV) until the decibel
equivalent of the voltage VSET is reached at the input, when
Each of the eight cascaded stages has a nominal voltage gain of
8 dB and a bandwidth of 3.5 GHz, and is supported by preci-
sion biasing cells which determine this gain and stabilize it
against supply and temperature variations. Since these stages are
direct-coupled and the dc gain is high, an offset-compensation
loop is included. The first four of these stages, and the biasing
system, are powered from Pin 4, while the later stages and the
output interfaces are powered from Pin 1. The biasing is con-
trolled by a logic interface PWDN (Pin 5); this is grounded for
normal operation, but may be taken high (to VS) to disable the
chip. The threshold is at VPOS/2 and the biasing functions are
enabled and disabled within 1.8 µs.
VOUT makes a rapid transition to a voltage close to VPOS (see
controller mode). The logarithmic intercept is nominally posi-
tioned at –100 dBm (re: 50 Ω) and this is effective in both the
log amp mode and the controller mode.
Thus, with Pins 7 and 8 connected (log amp mode) we have:
VOUT = VSLOPE (PIN + 100 dBm)
Each amplifier stage has a detector cell associated with its out-
put. These nonlinear cells essentially perform an absolute-value
(full-wave rectification) function on the differential voltages
along this backbone, in a transconductance fashion; their out-
puts are in current-mode form and are thus easily summed. A
ninth detector cell is added at the input of the AD8313. Since
the mid-range response of each of these nine detector stages is
separated by 8 dB, the overall dynamic range is about 72 dB
(Figure 21). The upper end of this range is determined by the
capacity of the first detector cell, and occurs at approximately
0 dBm. The practical dynamic range is over 70 dB, to the
±3 dB error points. However, some erosion of this range will
occur at temperature and frequency extremes. Useful operation to
over 3 GHz is possible, and the AD8313 remains serviceable at
10 MHz (see Typical Performance Characteristics), needing
only a small amount of additional ripple filtering.
where PIN is the input power, stated in dBm when the source is
directly terminated in 50 Ω. However, the input impedance of
the AD8313 is much higher than 50 Ω and the sensitivity of this
device may be increased by about 12 dB by using some type of
matching network (see below), which adds a voltage gain and
lowers the intercept by the same amount. This dependence on
the choice of reference impedance can be avoided by restating
the expression as:
VOUT = 20 × VSLOPE × log (VIN/2.2 µV)
where VIN is the rms value of a sinusoidal input appearing
across Pins 2 and 3; here, 2.2 µV corresponds to the intercept,
expressed in voltage terms. (For a more thorough treatment of
the effect of signal waveform and metrics on the intercept posi-
tioning for a log amp, see the AD8307 data sheet).
–8–
REV. B
AD8313
With Pins 7 and 8 disconnected (controller mode), the output
may be stated as
TO STAGES
1 THRU 4
VPOS
1
~
0.75V
2.5k⍀ 2.5k⍀
0.7pF
125⍀
125⍀
0.5pF
V
OUT v VS when VSLOPE (PIN + 100) > VSET
OUT v 0 when VSLOPE (PIN + 100) < VSET
TO 2ND
STAGE
1.25k⍀
2
3
INHI
V
INLO
when the input is stated in terms of the power of a sinusoidal
signal across a net termination impedance of 50 Ω. The transi-
tion zone between high and low states is very narrow, since the
output stage behaves essentially as a fast integrator. The above
equations may be restated as
1.25k⍀
0.5pF
4
GAIN BIAS
1.24V
(1ST DETECTOR)
VPOS
~
1.4mA
250⍀
COMM
V
OUT v VS when
VSLOPE log (VIN/2.2 µV) > VSET
Figure 23. Input Interface Simplified Schematic
VOUT v 0 when VSLOPE log (VIN/2.2 µV) < VSET
For high frequency use, Figure 24 shows the input impedance
plotted on a Smith chart. This measured result of a typical de-
vice includes a 191 mil 50 Ω trace and a 680 pF capacitor to
ground from the INLO pin.
A further use of the separate VOUT and VSET pins is in raising
the load-driving current capability by the inclusion of an ex-
ternal NPN emitter follower. More complete information about
usage in these various modes is provided in the Applications
section.
Frequency
R
+j X
100MHz
100MHz 650 –j 400
900MHz 55 –j 135
1.9GHz 22 –j 65
2.5GHz 23 –j 43
INTERFACES
This section describes the signal and control interfaces and their
behavior. On-chip resistances and capacitances exhibit varia-
tions of up to ±20%. These resistances are sometimes tempera-
ture dependent and the capacitances may be voltage dependent.
AD8313 MEASURED
900MHz
Power-Down Interface, PWDN
2.5GHz
The power-down threshold is accurately centered at the midpoint
of the supply as shown in Figure 22. If Pin 5 is left unconnected or
tied to the supply voltage (recommended) the bias enable cur-
rent is shut off, and the current drawn from the supply is pre-
dominately through a nominal 300 kΩ chain (20 µA at 3 V). When
grounded, the bias system is turned on. The threshold level is
accurately at VPOS/2. The input bias current at the PWDN pin
when operating in the device “ON” state is approximately
5 µA for VPOS = 3 V.
1.9GHz
900⍀
1.1pF
Figure 24. Typical Input Impedance
Logarithmic/Error Output, VOUT
The rail-to-rail output interface is shown in Figure 25. VOUT
can run from within about 50 mV of ground, to within about
100 mV of the supply voltage, and is short-circuit safe to either
supply. However, the sourcing load current ISOURCE is limited by
that provided by the PNP transistor, to typically 400 µA. Larger
load currents can be provided by adding an external NPN tran-
sistor (see Applications). The dc open-loop gain of this amplifier
is high, and it may be regarded essentially as an integrator hav-
ing a capacitance of 2 pF (CINT) driven by the current-mode
signals generated by the summed outputs of the nine detector
stages, which is scaled approximately 4.0 µA/dB.
4
VPOS
150k⍀
50k⍀
75k⍀
TO BIAS
ENABLE
5
PWDN
150k⍀
1
6
VPOS
COMM
BIAS
STAGE
Figure 22. Power-Down Threshold Circuitry
Signal Inputs, INHI, INLO
I
SOURCE
FROM
400A
g
m
SET-POINT
VOUT
C
8
INT
SUMMED
DETECTOR
OUTPUTS
The simplest low frequency ac model for this interface consists
of just a 900 Ω resistance RIN in shunt with a 1.1 pF input ca-
pacitance, CIN connected across INHI and INLO. Figure 23
shows these distributed in the context of a more complete sche-
matic. The input bias voltage shown is for the enabled chip;
when disabled, it will rise by a few hundred millivolts. If the
input is coupled via capacitors, this change may cause a low-
level signal transient to be introduced, having a time-constant
formed by these capacitors and RIN. For this reason, large-
valued coupling capacitors should be well matched; this is not
necessary when using the small capacitors found in many im-
pedance transforming networks used at high frequencies.
LP
10mA
MAX
C
L
LM
6
COMM
Figure 25. Output Interface Circuitry
Thus, for a midscale RF input of about 3 mV, which is some
40 dB above the minimum detector output, this current is
160 µA and the output changes by 8 V/µs. When VOUT is
connected to VSET, the rise and fall times are approximately
40 ns (for RL ≥ 10 kΩ). The nominal slew rate is ±2.5 V/µs.
The HF compensation technique results in stable operation with
a large capacitive load, CL, though the positive-going slew rate
will then be limited by ISOURCE/CL to 1 V/µs for CL = 400 pF.
REV. B
–9–
AD8313
R1
10⍀
Setpoint Interface, VSET
R
PROT
1
2
3
4
The setpoint interface is shown in Figure 26. The voltage VSET
is divided by a factor of three in a resistive attenuator of total
resistance 18 kΩ. The signal is converted to a current by the
action of the op amp and the resistor R3 (1.5 kΩ), which bal-
ances the current generated by the summed output of the nine
detector cells at the input to the previous cell. The logarithmic
slope is nominally 3 × 4.0 µA/dB × 1.5 kΩ ≈ 18 mV/dB.
8
7
6
5
+V
VPOS VOUT
AD8313
S
0.1F
R
= 1M⍀
680pF
L
INHI
VSET
53.6⍀
680pF
INLO COMM
R2
10⍀
+V
VPOS
PWDN
S
0.1F
Figure 27. Basic Connections for Log (RSSI) Mode
1
VPOS
FDBK
TO O/P
STAGE
25A
25A
Operating in the Controller Mode
Figure 28 shows the basic connections for operation in control-
ler mode. The link between VOUT and VSET is broken and a
“setpoint” is applied to VSET. Any difference between VSET
and the equivalent input power to the AD8313, will drive VOUT
either to the supply rail or close to ground. If VSET is greater
than the equivalent input power, VOUT will be driven towards
ground and vice versa.
R1
12k⍀
LP
VSET
8
R2
6k⍀
R3
1.5k⍀
6
COMM
R1
10⍀
Figure 26. Setpoint Interface Circuitry
APPLICATIONS
R
PROT
CONTROLLER
OUTPUT
1
2
3
4
8
7
6
5
+V
VPOS VOUT
AD8313
S
0.1F
V
SETPOINT
INPUT
VSET
INHI
INLO COMM
VPOS
Basic Connections for Log (RSSI) Mode
Figure 27 shows the AD8313 connected in its basic measure-
ment mode. A power supply of +2.7 V to +5.5 V is required.
The power supply to each of the VPOS pins should be decoupled
with a 0.1 µF, surface mount ceramic capacitor and a series
resistor of 10 Ω.
R3
10⍀
+V
PWDN
S
0.1F
Figure 28. Basic Connections for Operation in the
Controller Mode
The PWDN pin is shown as grounded. The AD8313 may be
disabled by a logic “HI” at this pin. When disabled, the chip
current is reduced to about 20 µA from its normal value of
13.7 mA. The logic threshold is at VPOS/2 and the enable func-
tion occurs in about 1.8 µs; note, however, that further settling
time is generally needed at low input levels. While the input in
this case is terminated with a simple 50 Ω broadband resistive
match, there are a wide variety of ways in which the input termi-
nation can be accomplished. These are discussed in the Input
Coupling section.
This mode of operation is useful in applications where the out-
put power of an RF power amplifier (PA) is to be controlled by
an analog AGC loop (Figure 29). In this mode, a setpoint
voltage, proportional in dB to the desired output power, is ap-
plied to the VSET pin. A sample of the output power from the
PA, via a directional coupler or other means, is fed to the input
of the AD8313.
ENVELOPE OF
TRANSMITTED
SIGNAL
VSET is connected to VOUT to establish a feedback path that
controls the overall scaling of the logarithmic amplifier. The
load resistance, RL, should not be lower than 5 kΩ in order that
the full-scale output of 1.75 V can be generated with the limited
available current of 400 µA max.
POWER
AMPLIFIER
RF IN
As stated in the Absolute Maximum Ratings, an externally ap-
plied overvoltage on the VOUT pin that is outside the range 0 V
to VPOS is sufficient to cause permanent damage to the device. If
overvoltages are expected on the VOUT pin, a series resistor
(RPROT) should be included as shown. A 500 Ω resistor is suffi-
cient to protect against overvoltage up to ±5 V; 1000 Ω should
be used if an overvoltage of up to ±15 V is expected. Since the
output stage is meant to drive loads of no more than 400 µA,
this resistor will not impact device performance for more high
impedance drive applications (higher output current applications
are discussed in the Increasing Output Current section).
DIRECTIONAL
COUPLER
AD8313
VOUT
RFIN
SETPOINT
VSET
CONTROL DAC
Figure 29. Setpoint Controller Operation
VOUT is applied to the gain control terminal of the power ampli-
fier. The gain control transfer function of the power amplifier
should be an inverse relationship, i.e., increasing voltage de-
creases gain.
–10–
REV. B
AD8313
A positive input step on VSET (indicating a demand for in-
creased power from the PA) will drive VOUT towards ground.
This should be arranged to increase the gain of the PA. The
loop will settle when VOUT settles to a voltage that sets the input
3
2
BALANCED
power to the AD8313 to the dB equivalent of VSET
.
TERMINATED
DR = 66dB
1
MATCHED
Input Coupling
The signal may be coupled to the AD8313 in a variety of ways.
In all cases, there must not be a dc path from the input pins to
ground. Some of the possibilities include: dual input coupling
capacitors, a flux-linked transformer, a printed-circuit balun,
direct drive from a directional coupler, or a narrow-band imped-
ance matching network.
0
BALANCED
DR = 71dB
–1
–2
–3
MATCHED
DR = 69dB
Figure 30 shows a simple broadband resistive match. A termina-
tion resistor of 53.6 Ω combines with the internal input imped-
ance of the AD8313 to give an overall resistive input impedance
of approximately 50 Ω. The termination resistor should prefer-
ably be placed directly across the input pins, INHI to INLO,
where it serves to lower the possible deleterious effects of dc
offset voltages on the low end of the dynamic range. At low
frequencies, this may not be quite as attractive, since it necessi-
tates the use of larger coupling capacitors. The two 680 pF
input coupling capacitors set the high-pass corner frequency of
the network at 9.4 MHz.
–90 –80 –70 –60 –50 –40 –30 –20 –10
INPUT AMPLITUDE – dBm
0
10
Figure 31. Comparison of Terminated, Matched and
Balanced Input Drive at 900 MHz
3
TERMINATED
DR = 75dB
2
MATCHED
1
TERMINATED
C1
680pF
50⍀ SOURCE
50⍀
0
AD8313
MATCHED
DR = 73dB
BALANCED
R
53.6⍀
–1
–2
–3
MATCH
C2
680pF
C
R
IN
IN
BALANCED
DR = 75dB
Figure 30. A Simple Broadband Resistive Input Termination
0
–90 –80 –70 –60 –50 –40 –30 –20 –10
INPUT AMPLITUDE – dBm
10
The high pass corner frequency can be set higher according to
the equation:
Figure 32. Comparison of Terminated, Matched and
Balanced Input Drive at 1900 MHz
1
f3dB
=
2×π ×C ×50
A Narrow-Band LC Matching Example at 100 MHz
While numerous software programs are available that allow the
values of matching components to be easily calculated, a clear
understanding of the calculations involved is valuable. A low
frequency (100 MHz) value has been used for this exercise
because of the deleterious board effects at higher frequencies.
RF layout simulation software is useful when board design at
higher frequencies is required.
C1×C2
C1+C2
C =
where:
In high frequency applications, the use of a transformer, balun
or matching network is advantageous. The impedance match-
ing characteristics of these networks provide what is essentially a
gain stage before the AD8313 that increases the device sensitiv-
ity. This gain effect is further explored in the following match-
ing example.
A narrow-band LC match can be implemented either as a
series-inductance/shunt-capacitance or as a series-capacitance/
shunt-inductance. However, the concurrent requirement that the
AD8313 inputs, INHI and INLO, be ac-coupled, makes a
series-capacitance/shunt-inductance type match more appropri-
ate (see Figure 33).
Figures 31 and 32 show device performance under these three
input conditions at 900 MHz and 1900 MHz.
While the 900 MHz case clearly shows the effect of input
matching by realigning the intercept as expected, little improve-
ment is seen at 1.9 GHz. Clearly, if no improvement in sensitiv-
ity is required, a simple 50 Ω termination may be the best choice
for a given design based on ease of use and cost of components.
50⍀ SOURCE
AD8313
C1
50⍀
L
C
R
MATCH
IN
IN
C2
Figure 33. Narrow-Band Reactive Match
REV. B
–11–
AD8313
Typically, the AD8313 will need to be matched to 50 Ω. The
input impedance of the AD8313 at 100 MHz can be read from
the Smith Chart (Figure 24) and corresponds to a resistive input
impedance of 900 Ω in parallel with a capacitance of 1.1 pF.
C1 and C2 can be chosen in a number of ways. First C2 can be
set to a large value such as 1000 pF, so that it appears as an RF
short. C1 would then be set equal to the calculated value of
C
MATCH. Alternatively, C1 and C2 can each be set to twice
CMATCH so that the total series capacitance is equal to CMATCH
By making C1 and C2 slightly unequal (i.e., select C2 to be
about 10% less than C1) but keeping their series value the
same, the amplitude of the signals on INHI and INLO can be
equalized so that the AD8313 is driven in a more balanced
manner. Any one of the three options detailed above can be
.
To make the matching process simpler, the input capacitance of
the AD8313, CIN, can be temporarily removed from the calcula-
tion by adding a virtual shunt inductor (L2), which will resonate
away CIN (Figure 34). This inductor will be factored back into
the calculation later. This allows the main calculation to be
based on a simple resistive-to-resistive match (i.e., 50 Ω to
900 Ω).
used as long as the combined series value of C1 and C2 (i.e.,
C1 × C2/(C1 + C2)) is equal to CMATCH
.
The resonant frequency is defined by the equation
In all cases, the values of CMATCH and LMATCH must be chosen
from standard values. At this point, these values need now be
installed on the board and measured for performance at 100 MHz.
Because of board and layout parasitics, the component values
from the above example had to be tuned to the final values of
CMATCH = 8.9 pF and LMATCH = 270 nH shown in Table I.
1
ω =
L2 CIN
1
therefore: L2 =
= 2.3 µH
ω2 CIN
Assuming a lossless matching network and noting conservation
of power, the impedance transformation from RS to RIN (50 Ω
to 900 Ω) has an associated voltage gain given by
50⍀ SOURCE
50⍀
AD8313
C1
C2
RIN
RS
GaindB = 20×log
= 12.6 dB
C
R
L
L
IN
IN
1
2
Because the AD8313 input responds to voltage and not true
power, the voltage gain of the matching network will increase
the effective input low-end power sensitivity by this amount.
Thus, in this case, the dynamic range will be shifted down-
wards, that is, the 12.6 dB voltage gain will shift the 0 dBm to
–65 dBm input range downwards to –12.6 dBm to –77.6 dBm.
However, because of network losses this gain will not be fully
realized in practice. Reference Figures 31 and 32 for an example
of practical attainable voltage gains.
(C1 • C2)
(C1 + C2)
C
=
=
MATCH
TEMPORARY
INDUCTANCE
(L • L )
1
2
L
MATCH
(L + L )
1
2
Figure 34. Input Matching Example
With CIN and L2 temporarily out of the picture, the focus is now
on matching a 50 Ω source resistance to a (purely resistive) load
of 900 Ω and calculating values for CMATCH and L1.
Table I shows recommended values for the inductor and capaci-
tors in Figure 32 for some selected RF frequencies along with the
associated theoretical voltage gain. These values for a reactive
match are optimal for the board layout detailed as Figure 45.
As previously discussed, a modification of the board layout will
produce networks that may not perform as specified. At 2.5 GHz, a
shunt inductor is sufficient to achieve match. Consequently, C1
and C2 are set sufficiently high that they appear as RF shorts.
L1
CMATCH
When RS RIN
=
the input will look purely resistive at a frequency given by
1
fO =
= 100 MHz
2 π L1 CMATCH
Solving for CMATCH gives
Table I. Recommended Values for C1, C2 and LMATCH in
Figure 33
1
1
CMATCH
=
= 7.5 pF
2 π fO
RS RIN
F
req.
CMATCH
C1
C2
LMATCH Voltage
Solving for L1 gives
(MHz) (pF)
(pF)
(pF)
(nH)
Gain (dB)
100
8.9
22
9
3
1.5
3
1.5
390
15
1000
3
1000
3
1000
390
270
270
8.2
8.2
2.2
2.2
2.2
12.6
9.0
6.2
3.2
RS RIN
2 π fO
L1 =
= 337.6 nH
900
1.5
Because L1 and L2 are in parallel, they can be combined to give
the final value for LMATCH (i.e.)
1900
2500
1.5
L1 L2
L1 +L2
Large
LMATCH
=
= 294 nH
Figure 35 shows the voltage response of the 100 MHz matching
network; note the high attenuation at lower frequencies typical
of a high-pass network.
–12–
REV. B
AD8313
Table II. Values for REXT in Figure 37
15
10
5
Frequency
MHz
REXT
k⍀
Slope
mV/dB
VOUT Swing for Pin
–65 dBm to 0 dBm – V
100
900
1900
2500
100
900
1900
2500
0.953
2.00
2.55
0
29.4
32.4
33.2
26.7
20
20
20
20
0.44 to 1.74
0.58 to 1.88
0.70 to 2.00
0.54 to 1.84
1.10 to 4.35
1.46 to 4.74
1.74 to 4.98
1.34 to 4.57
50
50.4
49.8
49.7
0
The value for REXT is calculated using the equation:
–5
50
100
200
FREQUENCY – MHz
New Slope – Original Slope
(
=
)
× 18 kΩ
REXT
Figure 35. Voltage Response of 100 MHz Narrow-Band
Matching Network
Original Slope
The value for the Original Slope, at a particular frequency, can
be read from Figure 8. The resulting output swing is calculated
by simply inserting the New Slope value and the intercept at that
frequency (Figures 8 and 11) into the general equation for the
AD8313’s output voltage:
Adjusting the Log Slope
Figure 36 shows how the log slope may be adjusted to an exact
value. The idea is simple: the output at pin VOUT is attenuated
by the variable resistor R2 working against the internal 18 kΩ
of input resistance at the VSET pin. When R2 is zero, the
attenuation it introduces is zero, and thus the slope is the basic
18 mV/dB (note that this value varies with frequency, see
Figure 8). When R2 is set to its maximum value of 10 kΩ, the
attenuation from VOUT to VSET is the ratio 18/(18+10), and
the slope is raised to (28/18) × 18 mV, or 28 mV/dB. At about
the midpoint, the nominal scale will be 23 mV/dB. Thus, a
70 dB input range will change the output by 70 × 23 mV, or
1.6 V.
VOUT = Slope (PIN – Intercept)
Increasing Output Current
Where it is necessary to drive a more substantial load, one of
two methods can be used. In Figure 38, a 1 kΩ pull-up resistor
is added at the output which provides the load current necessary
to drive a 1 kΩ load to +1.7 V for VS = 2.7 V. The pull-up resis-
tor will slightly lower the intercept and the slope. As a result, the
transfer function of the AD8313 will be shifted upwards (inter-
cept shifts downward).
R1
10⍀
1
2
3
4
8
7
6
5
18-30mV/dB
+V
VPOS VOUT
AD8313
INHI
INLO COMM
VPOS
+V
S
S
0.1F
1k⍀
R1
VSET
10⍀
20mV/dB
R2
10k⍀
1
2
3
4
VPOS VOUT
AD8313
8
7
6
5
+V
S
0.1F
R
L
= 1k⍀
R3
10⍀
INHI
VSET
+V
PWDN
S
0.1F
INLO COMM
VPOS PWDN
R2
10⍀
+V
S
Figure 36. Adjusting the Log Slope
0.1F
As already stated, the unadjusted log slope varies with frequency
from 17 mV/dB to 20 mV/dB, as shown in Figure 8. By placing
a resistor between VOUT and VSET, the slope can be adjusted
to a convenient 20 mV/dB as shown in Figure 37. Table II
shows the recommended values for this resistor REXT. Also
shown are values for REXT that increase the slope to approxi-
mately 50 mV/dB. The corresponding voltage swings for a
–65 dBm to 0 dBm input range are also shown in Table II.
Figure 38. Increasing AD8313 Output Current Capability
In Figure 39, an emitter-follower is used to provide current
gain, when a 100 Ω load can readily be driven to full-scale out-
put. While a high β transistor such as the BC848BLT1 (min β =
200) is recommended, a 2 kΩ pull-up resistor between VOUT
and +VS can provide additional base current to the transistor.
+V
S
R1
10⍀
R1
10⍀

= 200
MIN
1
2
3
4
VPOS VOUT
AD8313
8
7
6
5
20mV/dB
+V
1
2
3
4
8
7
6
5
VPOS VOUT
AD8313
+V
S
BC848BLT1
S
0.1F
0.1F
R
EXT
13k⍀
OUTPUT
VSET
INLO COMM
VPOS
INHI
VSET
INHI
R
L
100⍀
10k⍀
INLO COMM
R3
10⍀
R3
10⍀
+V
PWDN
+V
S
VPOS
PWDN
S
0.1F
0.1F
Figure 37. Adjusting the Log Slope to a Fixed Value
REV. B
Figure 39. Output Current Drive Boost Connection
–13–
AD8313
In addition to providing current gain, the resistor/potentiometer
combination between VSET and the emitter of the transistor
increases the log slope to as much as 45 mV/dB, at maximum
resistance. This will give an output voltage of 4 V for a 0 dBm
input. If no increase in the log slope is required, VSET can be
connected directly to the emitter of the transistor.
The vacant portions of the signal and power layers are filled out
with ground plane for general noise suppression. To ensure a
low impedance connection between the planes, there are mul-
tiple through-hole connections to the RF ground plane. While
the ground planes on the power and signal planes are used as
general purpose ground returns, any RF grounds related to the
input matching network (e.g., C2) are returned directly to the
RF internal ground plane.
Effect of Waveform Type On Intercept
Although it is specified for input levels in dBm (dB relative to
1 mW), the AD8313 fundamentally responds to voltage and not
to power. A direct consequence of this characteristic is that
input signals of equal rms power but differing crest factors will
produce different results at the log amp’s output.
General Operation
The board should be powered by a single supply in the range,
+2.7 V to +5.5 V. The power supply to each of the VPOS pins
is decoupled by a 10 Ω resistor and a 0.1 µF capacitor.
The effect of different signal waveforms is to vary the effec-
tive value of the log amp’s intercept upwards or downwards.
Graphically, this looks like a vertical shift in the log amp’s trans-
fer function. The device’s logarithmic slope, however, is in
principle not affected. For example, consider the case of the
AD8313 being alternately fed from a continuous wave and a
single CDMA channel of the same rms power. The AD8313’s
output voltage will differ by the equivalent of 3.55 dB (64 mV)
over the complete dynamic range of the device (the output for a
CDMA input being lower).
The two signal inputs are ac-coupled using 680 pF high quality
RF capacitors (C1, C2). A 53.6 Ω resistor across the differential
signal inputs (INHI, INLO) combines with the internal 900 Ω
input impedance to give a broadband input impedance of 50.6 Ω.
This termination is not optimal from a noise perspective due to
the Johnson noise of the 53.6 Ω resistor. Neither does it take
account for the AD8313’s reactive input impedance or of the
decrease over frequency of the resistive component of the input
impedance. However, it does allow evaluation of the AD8313
over its complete frequency range without having to design
multiple matching networks.
Table III shows the correction factors that should be applied to
measure the rms signal strength of a various signal types. A
continuous wave input is used as a reference. To measure the
rms power of a square-wave, for example, the mV equivalent
of the dB value given in the table (18 mV/dB times 3.01 dB)
should be subtracted from the output voltage of the AD8313.
For optimum performance, a narrowband match can be imple-
mented by replacing the 53.6 Ω resistor (labeled L/R) with an
RF inductor and replacing the 680 pF capacitors with appropri-
ate values. The section on Input Matching includes a table of
recommended values for selected frequencies and explains the
method of calculation.
Table III. Shift in AD8313 Output for Signals with Differing
Crest Factors
Switch 1 is used to select between power-up and power-down
modes. Connecting the PWDN pin to ground enables normal
operation of the AD8313. In the opposite position, the PWDN
pin can either be driven externally (SMA connector labeled
EXT ENABLE) to either device state or allowed to float to a
disabled device state.
Correction Factor
(Add to Output Reading)
Signal Type
CW Sine Wave
0 dB
Square Wave or DC
Triangular Wave
–3.01 dB
+0.9 dB
The evaluation board ships with the AD8313 configured to
operate in RSSI measurement mode, the logarithmic output
appearing on the SMA connector labeled VOUT. This mode is
set by the 0 Ω resistor (R11), which shorts the VOUT and
VSET pins to each other.
GSM Channel (All Time Slots On) +0.55 dB
CDMA Channel
PDC Channel (All Time Slots On)
Gaussian Noise
+3.55 dB
+0.58 dB
+2.51 dB
Varying the Logarithmic Slope
The slope of the AD8313 can be increased from its nominal
value of 18 mV/dB to a maximum of 40 mV/dB by removing
R11, the 0 Ω resistor, which shorts VSET to VOUT. VSET and
VOUT are now connected through a 20 kΩ potentiometer.
EVALUATION BOARD
Schematic and Layout
Figure 44 shows the schematic of the evaluation board that was
used to characterize the AD8313. Note that uninstalled compo-
nents are drawn in as dashed.
Operating in Controller Mode
To put the AD8313 into controller mode, R7 and R11 should
be removed, breaking the link between VOUT and VSET. The
VSET pin can then be driven externally via the SMA connector
labeled EXT VSET IN ADJ.
This is a 3-layer board (signal, ground and power), with a Duroid
dielectric (RT 5880, h = 5 mil, εR = 2.2). FR4 can also be used,
but microstrip dimensions must be recalculated because of the
different dielectric constant and board height. The trace layout
and silkscreen of the signal and power layers are shown in Fig-
ures 40 to 43. A detail of the PCB footprint for the µSOIC
package and the pads for the matching components are shown
in Figure 45.
Increasing Output Current
To increase the output current of VOUT, set both R3 and R11 to
0 Ω and install potentiometer R4 (1 kΩ to 5 kΩ).
–14–
REV. B
AD8313
Figure 42. Signal Layer Silkscreen
Figure 40. Layout of Signal Layer
Figure 41. Layout of Power Layer
Figure 43. Power Layer Silkscreen
REV. B
–15–
AD8313
R5
0⍀
R1
10⍀
8
7
6
5
1
2
3
4
VPOS VOUT
AD8313
+V
VOUT
S
C3
C1
680pF
R11
R7
0⍀
R6
C6
0.1F
0⍀
SIG IN
INHI
VSET
R8
L/R
53.6⍀
C2
680pF
20k⍀
EXT VSET
EXT ENABLE
INLO COMM
R2
10⍀
R4
R3
+V
PWDN
VPOS
S
C4
0.1F
+V
S
SW1
Figure 44. Evaluation Board Schematic
NOT CRITICAL DIMENSIONS
35
48
TRACE WIDTH
54.4
15.4
90.6
50
16
28
10
19
UNIT = MILS
41
75
20
50
22
20
27.5
51
91.3
126
51.7
48
46
Figure 45. Detail of PCB Footprint for Package and Pads for Matching Network
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead SOIC Package
(RM-08)
0.122 (3.10)
0.114 (2.90)
5
4
8
1
0.199 (5.05)
0.187 (4.75)
0.122 (3.10)
0.114 (2.90)
PIN 1
0.0256 (0.65) BSC
0.120 (3.05)
0.112 (2.84)
0.120 (3.05)
0.112 (2.84)
0.043 (1.09)
0.037 (0.94)
0.006 (0.15)
0.002 (0.05)
33؇
27؇
0.018 (0.46)
0.008 (0.20)
0.011 (0.28)
0.003 (0.08)
0.028 (0.71)
0.016 (0.41)
SEATING
PLANE
–16–
REV. B
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