AD8320ARP [ADI]
Serial Digital Controlled Variable Gain Line Driver; 串行数字控制可变增益线路驱动器
| 型号： | AD8320ARP |
| 厂家： | 
ADI |
| 描述： | Serial Digital Controlled Variable Gain Line Driver |
| 文件： | 总20页 (文件大小：584K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Serial Digital Controlled
Variable Gain Line Driver
a
AD8320
FEATURES
8-Bit Serial Gain Control
FUNCTIO NAL BLO CK D IAGRAM
V/ V/ LSB Linear Gain Response
36 dB Gain Range
؎0.20 dB Gain Accuracy
VCC
GND
PWR AMP
AD8320
REFERENCE
Upper Bandw idth: 150 MHz
VOUT
22 dBm 1 dB Com pression Point (75 ⍀)
Drives Low Distortion Signals into 75 ⍀ Load:
–57 dBc SFDR at 42 MHz and 12 dBm Out
–46 dBc SFDR at 42 MHz and 18 dBm Out
Single Supply Operation from 5 V to 12 V
Maintains 75 ⍀ Output Im pedance
Pow er-Up and Pow er-Dow n Condition
Supports SPI Input Control Standard
VREF
VIN
REVERSE
AMP
INV.
BUF.
ATTENUATOR CORE
DATA LATCH
POWER-
DOWN/
SWITCH
INTER.
PD
DATA SHIFT REGISTER
APPLICATIONS
Coaxial Cable Driver
DATEN CLK
SDATA
HFC Cable Telephony System s
HFC High Speed Data Modem s
Interactive Set-Top Boxes
PC Plug-In Modem s
Interfaces w ith AD9853 I2C Controlled Digital Modulator
High Perform ance Digitally Controlled Variable Gain
Block
D ESCRIP TIO N
results in low glitch output during power-down and power-up
transitions, eliminating the need for an external switch.
T he AD8320 is a digitally controlled variable gain amplifier
optimized for coaxial line driving applications. An 8-bit serial
word determines the desired output gain over a 36 dB range
(256 gain levels). T he AD8320 provides linear gain response.
T he AD8320 is packaged in a 20-lead SOIC and operates from
a single +5 V through +12 V supply and has an operational
temperature range of –40°C to +85°C.
T he AD8320 is made up of a digitally controlled variable at-
tenuator of 0 dB to –36 dB, which is preceded by a low noise,
fixed gain buffer and followed by a low distortion high power
amplifier. T he AD8320 has a 220 Ω input impedance and ac-
cepts a single-ended input signal with a specified analog input
level of up to 0.310 V p-p. T he output is specified for driving a
75 Ω load, such as coaxial cable, although the AD8320 is ca-
pable of driving other loads. Distortion performance of –57 dBc
is achieved with an output level up to 12 dBm (3.1 V p-p) at
42 MHz, while –46 dBc distortion is achieved with an output
level up to 18 dBm (6.2 V p-p).
؊20
؊30
P
= 18dBm
O
؊40
؊50
؊60
P
= 12dBm
O
P
= 8dBm
O
A key performance and cost advantage of the AD8320 results
from the ability to maintain a constant 75 Ω output impedance
during power-up and power-down conditions. T his eliminates
the need for external 75 Ω back-termination, resulting in twice
the effective output voltage when compared to a standard opera-
tional amplifier. Additionally, the on-chip 75 Ω termination
؊70
؊80
P
= 4dBm
O
10
FREQUENCY – MHz
100
1
Figure 1. Worst Harm onic Distortion vs. Frequency for
Various Output Levels at VCC = 12 V
REV. 0
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 781/ 329-4700
Fax: 781/ 326-8703
World Wide Web Site: http:/ / w w w .analog.com
© Analog Devices, Inc., 1998
(@ V = 12 V, T = +25؇C, V = 0.310 V p-p, R = 75 ⍀, R = 75 ⍀ unless
CC
A
IN
L
S
otherwise noted)
AD8320–SPECIFICATIONS
P aram eter
Conditions
Min
Typ
Max
Units
INPUT CHARACT ERIST ICS
Full-Scale Input Voltage
Max Gain, POUT = 18 dBm, VCC = 12 V
Max Gain, POUT = 12 dBm, VCC = 5 V
0.310
0.155
220
V p-p
V p-p
Ω
Input Resistance
Input Capacitance
2.0
pF
GAIN CONT ROL INT ERFACE
Gain Range
36
dB
Full Scale (Max) Gain
Gain Offset (Min) Gain
Gain Scaling Factor
26 (20)
–10.0 (0.316)
0.077
dB (V/V)
dB (V/V)
V/V/LSB
OUT PUT CHARACT ERIST ICS
Bandwidth (–3 dB)
Bandwidth Roll-Off
All Gain Codes
F = 65 MHz
F = 65 MHz
150
0.7
0
MHz
dB
dB
Bandwidth Peaking
Output Offset Voltage
Output Offset Drift
Output Noise Spectral Density
All Gain Codes
±40
±0.25
73
mV
Full T emperature Range
Max. Gain, Frequency = 10 MHz
Min. Gain, Frequency = 10 MHz
PD = 0, Frequency = 10 MHz
VCC = 12 V
VCC = 5 V
Power Up and Power Down
Max Gain, VIN = 500 mV p-p
mV/°C
nV/√Hz
nV/√Hz
nV/√Hz
dBm
dBm
Ω
53
4.5
22.5
16
75
40
1 dB Compression Point
Output Impedance
Overload Recovery
65
85
ns
OVERALL PERFORMANCE
Worst Harmonic Distortion
F = 42 MHz, POUT = 12 dBm, VCC = 12 V
F = 42 MHz, POUT = 12 dBm, VCC = 5 V
F = 42 MHz, POUT = 18 dBm, VCC = 12 V
F = 65 MHz, POUT = 12 dBm, VCC = 12 V
F = 65 MHz, POUT = 12 dBm, VCC = 5 V
F = 65 MHz, POUT = 18 dBm, VCC = 12 V
F = 42 MHz, POUT = 18 dBm, VCC = 12 V
F = 42 MHz, POUT = 12 dBm, VCC = 5 V
F = 65 MHz, POUT = 18 dBm, VCC = 12 V
F = 65 MHz, POUT = 12 dBm, VCC = 5 V
F = 10 MHz
–57.0
–43.0
–46.0
–57.0
–42.5
–43.0
34
–52.0
–39.0
–42.0
–52.0
–39.0
–40.0
dBc
dBc
dBc
dBc
dBc
dBc
dBm
dBm
dBm
dBm
dB
3rd Order Intercept
32
32.5
28.5
±0.1
±0.2
Full-Scale (Max Gain) Accuracy
Gain Offset (Min Gain) Accuracy
Gain Accuracy
F = 10 MHz
F = 10 MHz, All Gain Codes
dB
dB
–0.75 ±0.2
0.75
Gain Drift
Full T emperature Range
VCC = +5 V to 12 V
±0.5
35
mdB/°C
mdB/V
Gain Variation w/Supply
Output Settling to 1 mV
Gain Change @ TDATEN = 1
Input Change
Min to Max Gain, VIN = 0.31 V p-p
Max Gain, VIN = 0 V to 0.31 V p-p
30
25
ns
ns
POWER CONT ROL
Power-Down Settling T ime to 1 mV
Power-Up Settling T ime to 1 mV
Power-Down Pedestal Offset
Spectral Output Leakage
Max Gain, VIN = 0
Max Gain, VIN = 0
Max Gain, VIN = 0
F (PD) = 400 Hz @ 15% Duty Cycle
5 MHz ≤ F ≤ 65 MHz
PD = 0
45
65
±30
–70
ns
ns
mV
dBm
Maximum Reverse Power
5
dBm
POWER SUPPLY
Specified Operating Range
Quiescent Current
Power Down
Power Up, VCC = +12 V
Power Down, VCC =+12 V
+5
80
25
97
32
+12
85
30
105
37
V
PD = 1, VCC = +5 V
PD = 0, VCC = +5 V
PD = 1, VCC = +12 V
PD = 0, VCC = +12 V
mA
mA
mA
mA
–2–
REV. 0
AD8320
LOGIC INPUTS (TTL/CMOS Logic) (DATEN, CLK, SDATA, 5 V ≤ V ≤ 12 V; Full Temperature Range)
CC
P aram eter
Min
Typ
Max
Units
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current (VINH = 5 V) CLK, SDAT A, DATEN
Logic “0” Current (VINL = 0 V) CLK, SDAT A, DATEN
Logic “1” Current (VINH = 5 V) PD
Logic “0” Current (VINL = 0 V) PD
2.1
0
0
–450
0
–320
5.0
0.8
20
–75
190
–70
V
V
nA
nA
µA
µA
(Full Temperature Range, V Supply Range, T = T = 4 ns, FCLK = 8 MHz unless otherwise noted.)
TIMING REQUIREMENTS
P aram eter
CC
R
F
Min
Typ
Max
Units
Clock Pulse Width (TWH
Clock Period (TC)
Setup T ime SDAT A vs. Clock (TDS
Setup T ime DATEN vs. Clock (TES
Hold T ime SDAT A vs. Clock (TDH
)
12.0
32.0
6.5
17.0
5.0
ns
ns
ns
ns
ns
ns
ns
)
)
)
)
Hold T ime DATEN vs. Clock (TEH
Input Rise and Fall T imes, SDAT A, DATEN, Clock (TR, T F)
3.0
10
T
DS
VALID DATA WORD G1
VALID DATA WORD G2
SDATA
CLK
MSB. . . .LSB
T
C
T
WH
EH
T
T
ES
8 CLOCK CYCLES
DATEN
PD
GAIN TRANSFER (G1)
GAIN TRANSFER (G2)
T
OFF
T
GS
T
ON
ANALOG
OUTPUT
PEDESTAL
SIGNAL AMPLITUDE (p-p)
Figure 2. Serial Interface Tim ing
VALID DATA BIT
MSB-1
MSB
MSB-2
T
T
DH
DS
CLK
Figure 3.
–3–
REV. 0
AD8320
ABSO LUTE MAXIMUM RATINGS*
Supply Voltage +VS
P IN CO NFIGURATIO N
Pins 7, 8, 9, 17, 20 . . . . . . . . . . . . . . . . . . . –0.8 V to +13 V
Input Voltages
Pins 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3 V
Pins 1, 2, 3, 6 . . . . . . . . . . . . . . . . . . . . . . . . –0.8 V to +5 V
Internal Power Dissipation
Small Outline (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 W
Operating T emperature Range . . . . . . . . . . . –40°C to +85°C
Storage T emperature Range . . . . . . . . . . . . –65°C to +150°C
Lead T emperature, Soldering 60 seconds . . . . . . . . . . +300°C
1
2
20 VCC
SDATA
CLK
19
18
17
16
15
14
13
12
11
VIN
3
VREF
VCC
GND
GND
BYP
GND
GND
GND
DATEN
GND
4
5
VOCM
AD8320
TOP VIEW
(Not to Scale)
6
PD
VCC
VCC
VCC
VOUT
7
8
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. T his is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
9
10
O RD ERING GUID E
P ackage D escription
Model
Tem perature Range
P ackage O ption
RP-20
JA
AD8320ARP
AD8320-EB
–40°C to +85°C
20-Lead Thermally Enhanced Power SOIC*
Evaluation Board
53°C/W
*Shipped in tubes (38 pieces/tube) and dry packed per J-ST D-020.
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8320 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
P IN FUNCTIO N D ESCRIP TIO NS
P in
Function
D escription
1
SDAT A
Serial Data Input. T his digital input allows for an 8-bit serial (gain) word to be loaded into the internal
register with the MSB (most significant bit) first.
2
3
CLK
Clock Input. T he clock port controls the serial attenuator data transfer rate to the 8-bit master-slave
register. A Logic 0 to 1 transition latches the data bit and a 1 to 0 transfers the data bit to the slave.
T his requires the input serial data word to be valid at or before this clock transition.
DATEN
Data Enable Low Input. T his port controls the 8-bit parallel data latch and shift register. A Logic 0 to 1
transition transfers the latched data to the attenuator core (updates the gain) and simultaneously inhib-
its serial data transfer into the register. A 1 to 0 transition inhibits the data latch (holds the previous
gain state) and simultaneously enables the register for serial data load.
4, 11, 12,
13, 15, 16
GND
Common External Ground Reference.
5
VOCM
VCC/2 Reference Pin. A dc output reference level that is equal to 1/2 of the supply voltage (VCC).
T his port should be externally ac decoupled (0.1 µF cap).
6
PD
Power-Down Low Logic Input. A Logic 0 powers down (shuts off) the power amplifier disabling the
output signal and enabling the reverse amplifier. A Logic 1 enables the output power amplifier and
disables the reverse amplifier.
7, 8, 9, 17, 20 VCC
Common Positive External Supply Voltage.
10
14
18
VOUT
Output Signal Port. DC biased to approximately VCC/2.
Internal Bypass. T his pin must be externally ac decoupled (0.1 µF cap).
BYP
VREF
Input Reference Voltage (typically 1.9 V at 27°C). T his port should be externally ac decoupled
(0.1 µF cap).
19
VIN
Analog Voltage Input Signal Port. DC biased to VREF voltage.
–4–
REV. 0
Typical Performance Characteristics–AD8320
0.6
0.3
0.3
0.2
0.45
V
= 12V
CC
F = 10MHz
T = +25؇C
V
= 12V
F = 10MHz
CC
0.30
T = +25؇C
T = +25؇C
0.1
0.15
0
0
10MHz
42MHz
V
= 12V
CC
0
؊0.3
؊0.6
T = ؊40؇C
T = +85؇C
؊0.15
؊0.1
V
= 5V
CC
65MHz
؊0.30
؊0.45
؊0.2
؊0.3
؊0.9
؊1.2
256
0
64
128
192
0
64
128
192
256
0
64
128
192
256
GAIN CONTROL – Decimal
GAIN CONTROL – Decimal
GAIN CONTROL – Decimal
Figure 4. Gain Error vs. Gain Control
at Various Tem peratures
Figure 6. Gain Error vs. Gain Control
at Different Supply Voltages
Figure 5. Gain Error vs. Gain Control
at Various Frequencies
30
؊20
30
255D
255D
170D
V
= 5V
V
= 12V
CC
CC
MAX GAIN
PD = 0V
؊30
؊40
؊50
؊60
؊70
؊80
؊90
170D
85D
20
10
0
20
10
85D
0
V
= 5V, P = ؊14dBm
IN
CC
01D
00D
01D
00D
؊10
؊20
؊10
؊20
V
= 12V, P = ؊8dBm
IN
CC
؊100
100k
100k
1M
10M
100M
1G
1M
10M
100M
1G
100k
1M
10M
100M
1G
FREQUENCY – Hz
FREQUENCY – Hz
FREQUENCY – Hz
Figure 9. Input Signal Feedthrough
vs. Frequency
Figure 7. AC Response
Figure 8. AC Response
90
80
75
70
65
60
80
75
70
65
60
F = 10MHz
F = 10MHz
V
= 12V
CC
80
MAX GAIN, V = 12V
CC
+85؇C
70
V
= 12V
CC
+25؇C
MAX GAIN, V = 5V
CC
60
MIN GAIN, V = 12V
CC
؊40؇C
V
= 5V
55
50
CC
55
50
50
MIN GAIN, V = 5V
CC
40
30
45
40
45
40
256
128
192
10M
1M
FREQUENCY – Hz
100M
0
64
100k
256
128
192
0
64
GAIN CONTROL – Decimal
GAIN CONTROL – Decimal
Figure 10. Output Referred Noise vs.
Gain Control at Various Tem peratures
Figure 12. Output Referred Noise vs.
Frequency
Figure 11. Output Referred Noise vs.
Gain Control at Different Supply
Voltages
REV. 0
–5–
AD8320
؊30
؊20
؊30
؊40
؊50
؊60
؊20
؊30
؊40
V
= 12V
CC
F = 65MHz, P = 18dBm
O
؊40
؊50
؊60
؊70
P
= 12dBm
F = 42MHz, P = 18dBm
O
O
P
= 12dBm
O
P
= 10dBm
P
= 10dBm
O
O
؊50
؊60
P
= 8dBm
O
F = 42MHz, P = 12dBm
O
؊80
؊90
؊70
؊80
؊70
؊80
P = 4dBm
O
P
= 8dBm
F = 65MHz, P = 12dBm
O
O
P
= 4dBm
O
0
64
128
192
256
1
10
FREQUENCY – MHz
100
1
10
FREQUENCY – MHz
100
GAIN CONTROL – Decimal
Figure 13. Worst Harm onic Distor-
tion vs. Gain Control
Figure 14. Worst Harm onic Distor-
tion vs. Frequency for Various Output
Levels at VCC = 5 V
Figure 15. Worst Harm onic Distor-
tion vs. Frequency for Various Output
Levels at VCC = 6 V
؊20
؊30
؊20
؊30
40
V
P
= 12V
CC
= 18dBm
O
F = 42MHz
N = 30
P
= 18dBm
O
30
20
P
= 18dBm
O
؊40
؊40
؊50
؊60
P
O
= 12dBm
P
= 12dBm
؊50
؊60
O
P
= 8dBm
P
= 8dBm
O
O
10
0
؊70
؊80
؊70
؊80
P
= 4dBm
O
P
O
= 4dBm
10
FREQUENCY – MHz
100
1
1
10
100
؊47
؊46
؊45
؊44
؊43
FREQUENCY – MHz
HARMONIC DISTORTION – dBc
Figure 17. Worst Harm onic Distor-
tion vs. Frequency for Various Output
Levels at VCC = 12 V
Figure 16. Worst Harm onic Distor-
tion vs. Frequency for Various Output
Levels at VCC = 10 V
Figure 18. Distribution of Worst Har-
m onic Distortion
40
20
30.0
V
P
= 5V
V
P
= 12V
= 18dBm
V
P
= 12V
= 12dBm
CC
= 12dBm
CC
CC
O
O
O
F = 65MHz
N = 30
F = 65MHz
N = 30
F = 42MHz
N = 30
30
20
15
10
22.5
15.0
10
0
5
0
7.5
0
؊45
؊44
؊43
؊42
؊41
؊59
؊58
؊57
؊56
؊55
؊44
؊43
؊42
؊41
؊40
HARMONIC DISTORTION ؊ dBc
HARMONIC DISTORTION ؊ dBc
HARMONIC DISTORTION ؊ dBc
Figure 19. Distribution of Worst Har-
m onic Distortion
Figure 20. Distribution of Worst Har-
m onic Distortion
Figure 21. Distribution of Worst Har-
m onic Distortion
–6–
REV. 0
AD8320
45
40
؊35
؊40
؊45
20
0
V
= 12V
F = 42MHz, V = 5V, P = 12dBm
CC
CC
O
P
= 18dBm
O
MAX GAIN
= 12V
V
CC
P
= 12dBm
O
–20
–40
35
30
F = 65MHz
P = 18dBm
O
V
= 12V
CC
؊50
؊55
F = 42MHz
P
= 18dBm
O
V
= 12V
CC
P
= 18dBm
O
25
20
–60
–80
؊60
؊65
F = 65MHz, V = 12V, P = 12dBm
CC
O
0
25
50
75
100
؊50 ؊25
1
10
FREQUENCY – MHz
100
41.2
41.6
42.0
42.4
42.8
TEMPERATURE ؊ ؇C
FREQUENCY – MHz
Figure 22. Harm onic Distortion vs.
Tem perature
Figure 23. Two-Tone Interm odula-
tion Distortion
Figure 24. Third Order Intercept vs.
Frequency
30
V
= 5V
CC
MAX GAIN
V
V
= 12V
= 310mV p-p
V
V
= 12V
= 310mV p-p
27
24
21
CC
CC
C
= 0pF
L
IN
IN
MAX GAIN
F = 10MHz
MIN GAIN
F = 10MHz
C
= 22pF
L
C
= 100pF
L
C
= 150pF
L
18
15
1.2V
12.5nsec
12.5nsec
20mV
100k
1M
10M
100M
1G
FREQUENCY – Hz
Figure 26. Transient Response
Figure 25. Transient Response
Figure 27. AC Response for Various
Capacitive Loads
30
V
= 12V
CC
MAX GAIN
V
= 12V
V
= 5V
27
24
21
CC
CC
C
= 0pF
MAX GAIN
F = 1MHz
MAX GAIN
F = 1MHz
L
C
= 22pF
C
= 22pF
L
L
C
= 100pF
L
C
= 100pF
L
C
= 0pF
C
= 0pF
L
L
C
= 22pF
L
C
= 150pF
C
= 150pF
L
L
C
= 100pF
L
C
= 150pF
L
18
15
500mV
1V
5nsec
5nsec
TIME – Seconds
100k
1M
10M
100M
1G
FREQUENCY – Hz
Figure 29. AC Response for Various
Capacitive Loads
Figure 30. Transient Response for
Various Capacitive Loads
Figure 28. Transient Response for
Various Capacitive Loads
REV. 0
–7–
AD8320
V
= 12V
V
= 5V
100mV
1.25V
5mV
CC
CC
V
= 12V
CC
MAX GAIN
= 0V p-p
MAX GAIN
= 0V p-p
F = 40MHz
MAX GAIN
V
V
IN
OUT
V
IN
V
V
OUT
OUT
CLK
V
IN
PD
75nsec
DATEN
500mV
5V
20nsec
5V
250nsec
Figure 33. Overload Recovery
Figure 32. Clock Feedthrough
Figure 31. Power-Up/Power-Down
Glitch
V
= 12V, F = 40MHz
V
= 12V, F = 40MHz
CC
MIN TO MAX GAIN
= .310V p-p
2.50V
V
2.50V
V
= 12V
2.00V
V
CC
CC
MAX GAIN
F = 40MHz
MAX GAIN
V
IN
V
OUT
OUT
OUT
V
V
IN
IN
DATEN
5V
1V
20nsec
20nsec
250mV
20nsec
Figure 35. Output Settling Tim e Due
to Input Change
Figure 36. Output Settling Tim e Due
to Gain Change
Figure 34. Overload Recovery
80
90
120
V
= 5V
V
= 5V, PD = 0
CC
CC
R
= 115⍀
V
= 12V, PD = 1
= 5V, PD = 1
T
CC
V
= 5V, PD = 1
100
80
60
40
20
0
CC
80
70
70
V
V
CC
60
50
40
V
= 12V, PD = 1
CC
V
= 12V, PD = 0
CC
= 12V, PD = 0
= 5V, PD = 0
CC
60
50
V
CC
100k
1M
10M
100M
100k
1M
10M
100M
1G
–50
–25
0
25
50
75
100
FREQUENCY – Hz
FREQUENCY – Hz
TEMPERATURE – ؇C
Figure 38. Output Im pedance vs.
Frequency
Figure 37. Input Im pedance vs.
Frequency
Figure 39. Supply Current vs.
Tem perature
–8–
REV. 0
AD8320
32
24
16
8
O P ERATIO NAL D ESCRIP TIO N
T he AD8320 is a digitally controlled variable gain power ampli-
fier that is optimized for driving 75 Ω cable. A multifunctional
bipolar device on single silicon, it incorporates all the analog
features necessary to accommodate reverse path (upstream) high
speed (5 MH z to 65 MH z) cable data modem and cable tele-
phony requirements. T he AD8320 has an overall gain range of
36 dB (–10 dB to 26 dB) and is capable of greater than 100 MHz
of operation at output signal levels exceeding 18 dBm. Overall,
when considering the device’s wide gain range, low distortion,
wide bandwidth and variable load drive, the device can be used
in many variable gain block applications.
0
A
= 20
؋
LOG (0.316 + 0.077 ؋
CODE) 10
V
–8
T he digitally programmable gain is controlled by the three wire
“SPI” compatible inputs. T hese inputs are called SDAT A
(serial data input port), DATEN (data enable low input port)
and CLK (clock input port). See Pin Function Descriptions and
Functional Block diagram. T he AD8320 is programmed by an
8-bit “attenuator” word. T hese eight bits determine the 256
programmable gain settings. See attenuator core description
below. T he gain is linear in V/V/LSB and can be described by
the following equation:
–16
0
32
64
96
128
160
192
224
256
GAIN – Code – Decimal
Figure 41. Log Gain vs. Gain Control
T he attenuator core can be viewed as eight binarily weighted
(differential in–differential out) transconductance (gm) stages
with the “in phase” current outputs of all eight stages connected
in parallel to their respective differential load resistors (not
shown). T he core differential output signals are also 180 degrees
out of phase and equal in amplitude. T he input stages are like-
wise parallel, connected to the inverting input amplifier and
buffer outputs as shown. Nine bits plus of accuracy is achieved
for all gain settings over the specified frequency, supply voltage
and temperature range. T he actual total core GM × RL attenua-
tion is determined by which combination of binarily weighted
gm stages are selected by the data latch. With 8 bits, 256 levels
of attenuation can be programmed. T his results in a 36 dB
attenuation range (0 dB to –36 dB). See gain equation above.
AV = 0.316 + 0.077 × Code (RL = 75 Ω)
where code is the decimal equivalent of the 8-bit word. For ex-
ample, if all 8 bits are at a logic “1,” the decimal equivalent is
255 and AV equals 19.95 V/V or 26 dB. T he gain scaling factor
is 0.077 V/V/LSB, with an offset of 0.316 V/V (–10.0 dB). Fig-
ure 40 shows the linear gain versus decimal code and Figure 41
shows the gain in dB versus decimal code. Note the nonlin-
earity that results when viewed in dB versus code. T he dB step
size increases as the attenuation increases (i.e., gain decreases)
and reaches a maximum step size of approximately 1.9 dB (gain
change between 01 and 00 decimal).
VCC
GND
PWR AMP
22
20
18
AD8320
REFERENCE
VOUT
VREF
VIN
A
= 0.316 + 0.077
؋
CODE REVERSE
AMP
V
INV.
BUF.
ATTENUATOR CORE
16
14
12
10
POWER-UP
DATA LATCH
POWER–
DOWN
PD
8
6
4
SWITCH
INTER.
DATA SHIFT REGISTER
2
DATEN CLK
SDATA
POWER-DOWN
0
Figure 42. Functional Block Diagram
–2
0
32
64
96
128
160
192
224
256
T o update the AD8320 gain, the following digital load sequence
is required. T he attenuation setting is determined by the 8-bit
word in the data latch. T his 8-bit word is serially loaded (MSB
first) into the shift register at each rising edge of the clock. See
Figure 43. During this data load time (T ), DATEN is low and
the data latch is latched holding the previous (T – 1) data word
keeping the attenuation level unchanged. After eight clock
cycles the new data word is fully loaded and DATEN is
switched high. T his enables the data latch (becomes transpar-
ent) and the loaded register data is passed to the attenuator with
the updated gain value. Also at this DATEN transition, the
internal clock is disabled, thus inhibiting new serial input data.
GAIN – Code – Decimal
Figure 40. Linear Gain vs. Gain Control
The AD8320 is composed of three analog functions in the power-
up or forward mode (Figure 42). T he input inverter/buffer
amplifier provides single-ended to differential output conver-
sion. T he output signals are nominally 180 degrees out of phase
and equal in amplitude with a differential voltage gain of 2 (6 dB).
Maintaining close to 180 degrees and equal amplitude is re-
quired for proper gain accuracy of the attenuator core over the
specified operating frequency. T he input buffer/inverter also
provides equal dc voltages to the core inputs via the internal
reference. T his is required to ensure proper core linearity over
the full specified power supply range (5 V to 12 V).
REV. 0
–9–
AD8320
T
DS
VALID DATA WORD G1
MSB. . . .LSB
VALID DATA WORD G2
SDATA
CLK
T
C
T
WH
T
T
ES
EH
8 CLOCK CYCLES
DATEN
PD
GAIN TRANSFER (G1)
GAIN TRANSFER (G2)
T
OFF
T
GS
T
ON
ANALOG
OUTPUT
SIGNAL AMPLITUDE (p-p)
PEDESTAL
Figure 43. Serial Interface Tim ing
T he power amplifier has two basic modes of operation; forward
or power-up mode and reverse or power-down mode. In the
power-up mode (PD = 1), the power amplifier stage is enabled
and the differential output core signal is amplified by 20 dB.
With a core attenuation range of 0 dB to –36 dB and 6 dB of
input gain, the overall AD8320 gain range is 26 dB to –10 dB.
In this mode, the single-ended output signal maintains a dc
level of VCC/2. T his dc output level provides for optimum large
signal linearity and allows for dc coupling the output if neces-
sary. T he output stage is unique in that it maintains a dynamic
output impedance of 75 Ω. T his allows for a direct 75 Ω cable
connection and results in 6 dB of added load power versus using
a series 75 Ω back-termination resistor as required with tradi-
tional low output impedance amplifiers. T he power amplifier
will also drive lower or higher output loads, although the device’s
gain (not gain range) will change accordingly (see Applications
section).
what is referred to as sleep and standby modes, and VCC supply
switching via PFETS or equivalent, as described in the applica-
tions section, would be required.
AP P LICATIO NS
T he AD8320 is primarily intended to be used as the return path
(also called upstream path) line driver in cable modem and
cable telephony applications. Data to be transmitted is modu-
lated in either QPSK or QAM format. T his is done either in
DSP or by a dedicated QPSK/QAM modulator such as the
AD9853.
T he amplifier receives its input signal either from the dedicated
QPSK/QAM modulator or from a DAC. In both cases, the
signal must be low-pass filtered before being applied to the line
driving amplifier.
CENTRAL
OFFICE
SUBSCRIBER
TO MODEM
RECEIVE
In the power-down mode (PD = 0), the power amplifier is turned
off and a “reverse” amplifier (the inner triangle in Figure 42) is
enabled. During this 1 to 0 transition, the output power amplifier’s
input stage is also disabled, resulting in no forward output signal
(S21 is 0), although the attenuator core and input amplifier/
buffer signals are not affected (S11 ≈ 0). T he function of the
reverse amplifier is to maintain 75 Ω and VCC/2 at the output
port (VOUT ) during power-down. T his is required to minimize
line reflections (S22 ≈ 0) and ensures proper filter operation for
any forward mode device sharing the same bus (i.e., in a multi-
plexed configuration). (See Applications section.) In the time
domain, as PD switches states, a transitional glitch and pedestal
offset results. (See Figures 31 and 43.) T he powered down
supply current drops to 32 mA versus 97 mA (VCC = 12 V) in
power-up mode.
CIRCUITRY
DIPLEXER
75⍀
7TH ORDER
ELLIPTIC
LOW PASS
FILTER
AD9853
AD8320
Figure 44. Block Diagram of Cable Modem ’s Upstream
Driver Section
T he amplifier drives the line through a diplexer. T he insertion
loss of a diplexer is typically –3 dB. As a result, the line driver
must deliver a power level roughly 3 dB greater than required by
the applicable cable modem standard so that diplexer losses are
canceled out.
Because the distance to the central office varies from subscriber
to subscriber, signals from different subscribers will be attenu-
ated by differing amounts. As a result, the line driver is required
to vary its gain so that all signals arriving at the central office
have the same amplitude.
Generally, using the power-down low input (PD) for switching
allows for multiple devices to be multiplexed via splitters (N-1
off, 1 on) and reduces overall total power consumption as re-
quired for cable data applications. For cable telephony, the
power-down current generally needs to be much lower during
–10–
REV. 0
AD8320
Basic Connection
T he timing diagram for AD8320’s serial interface is shown in
Figure 43.
Figure 45 shows the basic schematic for operating the AD8320.
Because the amplifier operates from a single supply, the input
signal must be ac-coupled using a 0.1 µF capacitor. T he input
pin has a bias level of about 1.9 V. T his bias level is available on
the VREF pin (Pin 18) and can be used to externally bias signals
if dc-coupling is desired. Under all conditions, a 0.1 µF decoupling
capacitor must be connected to the VREF pin. If the VREF volt-
age is to be used externally, it should be buffered first.
T he write cycle to the device is initiated by the falling edge of
DATEN. T his is followed by eight clock pulses that clock in the
control word. Because the clock signal is level triggered, data is
effectively clocked on the falling edge of CLK.
After the control word has been clocked in, the DATEN line
goes back high, allowing the gain to be updated (this takes
about 30 ns).
T he VIN pin of the AD8320 (Pin 19) has an input impedance
of 220 Ω. T ypically, in video applications, 75 Ω termination is
favored. As a result, an external shunt resistance (R1) to ground
of 115 Ω is required to create an overall input impedance of
75 Ω. If 50 Ω termination is required, a 64.9 Ω shunt resistor
should be used. Note, to avoid dc loading of the VIN pin, the
ac-coupling capacitor should be placed between the input pin
and the shunt resistor as shown in Figure 45.
T he relationship between gain and control word is given by the
equation:
Gain (V/V) = 0.077 × Code + 0.316
where code is the decimal equivalent of the gain control word
(0 to 255).
T he gain in dB is given by the equation:
On the output side, the VOUT pin also has a dc bias level. In
this case the bias level is midway between the supply voltage and
ground. T he output signal must therefore be ac-coupled before
being applied to the load. T he dc bias voltage is available on the
VOCM pin (Pin 5) and can be used in dc-coupled applications.
T his node must be decoupled to ground using a 0.1 µF capaci-
tor. If the VOCM voltage is to be used externally, it should be
buffered.
Gain (dB) = 20 log10 (0.077 × Code + 0.316)
T he digital interface also contains an asynchronous power-down
mode. T he normally high PD line can be pulled low at any time.
T his turns off the output signal after 45 ns, and reduces the
quiescent current to between 25 mA and 32 mA (depending
upon the power supply voltage). In this mode, the programmed
gain is maintained.
Clock Line Feedthr ough
Since the AD8320 has a dynamic output impedance of 75 Ω, no
external back termination resistor is required. If the output
signal is being evaluated on 50 Ω test equipment such as a spec-
trum analyzer, a 75 Ω to 50 Ω adapter (commonly called a pad)
should be used to maintain a properly matched circuit.
Clock feedthrough results in a 5 mV p-p signal appearing super-
imposed on the output signal (see Figure 32). If this impinges
upon the dynamic range of the application, the clock signal
should be noncontinuous, i.e., should only be turned on for
eight cycles during programming.
Var ying the Gain
T he gain of the AD8320 can be varied over a range of 36 dB,
from –10 dB to +26 dB, by varying the 8-bit gain setting word.
P ower Supply and D ecoupling
T he AD8320 should be powered with a good quality (i.e., low
noise) single supply of between +5 V and +12 V. In order to
achieve an output power level of +18 dBm (6.2 V p-p) into
VCC
+5V TO +12V
C3
0.1F
C7
10F
C5
0.1F
C4
0.1F
C2
0.1F
C11
0.1F
C6
0.1F
VCC
VCC
VCC
VCC
GND
BYP
VCC
C10
0.1F
VOUT
AD8320
REFERENCE
C12
0.1F
TO DIPLEXER
RIN = 75⍀
C1
0.1F
VREF
VIN
VOCM
ATTENUATOR CORE
DATA LATCH
C8
0.1F
INPUT
R1*
115⍀
POWER-
DOWN
/
PD
*FOR A 75⍀ INPUT
IMPEDANCE
SWITCH
INTER.
DATA SHIFT REGISTER
SDATA GND GND GND GND GND
CLK
DATEN
CLK
SDATA
DATEN
PD
Figure 45. Basic Connection
–11–
REV. 0
AD8320
75 Ω, a supply voltage of at least +10 V is required. T o achieve
a signal level of +12 dBm (about 3.1 V p-p) into 75 Ω, a mini-
mum supply level of +5 V is required. However, for the lowest
possible distortion, the power supply voltage should be raised as
high as possible. In varying the power supply from +5 V to
+12 V, the quiescent current increases from 80 mA to 97 mA.
A HEXFET power MOSFET (International Rectifier part num-
ber IRLML5103) is used to turn on and off the current to the
supply pins of the AD8320. Under normal operating conditions,
the gate (labeled POWER-DOWN) should be grounded. Pull-
ing the gate to within 2 V of the supply will open the switch and
reduce the current to the amplifier to zero.
Careful attention must be paid to decoupling the power supply
pins. A 10 µF capacitor, located fairly close to the device, is
required to provide good decoupling for lower frequency signals.
In addition, five 0.1 µF decoupling capacitors should be located
close to each of the five power supply pins (7, 8, 9, 17 and 20).
A 0.1 µF capacitor must also be connected to the pin labeled
BYP (Pin 14), to provide decoupling to an internal node of the
device. All six ground pins should be connected to a low imped-
ance ground plane.
In cable modem and cable telephony applications the modem
must always present an output impedance of 75 Ω to the line.
T his forces the line driver to always present a 75 Ω impedance
to the diplexer. In this application, a single pole double throw
RF switch (AS103, Alpha Semiconductor) is used to switch in
an external 75 Ω impedance when the AD8320 is turned off.
T his resistor then mimics the dynamic output impedance of the
AD8320. T T L or CMOS logic can be used to drive the two
voltages driving the RF switch (V1 and V2).
Alter native P ower -D own Mode
Before the AD8320 is turned back on again, the gain needs to
be set to a known level. T his can be done by holding the PD pin
of the AD8320 low after POWER-DOWN has gone high. While
PD is held low, the 8-bit serial data stream can be clocked into
the AD8320. During this time the quiescent current will in-
crease to 32 mA. However, this time period can be as small as
about 1 µs. In this mode the output settles about 45 ns after the
rising edge of PD.
As previously mentioned, the AD8320 can be put into a low
power sleep mode by pulling the PD pin low. If lower power
consumption is required during power-down mode, an alternative
scheme can be used as shown in Figure 46.
VCC+12V
POWER-
S
DOWN
G
IRLML5103
Alternatively, if DATEN is held low as the AD8320 is powered
on, the device will power up in minimum gain. In this mode, the
output settles after about 200 µs. Note that for both cases, the
capacitor on VOCM has been reduced from 0.1 µF to 0.01 µF
to facilitate a faster turn-on time. All other capacitors in the
circuit should be connected as shown in Figure 45.
0.1F
D
VOUT
J1
PD
VDD
+5V
AS103
(SEETEXT)
J2
VCC
PD
DATEN
CLK
0.1F
0.1F
75⍀
VOUT
VOCM
J3
AD8320*
0.1F
SDATA
GND
75⍀
14
0.1F
V2
V1
0.01F
V2
V1
*ADDITIONAL PINS AND DECOUPLING CAPACITORS
OMITTED FOR CLARITY
10–12V
POWER-
DOWN
0V
3–5V
V1
V2
0V
3–5V
0V
PD
DATEN
0V
CLK
SDATA
OUTPUT
97mA
97mA
32mA
QUIESCENT
CURRENT
0mA
Figure 46. Alternative Power-Down Mode with Tim ing
–12–
REV. 0
AD8320
TO MODEM
RECEIVE
CHANNEL
58dBmV
DIPLEXER
75⍀
+5V
+12V
AD603*
VIN
VIN
VPOS
AD8320*
VOUT
11dBmV
0.1F
220⍀
75⍀
100⍀
FBDK
61dBmV
؉5V
20pF
41dBmV
220⍀
VNEG
GNEG
GPOS
COMM
–5V
PD
VDD
REFIN
CLR
+0.5V
1.5⍀
1k⍀
AD7801*
*ADDITIONAL PINS AND
DECOUPLING CAPACITORS
OMITTED FOR CLARITY
DGND
AGND
CS WR LDAC D0–D7
8
D0–D7
74HCT164*
CLK
A
B
DATA
CLK
ENABLE
PD
Figure 47. Enhanced Dynam ic Range Circuit
Enhanced D ynam ic Range Application
T he AD8320 can be combined with the AD603 to give addi-
tional dynamic range as shown in Figure 47. T he AD603 is a
voltage controlled variable gain amplifier. The gain of the AD603 is
determined by the difference in voltage between the GPOS and
GNEG pins. T his differential voltage has a range of ±0.5 V. In
this example, the voltage on GNEG is tied to +0.5 V. As the
voltage on GPOS is varied from 0 V to 1 V, the gain of the AD603
changes from –10 dB to +30 dB with a slope of 25 mV/dB (i.e.,
linear in dB). T he gain control voltage is supplied by the AD7801
DAC. T he output voltage of the DAC (0 V to +2.5 V) is divided
down to fit the 0 V to 1 V range of the AD603 using a resistor
attenuator network.
In order that the same gain control word can be used for both
the AD603 and the AD8320, the serial data stream is converted
to the parallel format of the AD7801 DAC using a serial-to-
parallel shift register. T he rising edge of the enable pulse simul-
taneously updates both amplifiers.
Figure 48. Output Spectrum of Enhanced Dynam ic Range
Circuit (Output Level = 61 dBm V, Frequency = 42 MHz)
60
50
As the control word is varied from 00Dec to 255Dec, the gain of
the signal chain varies from –26 dB to +50 dB (there is 6 dB of
attenuation between AD603 and AD8320). In practice, this
circuit is not usable at the lower end of the gain range due to the
small input signal (11 dBmV or about 10 mV p-p). Figure 48
shows the spectrum of the output signal at a frequency of
42 MHz and an output level of 61 dBmV (3.1 V p-p, max gain).
AD8320/AD603
40
30
AD8320
20
10
AD603
0
T he gain vs. code transfer function of the two amplifiers along
with the overall gain is shown in Figure 49. T he overall gain
transfer function combines a linear in dB transfer function with
a linear in Volts/Volt transfer function. It is clear from Figure 49
that the overall gain transfer function can be considered to be
approximately linear in dB over the top 50 dB of its range.
–10
–20
–30
0
21 41 61 81 101 121 141 161 181 201 221 241
GAIN CONTROL WORD – Decimal
Figure 49. Gain Transfer Function of Enhanced Dynam ic
Range Circuit
REV. 0
–13–
AD8320
Var ying Gain by Var ying Load Im pedance
and tested to demonstrate the specified high speed performance
of the device. Figure 51 shows the schematic of the evaluation
board. T he silkscreen for the component side layer is shown in
Figure 52. T he layout of the board is shown in Figure 53 and
Figure 54.
As already mentioned, the AD8320 has a dynamic output im-
pedance of 75 Ω. T he specified gain range assumes that the
output is terminated with a 75 Ω load impedance. Varying the
load impedance allows the gain to be varied, up to a maximum
of twice the specified gain (for RL
= ϱ). T he variation in gain
T he evaluation board package includes a fully populated board
with BNC-type connectors along with Windows®-based soft-
ware for controlling the board from a PC’s printer port via a
standard printer cable.
with load resistance is shown in Figure 50 for the case of a gain
control word of 255Dec (i.e., max gain).
32
30
28
26
24
22
20
A prototyping area is provided to allow for additional circuitry
on the board. The single supply and ground to the board are
brought over to this area and are available on two strips. T here
are also two extra strips available on the prototyping area which
can be used for additional power supplies.
T he board should be powered with a good quality (i.e., low
noise) single supply of between +5 V and +12 V. Extensive
decoupling is provided on the board. A 10 µF capacitor, located
fairly close to the device, provides good decoupling for lower
frequency signals. In addition, and more importantly, five
0.1 µF decoupling capacitors are located close to each of the
five power supply pins (7, 8, 9, 17 and 20).
0
100
1000
10000
Contr olling the Evaluation Boar d fr om a P C
R
– ⍀
LOAD
T he evaluation board ships with Windows-based control soft-
ware. A standard printer cable can be used to connect the
evaluation board to a PC’s printer port (also called parallel
port). T he cable length should be kept to less than about 5 feet.
T he wiring of a standard printer cable, with respect to the sig-
nal lines that are used in this application, is shown in Figure 55.
Although the software controls the evaluation board via the
PC’s parallel port, the AD8320 digital interface is serial. T hree
of the parallel port’s eight bits (and one digital ground line) are
used to implement this serial interface. A fourth bit is used to
control the PD pin.
Figure 50. Gain vs. RLOAD (Gain Control Word = 255Dec)
T he gain can be described by the following equation:
2 RLOAD
AV = 20 log10
0.316 +0.077 × Code
(
)
RLOAD +75
where Code is the decimal equivalent of the 8-bit word.
Evaluation Boar d
A two layer evaluation board for the AD8320 is available (part
number AD8320-EB). T his board has been carefully laid out
VCC
C7
C3
0.1F
C6
0.1F
C5
0.1F
C4
0.1F
C2
0.1F
C11
0.1F
10F
TP2
TP4
VCC
VCC
VCC
VCC
GND
BYP
VCC
VREF
C10
0.1F
OUTPUT
VOCM
VOUT
AD8320
C12
0.1F
REFERENCE
TP3
TP1
C1
0.1F
VREF
VIN
ATTENUATOR CORE
DATA LATCH
C8
0.1F
VOCM
R1
115⍀
INPUT
POWER-
DOWN
/
PD
SWITCH
INTER
DATA SHIFT REGISTER
SDATA
GND GNDGND GNDGND
CLK
DATEN
R4
0
C9
OPTIONAL
3
5
2
16, 19-30, 33
6
36-PIN CENTRONICS CONNECTOR
Figure 51. Evaluation Board Schem atic
All trademarks are the property of their respective holders.
–14–
REV. 0
AD8320
T he control software requires Windows 3.1 or later to operate.
T o install the software, insert the disk labeled “Disk # 1 of 2” in
the PC and run the file called SETUP.EXE. Additional installa-
tion instructions will be given on-screen. Before beginning installa-
tion, it is important to close any other Windows applications
that are running.
can power down or reset the device simply by clicking the
appropriate buttons. T he software also offers one volatile stor-
age location that can be used to store a particular gain. T his
functions in the same way as the memory on a pocket calculator.
O ver shoot on P C P r inter P or ts’ D ata Lines
T he data lines on some printer ports have excessive overshoot.
Overshoot on the pin used as the serial clock (Pin 6 on the D-
Sub-25 connector) can cause communication problems. T his
overshoot can be eliminated by applying mild filtering to the
CLK line on the evaluation board. T his can be done by putting
a small series resistor on the CLK line, combined with a
capacitor to ground. Pads are provided (C9, R4) on the com-
ponent side of the evaluation board to allow easy insertion of
these devices. Determining the size of these values will take
some experimentation. Depending upon the overshoot from the
printer port, this capacitor may need to be as large as 0.01 µF,
while the resistor is typically in the 50 Ω to 100 Ω range.
When you launch the installed control software from Windows,
you will be asked to select the printer port you are using. Most
modern PCs have only one printer port, usually called LPT 1.
However, some laptop computers use the PRN port.
Figure 56 shows the main screen of the control software. Using
the slider, you can set any gain in the AD8320’s 36 dB range.
T he gain is displayed on-screen in dB and V/V. T he 8-bit gain
setting byte is also displayed, in binary, hexadecimal and decimal.
Each time the slider is moved, the software automatically sends
and latches the required 8-bit data stream to the AD8320. You
Figure 52. Evaluation Board Silkscreen (Com ponent Side)
REV. 0
–15–
AD8320
Figure 53. Evaluation Board Layout (Com ponent Side)
–16–
REV. 0
AD8320
Figure 54. Evaluation Board Layout (Solder Side)
36 PIN CENTRONICS
D-SUB 25 PIN (MALE)
1
1
19
DATEN
14
PD
SDATA
CLK
GND
25
13
SIGNAL
D-SUB-25
2
36-PIN CENTRONICS
3
DATEN
PD
3
5
1
DATA
CLK
5
6
2
DGND
25
16, 19–30, 33
36
18
EVALUATION BOARD
PC
Figure 55. Interconnection Between AD8320EB and PC Printer Port
REV. 0
–17–
AD8320
Figure 56. Screen Display of Windows-Based Control Software
–18–
REV. 0
AD8320
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
20-Lead Ther m ally Enhanced P ower Sm all O utline P ackage
(RP -20)
0.5118 (13.00)
0.4961 (12.60)
20
11
0.1890 (4.80) 0.4193 (10.65)
0.1791 (4.55) 0.3937 (10.00)
HEAT
SINK
0.2992 (7.60)
0.2914 (7.40)
1
10
PIN 1
0.3340 (8.61)
0.3287 (8.35)
0.1043 (2.65)
0.0926 (2.35)
8°
0°
0.0500
(1.27)
BSC
0.0201 (0.51)
0.0118 (0.30)
0.0295 (0.75)
0.0098 (0.25)
SEATING
PLANE
0.0500 (1.27)
0.0057 (0.40)
x 45°
0.0130 (0.33)
0.0040 (0.10)
STANDOFF
REV. 0
–19–
–20–
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