AD8323ARU [ADI]
5 V CATV Line Driver Fine Step Output Power Control; 5 V CATV线路驱动器精细步骤输出功率控制
| 型号： | AD8323ARU |
| 厂家： | 
ADI |
| 描述： | 5 V CATV Line Driver Fine Step Output Power Control |
| 文件： | 总16页 (文件大小：278K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
5 V CATV Line Driver Fine Step
Output Power Control
a
AD8323
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Supports DOCSIS Standard for Reverse Path
Transmission
V
CC
(7 PINS)
BYP
Gain Programmable in 0.75 dB Steps Over a 53.5 dB
Range
R1
AD8323
Low Distortion at 60 dBmV Output
–56 dBc SFDR at 21 MHz
–55 dBc SFDR at 42 MHz
V
V
V
V
IN+
OUT+
DIFF OR
SINGLE
INPUT
AMP
POWER
AMP
ATTENUATION
CORE
BUFFER
IN–
OUT–
Output Noise Level
–48 dBmV in 160 kHz
Z
DIFF =
OUT
75⍀
8
DECODE
R2
Maintains 75 ⍀ Output Impedance
Power-Up and Power-Down Condition
Upper Bandwidth: 100 MHz (Full Gain Range)
5 V Supply Operation
Z
Z
(SINGLE) = 800⍀
(DIFF) = 1.6k⍀
IN
IN
8
POWER-DOWN
LOGIC
DATA LATCH
8
SHIFT
REGISTER
Supports SPI Interfaces
APPLICATIONS
Gain-Programmable Line Driver
HFC High-Speed Data Modems
Interactive Set-Top Boxes
DATEN DATA CLK GND (11 PINS)
PD
SLEEP
PC Plug-in Modems
General-Purpose Digitally Controlled Variable Gain Block
GENERAL DESCRIPTION
–50
–55
–60
–65
–70
The AD8323 is a low-cost, digitally controlled, variable gain ampli-
fier optimized for coaxial line driving applications such as cable
modems that are designed to the MCNS-DOCSIS upstream
standard. An 8-bit serial word determines the desired output gain
over a 53.5 dB range resulting in gain changes of 0.7526 dB/LSB.
F
= 42MHz
O
P
= 60dBmV @ MAX GAIN
O
HD3
HD2
The AD8323 comprises a digitally controlled variable attenuator
of 0 dB to –53.5 dB, which is preceded by a low noise, fixed
gain buffer and is followed by a low distortion high power am-
plifier. The AD8323 accepts a differential or single-ended input
signal. The output is specified for driving a 75 Ω load, such as
coaxial cable.
Distortion performance of –56 dBc is achieved with an output
level up to 60 dBmV at 21 MHz bandwidth. A key performance
and cost advantage of the AD8323 results from the ability to main-
tain a constant 75 Ω output impedance during power-up and
power-down conditions. This eliminates the need for external 75 Ω
termination, resulting in twice the effective output voltage when
compared to a standard operational amplifier. In addition, this
device has a sleep mode function that reduces the quiescent
current to 4 mA.
–75
0
8
16
24
32
40
48
56
64
72
GAIN CONTROL – DEC Code
Figure 1. Harmonic Distortion vs. Gain Control
The AD8323 is packaged in a low-cost 28-lead TSSOP, operates
from a single 5 V supply, and has an operational temperature
range of –40°C to +85°C.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000
(TA = 25؇C, VS = 5 V, RL = RIN = 75 ⍀, VIN = 116 mV p-p, VOUT measured through a 1:1
transformer1 with an insertion loss of 0.5 dB @ 10 MHz unless otherwise noted.)
AD8323–SPECIFICATIONS
Parameter
Conditions
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Specified AC Voltage
Noise Figure
Output = 60 dBmV, Max Gain
Max Gain, f = 10 MHz
Single-Ended Input
116
13.8
800
1600
2
mV p-p
dB
Input Resistance
Ω
Differential Input
Ω
Input Capacitance
pF
GAIN CONTROL INTERFACE
Gain Range
Maximum Gain
52.5
26.5
–27
53.5
27.5
–26
54.5
28.5
–25
dB
dB
dB
Gain Code = 71 Dec
Gain Code = 0 Dec
Minimum Gain
Gain Scaling Factor
0.7526
dB/LSB
OUTPUT CHARACTERISTICS
Bandwidth (–3 dB)
Bandwidth Roll-Off
All Gain Codes
f = 65 MHz
f = 65 MHz
100
1.3
0
MHz
dB
dB
Bandwidth Peaking
Output Noise Spectral Density
Max Gain, f = 10 MHz
–34
dBmV in
160 kHz
dBmV in
160 kHz
dBmV in
160 kHz
dBm
Min Gain, f = 10 MHz
–48
–68
Power-Down Mode, f = 10 MHz
1 dB Compression Point
Max Gain, f = 10 MHz
18.5
Differential Output Impedance
Power-Up and Power-Down
75 20%
Ω
OVERALL PERFORMANCE
Second Order Harmonic Distortion f = 21 MHz, POUT = 60 dBmV @ Max Gain
f = 42 MHz, POUT = 60 dBmV @ Max Gain
–77
–71
–64
–56
–55
–53
0.3
dBc
dBc
dBc
dBc
dBc
dBc
dB
f = 65 MHz, POUT = 60 dBmV @ Max Gain
Third Order Harmonic Distortion
f = 21 MHz, POUT = 60 dBmV @ Max Gain
f = 42 MHz, POUT = 60 dBmV @ Max Gain
f = 65 MHz, POUT = 60 dBmV @ Max Gain
f = 10 MHz, Code to Code
Gain Linearity Error
Output Settling to 1 mV
Due to Gain Change
Due to Input Step Change
Signal Feedthrough
Min to Max Gain
Max Gain, VIN = 0 V to 116 mV p-p
Max Gain, PD = 0, f = 42 MHz
60
30
–30
ns
ns
dBc
POWER CONTROL
Power-Up Settling Time to 1 mV
Max Gain, VIN = 0
300
40
3
ns
ns
mV p-p
Power-Down Settling Time to 1 mV Max Gain, VIN = 0
Between Burst Transients2
Equivalent Output = 31 dBmV
Equivalent Output = 60 dBmV
30
mV p-p
POWER SUPPLY
Operating Range
Quiescent Current
4.75
123
30
5
5.25
140
40
V
Power-Up Mode
Power-Down Mode
Sleep Mode
133
35
4
mA
mA
mA
2
7
OPERATING TEMPERATURE
RANGE
–40
+85
°C
NOTES
1TOKO 617DB-A0070 used for above specifications. MACOM ETC-1-IT-15 can be substituted.
2Between Burst Transients measured at the output of a 42 MHz diplexer.
Specifications subject to change without notice.
–2–
REV. 0
AD8323
(DATEN, CLK, SDATA, PD, SLEEP, V = 5 V: Full Temperature Range)
LOGIC INPUTS (TTL/CMOS Compatible Logic)
CC
Parameter
Min
Typ
Max
Unit
Logic “1” Voltage
Logic “0” Voltage
2.1
0
5.0
0.8
V
V
Logic “1” Current (VINH = 5 V) CLK, SDATA, DATEN
Logic “0” Current (VINL = 0 V) CLK, SDATA, DATEN
Logic “1” Current (VINH = 5 V) PD
Logic “0” Current (VINL = 0 V) PD
Logic “1” Current (VINH = 5 V) SLEEP
Logic “0” Current (VINL = 0 V) SLEEP
0
–600
50
–250
50
–250
20
nA
nA
µA
µA
µA
µA
–100
190
–30
190
–30
TIMING REQUIREMENTS
(Full Temperature Range, VCC = 5 V, TR = TF = 4 ns, fCLK = 8 MHz unless otherwise noted.)
Parameter
Min
Typ
Max
Unit
Clock Pulsewidth (TWH
Clock Period (TC)
Setup Time SDATA vs. Clock (TDS
Setup Time DATEN vs. Clock (TES
Hold Time SDATA vs. Clock (TDH
Hold Time DATEN vs. Clock (TEH
Input Rise and Fall Times, SDATA, DATEN, Clock (TR, TF)
)
16.0
32.0
5.0
15.0
5.0
ns
ns
ns
ns
ns
ns
ns
)
)
)
)
3.0
10
T
DS
VALID DATA WORD G1
VALID DATA WORD G2
SDATA
CLK
MSB. . . .LSB
T
C
T
WH
EH
T
T
ES
8 CLOCK CYCLES
DATEN
PD
GAIN TRANSFER (G1)
GAIN TRANSFER (G2)
T
OFF
T
GS
T
ON
ANALOG
OUTPUT
PEDESTAL
SIGNAL AMPLITUDE (p-p)
Figure 2. Serial Interface Timing
VALID DATA BIT
MSB-1
SDATA MSB
MSB-2
T
T
DH
DS
CLK
Figure 3. SDATA Timing
–3–
REV. 0
AD8323
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage +VS
Pins 5, 9, 10, 19, 20, 23, 27 . . . . . . . . . . . . . . . . . . . . . . 6 V
Input Voltages
Pins 25, 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pins 1, 2, 3, 6, 7 . . . . . . . . . . . . . . . . . . . . . –0.8 V to +5.5 V
Internal Power Dissipation
TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.9 W
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature, Soldering 60 seconds . . . . . . . . . . . 300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
PIN CONFIGURATION
1
2
GND
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DATEN
SDATA
CLK
V
CC
3
V
0.5 V
IN–
GND
4
V
IN+
V
5
GND
CC
6
V
PD
SLEEP
GND
CC
AD8323
TOP VIEW
(Not to Scale)
7
GND
BYP
8
V
9
V
CC
CC
V
10
V
CC
CC
GND 11
GND 12
GND 13
OUT– 14
GND
GND
GND
OUT+
ORDERING GUIDE
Model
Temperature Range
Package Description
JA
Package Option
AD8323ARU
AD8323ARU-REEL
AD8323-EVAL
–40°C to +85°C
–40°C to +85°C
28-Lead TSSOP
28-Lead TSSOP
Evaluation Board
67.7°C/W*
67.7°C/W*
RU-28
RU-28
*Thermal Resistance measured on SEMI standard 4-layer board.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8323 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Description
1
DATEN
Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A Logic
0-to-1 transition transfers the latched data to the attenuator core (updates the gain) and simulta-
neously inhibits serial data transfer into the register. A 1-to-0 transition inhibits the data latch
(holds the previous gain state) and simultaneously enables the register for serial data load.
2
3
SDATA
CLK
Serial Data Input. This digital input allows for an 8-bit serial (gain) word to be loaded into the
internal register with the MSB (Most Significant Bit) first.
Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit master-
slave register. A Logic 0-to-1 transition latches the data bit and a 1-to-0 transfers the data bit to
the slave. This requires the input serial data word to be valid at or before this clock transition.
4, 8, 11,12,
13, 16, 17, 18,
22, 24, 28
GND
VCC
Common External Ground Reference.
5, 9, 10, 19,
20, 23, 27
Common Positive External Supply Voltage. A 0.1 µF capacitor must decouple each pin.
6
7
PD
Logic “0” powers down the part. Logic “1” powers up the part.
SLEEP
Low Power Sleep Mode. In the Sleep mode, the AD8323’s supply current is reduced to 4 mA. A
Logic “0” powers down the part (High ZOUT State) and a Logic “1” powers up the part.
14
15
21
25
OUT–
OUT+
BYP
Negative Output Signal.
Positive Output Signal.
Internal Bypass. This pin must be externally ac-coupled (0.1 µF cap).
Noninverting Input. DC-biased to approximately VCC/2. For single-ended inverting operation,
use a 0.1 µF decoupling capacitor and a 39.2 Ω resistor between VIN+ and ground.
VIN+
26
VIN–
Inverting Input. DC-biased to approximately VCC/2. Should be ac-coupled with a 0.1 µF capacitor.
–4–
REV. 0
Typical Performance Characteristics–
AD8323
34
P
= 60dBmV
OUT
OUT
1:1
@ MAX GAIN
IN
C
V
V
L
IN–
31
28
25
R
75⍀
L
IN+
V
TOKO 617DB–A0070
CC
1:1
C
= 0pF
L
0.1F
V
IN
OUT
0.1F
V
IN–
R
75⍀
OUT–
L
R
82.5⍀
TI
OUT+
V
IN+
C
= 50pF
GND
L
0.1F
39.2⍀
C
= 20pF
L
0.1F
C
= 10pF
L
22
19
1
10
FREQUENCY – MHz
100
TPC 4. AC Response for Various Cap Loads
TPC 1. Basic Test Circuit
–30
1.5
1.0
0.5
f = 10MHz
PD = 1
–34
–38
–42
–46
–50
f = 10MHz
0.0
–0.5
–1.0
–1.5
f = 5MHz
f = 42MHz
f = 65MHz
0
8
16
24
32
40
48
56
64
72
0
8
16
24
32
40
48
56
64
72
GAIN CONTROL – Decimal
GAIN CONTROL – Decimal
TPC 5. Output Referred Noise vs. Gain Control
TPC 2. Gain Error vs. Gain Control
0
40
30
PD = 0
V
= 116mV p-p
IN
71D
46D
–20
–40
–60
20
MAX GAIN
10
0
23D
00D
–10
–20
–30
–40
MIN GAIN
–80
–100
0.1
1
10
100
1k
0.1
1
10
100
1k
FREQUENCY – MHz
FREQUENCY – MHz
TPC 6. Input Signal Feedthrough vs. Frequency
TPC 3. AC Response
REV. 0
–5–
AD8323
85
80
75
70
–60
R
= 82.5⍀
TI
–65
–70
–75
–80
P
= 62dBmV
OUT
@ MAX GAIN
PD = 0
PD = 1
P
= 61dBmV
OUT
@ MAX GAIN
P
= 60dBmV
OUT
@ MAX GAIN
65
60
55
P
= 58dBmV
OUT
@ MAX GAIN
–85
5
15
25
35
45
55
65
1
10
FREQUENCY – MHz
100
FUNDAMENTAL FREQUENCY – MHz
TPC 7. Second Order Harmonic Distortion vs. Frequency
for Various Output Levels
TPC 10. Input Impedance vs. Frequency
–45
80
75
70
P
= 62dBmV
OUT
@ MAX GAIN
P
= 61dBmV
OUT
–50
–55
PD = 1
PD = 0
@ MAX GAIN
65
60
55
50
P
= 60dBmV
OUT
@ MAX GAIN
–60
–65
P
= 58dBmV
OUT
@ MAX GAIN
5
15
25
35
45 55
65
1
10
100
FUNDAMENTAL FREQUENCY – MHz
FREQUENCY – MHz
TPC 8. Third Order Harmonic Distortion vs. Frequency for
Various Output Levels
TPC 11. Output Impedance vs. Frequency
140
60
P
= 60dBmV
OUT
130
120
50
40
@ MAX GAIN
PD = 1
110
100
90
30
20
10
80
70
0
60
50
40
–10
–20
PD = 0
–30
–40
30
20
–50
–25
0
25
50
75
100
41.0 41.2 41.4 41.6 41.8 42.0 42.2 42.4 42.6 42.8 43.0
TEMPERATURE – ؇C
FREQUENCY – MHz
TPC 9. Two-Tone Intermodulation Distortion
TPC 12. Supply Current vs. Temperature
–6–
REV. 0
AD8323
APPLICATIONS
The gain transfer function is as follows:
General Application
AV = 27.5 dB – (0.7526 dB × (71 – CODE)) for 0 ≤ CODE ≤ 71
The AD8323 is primarily intended for use as the upstream
power amplifier (PA) in DOCSIS (Data Over Cable Service
Interface Specifications) certified cable modems and CATV set-
top boxes. Upstream data is modulated in QPSK or QAM for-
mat, and done with DSP or a dedicated QPSK/QAM modulator.
The amplifier receives its input signal from the QPSK/QAM
modulator or from a DAC. In either case the signal must be
low-pass filtered before being applied to the amplifier. Because
the distance from the cable modem to the central office will vary
with each subscriber, the AD8323 must be capable of varying its
output power by applying gain or attenuation to ensure that all
signals arriving at the central office are of the same amplitude.
The upstream signal path contains components such as a trans-
former and diplexer that will result in some amount of power loss.
Therefore, the amplifier must be capable of providing enough
power into a 75 Ω load to overcome these losses without sacri-
ficing the integrity of the output signal.
where AV is the gain in dB and CODE is the decimal equivalent
of the 8-bit word.
Valid gain codes are from 0 to 71. Figure 4 shows the gain
characteristics of the AD8323 for all possible values in an 8-bit
word. Note that maximum gain is achieved at Code 71. From
Code 72 through 127 the 5.25 dB of attenuation from the ver-
nier stage is being applied over every eight codes, resulting in
the sawtooth characteristic at the top of the gain range. Because
the eighth bit is a “don’t care” bit, the characteristic for codes 0
through 127 repeats from Codes 128 through 255.
28
21
14
7
Operational Description
The AD8323 is composed of four analog functions in the
power-up or forward mode. The input amplifier (preamp) can
be used single-ended or differentially. If the input is used in
the differential configuration, it is imperative that the input
signals are 180 degrees out of phase and of equal amplitudes.
This will ensure the proper gain accuracy and harmonic
performance. The preamp stage drives a vernier stage that
provides the fine tune gain adjustment. The 0.7526 dB step
resolution is implemented in this stage and provides a total of
approximately 5.25 dB of attenuation. After the vernier stage,
a DAC provides the bulk of the AD8323’s attenuation (8 bits
or 48 dB). The signals in the preamp and vernier gain blocks
are differential to improve the PSRR and linearity. A differen-
tial current is fed from the DAC into the output stage, which
amplifies these currents to the appropriate levels necessary
to drive a 75 Ω load. The output stage utilizes negative feed-
back to implement a differential 75 Ω output impedance. This
eliminates the need for external matching resistors needed in
typical video (or video filter) termination requirements.
0
–7
–14
–21
–28
0
32
64
96
128
160
192
224
256
GAIN CODE – Decimal
Figure 4. Gain vs. Gain Code
Input Bias, Impedance, and Termination
The VIN+ and VIN– inputs have a dc bias level of approximately
CC/2, therefore the input signal should be ac-coupled. The
differential input impedance is approximately 1600 Ω while the
single-ended input impedance is 800 Ω. If the AD8323 is being
operated in a single-ended input configuration with a desired
input impedance of 75 Ω, the VIN+ and VIN– inputs should be
terminated as shown in Figure 5. If an input impedance other
than 75 Ω is desired, the values of R1 and R2 in Figure 5 can be
calculated using the following equations:
V
SPI Programming and Gain Adjustment
Gain programming of the AD8323 is accomplished using a
serial peripheral interface (SPI) and three digital control lines,
DATEN, SDATA, and CLK. To change the gain, eight bits of
data are streamed into the serial shift register through the
SDATA port. The SDATA load sequence begins with a falling
edge on the DATEN pin, thus activating the CLK line. Although
the CLK line is now activated, no change in gain is yet observed
at the output of the amplifier. With the CLK line activated, data
on the SDATA line is clocked into the serial shift register Most
Significant Bit (MSB) first, on the rising edge of each CLK
pulse. Because only a 7-bit shift register is used, the MSB of the
8-bit word is a “don’t care” bit and is shifted out of the register
on the eighth clock pulse. A rising edge on the DATEN line
latches the contents of the shift register into the attenuator core
resulting in a well controlled change in the output signal level.
The serial interface timing for the AD8323 is shown in Figures 2
and 3. The programmable gain range of the AD8323 is –26 dB
to +27.5 dB and scales 0.7526 dB per least significant bit (LSB).
Because the AD8323 was characterized with a TOKO transformer,
the stated gain values already take into account the losses associ-
ated with the transformer.
ZIN = R1800
R2 = ZIN R1
Z
= 75⍀
IN
–
AD8323
+
R1 = 82.5⍀
R2 = 39.2⍀
Figure 5. Single-Ended Input Termination
REV. 0
–7–
AD8323
input and output traces should be kept as short and symmetrical
as possible. In addition, the input and output traces should be
kept far apart in order to minimize coupling (crosstalk) through
the board. Following these guidelines will improve the overall
performance of the AD8323 in all applications.
Output Bias, Impedance, and Termination
The differential output pins VOUT+ and VOUT– are also biased to
a dc level of approximately VCC/2. Therefore, the outputs should
be ac-coupled before being applied to the load. This may be
accomplished by connecting 0.1 µF capacitors in series with the
outputs as shown in the typical applications circuit of Figure 6.
The differential output impedance of the AD8323 is internally
maintained at 75 Ω, regardless of whether the amplifier is in
forward transmit mode or reverse power-down mode, elimi-
nating the need for external back termination resistors. A 1:1
transformer (TOKO #617DB-A0070) is used to couple
the amplifier’s differential output to the coaxial cable while
maintaining a proper impedance match. If the output signal
is being evaluated on standard 50 Ω test equipment, a 75 Ω to
50 Ω pad must be used to provide the test circuit with the
correct impedance match.
Initial Power-Up
When the 5 V supply is first applied to the VCC pins of the
AD8323, the gain setting of the amplifier is indeterminate.
Therefore, as power is first applied to the amplifier, the PD pin
should be held low (Logic 0) thus preventing forward signal
transmission. After power has been applied to the amplifier, the
gain can be set to the desired level by following the procedure in
the SPI Programming and Gain Adjustment section. The PD
pin can then be brought from Logic 0 to 1, enabling forward
signal transmission at the desired gain level.
Asynchronous Power-Down
Power Supply Decoupling, Grounding, and Layout
Considerations
The asynchronous PD pin is used to place the AD8323 into
“Between Burst” mode while maintaining a differential output
impedance of 75 Ω. Applying a Logic 0 to the PD pin activates
the on-chip reverse amplifier, providing a 74% reduction in
consumed power. The supply current is reduced from approxi-
mately 133 mA to approximately 35 mA. In this mode of
operation, between burst noise is minimized and the amplifier
can no longer transmit in the upstream direction. In addition to
the PD pin, the AD8323 also incorporates an asynchronous
SLEEP pin, which may be used to place the amplifier in a high
output impedance state and further reduce the supply current to
approximately 4 mA. Applying a Logic 0 to the SLEEP pin
places the amplifier into SLEEP mode. Transitioning into or
out of SLEEP mode will result in a transient voltage at the output
of the amplifier. Therefore, use only the PD pin for DOCSIS
compliant “Between Burst” operation.
Careful attention to printed circuit board layout details will
prevent problems due to associated board parasitics. Proper RF
design technique is mandatory. The 5 V supply power should be
delivered to each of the VCC pins via a low impedance power bus
to ensure that each pin is at the same potential. The power bus
should be decoupled to ground with a 10 µF tantalum capacitor
located in close proximity to the AD8323. In addition to the
10 µF capacitor, each VCC pin should be individually decoupled to
ground with a 0.1 µF ceramic chip capacitor located as close to
the pin as possible. The pin labeled BYP (Pin 21) should also be
decoupled with a 0.1 µF capacitor. The PCB should have a low-
impedance ground plane covering all unused portions of the
component side of the board, except in the area of the input and
output traces (see Figure 11). It is important that all of the
AD8323’s ground pins are connected to the ground plane to
ensure proper grounding of all internal nodes. The differential
5V
10F
25V
0.1F
AD8323TSSOP
V
IN–
0.1F
GND11
DATEN
SDATA
CLK
DATEN
SDATA
CLK
V
CC6
Z
= 150⍀
IN
V
IN–
165⍀
0.1F
GND1
V
IN+
0.1F
0.1F
0.1F
V
GND10
CC
V
PD
PD
CC5
V
IN+
GND9
BYP
SLEEP
GND2
0.1F
0.1F
0.1F
V
V
V
1
CC
CC4
V
SLEEP
CC2
CC3
GND3
GND4
GND5
OUT–
GND8
GND7
GND6
OUT+
0.1F
0.1F
0.1F
TOKO 617DB-A0070
TO DIPLEXER Z = 75⍀
IN
Figure 6. Typical Applications Circuit
–8–
REV. 0
AD8323
Comparing the computed noise power of –48 dBmV to the
8 dBmV signal yields –56 dBc, which meets the required level of
–53 dBc set forth in DOCSIS Table 4-8. As the AD8323’s gain is
increased from this minimum value, the output signal increases at a
faster rate than the noise, resulting in a signal to noise ratio that
improves with gain. In transmit disable mode, the output noise
spectral density computed over 160 KSYM/SECOND is 1.0 nV/√Hz
or –68 dBmV.
Distortion, Adjacent Channel Power, and DOCSIS
In order to deliver 58 dBmV of high fidelity output power
required by DOCSIS, the PA should be able to deliver about
60 dBmV to 61 dBmV in order to make up for losses associated
with the transformer and diplexer. It should be noted that the
AD8323 was characterized with the TOKO 617DB-A0070
transformer. TPC 7 and TPC 8 show the AD8323 second and
third harmonic distortion performance versus fundamental
frequency for various output power levels. These figures are
useful for determining the inband harmonic levels from 5 MHz to
65 MHz. Harmonics higher in frequency will be sharply attenu-
ated by the low-pass filter function of the diplexer. Another
measure of signal integrity is adjacent channel power or ACP.
DOCSIS section 4.2.9.1.1 states, “Spurious emissions from a
transmitted carrier may occur in an adjacent channel that could
be occupied by a carrier of the same or different symbol rates.”
Figure 7 shows the measured ACP for a 16 QAM, 60 dBmV
signal, taken at the output of the AD8323 evaluation board (see
Figure 13 for evaluation board schematic). The transmit chan-
nel width and adjacent channel width in Figure 7 correspond to
symbol rates of 160 KSYM/SEC. Table I shows the ACP results for
the AD8323 for all conditions in DOCSIS Table 4-7 “Adjacent
Channel Spurious Emissions.”
Evaluation Board Features and Operation
The AD8323 evaluation board (Part # AD8323-EVAL) and
control software can be used to control the AD8323 upstream
cable driver via the parallel port of a PC. A standard printer
cable connected between the parallel port and the evaluation
board is used to feed all the necessary data to the AD8323 by
means of the Windows-based, Microsoft Visual Basic control
software. This package provides a means of evaluating the
amplifier by providing a convenient way to program the gain/
attenuation as well as offering easy control of the amplifiers’
asynchronous PD and SLEEP pins. With this evaluation kit the
AD8323 can be evaluated with either a single-ended or differential
input configuration. The amplifier can also be evaluated with or
without the PULSE diplexer in the output signal path. To remove
the diplexer from the signal path, move the 0 Ω chip resistor at
JP5 so the output signal is directed away from the diplexer
and toward the CABLE port of the evaluation board. Also,
remove the 0 Ω resistor at JP4. A schematic of the evaluation
board is provided in Figure 13.
RBW 500 Hz RF ATT 40dB
VBW 5 kHz
CH PWR
ACP UP
5.44 dBm
–10
–20
–30
–40
–50
–60
–70
–52.99 dB
SWT 12s UNIT dBm
ACP LOW –54.36 dB
Overshoot on PC Printer Ports
The data lines on some PC parallel printer ports have excessive
overshoot that may cause communications problems when pre-
sented to the CLK pin of the AD8323 (TP5 on the evaluation
board). The evaluation board was designed to accommodate a
series resistor and shunt capacitor (R1 and C15) to filter the
CLK signal if required.
C0
C0
CU1
F1
CL1
Transformer and Diplexer
CL1
CU1
–80
A 1:1 transformer is needed to couple the differential outputs of
the AD8323 to the cable while maintaining a proper impedance
match. The specified transformer is available from TOKO (Part
# 617DB-A0070); however, MA/COM part # ETC-1-1T-15
can also be used. The evaluation board is equipped with the
TOKO transformer, but is also designed to accept the MA/
COM transformer. The PULSE diplexer included on the
evaluation board provides a high-order low-pass filter function,
typically used in the upstream path. The ability of the PULSE
diplexer to achieve DOCSIS compliance is neither expressed
nor implied by Analog Devices Inc. Data on the diplexer should
be obtained from PULSE.
CENTER 10 MHz
60 kHz
SPAN 600 kHz
Figure 7. Adjacent Channel Power
Table I. ACP Performance for All DOCSIS Conditions
(All Values in dBc)
TRANSMIT
CHANNEL
SYMBOL RATE
ADJACENT CHANNEL SYMBOL RATE
320 K 640 K 1280 K
160 K
SYM/SEC
2560 K
SYM/SEC
SYM/SEC SYM/SEC SYM/SEC
160 K
–53.0
–53.8 –56.6
–55.0
–53.8
–53.3
–53.0
–53.6
–56.3
SYM/SEC
320 K
–52.7
–53.8
–53.7
–55.4
–53.4
–52.9
–53.4
–54.0
–54.8
–53.6
–53.3
–53.1
–55.4
–54.2
–53.5
–53.3
SYM/SEC
640 K
SYM/SEC
1280 K
2560 K
SYM/SEC
Differential Inputs
SYM/SEC
The AD8323-EVAL evaluation board is designed to accommodate
a Mini-Circuits T1-6T-KK81 1:1 transformer for the purpose of
converting a single-ended (ground-referenced) input signal to
differential inputs. Figure 8 and the following paragraphs identify
two options for providing differential input signals to the AD8323
evaluation board.
Noise and DOCSIS
At minimum gain, the AD8323’s output noise spectral density is
10 nV/√Hz measured at 10 MHz. DOCSIS Table 4-8, “Spurious
Emissions in 5 MHz to 42 MHz,” specifies the output noise for
various symbol rates. The calculated noise power in dBmV for
160 KSYM/SECOND is:
2
10 nV
Hz
20 log
×160 kHz + 60 = –48 dBmV
REV. 0
–9–
AD8323
Single-Ended-to-Differential Input (Figure 8, Option 1)
Install the Mini-Circuits T1-6T-KK81 1:1 transformer in the
T1 location of the evaluation board. Place 0 Ω chip resistors at
locations JP1, JP2, and JP3 such that the signal coming in VIN+
is directed toward the transformer and the differential signal
coming out of the transformer is directed toward TP13 and
TP14. For 75 Ω input impedance, install 39.2 Ω resistors in R5
and R6 located on the back side of the evaluation board. In this
configuration the input signal must be applied to the VIN+ port
of the evaluation board from a single-ended 75 Ω signal source.
For input impedances other than 75 Ω, the correct value for R5
and R6 can be computed using the following equation:
Installing the Visual Basic Control Software
To install the “CABDRIVE_23” evaluation board control soft-
ware, close all Windows applications and then run “SETUP.EXE”
located on Disk 1 of the AD8323 Evaluation Software. Follow
the on-screen instructions and insert Disk 2 when prompted to
do so. Enter the path of the directory into which the software
will be installed and select the button in the upper left corner to
complete the installation.
Running the Software
To invoke the control software, go to START -> PROGRAMS
-> CABDRIVE_23, or select the AD8323.EXE icon from the
directory containing the software.
Controlling the Gain/Attenuation of the AD8323
The slide bar controls the AD8323’s gain/attenuation, which is
displayed in dB and in V/V. The gain scales at 0.7526 dB per
LSB with the valid codes being from decimal 0 to 71. The gain
code (i.e., position of the slide bar) is displayed in decimal, binary,
and hexadecimal (see Figure 9).
R5 = R6 = R , Desired Impedance = 2 × R 800
(
)
(
)
Differential Input (Figure 8, Option 2)
If a differential signal source is available, it may be applied
directly to both the VIN+ and VIN– input ports of the evaluation
board. In this case, 0 Ω chip resistors should be placed at loca-
tions R8, JP1, JP2, and JP3 such that the VIN+ and VIN– signals
are directed toward TP13 and TP14. Referring to Figure 8,
Option 2, a differential input impedance of 150 Ω can be
achieved by using a 165 Ω resistor for R7. For input imped-
ances other than 150 Ω, the correct value for R7 can be computed
using the following equation:
POWER-UP, POWER-DOWN AND SLEEP
The “Power-Up” and “Power-Down” buttons select the mode
of operation of the AD8323 by controlling the logic level on the
asynchronous PD pin. The “Power-Up” button applies a
Logic 1 to the PD pin putting the AD8323 in forward transmit
mode. The “Power-Down” button applies a Logic 0 to the PD
pin selecting reverse mode, where the forward signal transmission
is disabled while a back termination of 75 Ω is maintained.
Checking the “Enable SLEEP Mode” box applies a Logic 0 to
the asynchronous SLEEP pin, putting the AD8323 into SLEEP
mode.
Desired Impedance = R7 1600
(
)
R6
DIFF IN
T1
AD8323
Memory Section
The “MEMORY” section of the software provides a convenient
way to alternate between two gain settings. The “X->M1” but-
ton stores the current value of the gain slide bar into memory
while the “RM1” button recalls the stored value, returning the
gain slide bar to that level. The “X->M2” and “RM2” buttons
work in the same manner.
R5
OPTION 1 DIFFERENTIAL INPUT TERMINATION
VIN+
R7
AD8323
VIN–
OPTION 2 DIFFERENTIAL INPUT TERMINATION
Figure 8. Differential Input Termination Options
–10–
REV. 0
AD8323
EVALUATION BOARD FEATURES AND OPERATION
Figure 9. Screen Display of Windows-Based Control Software
REV. 0
–11–
AD8323
Figure 10. Evaluation Board—Assembly (Component Side)
Figure 11. Evaluation Board Layout (Component Side)
–12–
REV. 0
AD8323
Figure 12. Evaluation Board—Solder Side
REV. 0
–13–
AD8323
G 9
G 8
G 7
G 6
G 5
G 4
G 3
G 2
G 1
O U T = 2 , 4 , 6 , 7 , 8
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
P U L S E B 5 0 0 8
9
B
5
B – A
3
1
A
Figure 13. Evaluation Board Schematic
–14–
REV. 0
AD8323
EVALUATION BOARD BILL OF MATERIALS
AD8323 Evaluation Board Rev. C SINGLE-ENDED INVERTING INPUT – Revised – June 22, 2000
Qty.
Description
Vendor
Ref Desc.
1
12
6
1
1
2
10
1
1
3
4
1
2
1
1
1
1
4
4
2
2
2
3
10 µF 16 V. ‘C’ size tantalum chip capacitor
0.1 µF 50 V. 1206 size ceramic chip capacitor
0 Ω 1/8 W. 1206 size chip resistor
39.2 Ω 1% 1/8 W. 1206 size chip resistor
82.5 Ω 1% 1/8 W. 1206 size chip resistor
Yellow Test Point [INPUTS] (Bisco TP104-01-04)
White Test Point [DATA] (Bisco TP104-01-09)
Red Test Point [VCC] (Bisco TP104-01-02)
Black Test Point [A.GND] (Bisco TP104-01-00)
0 Ω 0805 size chip resistors
75 Ω right-angle BNC Telegartner # J01003A1949
Centronics type 36 pin Right-Angle Connector
5-way Metal Binding Post (E F Johnson # 111-2223-001)
1:1 Transformer TOKO # 617DB - A0070
Diplexer PULSE*
ADS# 4-7-6
C18
C1–8, 10–13
R1–3, 8, 11, 12
R6
R5
TP13, 14
TP1–6, 16–19
TP15
ADS# 4-5-18
ADS# 3-18- 88
ADS# 3-18-113
ADS# 3-18-189
ADS# 12-18-32
ADS# 12-18-42
ADS# 12-18-43
ADS# 12-18-44
ADS# 3-27-22
ADS# 12-6-28
ADS# 12-3-50
ADS# 12-7-7
TOKO
PULSE
ADI# AD8323XRU
D C S
ADS# 30-1-1
ADS# 30-16-3
ADS# 30-1-17
ADS# 30-6-6
ADS# 30-5-2
ADS# 30-7-6
TP20
JP1–3
VIN+, VIN–, HPP, CABLE
P1
VCC, GND
T2 B
U2
U1
AD8323 (TSSOP) UPSTREAM Cable Driver
AD8323 REV. C Evaluation PC board
#4 - 40 × 1/4 inch STAINLESS panhead machine screw
#4 - 40 × 3/4 inch long aluminum round stand-off
# 2 - 56 × 3/8 inch STAINLESS panhead machine screw
# 2 steel flat washer
Evaluation PC Board
(p1 hardware)
(p1 hardware)
(p1 hardware)
(p1 hardware)
# 2 steel internal tooth lockwasher
# 2 STAINLESS STEEL hex. machine nut
DO NOT INSTALL C14–C17, R4, R7, R9, T1, T2A, TP7–TP12, TP21, TP22.
*PULSE Diplexer part #’s B5008 (42 MHz), CX6002 (42 MHz), B5009 (65 MHz).
REV. 0
–15–
AD8323
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead TSSOP
(RU-28)
0.386 (9.80)
0.378 (9.60)
28
15
0.177 (4.50)
0.169 (4.30)
0.256 (6.50)
0.246 (6.25)
14
1
PIN 1
0.006 (0.15)
0.002 (0.05)
0.0433 (1.10)
MAX
8؇
0؇
0.0256 (0.65) 0.0118 (0.30)
0.028 (0.70)
0.020 (0.50)
SEATING
PLANE
0.0079 (0.20)
0.0035 (0.090)
BSC
0.0075 (0.19)
–16–
REV. 0
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