AD8328ARQ-REEL [ADI]
5 V Upstream Cable Line Driver; 5 V上行电缆线路驱动器
| 型号： | AD8328ARQ-REEL |
| 厂家： | 
ADI |
| 描述： | 5 V Upstream Cable Line Driver |
| 文件： | 总16页 (文件大小：529K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
5 V Upstream
a
Cable Line Driver
AD8328*
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Supports DOCSIS and EuroDOCSIS Standards for
Reverse Path Transmission Systems
Gain Programmable in 1 dB Steps over a 59 dB Range
Low Distortion at 60 dBmV Output:
–57.5 dBc SFDR at 21 MHz
BYP
AD8328
V
V
IN+
OUT+
DIFF OR
SINGLE
INPUT
AMP
–54 dBc SFDR at 65 MHz
POWER
AMP
ATTENUATION
VERNIER
CORE
Output Noise Level @ Minimum Gain 1.2 nV/√Hz
Maintains 300 ꢀ Output Impedance TX-Enable and
Transmit-Disable Condition
V
IN–
V
OUT–
Z
DIFF =
OUT
300ꢀ
8
DECODE
Upper Bandwidth: 107 MHz (Full Gain Range)
5 V Supply Operation
Z
Z
IN
(SINGLE) = 800ꢀ
(DIFF) = 1.6kꢀ
IN
8
POWER-DOWN
LOGIC
RAMP
DATA LATCH
Supports SPI Interfaces
8
SHIFT
REGISTER
APPLICATIONS
DOCSIS and EuroDOCSIS Cable Modems
CATV Set-Top Boxes
CATV Telephony Modems
Coaxial and Twisted Pair Line Driver
GND
SDATA CLK
TXEN
DATEN
SLEEP
–50
–52
–54
–56
–58
–60
–62
–64
–66
–68
–70
GENERAL DESCRIPTION
The AD8328 is a low cost amplifier designed for coaxial line
driving. The features and specifications make the AD8328
ideally suited for MCNS-DOCSIS and Euro-DOCSIS applica-
tions. The gain of the AD8328 is digitally controlled. An 8-bit
serial word determines the desired output gain over a 59 dB range,
resulting in gain changes of 1 dB/LSB.
V
= 60dBmV
OUT
@MAX GAIN,
THIRD HARMONIC
The AD8328 accepts a differential or single-ended input signal. The
output is specified for driving a 75 Ω load through a 2:1 transformer.
V
= 60 dBmV
OUT
@MAX GAIN,
SECOND HARMONIC
Distortion performance of –53 dBc is achieved with an output
level up to 60 dBmV at 65 MHz bandwidth over a wide tempera-
ture range.
This device has a sleep mode function that reduces the quiescent
current to 2.6 mA and a full power-down function that reduces
power-down current to 20 µA.
5
15
25
35
45
55
65
FREQUENCY – MHz
Figure 1. Worst Harmonic Distortion vs. Frequency
The AD8328 is packaged in a low cost 20-lead LFCSP package
and a 20-lead QSOP package. The AD8328 operates from a single
5 V supply and has an operational temperature range of –40°C
to +85°C.
*Patent Pending
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2002
(TA = 25ꢁC, VS = 5 V, RL = RIN = 75 ꢀ, VIN (Differential) = 29 dBmV.
The AD8328 is characterized using a 2:1 transformer1 at the device output.)
AD8328–SPECIFICATIONS
Parameter
Conditions
Min
Typ
Max Unit
INPUT CHARACTERISTICS
Specified AC Voltage
Input Resistance
Output = 60 dBmV, Max Gain
Single-Ended Input
Differential Input
29
dBmV
Ω
800
1600
2
Ω
Input Capacitance
pF
GAIN CONTROL INTERFACE
Voltage Gain Range
Max Gain
58
30.5
–28.5 –27.5
59.0
31.5
60
32.5
–26.5 dB
dB
dB
Gain Code = 60 Dec
Gain Code = 1 Dec
Min Gain
Output Step Size
Output Step Size Temperature
Coefficient
0.6
1.0
0.0005
1.4
dB/LSB
dB/°C
TA = –40°C to +85°C
OUTPUT CHARACTERISTICS
Bandwidth (–3 dB)
All Gain Codes (1–60 Decimal Codes)
f = 65 MHz
Max Gain, f = 10 MHz, Output Referred
Min Gain, f = 10 MHz, Input Referred
107
1.2
18.4
3.3
MHz
dB
dBm
dBm
Bandwidth Roll-Off
1 dB Compression Point2
17.9
2.2
Output Noise2
Max Gain
Min Gain
f = 10 MHz
f = 10 MHz
f = 10 MHz
135
1.2
1.1
151
1.3
1.2
nV/√Hz
nV/√Hz
nV/√Hz
Transmit Disable
Noise Figure2
Max Gain
Differential Output Impedance
f = 10 MHz
TX Enable and TX Disable
16.7
17.7
dB
Ω
75 30%3
OVERALL PERFORMANCE
Second-Order Harmonic Distortion4, 5
f = 33 MHz, VOUT = 60 dBmV @ Max Gain
f = 65 MHz, VOUT = 60 dBmV @ Max Gain
f = 21 MHz, VOUT = 60 dBmV @ Max Gain
f = 65 MHz, VOUT = 60 dBmV @ Max Gain
–67
–61
–57.5
–54
–58
–85
–56
–55
–56
–52.5 dBc
–56
–81
dBc
dBc
dBc
Third-Order Harmonic Distortion4, 5
ACPR2, 6
dBc
dB
Isolation (Transmit Disable)2
Max Gain, f = 65 MHz
POWER CONTROL
TX Enable Settling Time
TX Disable Settling Time
Output Switching Transients2
Max Gain, VIN = 0
Max Gain, VIN = 0
Equivalent Output = 31 dBmV
Equivalent Output = 61 dBmV
2.5
3.8
2.5
16
µs
µs
6
54
mV p-p
mV p-p
Output Settling
Due to Gain Change
Due to Input Step Change
Min to Max Gain
Max Gain, VIN = 29 dBmV
60
30
ns
ns
POWER SUPPLY
Operating Range
Quiescent Current
4.75
98
18
1
5
5.25
140
34
3.5
100
V
Max Gain
Min Gain
Transmit Disable (TXEN = 0)
SLEEP Mode (Power-Down)
120
26
2.6
20
mA
mA
mA
µA
1
OPERATING TEMPERATURE
RANGE
–40
+85
°C
NOTES
1TOKO 458PT-1087 used for above specifications. Typical insertion loss of 0.3 dB @ 10 MHz.
2Guaranteed by design and characterization to 4 sigma for TA = 25°C.
3Measured through a 2:1 transformer.
4Specification is worst case over all gain codes.
5Guaranteed by design and characterization to 3 sigma for TA = 25°C.
6VIN = 29 dBmV, QPSK modulation, 160 KSPS symbol rate.
–2–
REV. 0
AD8328
LOGIC INPUTS (TTL/CMOS Compatible Logic) (DATEN, CLK, SDATA, TXEN, SLEEP, VCC = 5 V. Full Temperature Range.)
Parameter
Min
Typ
Max
Unit
Logic 1 Voltage
Logic 0 Voltage
2.1
0
5.0
0.8
V
V
Logic 1 Current (VINH = 5 V) CLK, SDATA, DATEN
Logic 0 Current (VINL = 0 V) CLK, SDATA, DATEN
Logic 1 Current (VINH = 5 V) TXEN
Logic 0 Current (VINL = 0 V) TXEN
Logic 1 Current (VINH = 5 V) SLEEP
Logic 0 Current (VINL = 0 V) SLEEP
0
–600
50
–250
50
20
nA
nA
µA
µA
µA
µA
–100
190
–30
190
–30
–250
Specifications subject to change without notice.
(Full Temperature Range, V = 5 V, t = t = 4 ns, fCLK = 8 MHz, unless otherwise noted.)
TIMING REQUIREMENTS
CC
R
F
Parameter
Min
Typ
Max
Unit
Clock Pulsewidth (tWH
Clock Period (tC)
Setup Time SDATA vs. Clock (tDS
Setup Time DATEN vs. Clock (tES
Hold Time SDATA vs. Clock (tDH
Hold Time DATEN vs. Clock (tEH
Input Rise and Fall Times, SDATA, DATEN, Clock (tR, tF)
)
16.0
32.0
5.0
15.0
5.0
ns
ns
ns
ns
ns
ns
ns
)
)
)
)
3.0
10
Specifications subject to change without notice.
tDS
VALID DATA-WORD G1
VALID DATA-WORD G2
SDATA
CLK
MSB. . . .LSB
tC
tWH
tEH
tES
8 CLOCK CYCLES
DATEN
GAIN TRANSFER (G1)
tOFF
GAIN TRANSFER (G2)
TXEN
tGS
tON
ANALOG
OUTPUT
SIGNAL AMPLITUDE (p-p)
Figure 2. Serial Interface Timing
VALID DATA BIT
SDATA
MSB
MSB-1
MSB-2
tDH
tDS
CLK
Figure 3. SDATA Timing
–3–
REV. 0
AD8328
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
Input Voltage
PIN CONFIGURATIONS
20-Lead
20-Lead
QSOP
LFCSP
VIN+, VIN– . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V p-p
DATEN, SDATA, CLK,
SLEEP, TXEN . . . . . . . . . . . . . . . . . . . . –0.8 V to +5.5 V
1
2
GND
20
19
18
17
16
15
14
13
12
GND
V
V
CC
CC
20 19 18 17 16
3
Internal Power Dissipation
GND
GND
TXEN
RAMP
V
1
2
3
15
14
13
RAMP
V
GND
GND
4
QSOP, LFCSP . . . . . . . . . . . . . . . . . . . . . . . . . . . 700 mW
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature, Soldering 60 seconds . . . . . . . . . . 300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
AD8328
OUT
+
5
V
OUT
+
IN+
AD8328
TOP VIEW
V
V
(Not to Scale)
TOP VIEW
6
OUT–
V
IN+
V
IN–
OUT
–
(Not to Scale)
V
4
5
12 BYP
11
7
GND
DATEN
SDATA
CLK
IN–
BYP
NC
NC
GND
8
9
SLEEP
6
7
8
9
10
10
11 GND
NC = NO CONNECT
PIN FUNCTION DESCRIPTIONS
Pin No. Pin No.
20-Lead 20-Lead
LFCSP QSOP
Mnemonic
Description
Common External Ground Reference
1 ,2, 5,
1, 3, 4, 7,
GND
9, 18, 19 11, 20
17, 20
2, 19
VCC
Common Positive External Supply Voltage. A 0.1 µF capacitor must decouple each pin.
3
4
6
5
6
8
VIN+
Noninverting Input. DC-biased to approximately VCC/2. Should be ac-coupled with a 0.1 µF capacitor.
Inverting Input. DC-biased to approximately VCC/2. Should be ac-coupled with a 0.1 µF capacitor.
Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A Logic 0-to-1
transition transfers the latched data to the attenuator core (updates the gain) and simultaneously
inhibits serial data transfer into the register. A 1-to-0 transition inhibits the data latch (holds the previous
gain state) and simultaneously enables the register for serial data load.
VIN–
DATEN
7
8
9
SDATA
CLK
Serial Data Input. This digital input allows for an 8-bit serial (gain) word to be loaded into the internal
register with the MSB (most significant bit) first.
10
Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit master-slave
register. A Logic 0-to-1 transition latches the data bit and a 1-to-0 transfers the data bit to the slave.
This requires the input serial data-word to be valid at or before this clock transition.
10
12
SLEEP
Low Power Sleep Mode. In the Sleep mode, the AD8328’s supply current is reduced to 20 µA. A Logic 0
powers down the part (High ZOUT State), and a Logic 1 powers up the part.
12
13
14
15
16
14
15
16
17
18
BYP
Internal Bypass. This pin must be externally ac-coupled (0.1 µF capacitor).
Negative Output Signal
VOUT–
VOUT+
RAMP
TXEN
Positive Output Signal
External RAMP Capacitor (optional)
Logic 0 disables forward transmission. Logic 1 enables forward transmission.
ORDERING GUIDE
Model
Temperature Range
Package Description
θJA
Package Option
AD8328ARQ
–40°C to +85°C
–40°C to +85°C
20-Lead QSOP
20-Lead QSOP
Evaluation Board
20-Lead LFCSP
20-Lead LFCSP
Evaluation Board
83.2°C/W1
RQ-20
RQ-20
AD8328ARQ-REEL
AD8328ARQ-EVAL
AD8328ACP
AD8328ACP-REEL
AD8328ACP-EVAL
83.2°C/W1
–40°C to +85°C
–40°C to +85°C
30.4°C/W2
30.4°C/W2
CP-20
CP-20
1Thermal Resistance measured on SEMI standard 4-layer board.
2Thermal Resistance measured on SEMI standard 4-layer board, paddle soldered to board.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8328 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
–4–
REV. 0
Typical Performance Characteristics–AD8328
ꢂ55
ꢂ60
ꢂ65
ꢂ70
ꢂ75
ꢂ50
V
= 60dBmV
OUT
@MAX GAIN
V
= 61dBmV
OUT
@MAX GAIN
ꢂ55
ꢂ60
ꢂ65
ꢂ70
V
= 60dbmV
OUT
@MAX GAIN
V
= 61dbmV
OUT
@MAX GAIN
V
= 59dBmV
OUT
@MAX GAIN
V
= 59dbmV
OUT
@MAX GAIN
5
35
45
55
65
5
35
45
55
65
25
25
15
15
FREQUENCY – MHz
FREQUENCY – MHz
TPC 1. Second-Order Harmonic Distortion
vs. Frequency for Various Output Powers
TPC 4. Third-Order Harmonic Distortion vs.
Frequency for Various Output Powers
–50
–55
–60
–65
–70
–75
–50
–55
–60
V
= 60dBmV
V
= 60dBmV
OUT
OUT
@ MAX GAIN
@ MAX GAIN
T
= +25 C
A
T
= +85 C
A
T
= –40 C
A
T
= +25 C
A
T
= –40 C
A
T
= +85 C
A
–65
55
5
15
25
35
45
65
5
15
25
35
45
55
65
FREQUENCY – MHz
FREQUENCY – MHz
TPC 2. Second-Order Harmonic Distortion
vs. Frequency vs. Temperature
TPC 5. Third-Order Harmonic Distortion vs.
Frequency vs. Temperature
10
0
60
50
CH PWR
ACP
60dBmV
–58.2dB
V
= 57dBmV/TONE
OUT
@ MAX GAIN
–10
–20
–30
–40
–50
–60
–70
–80
–90
40
30
20
10
0
–10
–20
–30
–40
C0
C0
c11
c11
cu1
cu1
75kHz/DIV
SPAN 750kHz
41.6 41.7 41.8 41.9
42
42.1 42.2 42.3 42.4 42.5
FREQUENCY – MHz
TPC 3. Adjacent Channel Power
TPC 6. Two-Tone Intermodulation Distortion
REV. 0
–5–
AD8328
40.0
0
ꢂ10
ꢂ20
ꢂ30
ꢂ40
ꢂ50
ꢂ60
ꢂ70
ꢂ80
TXEN = 0
= 29dBmV
V
IN
30.0
DEC60
20.0
10.0
DEC54
DEC48
DEC42
DEC36
0
DEC30
DEC24
DEC18
DEC12
–10.0
–20.0
–30.0
–40.0
MAX GAIN
10
ꢂ90
DEC 1 TO DEC 6
MIN GAIN
ꢂ100
0.1
1
10
100
1000
1
100
FREQUENCY – MHz
1000
FREQUENCY – MHz
TPC 10. Isolation in Transmit Disable
Mode vs. Frequency
TPC 7. AC Response
1.4
1.2
1.0
0.8
0.6
1.6
1.2
f = 10MHz
0.8
0.4
f
= 10MHz
= 5MHz
0
f
ꢂ0.4
ꢂ0.8
ꢂ1.2
ꢂ1.6
f
= 42MHz
f
= 65MHz
0
6
12
18
24
30
36
42
48
54
60
0
6
12
18
24
30
36
42
48
54
60
GAIN CONTROL – Decimal Code
GAIN CONTROL – Decimal Code
TPC 8. Output Step Size vs. Gain Control
TPC 11. Gain Error vs. Gain Control
140
120
100
130
120
110
100
f
= 10MHz
TXEN = 1
90
80
70
80
60
40
60
50
40
20
0
30
20
0
10
20
30
40
50
60
0
6
12
18
24
30
36
42
48
54
60
GAIN CONTROL – Decimal Code
GAIN CONTROL – Decimal Code
TPC 9. Output Referred Voltage Noise vs. Gain Control
TPC 12. Supply Current vs. Gain Control
–6–
REV. 0
AD8328
5V
signals in the preamp and DAC gain blocks are differential to
improve the PSRR and linearity. A differential current is fed from
the DAC into the output stage. The output stage maintains 300 Ω
differential output impedance, which maintains proper match to 75 Ω
when used with a 2:1 balun transformer.
SPI Programming and Gain Adjustment
V
CC
V
The AD8328 is controlled through a serial peripheral interface
(SPI) of three digital data lines: CLK, DATEN, and SDATA.
Changing the gain requires eight bits of data to be streamed into
the SDATA port. The sequence of loading the SDATA register
begins on the falling edge of the DATEN pin, which activates the
CLK line. With the CLK line activated, data on the SDATA line
is clocked into the serial shift register on the rising edge of the
CLK pulses, most significant bit (MSB) first. The 8-bit data-word
is latched into the attenuator core on the rising edge of the
DATEN line. This provides control over the changes in the
output signal level. The serial interface timing for the AD8328
is shown in Figures 2 and 3. The programmable gain range of
the AD8328 is –28 dB to +31 dB with steps of 1 dB per least
significant bit (LSB). This provides a total gain range of 59 dB.
The AD8328 was characterized with a differential signal on the
input and a TOKO 458PT-1087 2:1 transformer on the output.
The AD8328 incorporates supply current scaling with gain code,
as seen in TPC 12. This allows reduced power consumption when
operating in lower gain codes.
IN+
V
OUT+
R
AD8328
L
V
OUT–
V
IN–
1
2
1
2
V
V
IN
GND
BYP
IN
Figure 4. Characterization Circuit
APPLICATIONS
General Applications
The AD8328 is primarily intended for use as the power amplifier
(PA) in DOCSIS (Data Over Cable Service Interface Specification)
certified cable modems and CATV set-top boxes. The upstream
signal is either a QPSK or QAM signal generated by a DSP, a
dedicated QPSK/QAM modulator, or a DAC. In all cases, the
signal must be low-pass filtered before being applied to the PA in
order to filter out-of-band noise and higher order harmonics from
the amplified signal.
Input Bias, Impedance, and Termination
Due to the varying distances between the cable modem and the
head-end, the upstream PA must be capable of varying the output
power by applying gain or attenuation. The ability to vary the
output power of the AD8328 ensures that the signal from the cable
modem will have the proper level once it arrives at the head-end.
The upstream signal path commonly includes a diplexer and cable
splitters. The AD8328 has been designed to overcome losses asso-
ciated with these passive components in the upstream cable path.
The VIN+ and VIN– inputs have a dc bias level of VCC/2; therefore
the input signal should be ac-coupled as seen in the typical
application circuit (see Figure 5). The differential input impedance
of the AD8328 is approximately 1.6 kΩ, while the single-ended
input is 800 Ω. The high input impedance of the AD8328 allows
flexibility in termination and properly matching filter networks.
The AD8328 will exhibit optimum performance when driven
with a pure differential signal.
Circuit Description
Output Bias, Impedance, and Termination
The AD8328 is composed of three analog functions in the power-up
or forward mode. The input amplifier (preamp) can be used
single-ended or differentially. If the input is used in the differential
configuration, it is imperative that the input signals be 180 degrees out
of phase and of equal amplitude. A vernier is used in the input
stage for controlling the fine 1 dB gain steps. This stage then drives
a DAC, which provides the bulk of the AD8328’s attenuation. The
The output stage of the AD8328 requires a bias of +5 V. The
+5 V power supply should be connected to the center tap of the
output transformer. Also, the VCC that is being applied to the
center tap of the transformer should be decoupled as seen in the
typical applications circuit (Figure 5).
V
CC
10ꢃF
AD8328
1
2
20
QSOP
GND
GND
19
V
V
0.1ꢃF
CC
CC
3
0.1ꢃF
0.1ꢃF
18
17
16
15
14
13
12
11
TO DIPLEXER
= 75ꢀ
TXEN
GND
GND
Z
4
V
IN
IN+
RAMP
Z
= 150ꢀ
5
IN
V
V
OUT+
IN+
165ꢀ
TOKO 458PT-1087
6
V
V
OUT–
IN–
7
BYP
NC
GND
8
V
IN–
0.1ꢃF
DATEN
SDATA
CLK
9
0.1ꢃF
SLEEP
GND
10
1kꢀ
DATEN
SDATA
CLK
1kꢀ
1kꢀ
1kꢀ
1kꢀ
TXEN
SLEEP
Figure 5. Typical Application Circuit
–7–
REV. 0
AD8328
Table I. Adjacent Channel Power
Adjacent Channel Symbol Rate (kSym/s)
Channel Symbol Rate (kSym/s)
160
320
640
1280
2560
5120
160
320
640
1280
2560
5120
–58
–58
–60
–62
–64
–66
–60
–59
–58
–60
–62
–65
–63
–60
–59
–59
–60
–62
–66
–64
–61
–60
–59
–61
–66
–66
–64
–61
–60
–59
–64
–65
–65
–63
–61
–60
The output impedance of the AD8328 is 300 Ω, regardless of
and Gain Adjustment section. The TXEN pin can then be brought
from Logic 0 to Logic 1, enabling forward signal transmission at
the desired gain level.
whether the amplifier is in transmit enable or transmit disable
mode. This, when combined with a 2:1 voltage ratio (4:1 imped-
ance ratio) transformer, eliminates the need for external back
termination resistors. If the output signal is being evaluated
using standard 50 Ω test equipment, a minimum loss 75 Ω–50 Ω
pad must be used to provide the test circuit with the proper
impedance match. The AD8328 evaluation board provides a
convenient means to implement a matching attenuator. Soldering
a 43.3 Ω resistor in the R15 placeholder and an 86.6 Ω resistor in
the R16 placeholder will allow testing on a 50 Ω system. When
using a matching attenuator, it should be noted that there will
be a 5.7 dB of power loss (7.5 dB voltage) through the network.
RAMP Pin and BYP Pin Features
The RAMP pin (Pin 15) is used to control the length of the burst
on and off transients. By default, leaving the RAMP pin unconnected
will result in a transient that is fully compliant with DOCSIS 2.0
Section 6.2.21.2, Spurious Emissions During Burst On/Off Transients.
DOCSIS requires that all between burst transients must be dissi-
pated no faster than 2 µs. Adding capacitance to the RAMP pin
will add more time to the transient.
The BYP pin is used to decouple the output stage at midsupply.
Typically, for normal DOCSIS operation, the BYP pin should
be decoupled to ground with a 0.1 µF capacitor. However, in
applications that may require transient on/off times faster than
2 µs, smaller capacitors may be used, but it should be noted that
the BYP pin should always be decoupled to ground.
Power Supply
The 5 V supply should be delivered to each of the VCC pins via a
low impedance power bus to ensure that each pin is at the same
potential. The power bus should be decoupled to ground using
a 10 F tantalum capacitor located close to the AD8328. In
addition to the 10 F capacitor, each VCC pin should be indi-
vidually decoupled to ground with ceramic chip capacitors
located close to the pins. The bypass pin, labeled BYP, should
also be decoupled. The PCB should have a low impedance
ground plane covering all unused portions of the board, except
in areas of the board where input and output traces are in close
proximity to the AD8328 and the output transformer. All AD8328
ground pins must be connected to the ground plane to ensure
proper grounding of all internal nodes.
Transmit Enable (TXEN) and SLEEP
The asynchronous TXEN pin is used to place the AD8328 into
between-burst mode. In this reduced current state, the output
impedance of 75 Ω is maintained. Applying Logic 0 to the TXEN
pin deactivates the on-chip amplifier, providing a 97.8% reduction
in consumed power. For 5 V operation, the supply current is
typically reduced from 120 mA to 2.6 mA. In this mode of opera-
tion, between-burst noise is minimized and high input to
output isolation is achieved. In addition to the TXEN pin, the
AD8328 also incorporates an asynchronous SLEEP pin, which
may be used to further reduce the supply current to approximately
20 µA. Applying Logic 0 to the SLEEP pin places the amplifier into
SLEEP mode. Transitioning into or out of SLEEP mode may
result in a transient voltage at the output of the amplifier.
Signal Integrity Layout Considerations
Careful attention to printed circuit board layout details will
prevent problems due to board parasitics. Proper RF design
techniques are mandatory. The differential input and output
traces should be kept as short as possible. Keeping the traces
short will minimize parasitic capacitance and inductance. This
is most critical between the outputs of the AD8328 and the 2:1
output transformer. It is also critical that all differential signal
paths be symmetrical in length and width. In addition, the input
and output traces should be adequately spaced to minimize
coupling (crosstalk) through the board. Following these guide-
lines will optimize the overall performance of the AD8328 in all
applications.
Distortion, Adjacent Channel Power, and DOCSIS
To deliver the DOCSIS required 58 dBmV of QPSK signal and
55 dBmV of 16 QAM signal, the PA is required to deliver up to
60 dBmV. This added power is required to compensate for losses
associated with the diplex filter or other passive components that
may be included in the upstream path of cable modems or set-top
boxes. It should be noted that the AD8328 was characterized with
a differential input signal. TPCs 1 and 4 show the AD8328 second
and third harmonic distortion performance versus the fundamental
frequency for various output power levels. These figures are
useful for determining the in-band harmonic levels from 5 MHz
to 65 MHz. Harmonics higher in frequency (above 42 MHz for
DOCSIS and above 65 MHz for EuroDOCSIS) will be sharply
attenuated by the low-pass filter function of the diplexer.
Initial Power-Up
When the supply voltage is first applied to the AD8328, the gain
of the amplifier is initially set to gain code 1. As power is first
applied to the amplifier, the TXEN pin should be held low
(Logic 0) to prevent forward signal transmission. After power has
been applied to the amplifier, the gain can be set to the desired
level by following the procedure provided in the SPI Programming
Another measure of signal integrity is adjacent channel power,
commonly referred to as ACP. DOCSIS 2.0, section 6.2.21.1.1
–8–
REV. 0
AD8328
states, “Spurious emissions from a transmitted carrier may occur
in an adjacent channel that could be occupied by a carrier of the
same or different symbol rates.” TPC 3 shows the measured
ACP for a 60 dBmV QPSK signal taken at the output of the
AD8328 evaluation board. The transmit channel width and adja-
cent channel width in TPC 3 correspond to the symbol rates of
160 kSym/s. Table I shows the ACP results for the AD8328
driving a QPSK, 60 dBmV signal for all conditions in DOCSIS
Table 6-9, Adjacent Channel Spurious Emissions.
Differential Signal from Single-Ended Source
The default configuration of the evaluation board implements a
differential signal drive from a single-ended signal source. This
configuration uses a 1:1 balun transformer to approximate a
differential signal. Because of the nonideal nature of real trans-
formers, the differential signal is not purely equal and opposite
in amplitude. Although this circuit slightly sacrifices even order
harmonic distortion due to asymmetry, it does provide a con-
venient way to evaluate the AD8328 with a single-ended source.
Noise and DOCSIS
The AD8328 evaluation board is populated with a TOKO
617DB-A0070 1:1 for this purpose (T1). Table II provides
typical R4 values for common input configurations. Other input
impedances may be calculated using the equation in Figure 7.
Refer to Figure 10 for an evaluation board schematic. To utilize
the transformer for converting a single-ended source into a
At minimum gain, the AD8328 output noise spectral density is
1.2 nV/√Hz measured at 10 MHz. DOCSIS Table 6-10, Spurious
Emissions in 5 MHz to 42 MHz, specifies the output noise for
various symbol rates. The calculated noise power in dBmV for
160 kSym/s is:
differential signal, the input signal must be applied to VIN+
.
ZIN ×1.6k
R4 =
2
1.2 nV
20 × log
× 160 kHz + 60 = – 66.4 dBmV
1.6k – ZIN
Hz
V
ꢄ
IN
Z
IN
Comparing the computed noise power of –66.4 dBmV to the
+8 dBmV signal yields –74.4 dBc, which meets the required level
set forth in DOCSIS Table 6-10. As the AD8328 gain is increased
above this minimum value, the output signal increases at a
faster rate than the noise, resulting in a signal-to-noise ratio that
improves with gain. In transmit disable mode, the output noise
spectral density is 1.1 nV/√Hz, which results in –67 dBmV when
computed over 160 kSym/s. The noise power was measured
directly at the output of the AD8328AR-EVAL board.
AD8328
R4
Figure 7. Single to Differential Circuit
Single-Ended Source
Although the AD8328 was designed to have optimal DOCSIS
performance when used with a differential input signal, the
AD8328 may also be used as a single-ended receiver, or an IF
digitally controlled amplifier. However, as with the single-ended
to differential configuration noted above, even order harmonic
distortion will be slightly degraded.
Evaluation Board Features and Operation
The AD8328 evaluation board and control software can be used
to control the AD8328 upstream cable driver via the parallel port
of a PC. A standard printer cable connected to the parallel port
of the PC is used to feed all the necessary data to the AD8328
When operating the AD8328 in a single-ended input mode,
IN+ and VIN– should be terminated as illustrated in Figure 8.
V
On the AD8328 evaluation boards, this termination method
requires the removal of R2 and R3 to be shorted with R4 open,
as well as the addition of 82.5 Ω at R1 and 39.2 Ω at R17 for 75
Ω termination. Table II shows the correct values for R11 and
R12 for some common input configurations. Other input
impedance configurations may be accommodated using the
equations in Figure 8.
®
using the Windows -based control software. This package pro-
vides a means of controlling the gain and the power mode of the
AD8328. With this evaluation kit, the AD8328 can be evaluated
in either a single-ended or differential input configuration. A
schematic of the evaluation board is provided in Figure 11.
Differential Signal Source
Typical applications for the AD8328 use a differential input signal
from a modulator or a DAC. See Table II for common values of
R4, or calculate other input configurations using the equation in
Figure 6. This circuit configuration will give optimal distortion
results due to the symmetric input signals. It should be noted that
this is the configuration that was used to characterize the AD8328.
ZIN × 800
800 – ZIN
ZIN × R1
R1+ ZIN
R1 =
R17 =
ꢂ
V
+
IN
ZIN ×1.6k
R4 =
AD8328
ꢄ
R1
Z
IN
1.6k – ZIN
R17
V
+
IN
ꢄ
Figure 8. Single-Ended Circuit
Z
IN
R4
AD8328
ꢂ
V
–
IN
Figure 6. Differential Circuit
REV. 0
–9–
AD8328
Table II. Common Matching Resistors
Controlling Gain/Attenuation of the AD8328
The slide bar controls the gain/attenuation of the AD8328, which
is displayed in dB and in V/V. The gain scales 1 dB per LSB. The
gain code from the position of the slide bar is displayed in decimal,
binary, and hexadecimal (Figure 10).
Differential Input Termination
ZIN (Ω)
R2/R3
R4 (Ω)
R1/R17
50
75
100
150
Open
Open
Open
Open
51.1
78.7
107.0
165.0
Open/Open
Open/Open
Open/Open
Open/Open
Single-Ended Input Termination
ZIN (Ω)
R2/R3
R4 (Ω)
R1/R17
50
75
0 Ω/0 Ω
0 Ω/0 Ω
Open
Open
53.6 Ω/25.5 Ω
82.5 Ω/39.2 Ω
Overshoot on PC Printer Ports
The data lines on some PC parallel printer ports have excessive
overshoot that may cause communications problems when pre-
sented to the CLK pin of the AD8328. The evaluation board was
designed to accommodate a series resistor and shunt capacitor
(R2 and C5 in Figure 11) to filter the CLK signal if required.
-
Installing Visual Basic Control Software
Install the CabDrive_28 software by running the setup.exe file on
disk one of the AD8328 evaluation software. Follow the on-screen
directions and insert disk two when prompted. Choose installation
directory and then select the icon in the upper left to complete
the installation.
Running AD8328 Software
Figure 10. Control Software Interface
To load the control software, go to START, PROGRAMS,
CABDRIVE_28 or select the AD8328.exe file from the installed
directory. Once loaded, select the proper parallel port to com-
municate with the AD8328 (Figure 9).
Transmit Enable and Sleep Mode
The Transmit Enable and Transmit Disable buttons select the
mode of operation of the AD8328 by asserting logic levels on the
asynchronous TXEN pin. The Transmit Disable button applies
Logic 0 to the TXEN pin, disabling forward transmission. The
Transmit Enable button applies Logic 1 to the TXEN pin, enabling
the AD8328 for forward transmission. Checking the Enable
SLEEP Mode checkbox applies Logic 0 to the asynchronous
SLEEP pin, setting the AD8328 for SLEEP mode.
Memory Functions
The Memory section of the software provides a way to alternate
between two gain settings. The X->M1 button stores the current
value of the gain slide bar into memory, while the RM1 button
recalls the stored value, returning the gain slide bar to the stored
level. The same applies to the X->M2 and RM2 buttons.
Figure 9. Parallel Port Selection
–10–
REV. 0
AD8328
V
ꢄ_A
ꢂ_A
C1A 0.1ꢃF
R2
T1
IN
TP9
R1
R4
78.7ꢀ
TOKO
617DB-A0070
V
CC
ꢄ
C8
10ꢃF
V
C2A 0.1ꢃF
C9 0.1ꢃF
IN
1
2
20
19
18
17
16
15
14
13
12
11
GND
GND
R3
R17
V
V
CC
CC
3
C10 0.1ꢃF
GND
GND
TXEN
4
TP1
RAMP
R5
1kꢀ
R6
0ꢀ
C11
5
V
+
–
V
+
–
IN
OUT
P1 2
R15
0ꢀ
TOKO
458PT-1087
6
CABLE_OA
V
V
IN
OUT
C3
C4
C5
7
1
2
6
GND
BYP
NC
V
1
CC
R16
8
C12 0.1ꢃF
DATEN
SDATA
CLK
TP2
TP3
9
4
3
R7
R8
SLEEP
1kꢀ
0ꢀ
10
GND
P1 3
AD8328
QSOP
C13
0.1ꢃF
P1 19
P1 20
P1 21
P1 22
P1 23
P1 24
P1 25
P1 26
P1 27
P1 28
P1 29
P1 30
P1 33
R9
1kꢀ
R10
0ꢀ
P1 5
TP10
TP11
TP12
TP4
R11
1kꢀ
R12
0ꢀ
P1 6
C6
C7
TP_AGND1 TP_V
1
CC
V
1
AGND1
CC
TP5
R13
1kꢀ
R14
0ꢀ
P1 7
P1 16
Figure 11. AD8328 Evaluation Board Schematic
REV. 0
–11–
AD8328
Figure 12. Primary Side
Figure 15. Internal Ground Plane
Figure 13. Component Side Silkscreen
Figure 16. Secondary Side
Figure 14. Internal Power Plane
Figure 17. Secondary Side Silkscreen
–12–
REV. 0
AD8328
OUTLINE DIMENSIONS
20-Lead Frame Chip Scale Package [LFCSP]
4 mm ꢅ 4 mm Body
(CP-20)
Dimensions shown in millimeters
0.60
MAX
4.0
BSC SQ
0.60
MAX
16
15
20
1
5
PIN 1
INDICATOR
2.25
2.10 SQ
1.95
3.75
BSC SQ
TOP
VIEW
BOTTOM
VIEW
11
10
0.75
0.55
0.35
6
0.70 MAX
0.65 NOM
0.30
0.23
0.18
12ꢁ MAX
1.00
0.90
0.80
0.05
0.02
0.00
SEATING
PLANE
COPLANARITY
0.08
0.50
BSC
0.25
REF
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1
CONTROLLING DIMENSIONS ARE IN MILLIMETERS
20-Lead SOIC, 0.025 Lead Pitch [QSOP]
(RQ-20)
Dimensions shown in millimeters and (inches)
8.74 (0.3341)
8.56 (0.3370)
24
1
13
3.99 (0.1571)
3.81 (0.1500)
6.20 (0.2441)
5.79 (0.2280)
12
PIN 1
0.30 (0.0118)
0.20 (0.0079)
1.75 (0.0689)
1.35 (0.0531)
1.50 (0.0591)
MAX
8ꢁ
0ꢁ
0.25 (0.0098)
0.10 (0.0039)
0.64 (0.0252)
BSC
SEATING
PLANE
1.27 (0.0500)
0.41 (0.0161)
0.20 (0.0079)
0.18 (0.0071)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
REV. 0
–13–
–14–
–15–
–16–
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