AD8338 [ADI]
Low Power, 18 MHz Variable Gain Amplifier; 低功耗， 18 MHz可变增益放大器
| 型号： | AD8338 |
| 厂家： | 
ADI |
| 描述： | Low Power, 18 MHz Variable Gain Amplifier |
| 文件： | 总16页 (文件大小：406K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Power, 18 MHz Variable Gain Amplifier
AD8338
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
VBAT OFSN VREF
Voltage controlled gain range of 0 dB to 80 dB
3 mA supply current at gain of 40 dB
Low frequency (LF) to 18 MHz operation
Supply range: 3.0 V to 5.0 V
Adjustable gain range
Low noise: 4.5 nV/√Hz
Fully differential signal path
Offset correction (offset null) feature
Adjustable bandwidth
Internal 1.5 V reference
16-lead LFCSP
OFFSET NULL
FBKP
AD8338
VGA CORE
+
INPR
+
OUTP
OUTM
OUTPUT
STAGE
0dB
–
–
INMR
INPD
INMD
0dB TO 80dB
VREF
FBKM
AUTOMATIC
GAIN
CONTROL
GAIN INTERFACE
Automatic gain control feature
Wide gain range for high dynamic range signals
COMM
MODE GAIN
DETO
VAGC
APPLICATIONS
Figure 1.
Front end for inductive telemetry systems
Ultrasonic signal receivers
RF baseband signal conditioning
100
80
V
= 1.1V
GAIN
V
V
V
V
V
V
V
V
= 1.0V
= 0.9V
= 0.8V
= 0.7V
= 0.6V
= 0.5V
= 0.4V
= 0.3V
GAIN
GAIN
GAIN
GAIN
GAIN
GAIN
GAIN
GAIN
60
GENERAL DESCRIPTION
40
The AD8338 is a variable gain amplifier (VGA) for applications
that require a fully differential signal path, low power, low noise,
and a well-defined gain over frequencies from LF to 18 MHz. The
device can also operate using single-ended sources if required.
20
V
V
= 0.2V
= 0.1V
GAIN
GAIN
0
The basic gain function is linear-in-dB with a nominal gain range
of 0 dB to 80 dB; the nominal gain range corresponds to a control
voltage on the GAIN pin of 0.1 V to 1.1 V. The gain range can be
adjusted up or down via direct access to the internal summing
nodes at the INPD and INMD pins. For example, if a 47 Ω resistor
is applied to the INPD and INMD pins, a gain range of 20 dB to
100 dB is set with an input referred noise level of 1.5 nV√Hz.
–20
–40
10k
100k
1M
FREQUENCY (Hz)
10M
100M
Figure 2. Gain vs. Frequency
The AD8338 offers additional versatility by allowing user access
to the internal summing nodes. With a few discrete components,
users can customize the gain, bandwidth, input impedance, and
noise profile of the part to fit their application.
The AD8338 includes additional circuits to enable offset correction
and automatic gain control (AGC). DC offset voltages are removed
by the offset correction circuit, which behaves like a high-pass filter.
The high-pass filter corner frequency is set using an external
capacitor. The AGC function varies the gain of the AD8338 to
maintain a constant rms output voltage. A user supplied voltage
controls the target output rms voltage. A user supplied capacitor
to ground at the DETO pin controls the response time of the
AGC circuit.
The AD8338 uses a single supply voltage of 3.0 V to 5.0 V and is
very power efficient, consuming as little as 3 mA quiescent current.
The AD8338 is available in a 3 mm × 3 mm, RoHS compliant,
16-lead LFCSP. It is specified over the industrial temperature range
of −40°C to +85°C.
Rev. 0
Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Tel: 781.329.4700
Technical Support
©2013 Analog Devices, Inc. All rights reserved.
www.analog.com
AD8338
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 12
Getting Started with the AD8338............................................. 12
Offset Correction Circuit.......................................................... 12
Explanation of the Gain Function............................................ 12
AGC Circuit ................................................................................ 13
Adjusting the Output Common-Mode Voltage ..................... 14
Applications Information.............................................................. 15
Simple On-Off Keyed (OOK) Receiver................................... 15
Interfacing the AD8338 to an ADC......................................... 15
Outline Dimensions....................................................................... 16
Ordering Guide .......................................................................... 16
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AC Specifications.......................................................................... 3
Absolute Maximum Ratings............................................................ 4
Thermal Resistance ...................................................................... 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Typical Performance Characteristics ............................................. 6
REVISION HISTORY
4/13—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
Data Sheet
AD8338
SPECIFICATIONS
AC SPECIFICATIONS
VBAT = 3.0 V, TA = 25°C, CL = 2 pF on OUTP and OUTM, RL = ∞, MODE pin high, RIN = 2 × 500 Ω, VGAIN = 0.6 V, differential operation,
unless otherwise noted.
Table 1.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
INPUT INTERFACE
Gain Range
Standard configuration using the INPR
and INMR inputs
0
80
dB
Gain Span
Input Voltage Range
Input 1 dB Compression
80
3
dB
V p-p
Differential input, VCM = 1.5 V,
gain = 0.1 V/0 dB
f = 400 kHz
f = 1 MHz
f = 4 MHz
f = 10 MHz
2.2
2
1.6
0.75
18
V p-p
V p-p
V p-p
V p-p
MHz
dB
−3 dB Bandwidth
Gain Accuracy
Standard configuration using the INPR
and INMR inputs; 0.1 V < VGAIN < 1.1 V
−2
+0.5
+2
Input Resistance
Standard configuration using the INPR
and INMR inputs
0.8
1
2
1.2
kΩ
pF
Input Capacitance
OUTPUT INTERFACE
Small Signal Bandwidth
Peak Slew Rate
OUTP and OUTM pins
VGAIN = 0.6 V
VGAIN = 0.6 V
18
50
2.8
1.5
4.5
MHz
V/μs
V p-p
V
Peak-to-Peak Output Swing
Common-Mode Voltage
Input-Referred Noise Voltage
Differential output
Standard configuration using the INPR
and INMR inputs
nV/√Hz
Driving external 47 Ω input resistors
connected to INPD and INMD
1.5
nV/√Hz
Offset Voltage
RTO, VGAIN = 0.1 V, offset null on
RTO, VGAIN = 0.6 V, offset null on
RTO, VGAIN = 0.1 V, offset null off
RTO, VGAIN = 0.6 V, offset null off
−10
−10
−50
−200
+10
+10
+50
+200
mV
mV
mV
mV
POWER SUPPLY
VBAT
IVBAT
3.0
5.0
8.0
3.8
6.0
V
Min gain, VGAIN = 0.1 V
Mid gain, VGAIN = 0.6 V
Max gain, VGAIN = 1.1 V
6.0
3.0
4.5
mA
mA
mA
GAIN CONTROL
Gain Voltage
Gain Slope
0.1
77
1.1
83
V
80
12.5
2
dB/V
mV/dB
%
VREF ACCURACY
VREF = 1.5 V
MODE = 0 V
DETO OUTPUT CURRENT
AGC CONTROL
10
μA
Maximum Target Amplitude
Expected rms output value for target =
VAGC − VREF = 1.0 V
1.0
V rms
Rev. 0 | Page 3 of 16
AD8338
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 2.
Parameter
Rating
Table 3. Thermal Resistance
VBAT to COMM
−0.3 V to +5.5 V
Package Type
θJA
Unit
INPR, INPD, INMD, INMR, MODE, GAIN, COMM to VBAT
FBKM, FBKP, OUTM, OUTP, VAGC,
VREF, OFSN
16-Lead LFCSP
48.75
°C/W
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
Lead Temperature (Soldering, 10 sec)
−40°C to +85°C
−65°C to +150°C
150°C
ESD CAUTION
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 4 of 16
Data Sheet
AD8338
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
12 FBKP
11 OUTP
10 OUTM
INPR
INPD
INMD
INMR
1
2
3
4
AD8338
TOP VIEW
(Not to Scale)
9
FBKM
NOTES
1. THE EXPOSED PAD SHOULD BE TIED
TO A QUIET ANALOG GROUND.
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
0
1
2
3
4
5
6
EPAD
INPR
INPD
INMD
INMR
COMM
MODE
Exposed Pad. The exposed pad should be tied to a quiet analog ground.
Positive 500 Ω Resistor Input for Voltage Input Applications.
Positive Input for Current Input Applications.
Negative Input for Current Input Applications.
Negative 500 Ω Resistor Input for Voltage Input Applications.
Ground.
Gain Mode. This pin selects positive or negative gain slope for gain control. When this pin is tied to VBAT, the
gain of the AD8338 increases proportionally with an increase of the voltage on the GAIN pin. When this pin is
tied to COMM, the gain decreases with an increase of the voltage on the GAIN pin.
7
8
9
10
11
12
13
GAIN
DETO
FBKM
OUTM
OUTP
FBKP
Gain Control Input, 12.5 mV/dB or 80 dB/V.
Detector Output Terminal, 10 µA. If the AGC feature is not used, tie this pin to COMM.
Negative Feedback Node. For more information, see the Adjusting the Output Common-Mode Voltage section.
Negative Output.
Positive Output.
Positive Feedback Node. For more information, see the Adjusting the Output Common-Mode Voltage section.
Voltage for Automatic Gain Control Circuit. This pin controls the target rms output voltage for the AGC circuit.
For more information, see the AGC Circuit section.
VAGC
14
15
16
OFSN
VBAT
VREF
Offset Null Terminal. For more information, see the Offset Correction Circuit section.
Positive Supply Voltage.
Internal 1.5 V Voltage Reference.
Rev. 0 | Page 5 of 16
AD8338
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
80
80
60
V
V
V
= 600mV
= 350mV
= 100mV
GAIN
GAIN
GAIN
70
MODE PIN LOW
MODE PIN HIGH
60
50
40
30
20
10
0
40
20
0
–20
–40
–60
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
100k
1M
10M
FREQUENCY (Hz)
100M
V
(V)
GAIN
Figure 4. Gain vs. VGAIN
Figure 7. Gain vs. Frequency, RIN = 50 Ω
80
80
V
V
V
V
V
= 1100mV
= 850mV
= 600mV
= 350mV
= 100mV
GAIN
GAIN
GAIN
GAIN
GAIN
60
40
70
60
50
40
30
20
10
0
20
0
–20
–40
–60
–80
78.0 78.3 78.6 78.9 79.2 79.5 79.8 80.1 80.4
GAIN SLOPE (dB/V)
100k
1M
10M
FREQUENCY (Hz)
100M
Figure 8. Gain vs. Frequency, RIN = 5 kΩ
Figure 5. Gain Slope Histogram
5
4
100
V
= 3V
S
f = 1MHz
V
= 1.1V
GAIN
80
60
V
V
V
V
V
V
V
V
= 1.0V
= 0.9V
= 0.8V
= 0.7V
= 0.6V
= 0.5V
= 0.4V
= 0.3V
GAIN
GAIN
GAIN
GAIN
GAIN
GAIN
GAIN
GAIN
3
2
1
40
–40°C
+25°C
0
20
–1
–2
–3
–4
–5
V
V
= 0.2V
= 0.1V
GAIN
GAIN
0
+85°C
–20
+105°C
–40
10k
100k
1M
FREQUENCY (Hz)
10M
100M
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
V
(V)
GAIN
Figure 6. Gain vs. Frequency
Figure 9. Gain Error vs. VGAIN over Temperature
Rev. 0 | Page 6 of 16
Data Sheet
AD8338
1.0
5
4
V
= 3V
S
0.5
3
0
2
–0.5
–1.0
–1.5
1
0
–1
–2
–3
–4
–5
10kHz
100kHz
1MHz
–2.0
–2.5
–3.0
–3.5
2MHz
4MHz
–40°C
8MHz
+25°C
+85°C
+105°C
10MHz
12MHz
14MHz
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
V
(V)
V
(V)
GAIN
GAIN
Figure 13. Differential Offset Voltage vs. VGAIN, Offset Null On
Figure 10. Gain Error vs. VGAIN over Frequency
350
30
25
20
15
10
5
300
250
200
150
100
50
DIFFERENTIAL
SINGLE-ENDED
100M
0
100k
0
100k
1M
10M
FREQUENCY (Hz)
1M
10M
FREQUENCY (Hz)
100M
Figure 11. Group Delay vs. Frequency
Figure 14. Output Impedance vs. Frequency
20
0
OFFSET NULL ON
RELATIVE TO OUTPUT
= 0.6V
V
60
50
40
30
20
10
0
GAIN
GAIN = 1000
GAIN = 100
GAIN = 10
–20
–40
–60
–80
–100
–120
GAIN = 1
–3
–2
–1
0
1
2
100k
1M
10M
FREQUENCY (Hz)
100M
DIFFERENTIAL OFFSET VOLTAGE (mV)
Figure 12. Differential Offset Voltage Histogram
Figure 15. Output Balance Error vs. Frequency
Rev. 0 | Page 7 of 16
AD8338
Data Sheet
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
1000
100
10
0dB
1
GAIN = 1, OFFSET NULL OFF
GAIN = 10, OFFSET NULL OFF
GAIN = 100, OFFSET NULL OFF
GAIN = 1000, OFFSET NULL ON
GAIN = 10000, OFFSET NULL ON
20dB
40dB
60dB
80dB
–100
10k
0.1
10k
100k
1M
10M
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 16. CMRR vs. Frequency over Gain, Offset Null On,
Referred to Input
Figure 19. Input Referred Noise vs. Frequency, VBAT = 3 V
100k
0
+85°C
+25°C
–40°C
HD2, 1kΩ
HD3, 1kΩ
HD2, 10kΩ
HD3, 10kΩ
V
= 0.5V p-p
OUT
–10
–20
–30
–40
–50
–60
–70
–80
–90
10k
1k
100
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
50k
500k
5M
V
(V)
FREQUENCY (Hz)
GAIN
Figure 17. Output Referred Noise vs. VGAIN
Figure 20. Harmonic Distortion vs. Frequency
1k
0
–10
–20
–30
–40
–50
–60
–70
–80
+85°C
+25°C
–40°C
100
10
HD2
HD3
1
0.5
1.0
1.5
V
2.0
(V p-p)
2.5
3.0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
(V)
V
OUT
GAIN
Figure 18. Input Referred Noise vs. VGAIN
Figure 21. Harmonic Distortion vs. Output Amplitude
Rev. 0 | Page 8 of 16
Data Sheet
AD8338
0
0
–10
–20
–30
–40
–50
–60
–70
–80
HD2, MODE PIN HIGH
HD3, MODE PIN HIGH
HD2, MODE PIN LOW
HD3, MODE PIN LOW
V
= 0.5V p-p
OUT
–10
–20
–30
–40
–50
–60
–70
–80
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.1
1.1
20k
200k
FREQUENCY (Hz)
2M
20M
V
(V)
GAIN
Figure 22. Harmonic Distortion vs. VGAIN
Figure 25. IMD3 Distortion vs. Frequency
20
10
2.0
1.5
V
= 2V p-p
OUTPUT
OUT
f = 1MHz
GAIN = 0dB
0
1.0
–10
–20
–30
–40
–50
–60
–70
0.5
0
–0.5
–1.0
–1.5
–2.0
INPUT
0.1
0.3
0.5
0.7
0.9
0
100
200
300
400
500
600
700
800
V
(V)
TIME (ns)
GAIN
Figure 23. Input and Output 1 dB Compression vs. VGAIN
Figure 26. Large Signal Pulse Response vs. Time, VGAIN = 0 V
25
20
15
10
5
2.0
1.5
V
= 2V p-p
OUT
f = 1MHz
GAIN = 80dB
1.0
100kHz
0.5
0
–0.5
–1.0
–1.5
–2.0
1MHz
0
0.1
0
0.2
0.4
0.6
0.8
0.3
0.5
0.7
0.9
TIME (µs)
V
(V)
GAIN
Figure 24. OIP3 vs. VGAIN
Figure 27. Large Signal Pulse Response vs. Time, VGAIN = 1.0 V
Rev. 0 | Page 9 of 16
AD8338
Data Sheet
2.0
V
1.5
1.0
f = 100kHz
= 2V p-p
OUT
V
V
LOW = 2mV
HIGH = 20mV
IN
IN
f = 1MHz
1.5
GAIN = 40dB
GAIN = 40dB
1.0
0.5
0.5
0
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
0
0.2
0.4
0.6
0.8
0
20
40
60
80
100 120 140 160 180 200
TIME (µs)
TIME (µs)
Figure 28. Large Signal Pulse Response vs. Time, VGAIN = 0.6 V
Figure 31. Overdrive Recovery vs. Time
100
12
10
8
C
C
C
C
= 0pF
L
L
L
L
–40°C, MODE PIN HIGH
+25°C, MODE PIN HIGH
+85°C, MODE PIN HIGH
–40°C, MODE PIN LOW
+25°C, MODE PIN LOW
+85°C, MODE PIN LOW
= 10pF
= 20pF
= 47pF
80
60
40
20
6
0
–20
–40
–60
–80
–100
4
2
V
= 100mV p-p
OUT
f = 1.5MHz
GAIN = 1
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
(V)
0
0.2
0.4
0.6
0.8
V
TIME (µs)
GAIN
Figure 29. Small Signal Pulse Response vs. Time (Varying Capacitive Loads)
Figure 32. Supply Current vs. VGAIN
50
40
OFFSET NULL OFF
V
GAIN
0.6
0.1
30
10µF
1µF
20
0.1µF
10
0.01µF
V
OUT
0
1.0
0
–10
–20
–30
–40
–1.0
GAIN = 100
10M 100M
0
1
2
3
4
5
TIME (µs)
6
7
8
9
10
20
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 30. Gain Step Response vs. Time
Figure 33. Offset Null Bandwidth vs. Offset Null Capacitor
Rev. 0 | Page 10 of 16
Data Sheet
AD8338
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
3.0
2.5
2.0
1.5
1.0
0.5
0
V
= 3V
S
V
= 5V
S
–100
100
1k
10k
100k
1M
10M
20k
100k
FREQUENCY (Hz)
RESISTANCE (Ω)
Figure 34. PSRR vs. Frequency
Figure 37. Output Common-Mode Voltage vs. RCM to VBAT
3.0
AGC VOLTAGE
0.6
0.1
2.5
2.0
1.5
1.0
0.5
0
V
= 3V
S
OUTPUT VOLTAGE
1.0
0
–1.0
0
5
10
15
20
25
30
35
40
10k
100k
TIME (µs)
RESISTANCE (Ω)
Figure 35. AGC Response vs. Time, No Load
Figure 38. Output Common-Mode Voltage vs. RCM to COMM
AGC VOLTAGE
0.6
0.1
OUTPUT VOLTAGE
1.0
0
–1.0
0
1
2
3
4
5
6
7
8
9
10
TIME (ms)
Figure 36. AGC Response vs. Time, CL = 0.01 µF
Rev. 0 | Page 11 of 16
AD8338
Data Sheet
THEORY OF OPERATION
GETTING STARTED WITH THE AD8338
OFFSET CORRECTION CIRCUIT
The AD8338 is a variable gain amplifier (VGA) that provides a
variable gain range of 80 dB. With a constant −3 dB bandwidth
of 18 MHz across all gains, a gain bandwidth product of 180 GHz
is achieved at the highest gain using only 4.5 mA of supply current.
The differential output allows the AD8338 to directly drive an
ADC input, simplifying board design and saving space and power.
The AD8338 provides an offset correction circuit to cancel out
any dc offsets that may be present. Connecting a 0.2 µF capacitor
from the OFSN pin to VREF allows frequencies above 400 Hz to
pass through, but eliminates dc offsets. For dc-coupled operation,
disable the offset correction circuit by connecting the OFSN pin
directly to the COMM pin. When the part is operated without
offset correction, exercise caution with large gains because any
offsets present large errors on the outputs.
In addition to its gain, bandwidth, and power performance, the
AD8338 includes a range of features that increase its versatility.
Unlike a high-pass filter, the offset correction circuit allows signals
below the corner frequency to pass through with high levels of
crossover distortion. If a frequency below the band of interest may
present itself to the inputs, apply a filter in front of the VGA for
best performance.
•
•
•
Single-supply operation ranging from 3.0 V to 5.0 V
Built-in offset correction circuit to cancel out dc offsets
Automatic gain control (AGC) circuit to control the gain
and keep the output at a steady rms level
Access to internal nodes at both the input and output allows the
user to adjust the gain range, adjust the output common-mode
voltage, and tune the bandwidth.
For lower frequency operation, a larger value of COFSN gives
unpredictable results. If the part is operated at frequencies below
400 Hz, disable the offset correction circuit and compensate the
offset externally.
INPR and INMR Pins in the Standard Configuration
The gain is controlled by a user supplied voltage input applied to
the GAIN pin. The gain can be varied from 0 dB to 80 dB when
the default internal resistors are used; the voltage at the GAIN pin
can be varied from 0.1 V to 1.1 V. The default internal resistors
are used by applying the input voltage to the INPR and INMR
pins (Pin 1 and Pin 4; see Figure 39).
The corner frequency can be approximately calculated as follows:
1
fC =
(1)
2π × 600 × COFSN
EXPLANATION OF THE GAIN FUNCTION
From a designer’s standpoint, the gain of the AD8338 can be
modeled as three cascaded gain stages. The first stage can be
thought of as a differential input transconductance stage, where
the input current is proportional to the differential input voltage
that is applied to the input resistors, as follows:
500Ω
OUTP
INPR
INPD
+V
/2 + VREF
OUT
I
V
IN
IN
INPx − INMx
INMD
INMR
IIN
=
(2)
RP + RN
500Ω
–V
/2 + VREF
OUT
OUTM
This current is then fed into the conceptual second stage, a
current input-current output VGA, which has a gain range
of −26 dB to +54 dB. The conceptual output current is given
by Equation 3.
0dB TO 80dB
Figure 39. Input Voltage Applied to the INPR and INMR Pins
In the standard configuration, a differential input voltage applied
across INPR and INMR is amplified, with the output voltage
appearing differentially across OUTP and OUTM. The outputs
have a default common-mode voltage of VREF, which is equal
to 1.5 V.
− 0.1)/20)
OUT_VGA = IIN × 10−26 + 80 × ((V
(3)
GAIN
I
When VGAIN = 0.1 V, the output current is −26 dB less than the
input current; when VGAIN = 1.1 V, t h e output current is +54 dB
greater than the input current.
The third and final stage can be modeled as a transimpedance
stage, expressed as follows:
GAIN and MODE Pins
The gain of the AD8338 is controlled by the GAIN and MODE
pins. Adjusting the voltage at the GAIN pin from 0.1 V to 1.1 V
adjusts the gain from its lowest to highest value.
V
V
V
OP = IOUT_VGA × RFEEDBACK
(4a)
(4b)
(4c)
ON = −IOUT_VGA × RFEEDBACK
The MODE pin controls the polarity of the gain adjustment. When
MODE is tied to VBAT, the gain of the AD8338 increases propor-
tionally with an increase of the voltage on the GAIN pin. When
MODE is tied to COMM, the gain decreases with an increase of
the voltage on the GAIN pin.
OUT = VOP − VON = 2 × IOUT_VGA × RFEEDBACK
Rev. 0 | Page 12 of 16
Data Sheet
AD8338
For example, if the 500 Ω input resistors and 9.5 kΩ feedback
resistors are used and a 1 V p-p signal is applied with VGAIN set
to 0.1 V, the output value is as follows:
Similarly, if the user requires a minimum gain of −10 dB,
applying a 1.5 kΩ resistor to both the INPD and INMD pins
sets a gain range of −10 dB to +70 dB.
I
IN = 1/(500 + 500) = 1 mA
(5a)
(5b)
(5c)
Effects of Using External Resistors
OUT_VGA = 1 mA × 10−26/20 = 50 µA
When the gain is modified through the use of external resistors,
several trade-offs must be considered. For example, with the appli-
cation of 47 Ω resistors at the inputs, the input noise decreases
to approximately 1.5 nV/√Hz, less than the 4.5 nV/√Hz obtained
when using the internal 500 Ω resistors. However, the −3 dB
bandwidth is reduced from 18 MHz to approximately 3 MHz.
I
V
OUT = 2 × 50 µA × 9.5 kΩ = 0.95 V p-p
The calculation in Equation 5 results in a total gain of approx-
imately −0.4 dB under the specified conditions. Compressing
Equation 2 through Equation 4 produces the following simplified
gain equation:
AGC CIRCUIT
Gain (dB) = (VGAIN − 0.1) × 80 + 20log(RFEEDBACK/RIN) − 26
(6)
The automatic gain control (AGC) circuit compares the rms
output of the part with the desired rms output at the VAGC pin.
Based on this comparison, the DETO pin either sources or sinks
current. By connecting the DETO and GAIN pins together and
by connecting the MODE pin to ground, the AGC circuit can
be used to keep the output rms voltage constant.
where RFEEDBACK and RIN are the resistor values from a single
input to a single output.
VBAT OFSN VREF
AD8338
OFFSET NULL
FBKP
9.5kΩ
500Ω
INPR
To ensure that the AGC circuit reacts fast enough to adjust the
gain, but slow enough to allow signals through, place a capacitor
from DETO to ground. For example, in an on-off keying (OOK)
application with a carrier frequency of 6.795 MHz and a bit rate
of 10 kb/sec, a capacitor value of 0.01 µF is recommended. This
value ensures that the gain reacts to the bit energy but does not
react to the carrier signal.
VGA CORE
OUTP
INPD
I
I
OUT
IN
VREF
INMD
INMR
OUTM
FBKM
–26dB TO +54dB
GAIN INTERFACE
9.5kΩ
500Ω
To set the target rms output voltage, apply a voltage to VAGC.
The target output voltage is lowest when VAGC is set to 1.5 V
and increases when the applied voltage diverges from the 1.5 V
reference voltage. To enable an increasing voltage at the VAGC
pin to increase the rms output voltage, use Equation 7.
AUTOMATIC
GAIN
CONTROL
COMM
MODE GAIN
DETO
VAGC
Figure 40. Functional Block Diagram
V
ORMS = 1.7 × VAGC − 2.264
(7)
For example, if a design requires a minimum gain of 20 dB using
a few additional components, Equation 6 shows that applying a
47 Ω resistor to both the INPD and INMD pins (overriding the
value of RIN) sets a gain range of 20 dB to 100 dB (see Figure 41).
To enable a decreasing voltage at the VAGC pin to increase
the rms output voltage, use Equation 8.
V
ORMS = −1.7 × VAGC + 2.864
(8)
If the AGC feature is not used, tie the DETO pin to COMM.
500Ω
OUTP
+V
/2 + VREF
OUT
INPR
INPD
47Ω
I
V
IN
IN
INMD
47Ω
500Ω
INMR
–V
/2 + VREF
OUT
OUTM
20dB TO 100dB
Figure 41. Using External Resistors at the INPD and INMD Pins
Rev. 0 | Page 13 of 16
AD8338
Data Sheet
Table 6. Resistor Values for Increasing the Output
Common-Mode Voltage (Resistor Tied to COMM)
ADJUSTING THE OUTPUT COMMON-MODE
VOLTAGE
VBAT (V)
Target VOCM (V)
Resistor Value (Ω) Tied to
As with any differential output, the output of the AD8338 is
a differential voltage that is centered about a common-mode
voltage. The output common-mode voltage (VOCM) of the
AD8338 is nominally set to 1.5 V using an internal reference
(see Figure 42).
Any
Any
Any
1.8
2.0
2.5
47,500
28,500
14,250
COMM
COMM
COMM
FBKP
VBAT
FBKP
R1
9.5kΩ
9.5kΩ
(VBAT – 1.5V) × 9.5kΩ
OUTP = 1.5V –
+ V
+ V
/2
OUT
R1
OUTP = 1.5V + V
/2
OUT
I
OUT
VREF = 1.5V
I
OUT
VREF = 1.5V
(VBAT – 1.5V) × 9.5kΩ
OUTM = 1.5V –
/2
OUT
R2
OUTM = 1.5V – V
/2
OUT
9.5kΩ
FBKM
VBAT
9.5kΩ
R2
FBKM
Figure 43. Decreasing the Output Common-Mode Voltage (Resistors
Connected Between the FBKP and FBKM Pins to the VBAT Pin)
Figure 42. Output Common-Mode Voltage Set to 1.5 V (Default Setting)
The output common-mode voltage of the AD8338 can be
adjusted to directly drive ADCs with various input common-
mode requirements. To adjust the output common-mode voltage,
add a resistor from each feedback node (FBKP and FBKM) to
either COMM or VBAT. Adding a resistor from each feedback
node to VBAT decreases the output common-mode voltage; add-
ing a resistor from each feedback node to COMM increases the
output common-mode voltage (see Figure 43 and Figure 44).
FBKP
COMM
R1
9.5kΩ
(0 – 1.5V) × 9.5kΩ
OUTP = 1.5V –
+ V
+ V
/2
OUT
R1
I
OUT
VREF = 1.5V
(0 – 1.5V) × 9.5kΩ
OUTM = 1.5V –
/2
OUT
R2
Table 5 and Table 6 provide examples of resistor values for
decreasing or increasing the output common-mode voltage.
9.5kΩ
FBKM
COMM
R2
Figure 44. Increasing the Output Common-Mode Voltage (Resistors
Connected Between the FBKP and FBKM Pins to the COMM Pin)
Table 5. Resistor Values for Decreasing the Output
Common-Mode Voltage (Resistor Tied to VBAT)
The AD8338 uses its internal reference for all signal processing.
Therefore, although the output common-mode voltage can be
changed through the application of external resistors, the VREF
signal cannot be changed. For applications that require dc coupling
to an ADC, a differential amplifier must be used.
VBAT (V)
Target VOCM (V)
Resistor Value (Ω) Tied to
5.0
3.3
3.0
0.9
0.9
0.9
55,417
28,500
23,750
VBAT
VBAT
VBAT
Rev. 0 | Page 14 of 16
Data Sheet
AD8338
APPLICATIONS INFORMATION
The excellent performance of the AD8338 results in a flat response
over various gains with rail-to-rail output signal swing, high drive
capability, and a very high dynamic range at a low 12 mW. These
features make the AD8338 an exceptional choice for use in battery-
operated equipment, low frequency and baseband applications,
and many other applications.
Table 7 provides typical values for these components at two data
rates. Note that Capacitors C1 through C4 are all of equal value,
and Inductor L2 has the same value as L1.
Table 7. Typical Values for Components in Reactive Filter
Carrier Attenuation,
L1 and L2 f = 6.78 MHz
Data Rate
C1 to C4
SIMPLE ON-OFF KEYED (OOK) RECEIVER
19,200 bps 12 nF
57,600 bps 3.9 nF
240 µH
82 µH
−101 dB
−73 dB
For low complexity, low power data communications, a simple
link built using a modulating carrier tone in an on/off state
provides a fast and cost-effective solution to the designer. Such
designs are used in a variety of applications, including near-field
communications among noninterference mechanical systems,
low data rate sensors, RFID tags, and so on.
INTERFACING THE AD8338 TO AN ADC
The AD8338 is well suited to drive a high speed analog-to-digital
converter (ADC) and is compatible with many ADCs from Analog
Devices, Inc. This example illustrates the interfacing of the AD8338
to the AD7451. The AD7451 is a low power, 3.0 V ADC, which
is also competitively priced for a low cost total solution.
The schematic shown in Figure 45 demonstrates a complete
inductive telemetry on-off keyed (OOK) front end. The crystal
is cut for the target receive frequency of interest, creating a very
narrow-band filter, typically around the 6.78 MHz ISM band.
Figure 46 shows the basic connections between the AD8338
and the AD7451. The common-mode voltage provided by the
AD8338 is within the specifications of the AD7451.
The AD8338 amplifies the signal (the gain is set by an external
controller) and drives a full-wave rectifier bridge. The output of
this bridge is then low-pass filtered into 100 Ω terminations. This
design provides excellent rejection of RF and excellent baseband
information recovery for the decision stage that follows.
The AD8338 can be coupled directly to the AD7451 for full
dc-to-18 MHz operation at the highest level of performance with
low operating power (160 mW typical). The glueless interface
enables a physically small, high performance data acquisition
system that is ideal for many field instruments. A filter before
the VGA provides the antialiasing function and noise limiting.
The reactive filter components—Capacitors C1 through C4 and
Inductors L1 and L2—set the baseband recovery performance. A
design trade-off exchanges baseband response for RF attenuation.
In applications where the modulated information is not encoded
in the signal amplitude, use the AGC feature of the AD8338 to
reduce any bit errors in the sampled signal.
3.0V
VREF
L1
CRYSTAL
MODE
OOK_P
R1
C1
C2
D1
OUTP
D2
D3
INPR
INMR
100Ω
U1
AD8338
OUTM
D4
R2
100Ω
L2
C6
0.01µF
OOK_M
C3
C4
GAIN
C5
0.1µF
VREF
Figure 45. Complete, Low Power OOK Receiver
3.0V
R1
49.9Ω
3.0V
VREF
C1
C2
0.1µF
0.1µF
MODE
V
V
REF
INPR
INMR
DD
V
V
SCLK
SDATA
CS
IN+
IN–
U1
AD8338
OUTP
OUTM
TO
FILTER
OUTPUT
AD7451
GND
MICRO-
CONTROLLER
C3
0.1µF
VREF
Figure 46. Basic Connections to the AD7451 ADC
Rev. 0 | Page 15 of 16
AD8338
Data Sheet
OUTLINE DIMENSIONS
3.10
3.00 SQ
2.90
0.30
0.23
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
13
16
0.50
BSC
1
4
12
EXPOSED
PAD
1.75
1.60 SQ
1.45
9
8
5
0.50
0.40
0.30
0.25 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6.
Figure 47. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
3 mm × 3 mm Body, Very Very Thin Quad
(CP-16-22)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD8338ACPZ-R7
AD8338ACPZ-RL
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option
Branding
Y4K
Y4K
16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
CP-16-22
CP-16-22
1 Z = RoHS Compliant Part.
©2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11279-0-4/13(0)
Rev. 0 | Page 16 of 16
相关型号：
AD8340ACP
IC TELECOM, CELLULAR, RF AND BASEBAND CIRCUIT, QCC24, LFCSP-24, Cellular Telephone Circuit
ADI
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