AD8353 [ADI]
100 MHz-2.7 GHz RF Gain Block; 100兆赫， 2.7千兆赫的射频增益模块
| 型号： | AD8353 |
| 厂家： | 
ADI |
| 描述： | 100 MHz-2.7 GHz RF Gain Block |
| 文件： | 总12页 (文件大小：200K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
100 MHz–2.7 GHz
RF Gain Block
a
AD8353
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Fixed Gain of 20 dB
Operational Frequency of 100 MHz to 2.7 GHz
Linear Output Power Up to 9 dBm
Input/Output Internally Matched to 50 ⍀
Temperature and Power Supply Stable
Noise Figure 5.3 dB
VPOS
VOUT
BIAS AND VREF
INPT
Power Supply 3 V or 5 V
COM1
COM2
AD8353
APPLICATIONS
VCO Buffers
General Tx/Rx Amplification
Power Amplifier Predriver
Low Power Antenna Driver
PRODUCT DESCRIPTION
The noise figure is 5.3 dB at 900 MHz. The reverse isolation
(S12) is –36 dB at 900 MHz and –30 dB at 2.7 GHz.
The AD8353 is a broadband, fixed-gain linear amplifier that
operates at frequencies from 100 MHz up to 2.7 GHz. It is
intended for use in a wide variety of wireless devices including
cellular, broadband, CATV, and LMDS/MMDS applications.
The AD8353 can also operate with a 5 V power supply, in which
case no external inductor is required. Under these conditions,
the AD8353 delivers 8 dBm with 20 dB of gain at 900 MHz.
The dc supply current is 42 mA. At 900 MHz, the OIP3 is
greater than 22 dBm and is 19 dBm at 2.7 GHz. The noise
figure is 5.6 dB at 900 MHz. The reverse isolation (S12) is –35 dB.
By taking advantage of Analog Devices’ high-performance
complementary Si bipolar process, these gain blocks provide
excellent stability over process, temperature, and power supply.
This amplifier is single-ended and internally matched to 50 Ω
with a return loss of greater than 10 dB over the full operating
frequency range.
The AD8353 is fabricated on Analog Devices’ proprietary, high-
performance 25 GHz Si complementary bipolar IC process. The
AD8353 is available in a chip scale package that utilizes an
exposed paddle for excellent thermal impedance and low imped-
ance electrical connection to ground. It operates over a –40°C
to +85°C temperature range.
The AD8353 provides linear output power of 9 dBm with 20 dB
of gain at 900 MHz when biased at 3 V and an external RF
choke is connected between the power supply and the output
pin. The dc supply current is 42 mA. At 900 MHz, the output third
order intercept (OIP3) is greater than 23 dBm, and is 19 dBm
at 2.7 GHz.
An evaluation board is available.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2002
(VS = 3 V, TA = 25؇C, 100 nH external inductor between VOUT and VPOS, ZO = 50 ⍀,
AD8353–SPECIFICATIONS unless otherwise noted.)
Parameters
Conditions
Min
Typ
Max
Unit
OVERALL FUNCTION
Frequency Range
Gain
0.1
2.7
GHz
dB
f = 900 MHz
19.8
f = 1.9 GHz
17.7
dB
f = 2.7 GHz
15.6
dB
dB
dB
dB
dB/V
dB/V
dB/V
dB
dB
dB
Delta Gain
f = 900 MHz, –40°C Յ TA Յ +85°C
f = 1.9 GHz, –40°C Յ TA Յ +85°C
f = 2.7 GHz, –40°C Յ TA Յ +85°C
VPOS 10%, f = 900 MHz
f = 1.9 GHz
f = 2.7 GHz
f = 900 MHz
f = 1.9 GHz
f = 2.7 GHz
–0.97
–1.15
–1.34
0.04
–0.004
–0.04
–35.6
–34.9
–30.3
Gain Supply Sensitivity
Reverse Isolation (S12)
RF INPUT INTERFACE
Input Return Loss
Pin RFIN
f = 900 MHz
f = 1.9 GHz
f = 2.7 GHz
22.3
20.9
11.2
dB
dB
dB
RF OUTPUT INTERFACE
Output Compression Point
Pin VOUT
f = 900 MHz, 1 dB compression
f = 1.9 GHz
f = 2.7 GHz
f = 900 MHz, –40°C Յ TA Յ +85°C
f = 1.9 GHz, –40°C Յ TA Յ +85°C
f = 2.7 GHz, –40°C Յ TA Յ +85°C
f = 900 MHz
f = 1.9 GHz
f = 2.7 GHz
9.1
8.4
7.6
–1.46
–1.17
–1
26.3
16.9
13.3
dBm
dBm
dBm
dB
dB
dB
dB
dB
dB
Delta Compression Point
Output Return Loss
DISTORTION/NOISE
Output Third Order Intercept
f = 900 MHz, ⌬f = 1 MHz, PIN = –28 dBm
f = 1.9 GHz, ⌬f = 1 MHz, PIN = –28 dBm
f = 2.7 GHz, ⌬f = 1 MHz, PIN = –28 dBm
f = 900 MHz, ⌬f = 1 MHz, PIN = –28 dBm
f = 900 MHz
23.6
20.8
19.5
31.6
5.3
dBm
dBm
dBm
dBm
dB
Output Second Order Intercept
Noise Figure
f = 1.9 GHz
6
dB
f = 2.7 GHz
6.8
dB
POWER INTERFACE
Supply Voltage
Total Supply Current
Supply Voltage Sensitivity
Temperature Sensitivity
Pin VPOS
2.7
35
3
3.3
48
V
mA
mA/V
A/°C
41
15.3
60
–40°C Յ TA Յ +85°C
Specifications subject to change without notice.
–2–
REV. 0
AD8353
SPECIFICATIONS (VS = 5 V, TA = 25؇C, no external inductor between VOUT and VPOS, ZO = 50 ⍀, unless otherwise noted.)
Parameters
Conditions
Min
Typ
Max
Unit
OVERALL FUNCTION
Frequency Range
Gain
0.1
2.7
GHz
dB
f = 900 MHz
19.5
f = 1.9 GHz
17.6
dB
f = 2.7 GHz
15.7
dB
dB
dB
dB
dB/V
dB/V
dB/V
dB
dB
dB
Delta Gain
f = 900 MHz, –40°C Յ TA Յ +85°C
f = 1.9 GHz, –40°C Յ TA Յ +85°C
f = 2.7 GHz, –40°C Յ TA Յ +85°C
VPOS 10%, f = 900 MHz
f = 1.9 GHz
f = 2.7 GHz
f = 900 MHz
f = 1.9 GHz
f = 2.7 GHz
–0.96
–1.18
–1.38
0.09
–0.01
–0.09
–35.4
–34.6
–30.2
Gain Supply Sensitivity
Reverse Isolation (S12)
RF INPUT INTERFACE
Input Return Loss
Pin RFIN
f = 900 MHz
f = 1.9 GHz
f = 2.7 GHz
22.9
21.7
11.5
dB
dB
dB
RF OUTPUT INTERFACE
Output Compression Point
Pin VOUT
f = 900 MHz
f = 1.9 GHz
f = 2.7 GHz
f = 900 MHz, –40°C Յ TA Յ +85°C
f = 1.9 GHz, –40°C Յ TA Յ +85°C
f = 2.7 GHz, –40°C Յ TA Յ +85°C
f = 900 MHz
8.3
8.1
7.5
–1.05
–1.49
–1.33
27
dBm
dBm
dBm
dB
dB
dB
Delta Compression Point
Output Return Loss
dB
f = 1.9 GHz
22
dB
f = 2.7 GHz
14.3
dB
DISTORTION/NOISE
Output Third Order Intercept
f = 900 MHz, ⌬f = 1 MHz, PIN = –28 dBm
f = 1.9 GHz, ⌬f = 1 MHz, PIN = –28 dBm
f = 2.7 GHz, ⌬f = 1 MHz, PIN = –28 dBm
f = 900 MHz, ⌬f = 1 MHz, PIN = –28 dBm
f = 900 MHz
22.8
20.6
19.5
30.3
5.6
dBm
dBm
dBm
dBm
dB
Output Second Order Intercept
Noise Figure
f = 1.9 GHz
f = 2.7 GHz
6.3
7.1
dB
dB
POWER INTERFACE
Supply Voltage
Total Supply Current
Supply Voltage Sensitivity
Temperature Sensitivity
Pin VPOS
4.5
35
5
42
4.3
45.7
5.5
52
V
mA
mA/V
A/°C
–40°C Յ TA Յ +85°C
Specifications subject to change without notice.
–3–
REV. 0
AD8353
ABSOLUTE MAXIMUM RATINGS*
PIN CONFIGURATION
Supply Voltage VPOS . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Input Power (re: 50 Ω) . . . . . . . . . . . . . . . . . . . . . . . 10 dBm
Equivalent Voltage . . . . . . . . . . . . . . . . . . . . . . 700 mV rms
Internal Power Dissipation
Paddle Not Soldered . . . . . . . . . . . . . . . . . . . . . . . 325 mW
Paddle Soldered . . . . . . . . . . . . . . . . . . . . . . . . . . . 812 mW
1
2
3
4
8
7
6
5
COM1
VOUT
VPOS
COM2
COM1
NC
AD8353
TOP VIEW
INPT
COM2
(Not to Scale)
JA (Paddle Soldered) . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
JA (Paddle Not Soldered) . . . . . . . . . . . . . . . . . . . . 200°C/W
NC = NO CONNECT
Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . 240°C
PIN FUNCTION DESCRIPTIONS
Pin Mnemonic Description
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
1, 8 COM1
Device Common.
Connect to low
impedance ground.
RF Input Connection.
Must be ac-coupled.
Device Common.
Connect to low
impedance ground.
Positive Supply Voltage
No Connection
RF Output Connection.
Must be ac-coupled.
3
INPT
4, 5 COM2
ORDERING GUIDE
Temperature Package
Range Description
Package
Option
6
2
7
VPOS
NC
VOUT
Model
AD8353ACP–REEL7 –40°C to +85°C 7" Tape and Reel CP-8
AD8353–EVAL
Evaluation Board
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8353 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. 0
Typical Performance Characteristics–AD8353
90
90
120
120
60
60
150
150
30
30
180
0
180
0
330
210
330
210
300
240
300
240
270
270
TPC 1. S11 vs. Frequency, VS = 3 V, TA = 25؇C,
100 MHz ≤ f ≤ 3 GHz
TPC 4. S22 vs. Frequency, VS = 3 V, TA = 25؇C,
100 MHz ≤ f ≤ 3 GHz
25
25
GAIN AT 3.3V
GAIN AT –40؇C
20
20
15
10
5
15
GAIN AT +25؇C
GAIN AT 2.7V
GAIN AT +85؇C
10
GAIN AT 3.0V
5
0
0
0
500
1000
1500
2000
2500
3000
0
500
1000
1500
2000
2500
3000
FREQUENCY – MHz
FREQUENCY – MHz
TPC 2. Gain vs. Frequency, VS = 2.7 V, 3 V, and 3.3 V,
TA = 25؇C
TPC 5. Gain vs. Frequency, VS = 3 V, TA = –40؇C, +25؇C,
and +85؇C
0
–5
0
–5
–10
–15
–20
–25
–10
–15
–20
–25
S
AT 3.0V
S
AT +25
؇
C
S
12
S AT –40
12
؇
C
12
S
AT 2.7V
12
–30
–35
–40
–30
–35
–40
S
AT 3.3V
500
12
12 AT +85
؇C
0
1000
1500
2000
2500
3000
0
500
1000
1500
2000
2500 3000
FREQUENCY – MHz
FREQUENCY – MHz
TPC 6. Reverse Isolation vs. Frequency, VS = 3 V,
TPC 3. Reverse Isolation vs. Frequency, VS = 2.7 V, 3 V,
TA = –40؇C, +25؇C, and +85؇C
and 3.3 V, TA = 25؇C
–5–
REV. 0
AD8353
12
10
8
12
P
AT –40؇C
1 dB
10
8
P
AT 3.3V
AT 2.7V
dB
1
P
AT 3.0V
dB
1
P
AT +85؇C
dB
1
P
P
AT +25؇C
6
dB
6
1
1 dB
4
4
2
0
2
0
0
0
500
1000
1500
2000
2500
3000
1000
1500
2000
2500
3000
500
FREQUENCY – MHz
FREQUENCY – MHz
TPC 7. P1 dB vs. Frequency, VS = 2.7 V, 3 V, and 3.3 V,
TA = 25؇C
TPC 10. P1 dB vs. Frequency, VS = 3 V, TA = –40؇C, +25؇C,
and +85؇C
45
40
35
30
25
20
15
10
5
30
25
20
15
10
5
0
0
7.0
7.2
7.4
7.6
7.8
8.0
8.2
8.4
8.6
8.8
9.0
19.1
19.5
19.9
20.3
20.7
21.1
21.5
21.9
OUTPUT 1 dB COMPRESSION POINT – dBm
OIP3 – dBm
TPC 8. Distribution of P1 dB VS = 3 V, TA = 25؇C,
TPC 11. Distribution of OIP3, VS = 3 V, TA = 25؇C,
f = 2.2 GHz
f = 2.2 GHz
28
26
24
28
26
OIP3 AT –40
؇C
24
22
20
18
16
14
12
10
22
OIP3 AT 3.3V
OIP3 AT +85؇C
20
OIP3 AT +25؇C
18
16
14
12
10
OIP3 AT 3.0V
OIP3 AT 2.7V
0
500
1000
1500
2000
2500
3000
0
500
1000
1500
2000
2500
3000
FREQUENCY – MHz
FREQUENCY – MHz
TPC 9. OIP3 vs. Frequency, VS = 2.7 V, 3 V, and 3.3 V,
TA = 25؇C
TPC 12. OIP3 vs. Frequency, VS = 3 V, TA = –40؇C, +25؇C,
and +85؇C
–6–
REV. 0
AD8353
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
NF AT 3.3V
NF AT +85؇C
NF AT +25؇C
NF AT 2.7V
NF AT –40؇C
NF AT 3.0V
0
500
1000
1500
2000
2500
3000
0
500
1000
1500
2000
2500
3000
FREQUENCY – MHz
FREQUENCY – MHz
TPC 13. Noise Figure vs. Frequency, VS = 2.7 V, 3 V,
TPC 16. Noise Figure vs. Frequency, VS = 3 V,
and 3.3 V, TA = 25؇C
TA = –40°C, +25°C, and +85°C
50
45
40
25
20
15
10
5
I
AT 3.3V
AT 3.0V
S
45
40
35
30
25
20
15
10
5
I
S
I
AT 2.7V
S
0
0
–60
–40
–20
0
20
40
60
80
100
5.90 5.95 6.00 6.05 6.10 6.15 6.20 6.25 6.30 6.35 6.40 6.45 6.50 6.55 6.60
TEMPERATURE – ؇C
NOISE FIGURE – dB
TPC 14. Distribution of Noise Figure, VS = 3 V,
TA = 25؇C, f = 2.2 GHz
TPC 17. Supply Current vs. Temperature, VS = 2.7 V,
3 V, and 3.3 V
90
90
120
120
60
60
150
150
30
30
180
0
180
0
330
330
210
210
300
300
240
240
270
270
TPC 15. S11 vs. Frequency, VS = 5 V, TA = 25°C,
100 MHz ≤ f ≤ 3 GHz
TPC 18. S22 vs. Frequency, VS = 5 V, TA = 25°C,
100 MHz ≤ f ≤ 3 GHz
–7–
REV. 0
AD8353
25
20
15
10
5
25
GAIN AT 5.5V
GAIN AT –40؇C
20
15
10
5
GAIN AT +85؇C
GAIN AT 5.0V
GAIN AT 4.5V
GAIN AT +25؇C
0
0
0
0
500
1000
1500
2000
2500
3000
500
1000
1500
2000
2500
3000
FREQUENCY – MHz
FREQUENCY – MHz
TPC 19. Gain vs. Frequency, VS = 4.5 V, 5 V, and
5.5 V, TA = 25؇C
TPC 22. Gain vs. Frequency, VS = 5 V, TA = –40°C,
+25؇C, and +85؇C
0
–5
0
–5
–10
–15
–20
–25
–10
–15
–20
–25
S
AT +85؇C
S AT +25؇C
12
S
AT 5V
12
12
–30
–35
–40
–30
–35
–40
S
AT 5.5V
1500
12
S
AT –40؇C
S
AT 4.5V
2500
12
12
0
500
1000
1500
2000
2500
3000
0
500
1000
2000
3000
FREQUENCY – MHz
FREQUENCY – MHz
TPC 20. Reverse Isolation vs. Frequency, VS = 4.5 V,
TPC 23. Reverse Isolation vs. Frequency, VS = 5 V,
5 V, and 5.5 V, TA = 25؇C
TA = –40؇C, +25؇C, and +85؇C
10
12
P
AT 5.5V
1 dB
9
8
7
6
5
4
3
2
1
0
P
AT +85؇C
1 dB
10
8
P
AT +25؇C
1 dB
P
AT 4.5V
1 dB
P
AT 5.0V
1 dB
P
AT –40؇C
1 dB
6
4
2
0
0
500
1000
1500
2000
2500
3000
500
1000
1500
2000
2500
3000
0
FREQUENCY – MHz
FREQUENCY – MHz
TPC 24. P1 dB vs. Frequency, VS = 5 V, TA = –40؇C,
+25؇C, and +85؇C
TPC 21. P1 dB vs. Frequency, VS = 4.5 V, 5 V,
and 5.5 V, TA = 25؇C
–8–
REV. 0
AD8353
45
40
35
30
25
20
15
10
5
30
25
20
15
10
5
0
0
7.0
7.2
7.4
7.6
7.8
8.0
8.2
8.4
8.6
8.8
18.8
19.2
19.6
20.0
20.4
20.8
21.2
21.6
OUTPUT 1 dB COMPRESSION POINT – dBm
OIP3 – dBm
TPC 25. Distribution of P1 dB, VS = 3 V, TA = 25°C,
f = 2.2 GHz
TPC 28. Distribution of OIP3, VS = 5 V, TA = 25؇C,
f = 2.2 GHz
26
24
26
24
22
20
18
16
14
12
10
OIP3 AT –40؇C
22
OIP3 AT 5.5V
20
18
OIP3 AT +25
؇C
OIP3 AT 4.5V
OIP3 AT 5.0V
OIP3 AT +85؇C
16
14
12
10
0
1000
1500
2000
2500
3000
0
500
1000
1500
2000
2500
3000
500
FREQUENCY – MHz
FREQUENCY – MHz
TPC 26. OIP3 vs. Frequency, VS = 4.5 V, 5 V, and
5.5 V, TA = 27؇C
TPC 29. OIP3 vs. Frequency, VS = 5 V, TA = –40؇C,
+25؇C, and +85؇C
9.0
8.5
8.0
7.5
10
9
8
7.0
NF AT 5.5V
6.5
7
NF AT +85
؇
C
C
6.0
NF AT 4.5V
6
5
4
5.5
NF AT +25
؇
NF AT 5.0V
500
5.0
4.5
4.0
NF AT –40؇C
0
1000
1500
2000
2500
3000
0
500
1000
1500
2000
2500
3000
FREQUENCY – MHz
FREQUENCY – MHz
TPC 27. Noise Figure vs. Frequency, VS = 4.5 V, 5 V,
and 5.5 V, TA = 25؇C
TPC 30. Noise Figure vs. Frequency, VS = 5 V, TA = –40؇C,
+25؇C, and +85؇C
–9–
REV. 0
AD8353
30
15
10
5
20
19
18
17
25
20
15
10
5
0
–5
–10
–15
16
15
14
0
–25
–20
–15
–10
–5
0
5
6.10 6.15 6.20 6.25 6.30 6.35 6.40 6.45 6.50 6.55 6.60 6.65 6.70
–30
P
– dBm
NOISE FIGURE – dB
IN
TPC 33. Output Power and Gain vs. Input Power,
VS = 3 V, TA = 25ºC, f = 900 MHz
TPC 31. Distribution of Noise Figure, VS = 5 V,
TA = 25؇C, f = 2.2 GHz
50
15
10
5
20
19
18
17
I
AT 5.5V
S
45
40
35
30
25
20
15
10
5
I
AT 4.5V
S
I
AT 5.0V
S
0
–5
–10
–15
16
15
14
0
–60
–40
–20
0
20
40
60
80
100
–25
–20
–15
–10
– dBm
–5
0
5
–30
TEMPERATURE – ؇C
P
IN
TPC 34. Output Power and Gain vs. Input Power,
VS = 5 V, TA = 25ºC, f = 900 MHz
TPC 32. Supply Current vs. Temperature, VS = 4.5 V,
5 V, and 5.5 V
–10–
REV. 0
AD8353
THEORY OF OPERATION
APPLICATIONS
The AD8353 is a two-stage feedback amplifier employing both
shunt-series and shunt-shunt feedback. The first stage is degen-
erated and resistively loaded, and provides approximately 10 dB
of gain. The second stage is a PNP-NPN Darlington output
stage, which provides another 10 dB of gain. Series-shunt feed-
back from the emitter of the output transistor sets the input
impedance to 50 Ω over a broad frequency range. Shunt-shunt
feedback from the amplifier output to the input of the Darlington
stage helps to set the output impedance to 50 Ω. The amplifier
can be operated from a 3 V supply by adding a choke inductor
from the amplifier output to VPOS. Without this choke induc-
tor, operation from a 5 V supply is also possible.
The AD8353 RF Gain Block may be used as a general purpose
fixed-gain amplifier in a wide variety of applications, such as a
driver for a transmitter power amplifier (Figure 1). Its excellent
reverse isolation also makes this amplifier suitable for use as a
local oscillator buffer amplifier that would drive the local oscilla-
tor port of an up or down converter mixer (Figure 2).
HIGH POWER
AMPLIFIER
AD8353
Figure 1. AD8353 as a Driver Amplifier
BASIC CONNECTIONS
The AD8353 RF Gain Block is a fixed-gain amplifier with
single-ended input and output ports whose impedances are
nominally equal to 50 Ω over the frequency range 100 MHz to
2.7 GHz. Consequently, it can be directly inserted into a 50 Ω
system with no impedance-matching circuitry required. The input
and output impedances are sufficiently stable versus variations
in temperature and supply voltage that no impedance matching
compensation is required. A complete set of scattering parameters
is available at the Analog Devices website (www.analog.com).
MIXER
AD8353
LOCAL
OSCILLATOR
Figure 2. AD8353 as a LO Driver Amplifier
AD8353
The input pin (INPT) is connected directly to the base of the
first amplifier stage, which is internally biased to approximately 1 V,
so a dc-blocking capacitor should be connected between the
source that drives the AD8353 and the input pin, INPT.
1
2
3
COM1
VOUT
VPOS
8
7
6
COM1
C2
OUTPUT
VP
1000pF
NC
C1
1000pF
L1
INPUT
INPT
It is critical to supply very low inductance ground connections
to the ground pins (pins 1, 4, 5, and 8) as well as to the back-
side exposed paddle. This will ensure stable operation.
C3
100pF
C4
0.47F
4
COM2
COM2
5
The AD8353 is designed to operate over a wide supply voltage
range, from 2.7 V to 5.5 V. The output of the part, VOUT, is
taken directly from the collector of the output amplifier stage.
This node is internally biased to approximately 2.2 V when the
supply voltage is 5 V. Consequently, a dc-blocking capacitor
should be connected between the output pin, VOUT, and the
load that it drives. The value of this capacitor is not critical, but
it should be 100 pF or larger.
NC = NO CONNECT
Figure 3. Evaluation Board Schematic
EVALUATION BOARD
Figure 3 shows the schematic of the AD8353 evaluation board.
Note that L1 is shown as an optional component that is used to
obtain maximum gain only when VP = 3 V. The board is powered
by a single supply in the range 2.7 V to 5.5 V. The power supply
is decoupled by a 0.47 µF and a 100 pF capacitor.
When the supply voltage is 3 V, it is recommended that an
external RF choke be connected between the supply voltage and
the output pin, VOUT. This will increase the dc voltage applied
to the collector of the output amplifier stage, which will improve
performance of the AD8353 to be very similar to the performance
produced when 5 V is used for the supply voltage. The inductance
of the RF choke should be approximately 100 nH, and care should
be taken to ensure that the lowest series self-resonant frequency
of this choke is well above the maximum frequency of operation
for the AD8353.
Table I. Evaluation Board Configuration Options
Component
Function
Default Value
C1, C2
C3
AC-Coupling Capacitors
High-Frequency Bypass
Capacitor
Low-Frequency Bypass
Capacitor
Optional RF Choke,
used to increase current
through output stage
when VP = 3 V.
1000 pF, 0603
100 pF, 0603
C4
L1
0.47 µF, 0603
The supply voltage input, VPOS, should be bypassed using a
large value capacitance (approximately 0.47 µF or larger) and a
smaller, high-frequency bypass capacitor (approximately 100 pF)
physically located close to the VPOS pin.
The recommended connections and components are shown in
the schematic of the AD8353 evaluation board.
Not recommended for use
when VP = 5 V.
100 nH, 0603
REV. 0
–11–
AD8353
Figure 5. Component Side
Figure 4. Silkscreen Top
OUTLINE DIMENSIONS
Dimensions shown in millimeters.
8-Lead LFCSP
(CP-8)
1.89
3.25
1.74
1.59
3.00
2.75
0.55
0.40
0.30
5
4
8
BOTTOM VIEW
0.60
0.45
0.30
1.95
1.75
1.55
2.25
2.00
1.75
0.15
1
0.10
0.05
PIN 1
INDICATOR
2.95
2.75
2.55
0.50 BSC
0.25
0.20
0.15
0.30
0.23
0.18
12؇
0؇
1.00
0.90
0.80
0.25 REF
SEATING
PLANE
0.05
0.02
0.00
NOTES
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2. PADDLE IS COPPER PLATED WITH LEAD FINISH.
–12–
REV. 0
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