AD835AR [ADI]
250 MHz, Voltage Output 4-Quadrant Multiplier; 250兆赫，电压输出4象限乘法器
| 型号： | AD835AR |
| 厂家： | 
ADI |
| 描述： | 250 MHz, Voltage Output 4-Quadrant Multiplier |
| 文件： | 总8页 (文件大小：203K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
250 MHz, Voltage Output
4-Quadrant Multiplier
a
AD835
FUNCTIO NAL BLO CK D IAGRAM
FEATURES
Sim ple: Basic Function is W = XY + Z
Com plete: Minim al External Com ponents Required
Very Fast: Settles to 0.1% of FS in 20 ns
DC-Coupled Voltage Output Sim plifies Use
High Differential Input Im pedance X, Y and Z Inputs
Low Multiplier Noise: 50 nV/ √Hz
X = X1 –X2
XY
X1
X2
AD835
XY + Z
+1
∑
W OUTPUT
Y1
Y2
APPLICATIONS
Very Fast Multiplication, Division, Squaring
Wideband Modulation and Dem odulation
Phase Detection and Measurem ent
Sinusoidal Frequency Doubling
Video Gain Control and Keying
Y = Y1 –Y2
Z INPUT
Voltage Controlled Am plifiers and Filters
P RO D UCT D ESCRIP TIO N
P RO D UCT H IGH LIGH TS
T he AD835 is a complete four-quadrant voltage output analog
multiplier fabricated on an advanced dielectrically isolated
complementary bipolar process. It generates the linear product
of its X and Y voltage inputs, with a –3 dB output bandwidth of
250 MHz (a small signal rise time of 1 ns). Full-scale (–1 V to
+1 V) rise/fall times are 2.5 ns (with the standard RL of 150 Ω)
and the settling time to 0.1% under the same conditions is typi-
cally 20 ns.
1. T he AD835 is the first monolithic 250 MHz four quadrant
voltage output multiplier.
2. Minimal external components are required to apply the
AD835 to a variety of signal processing applications.
3. High input impedances (100 kΩʈ2 pF) make signal source
loading negligible.
4. High output current capability allows low impedance loads
to be driven.
Its differential multiplication inputs (X, Y) and its summing in-
put (Z) are at high impedance. T he low impedance output volt-
age (W) can provide up to ±2.5 V and drive loads as low as
25 Ω. Normal operation is from ±5 V supplies.
5. State of the art noise levels achieved through careful device
optimization and the use of a special low noise bandgap volt-
age reference.
T hough providing state-of-the-art speed, the AD835 is simple
to use and versatile. For example, as well as permitting the addi-
tion of a signal at the output, the Z input provides the means
to operate the AD835 with voltage gains up to about ×10. In
this capacity, the very low product noise of this multiplier
(50 nV√Hz) makes it much more useful than earlier products.
6. Designed to be easy to use and cost effective in applications
which formerly required the use of hybrid or board level
solutions.
T he AD835 is available in an 8-pin plastic mini-DIP package
(N) and an 8-pin SOIC (R) and is specified to operate over the
–40°C to +85°C industrial temperature range.
REV. A
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1994
One Technology Way, P.O. Box 9106, Norw ood. MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
AD835–SPECIFICATIONS(T = +25؇C, V = ؎5 V, R = 150 ⍀, C ≤ 5 pF unless otherwise noted)
A
S
L
L
Model
AD 835AN/AR
( X 1 – X 2)(Y1 – Y 2)
W =
+ Z
T RANSFER FUNCT ION
U
P ar am eter
Conditions
Min
Typ
Max
Unit
INPUT CHARACT ERIST ICS (X, Y)
Differential Voltage Range
VCM = 0
±1
V
Differential Clipping Level
Low Frequency Nonlinearity
؎1.2
±1.4
0.3
0.1
V
% FS
% FS
X = ±1 V, Y = 1 V
Y = ±1 V, X = 1 V
T MIN to T MAX
0.5
0.3
1
vs. T emperature
X = ±1 V, Y = 1 V
Y = ±1 V, X = 1 V
0.7
0.5
+3
% FS
% FS
V
Common-Mode Voltage Range
Offset Voltage
vs. T emperature
CMRR
–2.5
±3
؎20
±25
mV
mV
dB
1
T MIN to TMAX
f ≤ 100 kHz; ±1 V p-p
70
Bias Current
10
20
27
µA
µA
µA
kΩ
pF
dB
dB
1
vs. T emperature
Offset Bias Current
Differential Resistance
Single-Sided Capacitance
Feedthrough, X
T MIN to T MAX
2
100
2
X = ±1 V, Y = 0 V
Y = ±1 V, X = 0 V
–46
–60
Feedthrough, Y
DYNAMIC CHARACT ERIST ICS
–3 dB Small-Signal Bandwidth
–0.1 dB Gain Flatness Frequency
Slew Rate
Differential Gain Error, X
Differential Phase Error, X
Differential Gain Error, Y
Differential Phase Error, Y
Harmonic Distortion
150
250
15
MHz
MHz
V/µs
W = –2.5 V to +2.5 V
f = 3.58 MHz
f = 3.58 MHz
f = 3.58 MHz
f = 3.58 MHz
X or Y = 10 dBm, 2nd and 3rd Harmonic
Fund = 10 MHz
Fund = 50 MHz
1000
0.3
0.2
0.1
0.1
%
Degrees
%
Degrees
–70
–40
20
dB
dB
ns
Settling T ime, X or Y
T o 0.1%, W = 2 V p-p
SUMMING INPUT (Z)
Gain
–3 dB Small-Signal Bandwidth
Differential Input Resistance
Single Sided Capacitance
Maximum Gain
From Z to W, f ≤ 10 MHz
0.990
0.995
250
60
2
50
MHz
kΩ
pF
X, Y to W, Z Shorted to W, f = 1 kHz
dB
Bias Current
50
µA
OUT PUT CHARACT ERIST ICS
Voltage Swing
±2.2
±2.0
±2.5
V
V
1
vs. T emperature
T MIN to T MAX
Voltage Noise Spectral Density
Offset Voltage
X = Y = 0, f < 10 MHz
50
±25
nV/√Hz
mV
mV
؎75
±10
1
vs. T emperature2
T MIN to T MAX
Short Circuit Current
Scale Factor Error
75
±5
mA
؎8
±9
؎1.0
±1.25
% FS
% FS
% FS
% FS
1
vs. T emperature
T MIN to T MAX
Linearity (Relative Error)3
vs. T emperature
±0.5
1
T MIN to T MAX
POWER SUPPLIES
Supply Voltage
For Specified Performance
Quiescent Supply Current
vs. T emperature
PSRR at Output vs. Vp
PSRR at Output vs. Vn
±4.5
±5
16
±5.5
25
26
0.5
0.5
V
mA
mA
%/V
%/V
1
T MIN to T MAX
+4.5 V to +5.5 V
–4.5 V to –5.5 V
NOT ES
1T MIN = –40°C, T MAX = +85°C.
2Normalized to zero at +25°C.
3Linearity is defined as residual error after compensating for input offset, output voltage offset and scale factor errors.
All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test.
Specifications subject to change without notice.
–2–
REV. A
AD835
ABSO LUTE MAXIMUM RATINGS1
P IN CO NNECTIO NS
8-P in P lastic D IP (N)
8-P in P lastic SO IC (R)
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6 V
Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . . 300 mW
Operating T emperature Range . . . . . . . . . . . . . –40°C to +85C
Storage T emperature Range . . . . . . . . . . . . –65°C to +150°C
Lead T emperature, Soldering 60 sec . . . . . . . . . . . . . . +300°C
Y1
Y2
VN
Z
1
2
3
4
8
7
6
5
X1
X2
VP
W
AD835
TOP VIEW
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500 V
NOT ES
(Not to Scale)
1Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum ratings for extended periods may affect device reliability.
2T hermal Characteristics:
O RD ERING GUID E
Tem perature Range
8-Pin Plastic DIP (N): θJC = 35°C/W; θJA = 90°C/W
8-Pin Plastic SOIC (R): θJC = 45°C/W; θJA = 115°C/W.
Model
P ackage O ptions*
AD835AN
AD835AR
–40°C to +85°C
–40°C to +85°C
N-8
R-8
*N = Plastic DIP; R = Small Outline IC Plastic Package (SOIC).
Typical Performance Characteristics
DG DP (NTSC)
FIELD = 1 LINE = 18
Wfm FCC COMPOSITE
0.00
0.06
0.11
0.16
0.19
0.20
0.4
0.2
X, Y, Z CH = 0dBm
R
C
= 150Ω
≤ 5pF
L
L
0.0
MIN = 0.00
2
0
180
90
MAX = 0.20
p-p/MAX = 0.20
–0.2
–0.4
GAIN
1ST
0.00
2ND
0.02
3RD
0.02
4TH
0.03
5TH
0.03
6TH
0.06
–2
–4
–6
–8
–10
0
PHASE
–90
–180
0.3
0.2
0.1
0.0
MIN = 0.00
MAX = 0.06
p-p = 0.06
–0.1
–0.2
–0.3
1M
10M
100M
1G
1ST
2ND
3RD
4TH
5TH
6TH
FREQUENCY – Hz
Figure 3. Gain & Phase vs. Frequency of X, Y, Z Inputs
Figure 1. Typical Com posite Output Differential Gain &
Phase, NTSC for X Channel; f = 3.58 MHz, RL = 150 Ω
DG DP (NTSC)
FIELD = 1 LINE = 18
Wfm
0.00
FCC COMPOSITE
0.00
0.01
–0.00
–0.01
–0.20
0.3
0.2
MIN = –0.02
MAX = 0.01
p-p/MAX = 0.03
X, Y CH = OdBm
R
C
= 150Ω
≤ 5pF
L
L
0.1
0.0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.1
–0.2
–0.3
1ST
0.00
2ND
0.03
3RD
0.04
4TH
0.07
5TH
0.10
6TH
0.16
0.20
0.10
0.00
MIN = 0.00
MAX = 0.16
p-p = 0.16
–0.10
–0.20
300k
1M
10M
FREQUENCY – Hz
100M
1G
1ST
2ND
3RD
4TH
5TH
6TH
Figure 4. Gain Flatness to 0.1 dB
Figure 2. Typical Com posite Output Differential Gain &
Phase, NTSC for Y Channel; f = 3.58 MHz, RL = 150 Ω
REV. A
–3–
AD835
X, Y CH = 5dBm
R
C
= 150Ω
< 5pF
L
L
–10
–20
–30
–40
–50
–60
0
20
40
60
80
Y FEEDTHROUGH
X FEEDTHROUGH
X FEEDTHROUGH
Y FEEDTHROUGH
10M
1M
100M
FREQUENCY – Hz
1G
1M
10M
100M
1G
FREQUENCY – Hz
Figure 5. X and Y Feedthrough vs. Frequency
Figure 8. CMRR vs. Frequency for X or Y Channel,
RL = 150 Ω, CL ≤ 5 pF
0dBm ON SUPPLY
X, Y = 1V
–10
–20
–30
–40
–50
–60
PSRR ON V+
0.200V
GND
PSRR ON V–
–0.200V
100mV
10ns
300k
1M
10M
100M
1G
FREQUENCY – Hz
Figure 9. PSRR vs. Frequency for V+ and V– Supply
Figure 6. Sm all Signal Pulse Response at W Output, RL =
150 Ω, CL ≤ 5 pF, X Channel = ±0.2 V, Y Channel = ±1.0 V
10MHz
1V
GND
–1V
10dB/DIV
30MHz
20MHz
500mV
10ns
Figure 10. Harm onic Distortion at 10 MHz; 10 dBm Input
Figure 7. Large Signal Pulse Response at W Output, RL =
to X or Y Channels, RL = 150 Ω, CL = ≤ 5 pF
150 Ω, CL ≤ 5 pF, X Channel = ±1.0 V, Y Channel = ±1.0 V
–4–
REV. A
AD835
15
10
5
OUTPUT OFFSET DRIFT WILL
TYPICALLY BE WITHIN SHADED AREA
50MHz
0
10dB/DIV
150MHz
100MHz
–5
–10
–15
OUTPUT V DRIFT, NORMALIZED TO 0 AT 25°C
OS
–55
–35
–15
5
25
45
65
85
105
125
TEMPERATURE – °C
Figure 11. Harm onic Distortion at 50 MHz, 10 dBm Input
Figure 14. VOS Output Drift vs. Tem perature
to X or Y Channel, RL = 150 Ω, CL ≤ 5 pF
35
X CH = 6dBm
Y CH = 10dBm
30
25
20
15
10
5
100MHz
R
= 100Ω
L
200MHz
300MHz
10dB/DIV
0
0
20
40
60
80 100 120 140 160 180 200
RF FREQUENCY INPUT X CHANNEL – MHz
Figure 15. Fixed LO on Y Channel vs. RF Frequency
Input to X Channel
Figure 12. Harm onic Distortion at 100 MHz, 10 dBm Input
to X or Y Channel, RL = 150 Ω, CL ≤ 5 pF
35
X CH = 6dBm
Y CH = 10dBm
RL = 100Ω
30
+2.5V
GND
25
20
15
10
5
–2.5V
1V
10ns
0
0
20
40
60
80 100 120 140 160 180 200
LO FREQUENCY ON Y CH – MHz
Figure 16. Fixed IF vs. LO Frequency on Y Channel
Figure 13. Maxim um Output Voltage Swing, RL = 50 Ω,
CL ≤ 5 pF
REV. A
–5–
AD835
P RO D UCT D ESCRIP TIO N
Simplified representations of this sort, where all signals are pre-
sumed to be expressed in volts, are used throughout this data
sheet, to avoid the needless use of less-intuitive subscripted vari-
ables (such as VX1). We can view all variables as being normal-
ized to 1 V. For example, the input X can either be stated as
being in the range –1 V to +1 V, or simply –1 to +1. T he latter
representation will be found to facilitate the development of new
functions using the AD835. T he explicit inclusion of the de-
nominator, U, is also less helpful, as in the case of the AD835, if
it is not an electrical input variable.
T he AD835 is a four-quadrant, voltage output, analog multi-
plier fabricated on an advanced, dielectrically isolated, comple-
mentary bipolar process. In its basic mode, it provides the linear
product of its X and Y voltage inputs. In this mode, the –3 dB
output voltage bandwidth is 250 MHz (a small signal rise time
of 1 ns). Full-scale (–1 V to +1 V) rise/fall times are 2.5 ns (with
the standard RL of 150 Ω) and the settling time to 0.1% under
the same conditions is typically 20 ns.
As in earlier multipliers from Analog Devices, a unique sum-
ming feature is provided at the Z-input. As well as providing in-
dependent ground references for inputs and output, and
enhanced versatility, this feature allows the AD835 to operate
with voltage gain. Its X-, Y- and Z-input voltages are all nomi-
nally ±1 V FS, with overrange of at least 20%. T he inputs are
fully differential and at high impedance (100 kΩʈ2 pF) and pro-
vide a 70 dB CMRR (f ≤ 1 MHz).
Scaling Adjustm ent
T he basic value of U in Equation 1 is nominally 1.05 V. Figure
18, which shows the basic multiplier connections, also
shows how the effective value of U can be adjusted to have any
lower voltage (usually 1 V) through the use of a resistive-divider
between W (Pin 5) and Z (Pin 4). Using the general resistor val-
ues shown, we can rewrite Equation 1 as
T he low impedance output is capable of driving loads as small
as 25 Ω. T he peak output can be as large as ±2.2 V minimum
for RL = 150 Ω, or ±2.0 V minimum into RL = 50 Ω. T he
AD835 has much lower noise than the AD534 or AD734, mak-
ing it attractive in low level signal-processing applications, for
example, as a wideband gain-control element or modulator.
XY
W =
+ kW +(1 – k)Z '
(3)
U
(where Z' is distinguished from the signal Z at Pin 4). It follows
that
XY
W =
+ Z'
(4)
(5)
(1 – k)U
Basic Theor y
In this way, we can modify the effective value of U to
T he multiplier is based on a classic form, having a translinear
core, supported by three (X, Y, Z) linearized voltage-to-current
converters, and the load driving output amplifier. T he scaling
voltage (the denominator U, in the equations below) is provided
by a bandgap reference of novel design, optimized for ultralow
noise. Figure 17 shows the functional block diagram.
U ' = (1 – k)U
without altering the scaling of the Z' input. (T his is to be ex-
pected, since the only “ground reference” for the output is
through the Z' input.)
T hus, to set U' to 1 V, remembering that the basic value of U is
1.05 V, we need to choose R1 to have a nominal value of 20
times R2. T he values shown here allow U to be adjusted
through the nominal range 0.95 V to 1.05 V, that is, R2 pro-
vides a 5% gain adjustment.
In general terms, the AD835 provides the function
(X 1 – X 2)(Y1 – Y 2)
(1)
W =
+ Z
U
where the variables W, U, X, Y and Z are all voltages. Con-
nected as a simple multiplier, with X = X1 – X2, Y = Y1 – Y2
and Z = 0, and with a scale factor adjustment (see below) which
sets U = 1 V, the output can be expressed as
+5+V5V
FB
4.7µF TANTALUM
(2)
W = XY
0.01µF CERAMIC
X
W
7
8
6
5
X1
X2
VP
W
X = X1 –X2
XY
X1
X2
AD835
R1 = (1–k) R
2kΩ
AD835
Y2
Y1
1
VN
Z
4
2
3
XY + Z
+1
∑
W OUTPUT
Y
R2 = kR
200Ω
Y1
Y2
4.7µF TANTALUM
0.01µF CERAMIC
Y = Y1 –Y2
1
Z
FB
Z INPUT
–5V
Figure 17. Functional Block Diagram
Figure 18. Multiplier Connections
Note that in many applications, the exact gain of the multiplier
may not be very important; in which case, this network may be
omitted entirely, or R2 fixed at 100 Ω.
–6–
REV. A
AD835
AP P LICATIO NS
T he AD835 is both easy to use and versatile. T he capability for
adding another signal to the output at the Z input is frequently
valuable. T hree applications of this feature are presented here: a
wideband voltage controlled amplifier, an amplitude modulator
and a frequency doubler. Of course, the AD835 may also be
used as a square law detector (with its X- and Y-inputs con-
nected in parallel) in which mode it is useful at input frequen-
cies to well over 250 MHz, since that is the bandwidth
limitation only of the output amplifier.
12dB
(VG = 1V)
6dB
(VG = 0.5V)
0dB
(VG = 0.25V)
Multiplier Connections
Figure 18 shows the basic connections for multiplication. T he
inputs will often be single sided, in which case the X2 and Y2
inputs will normally be grounded. Note that by assigning Pins 7
and 2 to these (inverting) inputs, respectively, an extra measure
of isolation between inputs and output is provided. T he X and
Y inputs may, of course, be reversed to achieve some desired
overall sign with inputs of a particular polarity, or they may be
driven fully differentially.
10k
100k
1M
10M
100M
START 10 000.000Hz
STOP 100 000 000.000Hz
Figure 20. AC Response of VCA
An Am plitude Modulator
Figure 21 shows a simple modulator. T he carrier is applied both
to the Y-input and the Z-input, while the modulating signal is
applied to the X-input. For zero modulation, there is no product
term, so the carrier input is simply replicated at unity gain by
the voltage follower action from the Z-input. At X = 1 V, the
RF output is doubled, while for X = –1 V, it is fully suppressed.
T hat is, an X-input of approximately ±1 V (actually ±U, or
about 1.05 V) corresponds to a modulation index of 100%. Car-
rier and modulation frequencies can be up to 300 MHz, some-
what beyond the nominal –3 dB bandwidth.
Power supply decoupling and careful board layout are always
important in applying wideband circuits. T he decoupling rec-
ommendations shown in Figure 18 should be followed closely.
In remaining figures in this data sheet, these power supply
decoupling components have been omitted for clarity, but
should be used wherever optimal performance with high speed
inputs is required. However, they may be omitted if the full high
frequency capabilities of AD835 are not being exploited.
A Wideband Voltage Contr olled Am plifier
Figure 19 shows the AD835 configured to provide a gain of
nominally 0 to 12 dB. (In fact, the control range extends from
well under –12 dB to about +14 dB.) R1 and R2 set the gain to
be nominally ×4. T he attendant bandwidth reduction that
comes with this increased gain can be partially offset by the ad-
dition of the peaking capacitor C1. Although this circuit shows
the use of dual supplies, the AD835 can operate from a single
9 V supply with slight revision.
Of course, a suppressed carrier modulator can be implemented
by omitting the feedforward to the Z-input, grounding that pin
instead.
+5V
MODULATED
MODULATION
CARRIER
INPUT
OUTPUT
8
7
6
5
X1
X2
VP
W
AD835
Y1
1
Y2
VN
Z
4
+5V
2
3
VG
VOLTAGE
OUTPUT
(GAIN CONTROL)
–5V
CARRIER
OUTPUT
8
7
6
5
R1
97.6Ω
X1
X2
VP
W
AD835
C1
33pF
Y1
1
Y2
VN
Z
4
2
3
Figure 21. Sim ple Am plitude Modulator Using the AD835
VIN
(SIGNAL)
Squar ing and Fr equency D oubling
R2
301Ω
Amplitude domain squaring of an input signal, E, is achieved
simply by connecting the X- and Y-inputs in parallel to pro-
duce an output of E2/U. T he input may have either polarity, but
the output in this case will always be positive. T he output polar-
ity may be reversed by interchanging either the X or Y inputs.
–5V
Figure 19. Voltage Controlled 50 MHz Am plifier Using the
AD835
When the input is a sine wave E sin ωt, a signal squarer behaves
as a frequency doubler, since
T he ac response of this amplifier for gains of 0 dB (VG
=
2
)
E2
2U
E sin ωt
(
0.25 V), 6 dB (VG = 0.5 V) and 12 dB (VG = 1 V) is shown in
Figure 20. In this application, the resistor values have been
slightly adjusted to reflect the nominal value of U = 1.05 V. T he
overall sign of the gain may be controlled by the sign of VG.
(6)
=
(1 – cos 2 ωt)
U
While useful, Equation 6 shows a dc term at the output which
will vary strongly with the amplitude of the input, E.
REV. A
–7–
AD835
Figure 22 shows a frequency doubler which overcomes this limi-
tation and provides a relatively constant output over a moder-
ately wide frequency range, determined by the time-constant C1
and R1. T he voltage applied to the X- and Y-inputs are exactly
in quadrature at a frequency f = 1/2 πC1R1 and their ampli-
tudes are equal. At higher frequencies, the X-input becomes
smaller while the Y-input increases in amplitude; the opposite
happens at lower frequencies. T he result is a double frequency
output, centered on ground, whose amplitude of 1 V for a 1 V
input varies by only 0.5% over a frequency range of ±10%. Be-
cause there is no “squared” dc component at the output, sud-
den changes in the input amplitude do not cause a “bounce” in
the dc level.
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
8-P in P lastic D IP
(N P ackage)
8
5
0.280 (7.11)
0.240 (6.10)
PIN 1
1
4
0.325 (8.25)
0.300 (7.62)
0.430 (10.92)
0.348 (8.84)
0.060 (1.52)
0.015 (0.38)
0.195 (4.95)
0.115 (2.93)
0.210
(5.33)
MAX
VG
+5V
0.130
(3.30)
MIN
C1
0.015 (0.381)
0.008 (0.204)
0.160 (4.06)
0.115 (2.93)
VOLTAGE
OUTPUT
8
7
6
5
SEATING
PLANE
0.100
(2.54)
0.070 (1.77)
0.045 (1.15)
0.022 (0.558)
0.014 (0.356)
X1
X2
VP
W
R2
97.6Ω
BSC
AD835
Y2
Y1
1
VN
Z
4
2
3
8-P in P lastic SO IC
(R P ackage)
R3
301Ω
R1
–5V
5
8
0.1574 (4.00)
0.1497 (3.80)
Figure 22. Broadband “Zero-Bounce” Frequency Doubler
PIN 1
0.2440 (6.20)
4
T his circuit is based on the identity
1
0.2284 (5.80)
1
2
cos θ sin θ = sin 2θ
( 7)
0.1968 (5.00)
0.1890 (4.80)
0.0196 (0.50)
x 45
°
0.0099 (0.25)
0.102 (2.59)
0.094 (2.39)
At ωO = 1/C1R1, the X input leads the input signal by 45° (and
is attenuated by √2, while the Y input lags the input signal by
45°, and is also attenuated by √2. Since the X and Y inputs are
90° out of phase, the response of the circuit will be
0.0098 (0.25)
0.0040 (0.10)
8
0
°
°
0.0500 (1.27)
0.0160 (0.41)
0.0500 0.0192 (0.49)
0.0098 (0.25)
0.0075 (0.19)
(1.27)
BSC
0.0138 (0.35)
1 E
E
E2
2U
W =
(sin ωt – 45° )
(sin ωt + 45° ) =
(sin 2ωt)
( 8 )
U
2
2
which has no dc component, R2 and R3 are included to restore
the output to 1 V for an input amplitude of 1 V (the same gain
adjustment as mentioned earlier). Because the voltage across the
capacitor, C1, decreases with frequency, while that across the
resistor, R1, increases, the amplitude of the output varies only
slightly with frequency. In fact, it is only 0.5% below its full
value (at its center frequency ωΟ = 1/C1R1) at 90% and 110%
of this frequency.
–8–
REV. A
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