AD8366ACPZ-R7 [ADI]
DC to 600 MHz, Dual-Digital Variable Gain Amplifiers; DC至600 MHz的双数字可变增益放大器
| 型号： | AD8366ACPZ-R7 |
| 厂家： | 
ADI |
| 描述： | DC to 600 MHz, Dual-Digital Variable Gain Amplifiers |
| 文件： | 总28页 (文件大小：894K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DC to 600 MHz,
Dual-Digital Variable Gain Amplifiers
AD8366
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Matched pair of differential, digitally controlled VGAs
Gain range: 4.5 dB to 20.25 dB
0.25 dB gain step size
Operating frequency
VPSIA
IPPA
BIT0/CS
BIT1/SDAT
BIT2/SCLK
BIT3
DC to 150 MHz (2 V p-p)
3 dB bandwidth: 600 MHz
Noise figure (NF)
11.4 dB at 10 MHz at maximum gain
18 dB at 10 MHz at minimum gain
OIP3: 45 dBm at 10 MHz
IPMA
ENBL
ICOM
IPMB
IPPB
DIGITAL GAIN
CONTROL LOGIC
OCOM
BIT4
HD2/HD3
Better than −90 dBc for 2 V p-p output at 10 MHz at
maximum gain
BIT 5
VPSIB
DENA
Differential input and output
Adjustable output common-mode
Optional dc output offset correction
Serial/parallel mode gain control
Power-down feature
Figure 1.
Single 5 V supply operation
APPLICATIONS
Baseband I/Q receivers
Diversity receivers
Wideband ADC drivers
GENERAL DESCRIPTION
The AD8366 is a matched pair of fully differential, low noise and
low distortion, digitally programmable variable gain amplifiers
(VGAs). The gain of each amplifier can be programmed separately
or simultaneously over a range of 4.5 dB to 20.25 dB in steps of
0.25 dB. The amplifier offers flat frequency performance from dc
to 70 MHz, independent of gain code.
The output common-mode voltage defaults to VPOS/2 but can
be programmed via the VCMA and VCMB pins over a range
of voltages. The input common-mode voltage also defaults
to VPOS/2 but can be driven down to 1.5 V. A built-in, dc offset
compensation loop can be used to eliminate dc offsets from prior
stages in the signal chain. This loop can also be disabled if dc-
coupled operation is desired.
The AD8366 offers excellent spurious-free dynamic range, suitable
for driving high resolution analog-to-digital converters (ADCs).
The NF at maximum gain is 11.4 dB at 10 MHz and increases
~2 dB for every 4 dB decrease in gain. Over the entire gain range,
the HD3/HD2 are better than −90 dBc for 2 V p-p at the output at
10 MHz into 200 Ω. The two-tone intermodulation distortion of
−90 dBc into 200 Ω translates to an OIP3 of 45 dBm (38 dBVrms).
The differential input impedance of 200 ꢀ provides a well-defined
termination. The differential output has a low impedance of ~25 ꢀ.
The digital interface allows for parallel or serial mode gain
programming. The AD8366 operates from a 4.75 V to 5.25 V
supply and consumes typically 180 mA. When disabled, the
part consumes roughly 3 mA. The AD8366 is fabricated using
Analog Devices, Inc., advanced silicon-germanium bipolar
process, and it is available in a 32-lead exposed paddle LFCSP
package. Performance is specified over the −40°C to +85°C
temperature range.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2010-2011 Analog Devices, Inc. All rights reserved.
AD8366
TABLE OF CONTENTS
Features .............................................................................................. 1
Output Differential Offset Correction .................................... 15
Output Common-Mode Control ............................................. 15
Gain Control Interface............................................................... 16
Applications Information.............................................................. 17
Basic Connections...................................................................... 17
Direct Conversion Receiver Design......................................... 18
Quadrature Errors and Image Rejection................................. 18
Low Frequency IMD3 Performance ........................................ 19
Baseband Interface..................................................................... 21
Characterization Setups................................................................. 22
Evaluation Board ............................................................................ 25
Outline Dimensions....................................................................... 28
Ordering Guide .......................................................................... 28
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Parallel and Serial Interface timing............................................ 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Circuit Description......................................................................... 15
Inputs ........................................................................................... 15
Outputs ........................................................................................ 15
REVISION HISTORY
3/11—Rev. 0 to Rev. A
Changes to Table 2, Internal Power Dissipation Value................ 6
10/10—Revision 0: Initial Version
Rev. A | Page 2 of 28
AD8366
SPECIFICATIONS
VS = 5 V, TA = 25°C, ZS = 200 Ω, ZL = 200 Ω, f = 10 MHz, unless otherwise noted.
Table 1.
Parameter
Test Conditions/Comments
Min Typ
Max Unit
DYNAMIC PERFORMANCE
Bandwidth
3 dB; all gain codes
1 dB; all gain codes
Maximum gain
Minimum gain
600
200
1100
1500
MHz
MHz
V/μs
V/μs
Slew Rate
INPUT STAGE
Linear Input Swing
IPPA, IPMA, IPPB, IPMB
At minimum gain AV = 4.5 dB, 1 dB gain compression
3.6
217
1.5
VPOS/2 + 0.075
VPOS/2
V p-p
Differential Input Impedance
Minimum Input Common-Mode Voltage
Maximum Input Common-Mode Voltage
Ω
V
V
V
Input pins left floating
GAIN
Minimum Voltage Gain
Maximum Voltage Gain
Gain Step Size
Gain Step Accuracy
Gain Flatness
Gain Mismatch
Group Delay Flatness
Mismatch
4.5
dB
dB
dB
dB
dB
dB
ns
ps
ns
ns
20.25
0.25
0.25
0.1
0.1
<0.5
2
All gain codes
All gain codes
Maximum gain, DC to 70 MHz
Channel A/Channel B at minimum/maximum gain code
All gain codes, 20% fractional bandwidth, fC < 100 MHz
Channel A and Channel B at same gain code
Maximum gain to minimum gain
Minimum gain to maximum gain
Gain Step Response
30
60
Common-Mode Rejection Ratio
OUTPUT STAGE
Linear Output Swing
Differential Output Impedance
Output DC Offset
−66.2
dB
OPPA, OPMA, OPPB, OPMB, VCMA, VCMB
1 dB gain compression
6
28
−10/−30
V p-p
Ω
mV
Inputs shorted, offset loop disabled at
minimum/maximum gain
Inputs shorted, offset loop enabled (across all gain codes)
HD3, HD2 > −90 dBc, 2 V p-p output
HD3, HD2 > −90 dBc, 2 V p-p output
VCMA and VCMB left floating
10
1.6
3
VPOS/2
4
mV
V
V
V
kΩ
Minimum Output Common-Mode Voltage
Maximum Output Common-Mode Voltage
Common-Mode Setpoint Input Impedance
NOISE/DISTORTION
3 MHz
Noise Figure
Maximum gain
Minimum gain
11.3
18.2
−82
−82
−87
−90
34
35
76
76
6.7
dB
dB
dBc
dBc
dBc
dBc
dBVrms
dBVrms
dBVrms
dBVrms
dBVrms
dBVrms
Second Harmonic
Third Harmonic
OIP31
2 V p-p output, maximum gain
2 V p-p output, minimum gain
2 V p-p output, maximum gain
2 V p-p output, minimum gain
2 V p-p composite, maximum gain
2 V p-p composite, minimum gain
2 V p-p composite, maximum gain
2 V p-p composite, minimum gain
Maximum gain
OIP21
Output 1 dB Compression Point1
Minimum gain
6.9
Rev. A | Page 3 of 28
AD8366
Parameter
Test Conditions/Comments
Min Typ
Max Unit
10 MHz
Noise Figure
Maximum gain
Minimum gain
11.4
18
dB
dB
Second Harmonic
Third Harmonic
OIP31
2 V p-p output, maximum gain
2 V p-p output, minimum gain
2 V p-p output, maximum gain
2 V p-p output, minimum gain
2 V p-p composite, maximum gain
2 V p-p composite, minimum gain
2 V p-p composite, maximum gain
2 V p-p composite, minimum gain
Maximum gain
−97
−96
−97
−90
38
36
72
76
7
dBc
dBc
dBc
dBc
dBVrms
dBVrms
dBVrms
dBVrms
dBVrms
dBVrms
OIP21
Output 1 dB Compression Point1
Minimum gain
6.7
50 MHz
Noise Figure
Maximum gain
Minimum gain
11.8
18.2
−82
−84
−80
−71
32
26
71
78
6.7
dB
dB
dBc
dBc
dBc
dBc
dBVrms
dBVrms
dBVrms
dBVrms
dBVrms
dBVrms
Second Harmonic
Third Harmonic
OIP31
2 V p-p output, maximum gain
2 V p-p output, minimum gain
2 V p-p output, maximum gain
2 V p-p output, minimum gain
2 V p-p composite, maximum gain
2 V p-p composite, minimum gain
2 V p-p composite, maximum gain
2 V p-p composite, minimum gain
Maximum gain
OIP21
Output 1 dB Compression Point1
Minimum gain
6.7
DIGITAL LOGIC
SENB, DENA, DENB, BIT0, BIT1, BIT2, BIT3, BIT4, BIT5
Input High Voltage, VINH
Input Low Voltage, VINL
Input Capacitance, CIN
Input Resistance, RIN
2.2
1.2
1
V
V
pF
kΩ
50
SPI INTERFACE TIMING
SENB = high
fSCLK
t1
t2
t3
t4
t5
t6
Serial clock frequency (maximum)
CS rising edge to first SCLK rising edge (minimum)
SCLK high pulse width (minimum)
SCLK low pulse width (minimum)
SCLK falling edge to CS low (minimum)
SDAT setup time (minimum)
44.4
7.5
7.5
15
7.5
7.5
15
MHz
ns
ns
ns
ns
ns
ns
SDAT hold time (minimum)
PARALLEL PORT TIMING
SENB = low
t7
t8
t9
t10
DENA/DENB high pulse width (minimum)
DENA/DENB low pulse width (minimum)
BITx setup time (minimum)
7.5
15
7.5
7.5
ns
ns
ns
ns
BITx hold time (minimum)
POWER AND ENABLE
Supply Voltage Range
Total Supply Current
Disable Current
Disable Threshold
Enable Response Time
VPSIA, VPSIB, VPSOA, VPSOB, ICOM, OCOM, ENBL
4.75
180
3.2
5.25
V
ENBL = 5 V
ENBL = 0 V
mA
mA
V
1.65
150
Delay following high-to-low transition until device
meets full specifications
ns
Disable Response Time
Delay following low-to-high transition until device
produces full attenuation
3
μs
1 To convert to dBm for a 200 Ω load impedance, add 7 dB to the dBVrms value.
Rev. A | Page 4 of 28
AD8366
PARALLEL AND SERIAL INTERFACE TIMING
CS
t3
t4
t2
t1
SCLK
t5
B-LSB
t6
X
B-MSB
A-LSB
A-MSB
X
SDAT
SENB
ALWAYS HIGH
Figure 2. SPI Port Timing Diagram
BIT[5:0]
DENA
DENB
SENB
GAIN A
t10
GAIN B
GAIN A, GAIN B
t9
t8
t7
ALWAYS LOW
Figure 3. Parallel Port Timing Diagram
Rev. A | Page 5 of 28
AD8366
ABSOLUTE MAXIMUM RATINGS
Table 2.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
5.5 V
Supply Voltages, VPSIx and VPSOx
ENBL, SENB, DENA, DENB, BIT0, BIT1, BIT2,
BIT3, BIT4, BIT5
5.5 V
IPPA, IPMA, IPPB, IPMB
5.5 V
OPPA, OPMA, OPPB, OPMB
OFSA, OFSB
5.5 V
5.5 V
DECA, DECB, VCMA, VCMB, CCMA, CCMB
Internal Power Dissipation
θJA (With Pad Soldered to Board)
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 60 sec)
5.5 V
1.4 W
ESD CAUTION
45.4°C/W
150°C
−40°C to +85°C
−65°C to +150°C
300°C
Rev. A | Page 6 of 28
AD8366
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
BIT0/CS
BIT1/SDAT
BIT2/SCLK
BIT3
OCOM
BIT4
VPSIA
IPPA
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
PIN 1
INDICATOR
IPMA
ENBL
ICOM
IPMB
IPPB
AD8366
TOP VIEW
(Not to Scale)
BIT5
DENA
VPSIB
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED
TO GROUND.
Figure 4. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 8, 13, 28
VPSIA, VPSIB, VPSOB, Input and Output Stage Positive Supply Voltage (4.75 V to 5.25 V).
VPSOA
2, 3, 6, 7
IPPA, IPMA, IPMB,
IPPB
Differential Inputs.
4
ENBL
Chip Enable. Pull this pin high to enable.
5, 20
ICOM, OCOM
Input and Output Ground Pins. Connect these pins via the lowest possible impedance to
ground.
9, 32
DECB, DECA
OFSB, OFSA
VPOS/2 Reference Decoupling Node. Connect a decoupling capacitor from these nodes to
ground.
Output Offset Correction Loop Compensation. Connect a capacitor from these nodes to
ground to enable the correction loop. Tie this pin to ground to disable.
10, 31
11, 30
12, 29
CCMB, CCMA
VCMB, VCMA
Connect These Nodes to Ground.
Output Common-Mode Setpoint. These pins default to VPOS/2 if left open. Drive these pins
from a low impedance source to change the output common-mode voltage.
14, 15, 26, 27
16, 17
OPPB, OPMB, OPMA,
OPPA
DENB, DENA
Differential Outputs.
Data Enable. Pull these pins high to address each or both channels for parallel gain
programming. These pins are not used in serial mode.
18, 19, 21, 22, 23, 24 BIT5, BIT4, BIT3,
Parallel Data Path (When SENB Is Low). When SENB is high, BIT0 becomes a chip select (CS),
BIT2/SCLK, BIT1/SDAT, BIT1 becomes a serial data input (SDAT), and BIT2 becomes a serial clock (SCLK). BIT3 to BIT5
BIT0/CS
are not used in serial mode.
25
SENB
Serial Interface Enable. Pull this pin high for serial gain programming mode and pull this pin low
for parallel gain programming mode.
EPAD
The exposed pad must be connected to ground.
Rev. A | Page 7 of 28
AD8366
TYPICAL PERFORMANCE CHARACTERISTICS
VS = 5 V, TA = 25°C, ZS = 200 Ω, ZL = 200 Ω, f = 10 MHz, unless otherwise noted.
22
20
18
16
14
12
10
8
0.5
FREQUENCY = 3MHz
FREQUENCY = 50MHz
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
0.4
0.3
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
6
4
0
5
10 15 20 25 30 35 40 45 50 55 60
GAIN CODE
0
5
10 15 20 25 30 35 40 45 50 55 60
GAIN CODE
Figure 8. Gain Error vs. Gain Code, Error Normalized to 10 MHz
Figure 5. Gain vs. Gain Code at 500 kHz, 3 MHz, 10 MHz, and 50 MHz
21.0
20.8
20.6
20.4
20.2
20.0
19.8
19.6
19.4
19.2
19.0
25
GAIN CODE 63
20
GAIN CODE 48
15
GAIN CODE 32
10
GAIN CODE 16
GAIN CODE 00
5
0
5
–10
100k
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
TEMPERATURE (°C)
1M
10M
100M
1G
FREQUENCY (Hz)
Figure 9. Gain vs. Temperature at Maximum Gain at 10 MHz
Figure 6. Frequency Response vs. Gain Code
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
–1.0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
–1.0
0
10
20
30
40
50
60
0
10
20
30
40
50
60
GAIN CODE
GAIN CODE
Figure 10. Channel A-to-Channel B Phase Mismatch vs. Gain Code,
2 V p-p Output
Figure 7. Channel A-to-Channel B Amplitude Mismatch vs. Gain Code,
2 V p-p Output
Rev. A | Page 8 of 28
AD8366
20
18
16
14
12
10
8
20
18
16
14
12
10
8
20
18
16
14
12
10
8
20
18
16
14
12
10
8
T
T
T
= +85°C
= +25°C
= –40°C
GAIN CODE 0
GAIN CODE 63
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
A
A
A
6
6
6
6
4
4
4
4
2
2
2
2
0
0
0
0
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
0
5
10 15 20 25 30 35 40 45 50 55 60
GAIN CODE
FREQUENCY (MHz)
Figure 14. OP1dB vs. Frequency at Gain Code 0 and Gain Code 63
Figure 11. OP1dB vs. Gain Code at 500 kHz, 3 MHz, 10 MHz, and 50 MHz
50
50
45
40
35
30
25
20
15
10
5
60
55
50
45
40
35
30
25
20
15
10
45
GAIN CODE 63
GAIN CODE 32
40
35
30
25
20
15
10
5
GAIN CODE 0
T
T
= +85°C
= +25°C
= –40°C
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
A
A
A
FREQUENCY = 10MHz
FREQUENCY = 50MHz
CHANNEL A
CHANNEL B
T
0
0
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
FREQUENCY (MHz)
0
5
10 15 20 25 30 35 40 45 50 55 60
GAIN CODE
Figure 15. OIP3 vs. Frequency, Gain Code 0, Gain Code 32, and Gain Code 63,
2 V p-p Composite Output
Figure 12. OIP3 vs. Gain Code at 10 MHz and 50 MHz Frequency, 2 V p-p
Composite Output
0
CHANNEL A
CHANNEL B
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
T
T
= +85°C
= +25°C
= –40°C
FREQUENCY = 10MHz
FREQUENCY = 50MHz
A
A
A
–10
–30
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
T
GAIN CODE 0
–50
–70
GAIN CODE 32
GAIN CODE 63
–90
–110
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
FREQUENCY (MHz)
0
5
10 15 20 25 30 35 40 45 50 55 60
GAIN CODE
Figure 16. Two-Tone Output IMD3 vs. Frequency at Gain Code 0,
Gain Code 32, and Gain Code 63, 2 V p-p Composite Output
Figure 13. Two-Tone Output IMD3 vs. Gain Code at 10 MHz and 50 MHz
Frequency, 2 V p-p Composite Output
Rev. A | Page 9 of 28
AD8366
100
90
80
70
60
50
40
30
20
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
GAIN CODE 63
GAIN CODE 0
T
= +85°C
= +25°C
= –40°C
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
A
10
FREQUENCY = 10MHz
FREQUENCY = 50MHz
T
A
CHANNEL A
CHANNEL B
T
A
0
0
5
10 15 20 25 30 35 40 45 50 55 60
GAIN CODE
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
FREQUENCY (MHz)
Figure 17. OIP2 vs. Gain Code at 10 MHz and 50 MHz Frequency,
2 V p-p Composite Output
Figure 20. OIP2 vs. Frequency at Gain Code 0 and Gain Code 63, 2 V p-p
Composite Output
0
0
T
T
T
= +85°C
= +25°C
= –40°C
CHANNEL A
CHANNEL B
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
FREQUENCY = 10MHz
FREQUENCY = 50MHz
A
A
A
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
GAIN CODE 0
GAIN CODE 63
0
5
10 15 20 25 30 35 40 45 50 55 60
GAIN CODE
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
FREQUENCY (MHz)
Figure 18. Two-Tone Output IMD2 vs. Gain Code at 10 MHz and 50 MHz
Frequency, 2 V p-p Composite Output
Figure 21. Two-Tone Output IMD2 vs. Frequency,
Gain Code 0 and Gain Code 63, 2 V p-p Composite Output
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
0
CHANNEL A
T
T
T
= +85°C
= +25°C
= –40°C
GAIN CODE 0
GAIN CODE 32
GAIN CODE 63
HD2
HD3
A
A
A
CHANNEL B
–10
–20
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
1
10
100
1000
VCMA, VCMB (V)
FREQUENCY (MHz)
Figure 22. HD3/HD2 vs. VOCM at 10 MHz, Gain Code 0, 2 V p-p Output
Figure 19. Harmonic Distortion vs. Frequency at Gain Code 0, Gain Code 32,
and Gain Code 63, 2 V p-p Output
Rev. A | Page 10 of 28
AD8366
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
60
50
40
30
20
10
0
T
T
T
= +85°C
= +25°C
= –40°C
GAIN CODE 0
GAIN CODE 63
A
A
A
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
GAIN CODE 0
GAIN CODE 63
–3
–2
–1
0
1
2
3
4
5
–3
–2
–1
0
1
2
3
4
5
P
PER TONE (dBm)
P
PER TONE (dBm)
OUT
OUT
Figure 26. IMD3 vs. Output Power (POUT) at Minimum-to-Maximum Gain
Codes, 10 MHz Frequency
Figure 23. OIP3 vs. Output Power (POUT) at Minimum and Maximum Gain
Codes, 10 MHz Frequency
0
100
90
80
70
60
50
40
30
20
GAIN CODE 0
GAIN CODE 63
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
10
0
GAIN CODE 0
GAIN CODE 63
–8 –7 –6 –5 –4 –3 –2 –1
0
1
2
3
4
5
–8 –7 –6 –5 –4 –3 –2 –1
0
1
2
3
4
5
P
PER TONE (dBm)
P
PER TONE (dBm)
OUT
OUT
Figure 27. IMD2 vs. Output Power (POUT) at Minimum and Maximum Gain
Codes, 10 MHz Frequency
Figure 24. OIP2 vs. Output Power (POUT) at Minimum and Maximum Gain
Codes, 10 MHz Frequency
–60
–60
T
T
T
= +85°C
= +25°C
= –40°C
GAIN CODE 0
GAIN CODE 63
A
A
A
T
T
T
= +85°C
= +25°C
= –40°C
GAIN CODE 0
GAIN CODE 63
A
A
A
–65
–70
–65
–70
–75
–75
–80
–80
–85
–90
–85
–95
–90
–100
–105
–110
–115
–120
–95
–100
–105
–110
–5
–4
–3
–2
–1
0
1
2
3
4
5
–5 –4 –3 –2 –1
0
1
2
3
4
5
6
7
8
P
(dBm)
P
(dBm)
OUT
OUT
Figure 28. HD3 vs. Output Power (POUT) for Gain Code 0 and Gain Code 63,
10 MHz Frequency
Figure 25. HD2 vs. Output Power (POUT) at Gain Code 0 and Gain Code 63,
10 MHz Frequency
Rev. A | Page 11 of 28
AD8366
60
55
50
45
40
35
30
25
20
15
10
300
280
260
240
220
200
180
160
140
120
CHANNEL A
CHANNEL B
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
GAIN CODE 63
GAIN CODE 47
GAIN CODE 48
GAIN CODE 31
GAIN CODE 32
GAIN CODE 15
GAIN CODE 16
GAIN CODE 0
100
0
0.1
1
10
100
1000
5
10 15 20 25 30 35 40 45 50 55 60
GAIN CODE
FREQUENCY (kHz)
Figure 32. Noise Spectral Density vs. Frequency
Figure 29. Supply Current vs. Gain Code at 10 MHz
30
28
26
24
22
20
18
16
14
12
10
30
28
26
24
22
20
18
16
14
12
10
CHANNEL A
CHANNEL B
CHANNEL B, FREQUENCY = 0.5MHz
CHANNEL A, FREQUENCY = 0.5MHz
CHANNEL B, FREQUENCY = 3MHz
CHANNEL A, FREQUENCY = 3MHz
CHANNEL B, FREQUENCY = 10MHz
CHANNEL A, FREQUENCY = 10MHz
CHANNEL B, FREQUENCY = 50MHz
CHANNEL A, FREQUENCY = 50MHz
GAIN CODE 0
GAIN CODE 15
GAIN CODE 16
GAIN CODE 31
GAIN CODE 32
GAIN CODE 47
GAIN CODE 48
GAIN CODE 63
0.1
1
10
100
1000
0
5
10 15 20 25 30 35 40 45 50 55 60
GAIN CODE
FREQUENCY (kHz)
Figure 33. Noise Figure vs. Frequency
Figure 30. Noise Figure vs. Gain Code at 0.5 MHz, 3 MHz, 10 MHz, and 50 MHz
40
37
34
31
28
25
22
19
16
13
10
7.5
7.2
6.9
6.6
6.3
6.0
5.7
5.4
5.1
4.8
4.5
280
270
260
250
240
230
220
210
200
190
180
3.0
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0
CHANNEL A: R
, GAIN CODE 0
, GAIN CODE 63
, GAIN CODE 32
, GAIN CODE 0
, GAIN CODE 63
, GAIN CODE 32
, GAIN CODE 32
, GAIN CODE 0
OUT
OUT
OUT
CHANNEL A: R , GAIN CODE 0
IN
CHANNEL A: R
CHANNEL B: R
CHANNEL A: L
CHANNEL A: L
CHANNEL B: L
CHANNEL A: R
CHANNEL A: R
CHANNEL A: R , GAIN CODE 63
IN
CHANNEL B: R , GAIN CODE 32
IN
OUT
OUT
OUT
OUT
OUT
CHANNEL A: C , GAIN CODE 0
IN
CHANNEL A: C , GAIN CODE 63
IN
CHANNEL B: C , GAIN CODE 32
IN
CHANNEL A: R , GAIN CODE 32
IN
CHANNEL A: R , GAIN CODE 0
IN
CHANNEL B: R , GAIN CODE 63
IN
CHANNEL B: R
, GAIN CODE 63
OUT
CHANNEL A: C , GAIN CODE 32
IN
CHANNEL A: L
CHANNEL B: L
CHANNEL B: L
, GAIN CODE 32
, GAIN CODE 0
, GAIN CODE 63
OUT
OUT
OUT
CHANNEL B: C , GAIN CODE 0
IN
CHANNEL B: C , GAIN CODE 63
IN
0
20
40
60
80
100 120 140 160 180 200
0
20
40
60
80
100 120 140 160 180 200
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 34. Differential Series Output Resistance and Inductance vs.
Frequency
Figure 31. Differential Parallel Input Resistance and Capacitance vs.
Frequency
Rev. A | Page 12 of 28
AD8366
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
140
130
120
110
100
90
PSRR GAIN CODE 0
PSRR GAIN CODE 63
80
70
60
50
40
30
20
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
FREQUENCY = 10MHz
FREQUENCY = 50MHz
10
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
0
5
10 15 20 25 30 35 40 45 50 55 60
GAIN CODE
FREQUENCY (MHz)
Figure 35. Power Supply Rejection Ratio (PSRR) vs. Frequency
Figure 38. SFDR vs. Gain Code at 10 MHz and 50 MHz,
1 Hz Analysis Bandwidth
2.0
90
80
70
60
50
40
30
20
10
0
GAIN CODE 32
GAIN CODE 0
1.8
GAIN CODE 63
GAIN CODE 63
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
GAIN CODE 32
GAIN CODE 0
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
1M
10M
100M
1G
FREQUENCY (MHz)
FREQUENCY (Hz)
Figure 36. Group Delay vs. Frequency at Gain Code 0, Gain Code 32, and
Gain Code 63
Figure 39. Common-Mode Rejection Ratio (CMRR) vs. Frequency
0
0
P
P
P
P
P
= +10dBm
= +5dBm
= 0dBm
= –5dBm
= –10dBm
MEASURED CHANNEL AT GAIN CODE 63
MEASURED CHANNEL AT GAIN CODE 32
MEASURED CHANNEL AT GAIN CODE 0
–20
IN
IN
IN
IN
IN
–20
–40
–40
–60
–60
–80
–100
–120
–140
–160
–80
–100
DRIVEN CHANNEL AT GAIN CODE 0
–120
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 37. Channel-to-Channel Isolation vs. Frequency,
Channel A Driven, Channel B Measured
Figure 40. Forward Leakage vs. Frequency, Part Disabled
Rev. A | Page 13 of 28
AD8366
1.2
1.0
1.4
1.2
0pF
0pF
1.0
0.8
0.8
0.6
10pF
10pF
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.2
–5
–4
–3
–2
–1
0
1
2
3
4
5
–5
–4
–3
–2
–1
0
1
2
3
4
5
TIME (ns)
TIME (ns)
Figure 41. Large Signal Pulse Response, Gain Code 0, Input Signal 1.2 V p-p,
0 pF and 10 pF Capacitive Loading Conditions
Figure 44. Large Signal Pulse Response, Gain Code 63, Input Signal 240 mV p-p,
0 pF and 10 pF Capacitive Loading Conditions
1
2
3
Ω
Ω
T
CH1 1V
CH2 100mV
M1µs
4.02µs
5GS/s A CH1
100k pts
1.60V
M 200ns 250MS/s
CH4 1V Ω
4.0ns/pt
A CH4
2.48V
CH3 50mV
Ω
Figure 42. ENBL Time Domain Response
Figure 45. Gain Step Time Domain Response, Minimum-to-Maximum Gain
(Time Scale 200 ns/division), CH4 = Digital Control Inputs
0
–20
–40
–60
–80
–100
–120
0.1
1
10
100
1000
FREQUENCY (MHz)
Figure 43. Reverse Isolation (S12) vs. Frequency
Rev. A | Page 14 of 28
AD8366
CIRCUIT DESCRIPTION
The AD8366 is a dual, differential, digitally controlled VGA
with 600 MHz of 3 dB bandwidth and a gain range of 4.5 dB to
20.25 dB adjustable in 0.25 dB steps. Using a proprietary variable
gain architecture, the AD8366 is able to achieve excellent linearity
(45 dBm) and noise performance (11.7 nV/√Hz) at 10 MHz at
minimum gain. Intended for use in direct conversion systems, the
part also includes dc offset correction that can be disabled easily
by grounding either OFSA or OFSB. In addition, the part offers
an adjustable output common-mode range of 1.6 V to 3 V.
OUTPUT DIFFERENTIAL OFFSET CORRECTION
To prevent significant levels of offset from appearing at the
outputs of the AD8366, each digitally controlled VGA has a
differential offset correction loop, as shown in Figure 47. This
loop senses any differential offset at the output and corrects for
it by injecting an opposing current at the input differential ground.
The loop is able to correct for input dc offsets of up to 20 mV.
Because the loop automatically nulls out any dc or low frequency
offset, the effect of the loop is to introduce a high-pass corner into
the transfer function of the digitally controlled VGA. The
location of this high-pass corner depends on both the gain
setting and the value of the capacitor connected to the OFSx pin
(OFSA for DVGA A and OFSB for DVGA B) and is given by
The main signal path is shown in Figure 46. It consists of an
input transconductance, a variable-gain cell, and an output
transimpedance amplifier.
VARIABLE
CURRENT-GAIN OUTPUT
STAGE
BUFFER
GC
100Ω
100Ω
12.5Ω
12.5Ω
4300
(
1.037
)
+ 4000
INP
INM
OUTP
OUTM
f3dB,HP kHz =
( )
2π
(
COFS +10
)
A
Z
I
VIRTUAL
GROUND
VIRTUAL
GROUND
where:
GC is the gain code (a value from 0 to 63).
OFS is the value of the capacitance connected to OFSA or OFSB,
Figure 46. Main Signal Path
C
The input transconductance provides a broadband 200 Ω
differential termination and converts the input voltage to a
current. This current is fed into the variable current-gain cell.
The output of this cell goes into the transimpedance stage, which
generates the output voltage. The transimpedance is fixed at 500 Ω,
with a roughly 25 Ω differential output impedance.
in picofarads (pF).
The offset correction loop can be disabled by grounding either
OFSA or OFSB.
VARIABLE-GAIN OUTPUT
STAGE
BUFFER
OUTP
OUTM
A
Z
I
INPUTS
The inputs to the digitally-controlled VGAs in the AD8366 are
differential and can be either ac- or dc-coupled. The AD8366
synthesizes a 200 Ω (differential) input impedance, with a return
loss (re: 200 Ω) of better than 10 dB to 200 MHz. The nominal
common-mode input voltage to the part is VPOS/2, but the AD8366
can be dc-coupled to parts with lower common modes if these
parts can sink current. The amount of current sinking required
depends on the input common-mode level and is given by
INP
INM
gm2
gm1
C
OFFSET
OFS
COMPENSATION
LOOP
Figure 47. Differential Offset Correction Loop
OUTPUT COMMON-MODE CONTROL
I
SINK (per leg) = (VPOS/2 − VICM)/100
To interface to ADCs that require different input common-mode
voltages, the AD8366 has an adjustable output common-mode
level. The output common-mode level is normally set to VPOS/2;
however, it can be changed between 1.6 V and 3 V by driving
the VCMA pin or the VCMB pin. The input equivalent circuit
for the VCMA pin is shown in Figure 48; the VCMB pin has the
same input equivalent circuit.
The input common-mode range is 1.5 V to VPOS/2.
OUTPUTS
The outputs of the digitally-controlled VGAs are differential and
can be either ac- or dc-coupled. The AD8366 synthesizes a 25 Ω
differential output impedance, with a return loss (re: 25 Ω) of
better than 10 dB to 120 MHz. The nominal common-mode
output voltage is VPOS/2; however, it can be lowered or raised by
driving the VCMA or VCMB pins.
4kΩ
V
/2
POS
500Ω
VCMA
Figure 48. Input Equivalent Circuit for VCMA
Rev. A | Page 15 of 28
AD8366
25.0
22.5
20.0
17.5
15.0
12.5
10.0
7.5
1.0
GAIN CONTROL INTERFACE
0.8
The AD8366 provides two methods of digital gain control:
serial or parallel. When the SENB pin is pulled low, the part
is in parallel gain control mode. In this mode, the two digitally
controlled VGAs can be programmed simultaneously, or one at
a time, depending on the levels at DENA and DENB. If the SENB
pin is pulled high, the part is in serial gain control mode, with
Pin 24, Pin 23, and Pin 22 corresponding to the CS, SDAT, and
SCLK signals, respectively.
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
5.0
The voltage gain of the AD8366 is well approximated by
2.5
Gain (dB) = GainCode × 0.253 + 4.5
0
0
5
10 15 20 25 30 35 40 45 50 55 60
GAIN CODE
Note that at several major transitions (15 to 16, 31 to 32, and 47 to
48), the gain changes significantly less (0 dB step) or significantly
more (0.5 dB step) than the desired 0.25 dB step. This is inherent
in the design of the part and is related to the partitioning of the
variable gain block into a fine-gain and a coarse-gain section.
Figure 49. Gain and Gain Step Error vs. Gain Code at 10 MHz
Rev. A | Page 16 of 28
AD8366
APPLICATIONS INFORMATION
The output buffers of the AD8366 are low impedance around
25 Ω designed to drive ADC inputs. The output common-mode
voltage defaults to VPOS/2; however, it can be adjusted by applying a
desired external voltage to VCMA/VCMB. The common-mode
voltage can be adjusted from 1.6 V to 3.0 V without significant
harmonic distortion degradation.
BASIC CONNECTIONS
Figure 50 shows the basic connections for operating the AD8366.
A voltage from 4.75 V to 5.25 V should be applied to the supply
pins. Each supply pin should be decoupled with at least one low
inductance, surface-mount ceramic capacitor of 0.1 μF placed as
close as possible to the device.
To enable the AD8366, the ENBL pin must be pulled high. Taking
ENBL low disables the device, reducing current consumption to
approximately 3 mA at ambient temperature.
The differential input impedance is 200 Ω and sits at a nominal
common-mode voltage of VPOS/2. The inputs can be dc-coupled
or ac-coupled. If using direct dc coupling, the common-mode
voltage, VCM, can range from 1.5 V to VPOS/2.
VPOS
0.01µF
8200pF
0.01µF
CHANNEL A
OUTPUT
0.01µF
VPOS
0.1µF
0.1µF
0.1µF
0.1µF
VPSIA
IPPA
BIT0/CS
BIT1/SDAT
BIT2/SCLK
CHANNEL A
INPUT
IPMA
ENBL
ICOM
IPMB
IPPB
VPOS
BIT3
AD8366
OCOM
0.1µF
BIT4
BIT5
CHANNEL B
INPUT
VPSIB
DENA
VPOS
0.1µF
0.01µF
0.01µF
CHANNEL B
OUTPUT
0.01µF
0.01µF
8200pF
VPOS
Figure 50. Basic Connections
Rev. A | Page 17 of 28
AD8366
LC LOW-
PASS
FILTER
LC LOW-
PASS
FILTER
PAD
FILTER
BALUN
0
LO
MATCHING
NETWORK
RF
TO
90
ADC
ADF4350
ADL5523
ADL5523
LC LOW-
PASS
FILTER
LC LOW-
PASS
FILTER
ADL5380
Figure 51. Direct Conversion Receiver Block Diagram
AD8366
The image rejection ratio is the ratio of the intermediate frequency
(IF) signal level produced by the desired input frequency to that
produced by the image frequency. The image rejection ratio is
expressed in decibels (dB). Appropriate image rejection is critical
because the image power can be much higher than that of the
desired signal, thereby plaguing the downconversion process.
Amplitude and phase balance between the I/Q channels are
critical for high levels of image rejection. Image rejection of
greater than 47 dB was measured for the combined ADL5380
and the AD8366 for a 5 MHz baseband frequency, as seen in
Figure 53. This level of image rejection corresponds to a 0.5°
phase mismatch and a 0.05 dB of amplitude mismatch for the
combined ADL5380 and AD8366. Looking back to Figure 7 and
Figure 10, the AD8366 exhibits only 0.05 dB of amplitude mismatch
and 0.05o of phase mismatch, thus implying that the AD8366
does not introduce additional amplitude and phase imbalance.
55
DIRECT CONVERSION RECEIVER DESIGN
A direct conversion receiver directly demodulates an RF modulated
carrier to baseband frequencies, where the signals can be detected
and the conveyed information recovered. Eliminating the IF
stages and directly converting the signal to effectively zero IF
results in reduced component count. The image problems
associated with the traditional superheterodyne architectures
can be ignored as well. However, there are different challenges
associated with direct conversion that include LO leakage, dc
offsets, quadrature imperfections, and image rejection. LO
leakage causes self mixing that results in squaring of the LO
waveform which generates a dc offset that falls in band for the
direct conversion receiver. Residual dc offsets create a similar
interfering signal that falls in band. I/Q amplitude and phase
mismatch lead to degraded SNR performance and poor image
rejection in the direct conversion system. Figure 51 shows the
block diagram for a direct conversion receiver system.
QUADRATURE ERRORS AND IMAGE REJECTION
50
45
40
35
30
An overall RF-to-baseband EVM performance was measured
with the ADL5380 IQ demodulator preceding the AD8366, as
shown in Figure 56. In this setup, no LC low-pass filters were used
between the ADL5380 and AD8366. A 1900 MHz W-CDMA RF
signal with a 3.84 MHz symbol rate was used. The local oscillator
(LO) is set at 1900 MHz to obtain a zero IF baseband signal.
The gain of the AD8366 is set to maximum gain (~20.25 dB).
Figure 52 shows the SNR vs. the input power of the cascaded
system for a 5 MHz analysis bandwidth. The broad input power
range over which the system exhibits strong SNR performance
reflects the superior dynamic range of the AD8366.
45
25
900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
RF FREQUENCY (MHz)
Figure 53. Image Rejection vs. RF Frequency
40
35
30
25
20
15
10
5
0
–75
–65
–55
–45
–35
–25
–15
–5
5
INPUT POWER (dBm)
Figure 52. SNR vs. RF Input Power Level
Rev. A | Page 18 of 28
AD8366
–20
–30
–40
–50
–60
–70
–80
–90
LOW FREQUENCY IMD3 PERFORMANCE
GC63
GC0
To measure the IMD3 data at low frequencies, wideband
transformer baluns from North Hills Signal Processing Corp.
were used, specifically the 0301BB and the 0520BB. Figure 55
shows the IMD3 performance vs. frequency for a 2 V p-p
composite output. The IMD3 performance was also measured
for the combined ADL5380 and AD8366 system, as shown in
Figure 56, with an FFT spectrum analyzer. An FFT spectrum
analyzer works very similar to a typical ADC, the input signal
is digitized at a high sampling rate that is then passed through an
antialiasing filter. The resulting signal is transformed to the
frequency domain using fast Fourier transforms (FFT).
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
The single-ended RF signal from the source generator is converted
to a differential signal using a balun that gets demodulated and
down converted to differential IF signals through the ADL5380.
This differential IF signal drives the AD8366, thus eliminating
the need for low frequency baluns. Figure 54 shows the IMD3
performance vs. frequency over the 500 kHz to 5 MHz range
for minimum and maximum gain code setting on the AD8366.
During the measurements, the output was set to 2 V p-p composite.
FREQUENCY (MHz)
Figure 54. System IMD3 vs. Frequency, 2 V p-p Composite at
the Output of the AD8366
50
45
40
35
30
25
20
15
10
5
0
FREQUENCY = 1MHz
FREQUENCY = 3MHz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
0
5
10 15 20 25 30 35 40 45 50 55 60
GAIN CODE
Figure 55. OIP3 on Low Frequency, 2 V p-p Composite
Rev. A | Page 19 of 28
AD8366
RFIN
BALUN
100pF
100pF
V
VPOS
POS
0.1µF
100pF
24
23
22
21
20
19
1
2
3
4
5
6
18
17
16
15
GND
GND
GND
IHI
GND
QHI
ADL5380
QLO
ILO
GND 14
VCC
GND
VCC
V
POS
13
V
POS
0.1µF
100pF
100pF
0.1µF
7
8
9
10
11
12
100pF
100pF
BALUN
LO
V
V
POS
POS
V
POS
0.1µF
0.1µF
0.1µF
0.01µF
0.01µF
C
C
OFS
OFS
0.01µF
0.1µF
0.01µF
OFSB
CCMB
VCMB
VPSOB
OPPB
OPMB
OFSA
CCMA
VCMA
VPSOA
OPPA
AD8366
V
V
POS
POS
0.01µF
0.01µF
0.1µF
OPMA
200Ω
200Ω
Q CHANNEL
I CHANNEL
PARALLEL/SERIAL
CONTROL INTERFACE
Figure 56. ADL5380 and AD8366 Interface Block Diagram
Rev. A | Page 20 of 28
AD8366
The order and type of filter network depends on the desired high
frequency rejection required, pass-band ripple, and group delay.
BASEBAND INTERFACE
In most direct-conversion receiver designs, it is desirable to select a
wanted carrier within a specified band. The desired channel can be
demodulated by tuning the LO to the appropriate carrier frequency.
If the desired RF band contains multiple carriers of interest, the
adjacent carriers would also be down converted to a lower IF
frequency. These adjacent carriers can be a problem if they are
large relative to the desired carrier because they can overdrive
the baseband signal detection circuitry. As a result, it is often
necessary to insert a filter to provide sufficient rejection of the
adjacent carriers.
Figure 57 shows the schematic for a typical fourth-order, Chebyshev,
low-pass filter. Table 4 shows the typical values of the filter
components for a fourth-order, Chebyshev, low-pass filter with
a differential source impedance of 25 ꢀ and a differential load
impedance of 200 ꢀ.
L1
L3
C1
C2
Z
Z
SOURCE
LOAD
It is necessary to consider the overall source and load impedance
presented by the AD8366 and the ADC input to design the
filter network. The differential baseband output impedance of
the AD8366 is 25 Ω and is designed to drive a high impedance
ADC input. It may be desirable to terminate the ADC input down
to the lower impedance by using a terminating resistor, such as
500 Ω. The terminating resistor helps to better define the input
impedance at the ADC input at the cost of a slightly reduced gain.
L2
L4
Figure 57. Schematic of a Fourth-Order, Chebyshev, Low-Pass Filter
Table 4. Typical Values for Fourth-Order, Chebyshev, Low-Pass Filter
3 dB Corner (MHz)
ZSOURCE (Ω)
ZLOAD (Ω)
L1 (μH)
L2 (μH)
6.6
3.3
L3 (μH)
L4 (μH)
C1 (pF)
220
110
C2 (pF)
180
90
5
10
28
25
25
25
200
200
200
6.6
3.3
1.2
6.0
3
1
6.0
3
1
1.2
39
33
Rev. A | Page 21 of 28
AD8366
CHARACTERIZATION SETUPS
Figure 58 and Figure 59 are characterization setups used
extensively to characterize the AD8366. Characterization was
done on single-ended and differential evaluation boards. The
bulk of the characterization was done using an automated VEE
program to control the equipment as shown in Figure 58. This
setup was used to measure P1dB, OIP3, OIP2, IMD2, IMD3,
harmonic distortion, gain, gain error, supply current, and noise
density. All measurements were done with a 200 Ω load. All balun,
output matching network, and filter losses were de-embedded.
Gain error was measured with constant input power. All other
measurements were done on 2 V p-p (4 dBm, re: 200 Ω) on
the output of the device under test (DUT), and 2 V p-p composite
output for two-tone measurements. To measure harmonic
distortion, band-pass and band-reject filters were used on
the input and output of the DUT.
Figure 59 shows the setup used to make differential measurements.
All measurements on this setup were done in a 50 Ω system and
post processed to reference the measurements to a 200 Ω system.
Gain and phase mismatch were measured with 2 V p-p on the
output, and small signal frequency responses were measured
with −30 dBm on the input of the DUT.
Rev. A | Page 22 of 28
AD8366
AGILENT E8251D
SIGNAL GENERATOR
AGILENT E8251A
SIGNAL GENERATOR
AGILENT E4440A
SPECTRUM ANALYZER
COMBINER
RF SWITCH
MATRIX
KEITHLEY
IEEE
RF SWITCH
MATRIX
KEITHLEY
IEEE
BAND PASS
BAND REJECT
CH2
RF IN
CH1
RF IN
CH2
RF OUT
CH1
RF OUT
AD8366
EVALUATION BOARD
AGILENT E3631A POWER
SUPPLY
AGILENT 34401A DMM
(IN DC I MODE FOR SUPPLY
CURRENT MEASUREMENT)
AGILENT 34980A
MULTIFUNCTION SWITCH
(WITH 34950 AND 34921 MODULES)
Figure 58. Characterization Setup, Single-Ended Measurements
Rev. A | Page 23 of 28
AD8366
Rohde & Schwarz ZVA8
RF SWITCH
MATRIX
KEITHLEY
CH2
IP
CH2
IP
AD8366
EVALUATION BOARD
CH2
IM
CH2
IM
CH1
OP
CH1
OM
CH2
OP
CH2
OM
AGILENT E3631A
POWER SUPPLY
Figure 59. Characterization Setup, Differential Measurements
Rev. A | Page 24 of 28
AD8366
EVALUATION BOARD
The schematic for the AD8366 evaluation board is shown in Figure 60. The board can be used for single-ended or differential baseband
analysis. The default configuration of the board is for single-ended baseband analysis.
C26
T3
C27
T4
R39
R29
R38
R31
R35
R34
R37
R36
R30
R67
R33
R80
C24
C25
R71
R70
R69
R74
R73
R72
R65
R68
C33
C29
C31
OPMA
OPPA
VPSOA
VCMA
CCMA
OFSA
OPMB
OPPB
VPSOB
VCMB
CCMB
OFSB
C28
VPSO_A
VPSO_B
AD8366
VCMA
C9
VCMB
C10
S12
S11
C12
C3
C2
C11
VPSI_A
VPSI_B
C22
C15
C16
R54
R50
C20
R48 R63
R62
C5
R58
R45
R13
R44
R14
R46
R47
R15
T1
T2
C23
R16
R17
R20
R18
R21
R12
R19
C30
C13
C1
C14
C18
C21
S1
Figure 60. Evaluation Board Schematic
Rev. A | Page 25 of 28
AD8366
Figure 61. AD8366 Evaluation Board Printed Circuit Board (PCB), Top Side
Figure 62. AD8366 Evaluation Board PCB, Bottom Side
Table 5. Evaluation Board Configuration Options
Components
Function
Default Conditions
C1, C13 to C16, R3 to R6
Power supply decoupling. Nominal supply decoupling consists of a
0.1 μF capacitor to ground followed by 0.01 μF capacitors to ground
positioned as close to the device as possible.
C1 = 0.1 μF (size 0603),
C13 to C16 = 0.01 μF (size 0402),
R3 to R6 = 0 Ω (size 0603)
T1, T2, C5, C18, C20, C21,
R12 to R21, R44 to R48,
R50, R54, R58, R62, R63
Input interface. The default configuration of the evaluation board is
for single-ended operation. T1 and T2 are 4:1 impedance ratio baluns to
transform a 50 Ω single-ended input into a 200 Ω balanced differential
signal. R12 to R14 and R15, R16, and R19 are populated for appropriate
balun interface. R44 to R48 and R50, R54, R58, R62, and R63 are
provided for generic placement of matching components. C5, C18,
C20, and C21 are balun decoupling capacitors. R17, R18, R20, and
R21 can be populated with 0 Ω, and the balun interfacing resistors
can be removed to bypass T1 and T2 for differential interfacing.
T1, T2 = ADT4-6T+ (Mini-Circuits),
C5, C20 = 0.1 μF (size 0402),
C18, C21 = do not install,
R12 to R16, R19, R44 to R47 = 0 Ω
(size 0402),
R17, R18, R20, R21,R48, R50, R54,
R58, R62, and R63 = open (size 0402)
T3, T4, C24 to C27, R29 to
R31, R33 to R39, R65, R67
to R74, R80
Output interface. The default configuration of the evaluation board
is for single-ended operation. T3 and T4 are 4:1 impedance ratio
baluns to transform a 50 Ω single-ended output into a 200 Ω balanced
differential load. R29 to R31, R33, R38, and R39 are populated for
appropriate balun interface. R65, R67 to R74, and R80 are provided
for generic placement of matching components. C24, C25, C26, and
C27 are balun decoupling capacitors. R34 to R37 can be populated
with 0 Ω, and the balun interfacing resistors can be removed to
bypass T3 and T4 for differential interfacing.
T3, T4 = ADT4-6T+ (Mini-Circuits),
C24, C25 = 0.1 μF (size 0402),
C26, C27 = do not install,
R29 to R31, R33, R38, R39, R65, R67,
R68, R80 = 0 Ω (size 0402),
R34 to R37, R69 to R74 = open (size 0402)
Rev. A | Page 26 of 28
AD8366
Components
Function
Default Conditions
S1, S5, S7, R53, R57, R79,
C29, C30, C31
Enable interface includes device enable and data enable.
S1, S5, S7 = installed,
R53, R57 = 5.1 kΩ (size 0603),
R79 = 10 kΩ (size 0402),
C30 = 0.01 μF (size 0402),
C29, C31 = 1500 pF (size 0402)
Device enable. The AD8366 is enabled by applying a logic high
voltage to the ENBL pin. The device is enabled when the S1 switch is
set in the down position (high), connecting the ENBL pin to VPSI_A.
Data enable. DENA and DENB are used to enable the data path for
Channel A and Channel B, respectively. Channel A is enabled when
the S5 switch is set in the down position (high), connecting the DENA
pin to VPSI_A. Likewise, Channel B is enabled when the S7 switch is
set in the down position (high), connecting the DENB pin to VPSI_A.
Both channels are disabled by setting the switches to the up position,
connecting the DENA and DENB pins to GND.
S2, S3, S4, S6, S8, S9, S10
R26, R32, R40 to R43, R61, either in parallel or serial mode. The parallel interface is enabled when
Serial/parallel interface control. SENB is used to set the data control
S2, S3, S4, S6, S8, S9, S10 = installed,
R26 = 698 kΩ (size 0603),
R64, C23, C33, U1
S4 is in the up position (low). The serial interface is enabled when S4
is in the down position (high).
R32, R40 to R43, R61, R64 = 5.1 kΩ
(size 0603),
C23, C33 = 1500 pF (size 0603),
U1 = SN74LVC2G14 inverter chip
For SENB pulled low, BIT0 (S9) sets 0.25 dB gain, BIT1 (S2) sets 0.5 dB
gain, BIT2 (S3) sets 1 dB gain, BIT3 (S6) sets 2 dB gain, BIT4 (S8) sets
4 dB gain, and BIT5 (S10) sets 8 dB gain.
For SENB pulled high, BIT0 becomes a chip select (CS), BIT1 becomes
a serial data input (SDAT), and BIT2 becomes serial clock (SCLK). BIT3 to
BIT5 are not used in serial mode. U1 is used to deglitch the SCLK signal.
S11, S12, C9, C10
DC offset correction loop compensation.
S11, S12 = installed,
C9, C10 = 8200 pF (size 0402)
The dc offset correction loop is enabled (high) with S11 and S12 for
Channel A and Channel B, respectively, when the enabled pins, OFSA/
OFSB, are connected to ground through the C9 and C10 capacitors.
When disabled (low), OFSA/OFSB are connected to ground directly.
R10, R22, R24, R28, C22,
C28
Output common-mode setpoint. The output common mode on
Channel A and Channel B can be set externally when applied to
VCMA and VCMB. The resistive change through the potentiometer
sets a variable VCMA voltage. If left open, the output common mode
defaults to VPOS/2.
R10, R24 = 10 kΩ potentiometers,
R22, R28 = 0 Ω,
C22, C28 = 0.1 μF (size 0402)
C2, C3, C11, C12
Reference output decoupling capacitor to circuit common.
C2, C3 = 0.1 μF (size 0402),
C11, C12 = 0.01 μF (size 0402)
Rev. A | Page 27 of 28
AD8366
OUTLINE DIMENSIONS
5.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
25
32
1
24
0.50
BSC
PIN 1
INDICATOR
TOP
VIEW
2.85
2.70 SQ
2.55
EXPOSED
PAD
(BOTTOM VIEW)
4.75
BSC SQ
0.50
0.40
0.30
17
16
8
9
0.20 MIN
3.50 REF
0.80 MAX
1.00
0.85
0.80
12° MAX
0.65 TYP
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
0.30
0.25
0.18
SEATING
PLANE
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 63. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-32-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
AD8366ACPZ-R7
AD8366-EVALZ
−40°C to +85°C
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Evaluation Board
CP-32-8
1 Z = RoHS Compliant Part.
©2010-2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07584-0-3/11(A)
Rev. A | Page 28 of 28
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