AD8375 [ADI]
24dB Range, 1dB Step Size Programmable VGA; 24分贝范围， 1dB步进尺寸可编程VGA
| 型号： | AD8375 |
| 厂家： | 
ADI |
| 描述： | 24dB Range, 1dB Step Size Programmable VGA |
| 文件： | 总6页 (文件大小：240K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
24dB Range, 1dB Step Size Programmable
VGA
Preliminary Technical Data
AD8375
FEATURES
-4 to 20dB Gain Range
FUNCTIONAL BLOCK DIAGRAM
1 dB Step Size ± 0.2 dB
Differential input and output
150 Ω Differential Input
Open Collector Differential Output
8dB noise figure @ maximum gain
OIP3 of ~50dBm at 140MHz
−3 dB bandwidth of 690 MHz
Parallel 5-bit Control Interface
Wide input dynamic range
Power-down feature
Single 5V Supply Operation
24 Lead LFCSP 4 x 4 mm Package
APPLICATIONS
Differential ADC drivers
High IF Sampling Receivers
High Output Power IF Amplification
Instrumentation
Figure 1.
GENERAL DESCRIPTION
The AD8375 is a digitally controlled, variable gain wide
bandwidth amplifier that provides precise gain control, high IP3
and low noise figure. The excellent distortion performance and
high signal bandwidth makes the AD8375 an excellent gain
control device for a variety of receiver applications.
Using a high speed SiGe process and incorporating proprietary
distortion cancellation techniques, the AD8375 achieves
50 dBm output IP3 at 140 MHz.
The AD8375 is powered on by applying the appropriate logic
level to the PWUP pin. The quiescent current of the AD8375 is
typically 130mA. When powered down, the AD8375 consumes
less than 5mA and offers excellent input to output isolation. The
gain setting is preserved when powered down.
For wide input dynamic range applications, the AD8375 pro-
vides a broad 24dB gain range with 1 dB resolution. The gain is
adjusted through a 5-pin control interface and can be driven
using standard TTL levels. The open-collector outputs provide a
flexible interface, allowing the overall signal gain to be set by
the loading resistance. The AD8375 offers a maximum trans-
conductance gain of 67 mΩ-1’s, resulting in a signal gain of 20dB
when driving a 150-Ohm load. The maximum signal gain
increases to ~24dB when driving a 250-Ohm differential load.
Fabricated on an ADI’s high speed SiGe process, the AD8375
provides precise gain adjustment capabilities with good distortion
performance. The AD8375 amplifier comes in a compact,
thermally enhanced 4 x 4mm 24-lead LFCSP package and
operates over the temperature range of −40°C to +85°C.
Rev. PrB
March 13, 2007
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2007 Analog Devices, Inc. All rights reserved.
AD8375
Preliminary Technical Data
SPECIFICATIONS
VS = 5 V, T = 25°C, ZS = ZL = 150Ω at 100MHz, 2 V p-p differential output unless otherwise noted.
Table 1.
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Slew Rate
VOUT < 2 V p-p (5.2dBm)
690
MHz
TBD
V/nsec
INPUT STAGE
Pins VIN+ and VIN-
For linear operation (AV = 0dB)
Differential
Maximum Input Swing
Differential Input Resistance
Common-Mode Input Voltage
CMRR
TBD
150
2
V p-p
Ω
V
Gain Code = 00000
TBD
dB
GAIN
Ω-1
Amplifier Transconductance
0.58
0.067 0.076
Maximum Voltage Gain
Gain Code = 00000
dB
20
Minimum Voltage Gain
Gain Step Size
−4
dB
dB
Gain Code ≥11000
-5.5
0.8
-2.5
From Gain Code 00000 to 11000
1.2
1.0
Gain Flatness
Gain Code = 00000 over 20% fractional
bandwidth for fC < 200MHz
dB
TBD
Gain Temperature Sensitivity
Gain Step Response
Gain Code = 00000
mdB/°C
TBD
TBD
For VIN = 0.2V, Gain Code 10100 to 00000
ns
OUTPUT STAGE
Pins OUT+ and OUT-
At P1dB, Gain Code = 00000
Differential
Output Voltage Swing
Output impedance
10
V p-p
Ω/pF
5k//1
NOISE/HARMONIC PERFORMANCE
46 MHz
Gain Code = 00000
Noise Figure
8.5
-94
-92
50
dB
Second Harmonic
Third Harmonic
VOUT = 2 V p-p
dBc
dBc
dBm
dBm
VOUT = 2 V p-p
Output IP3
Output 1 dB Compression Point
2 MHz spacing, +3 dBm per tone
19
70 MHz
Gain Code = 00000
Noise Figure
8.5
-94
-92
50
19
dB
Second Harmonic
Third Harmonic
Output IP3
Output 1 dB Compression Point
140 MHz
VOUT = 2 V p-p
VOUT = 2 V p-p
2 MHz spacing, +3 dBm per tone
dBc
dBc
dBm
dBm
Gain Code = 00000
Noise Figure
8.5
-86
-91
50
dB
Second Harmonic
Third Harmonic
Output IP3
VOUT = 2 V p-p
VOUT = 2 V p-p
2 MHz spacing, +3 dBm per tone
dBc
dBc
dBm
dBm
Output 1 dB Compression Point
19
Rev. PrB | Page 2 of 6
Preliminary Technical Data
AD8375
Parameter
Conditions
Min
Typ
Max
Unit
200 MHz
Gain Code = 00000
Noise Figure
8.5
-85
-88
50
dB
Second Harmonic
Third Harmonic
Output IP3
VOUT = 2 V p-p
VOUT = 2 V p-p
2 MHz spacing, +3 dBm per tone
dBc
dBc
dBm
dBm
Output 1 dB Compression Point
POWER-INTERFACE
Supply Voltage
18
4.5
5.5
V
thermal connection made to exposed paddle
under device
Quiescent Current per Channel
130
3
140
165
mA
vs. Temperature
Power Down Current
vs. Temperature
−40°C ≤ TA ≤ +85°C
PWUP Low
−40°C ≤TA ≤ +85°C
mA
mA
mA
TBD
1.6
ENABLE INTERFACE
Enable Threshold
PWUP Input Bias Current
GAIN CONTROL INTERFACE
VIH
Pin PWUP
Minimum voltage to enable the device
V
nA
0.5
Pins A0, A1, A2, A3, A4
Minimum voltage for a logic high
Maximum voltage for a logic low
V
1.6
VIL
0.8
Maximum Input Bias Current
900
nA
Table 2. Gain-Code versus Voltage Gain Look-Up Table
5-Bit Binary Gain Code
Voltage Gain (dB)
5-Bit Binary Gain Code
Voltage Gain (dB)
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
20
19
18
17
16
15
14
13
12
11
10
9
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
7
6
5
4
3
2
1
0
-1
-2
-3
-4
-4
01100
8
>11000
Rev. PrB | Page 3 of 6
AD8375
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
Supply Voltage, VPOS
5.5 V
PWUP, A0, A1, A2, A3, A4
Input Voltage, VIN+ ,VIN-
Internal Power Dissipation
θJA (Exposed paddle soldered down)
θJA (Exposed paddle not soldered down) TBD°C/W
θJC (At exposed paddle)
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature Range
(Soldering 60 sec)
-0.6 to (VPOS + 0.6V)
-0.6 to +3.1V
TBD mW
TBD°C/W
Stresses above those listed under Absolute Maximum
Ratings may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device at these or any other conditions above those
listed in the operational sections of this specification is
not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
TBD°C/W
TBD°C
–40°C to +85°C
–65°C to +150°C
TBD°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrB | Page 4 of 6
Preliminary Technical Data
AD8375
PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
Figure 2. 24 Lead LFCSP
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
VCOM
VIN+
VIN-
A4
A3
A2
A1
A0
Description
1
2
3
4
5
6
7
8
Common Mode Pin. Typically bypassed to ground using external capacitor.
Voltage Input Positive.
Voltage Input Negative.
The Most Significant Bit (MSB) for the 5-bit Gain Control Interface.
MSB-1 for the Gain Control Interface.
MSB-2 for the Gain Control Interface.
LSB+1 for the Gain Control Interface.
The Least Significant Bit (LSB) for the 5-bit Gain Control Interface.
Positive Supply Pins. Should be bypassed to Ground using suitable bypass capacitor.
9, 10,12, 13,
23
VPOS
11, 14, 20,
21, 22, 24
COMM
Device Common (DC Ground).
15, 17
16, 18
19
VOUT+
VOUT-
PWUP
Positive Ouptut Pins (Open Collector). Require DC bias of +5V nominal.
Negative Ouptut Pins (Open Collector). Require DC bias of +5V nominal.
Chip Enable Pin.
Rev. PrB | Page 5 of 6
AD8375
Preliminary Technical Data
OUTLINE DIMENSIONS
Figure2. 24-Lead LFCSP)
ORDERING GUIDE
Model
Temperature
Package Description
Package Option
AD8375ACPZ-WP
Waffle Pack, 24 Lead Frame Chip Scale
Package
CP-24
–40°C to +85°C
AD8375ACPZ-REEL7
AD8375-EVALZ
7” Reel, 24 Lead Frame Chip Scale Package
Evaluation Board
CP-24
–40°C to +85°C
©
2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR06724-0-3/07(PrB)
Rev. PrB | Page 6 of 6
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