AD8390ACP-EVAL [ADI]
Low Power, High Output Current Differential Amplifier; 低功耗，高输出电流差动放大器
| 型号： | AD8390ACP-EVAL |
| 厂家： | 
ADI |
| 描述： | Low Power, High Output Current Differential Amplifier |
| 文件： | 总16页 (文件大小：674K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Power, High Output Current
Differential Amplifier
AD8390
FEATURES
PIN CONFIGURATIONS
Voltage feedback amplifier
Ideal for ADSL and ADSL2+ central office (CO) and
customer premises equipment (CPE) applications
Enables high current differential applications
Low power operation
Single- or dual-power supply operation from 10 V ( 5 V)
up to 24 V ( 12 V)
NC
16
V
NC
NC
13
OCM
1
12
–OUT
+IN
PWDN1
PWDN0
V
EE
CC
V
4 mA total quiescent supply current for full power ADSL
and ADSL2+ CO applications
–IN 4
9
+OUT
Adjustable supply current to minimize power
consumption
High output voltage and current drive
400 mA peak output drive current
44.2 V p-p differential output voltage
Low distortion
5
8
NC
NC DGND
I
ADJ
NC = NO CONNECT
Figure 1. 4 mm × 4 mm 16-Lead LFCSP
–82 dBc @ 1 MHz second harmonic
–91 dBc @ 1 MHz third harmonic
High speed: 300 V/µs differential slew rate
1
16
NC
V
OCM
NC
–OUT
NC
APPLICATIONS
+IN
ADSL/ADSL2+ CO and CPE line drivers
xDSL line driver
High current differential amplifiers
PWDN1
PWDN0
–IN
V
V
EE
CC
GENERAL DESCRIPTION
NC
The AD8390 is a high output current, low power consumption
differential amplifier. It is particularly well suited for the central
office (CO) driver interface in digital subscriber line systems
such as ADSL and ADSL2+. While in full bias operation, the
driver is capable of providing 24.4 dBm output power into low
resistance loads. This is enough to power a 20.4 dBm line while
compensating for losses due to hybrid insertion, transformer
insertion, and back termination resistors.
NC
+OUT
8
9
DGND
I
ADJ
NC = NO CONNECT
Figure 2. 16-Lead QSOP/EP
The low power consumption, high output current, high output
voltage swing, and robust thermal packaging enable the AD8390
to be used as the central office line driver in ADSL, ADSL2+,
and proprietary xDSL systems, as well as in other high current
applications requiring a differential amplifier.
The AD8390 fully differential amplifier is available in a ther-
mally enhanced lead frame chip scale package (LFCSP-16) and
a 16-lead QSOP/EP. Significant control and flexibility in bias
current have been designed into the AD8390. The four power
modes are controlled by two digital bits, PWDN (1,0) which
provide three levels of driver bias and one powered-down state.
In addition, the IADJ pin can be used for fine quiescent current
trimming to tailor the performance of
the AD8390.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
AD8390
TABLE OF CONTENTS
Specifications..................................................................................... 3
Setting the Output Common-Mode Voltage .......................... 10
Power-Down Features and the IADJ Pin ................................... 10
PWDN Pins............................................................................. 10
ADSL and ADSL2+ Applications......................................... 10
ADSL and ADSL2+ Applications Circuit............................ 10
Multitone Power Ratio (MTPR)............................................... 11
Layout, Grounding, and Bypassing .......................................... 12
Power Dissipation and Thermal Management....................... 12
Outline Dimensions....................................................................... 13
Ordering Guide .......................................................................... 13
Absolute Maximum Ratings............................................................ 5
Typical Thermal Properties............................................................. 5
ESD Caution.................................................................................. 5
Typical Performance Characteristics ............................................. 6
Theory of Operation ........................................................................ 9
Applications....................................................................................... 9
Circuit Definitions ....................................................................... 9
Analyzing a Basic Application Circuit....................................... 9
Setting the Closed-Loop Gain .................................................... 9
Calculating Input Impedance ..................................................... 9
REVISION HISTORY
9/04–Data Sheet Changed from Rev. B to Rev. C
Change to Ordering Guide............................................................ 16
2/04–Data Sheet Changed from Rev. A to Rev. B.
Changed pub code.......................................................................... 16
1/04–Data sheet changed from Rev. Sp0f to Rev. A.
Added detailed description of product............................Universal
Updated Outline Dimensions....................................................... 13
Rev. C | Page 2 of 16
AD8390
SPECIFICATIONS
VS = 12 V or +24 V, RL = 100 Ω, G = 10, PWDN = (1,1), IADJ = NC, VOCM = float, TA = 25°C, unless otherwise noted.1, 2
Table 1.
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth
Large Signal Bandwidth
Peaking
VOUT = 0.2 V p-p, RF = 10 kΩ
VOUT = 4 V p-p
VOUT = 0.2 V p-p
40
25
60
40
0.1
300
MHz
MHz
dB
Slew Rate
VOUT = 4 V p-p
V/µs
NOISE/DISTORTION PERFORMANCE
Second Harmonic Distortion
Third Harmonic Distortion
Multitone Power Ratio (26 kHz to 1.1 MHz)
–82
–91
–70
dBc
dBc
dBc
fC = 1 MHz, VOUT = 2 V p-p
fC = 1 MHz, VOUT = 2 V p-p
ZLINE = 100 Ω, PLINE = 19.8 dBm,
crest factor (CF) = 5.4
Multitone Power Ratio (26 kHz to 2.2 MHz)
ZLINE = 100 Ω, PLINE = 19.8 dBm,
crest factor (CF) = 5.4
–65
dBc
Voltage Noise (RTI)
Input Current Noise
f = 10 kHz
f = 10 kHz
8
1
nV/√Hz
pA/√Hz
INPUT CHARACTERISTICS
RTI Offset Voltage (VOS,DM(RTI)
RTI Offset Voltage (VOS,DM(RTI)
Input Bias Current
Input Offset Current
Input Resistance
)
)
V+IN – V–IN, VOCM = midsupply
V+IN – V–IN, VOCM = float
–3.0
–3.0
1.0
1.0
–4.0
0.05
400
2
+3.0
+3.0
–7.0
mV
mV
µA
µA
kΩ
pF
–0.35
+0.35
Input Capacitance
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Differential Output Voltage Swing
Output Balance Error
(∆VOS,DM(RTI))/(∆VIN,CM
)
58
64
dB
∆VOUT
(∆VOS,CM)/∆VOUT
RL = 10 Ω, fC = 100 kHz
43.8
44.2
60
400
44.6
V
dB
mA
Linear Output Current
Worst harmonic = –60 dBc
(V+OUT + V–OUT)/2, VOCM = midsupply
(V+OUT + V–OUT)/2, VOCM = float
Output Common-Mode Offset
Output Common-Mode Offset
POWER SUPPLY
–75
–75
35
35
+75
+75
mV
mV
Operating Range (Dual Supply)
Operating Range (Single Supply)
Total Quiescent Current
5
+10
12
+24
6.5
5.0
3.5
1.0
11.0
8.0
5.0
1.0
V
V
PWDN1, PWDN0 = (1,1); IADJ = VEE
(1,0); IADJ = VEE
(0,1); IADJ = VEE
(0,0); IADJ = VEE
PWDN1, PWDN0 = (1,1); IADJ = NC
(1,0); IADJ = NC
(0,1); IADJ = NC
(0,0); IADJ = NC
∆VOS,DM/∆VS, ∆VS = 1 V, VOCM = midsupply
5.2
3.8
2.5
0.57
10.0
6.7
3.8
0.67
76
mA
mA
mA
mA
mA
mA
mA
mA
dB
V
Total Quiescent Current
Power Supply Rejection Ratio (PSRR)
PWDN = 0 (Low Logic State)
PWDN = 1 (High Logic State)
VOCM TO VOUT SPECIFICATIONS
Input Voltage Range
70
1.0
1.6
V
–11.0 to +10.0
V
Input Resistance
VOCM Accuracy
28
1.0
kΩ
V/V
∆VOUT,CM/∆VOCM
0.996
1.004
1 VOCM bypassed with 0.1 µF capacitor.
2 See Figure 3.
Rev. C | Page 3 of 16
AD8390
VS = 5 V or +10 V, RL = 100 Ω, G = 10, PWDN = (1,1), IADJ = NC, VOCM = float, TA = 25°C, unless otherwise noted.1, 2
Table 2.
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth
Large Signal Bandwidth
Peaking
VOUT = 0.2 V p-p, RF = 10 kΩ, G = 10
VOUT = 4 V p-p
VOUT = 0.2 V p-p
40
25
60
40
0.1
300
MHz
MHz
dB
Slew Rate
VOUT = 4 V p-p
V/µs
NOISE/DISTORTION PERFORMANCE
Second Harmonic Distortion
Third Harmonic Distortion
Voltage Noise (RTI)
fC = 1 MHz, VOUT = 2 V p-p
fC = 1 MHz, VOUT = 2 V p-p
f = 10 kHz
–82
–91
8
dBc
dBc
nV/√Hz
pA/√Hz
Input Current Noise
f = 10 kHz
1
INPUT CHARACTERISTICS
RTI Offset Voltage (VOS,DM(RTI)
RTI Offset Voltage (VOS,DM(RTI)
Input Bias Current
Input Offset Current
Input Resistance
)
)
V+IN – V–IN, VOCM = midsupply
V+IN – V–IN, VOCM = float
–3.0
–3.0
1.0
1.0
–4.0
0.05
400
2
+3.0
+3.0
–7.0
mV
mV
µA
µA
kΩ
pF
–0.35
+0.35
Input Capacitance
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Differential Output Voltage Swing
Output Balance Error
(∆VOS,DM(RTI))/(∆VIN,CM
)
58
64
dB
∆VOUT
(∆VOS,CM)/∆VOUT
RL = 10 Ω, fC = 100 kHz
16.0
16.4
60
400
16.8
V
dB
mA
Linear Output Current
Worst harmonic = –60 dBc
(V+OUT + V–OUT)/2, VOCM = midsupply
(V+OUT + V–OUT)/2, VOCM = float
–75
–75
Output Common-Mode Offset
Output Common-Mode Offset
POWER SUPPLY
35
35
+75
+75
mV
mV
Operating Range (Dual Supply)
Operating Range (Single Supply)
Total Quiescent Current
5
+10
12
+24
5.5
4.0
3.0
1.0
10.0
7.0
4.0
1.0
V
V
PWDN1, PWDN0 = (1,1); IADJ = VEE
(1,0); IADJ = VEE
(0,1); IADJ = VEE
(0,0); IADJ = VEE
PWDN1, PWDN0 = (1,1); IADJ = NC
(1,0); IADJ = NC
(0,1); IADJ = NC
(0,0); IADJ = NC
∆VOS,DM/∆VS, ∆VS = 1 V, VOCM = midsupply
4.5
3.3
2.1
0.43
8.7
5.8
3.3
0.55
76
mA
mA
mA
mA
mA
mA
mA
mA
dB
V
Total Quiescent Current
Power Supply Rejection Ratio
PWDN = 0 (Low Logic State)
PWDN = 1 (High Logic State)
VOCM TO VOUT SPECIFICATIONS
Input Voltage Range
70
1.0
1.6
V
–4.0 to +3.0
V
Input Resistance
VOCM Accuracy
28
1.0
kΩ
V/V
∆VOUT,CM/∆VOCM
0.996
1.004
1 VOCM bypassed with 0.1 µF capacitor.
2 See Figure 3.
Rev. C | Page 4 of 16
AD8390
ABSOLUTE MAXIMUM RATINGS
TYPICAL THERMAL PROPERTIES
Table 3.
Table 4.
Parameter
Rating
Package
Typical Thermal Resistance (θJA)
Supply Voltage
VOCM
13.2 V (26.4 V)
VEE < VOCM < VCC
(TJ MAX – TA)/θJA
150°C
–40°C to +85°C
–65°C to +150°C
300°C
16-lead LFCSP (CP-16)
JEDEC 2S2P – 0 airflow
Paddle soldered to board
Nine thermal vias in pad
30.4°C/W
Package Power Dissipation
Maximum Junction Temperature (TJ MAX
Operating Temperature Range (TA)
Storage Temperature Range
Lead Temperature (Soldering 10 s)
)
16-lead QSOP/EP (RC-16)
JEDEC 1S2P – 0 airflow
Paddle soldered to board
Nine thermal vias in pad
44.3°C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
R
= 10kΩ
F
49.9Ω
R
= 1kΩ
= 1kΩ
G
V
V
OUT,DM
IN
AD8390
R
= 100Ω
L,DM
R
G
49.9Ω
R
= 10kΩ
F
Figure 3. Basic Test Circuit
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. C | Page 5 of 16
AD8390
TYPICAL PERFORMANCE CHARACTERISTICS
Default Conditions: VS = 12 V or +24 V, RL = 100 Ω, G = 10, PWDN = (1,1), IADJ = NC, VOCM = float (bypassed with 0.1 μF capacitor),
TA = 25°C, unless otherwise noted. See Figure 3.
25
20
15
10
5
30
25
20
15
10
5
PWDN(0,1); I
= V
EE
PWDN(1,0); I
PWDN(1,1); I
PWDN(1,0); I
= V
= V
PWDN(1,0); I
= V
EE
ADJ
ADJ
ADJ
ADJ
EE
EE
ADJ
PWDN(1,1); I
= V
EE
ADJ
PWDN(0,1); I
= V
EE
ADJ
= NC
PWDN(0,1); I
= NC
ADJ
PWDN(1,1); I
= NC
ADJ
PWDN(0,1); I
= NC
ADJ
PWDN(1,0); I
= NC
ADJ
0
0
PWDN(1,1); I
= NC
ADJ
–5
–10
–5
–10
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 7. Small Signal Frequency Response;
VS = 5 V, Gain = 5, VOUT = 200 mV p-p
Figure 4. Small Signal Frequency Response;
VS = 12 V, Gain = 10, VOUT = 200 mV p-p
25
25
20
15
10
5
PWDN(1,0); I
ADJ
= V
EE
PWDN(0,1); I
ADJ
= V
EE
20
15
10
5
PWDN(1,1); I
ADJ
= V
EE
PWDN(1,0); I
PWDN(1,1); I
= V
= V
ADJ
EE
PWDN(1,0); I
PWDN(1,1); I
= NC
= NC
ADJ
ADJ
EE
PWDN(0,1); I
ADJ
= V
EE
ADJ
PWDN(0,1); I
ADJ
= NC
PWDN(0,1); I
ADJ
= NC
PWDN(1,0); I
= NC
= NC
ADJ
0
0
PWDN(1,1); I
ADJ
–5
–10
–5
–10
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 5. Large Signal Frequency Response;
VS = 12 V, Gain = 10, VOUT = 4 V p-p
Figure 8. Large Signal Frequency Response;
VS = 5 V, Gain = 5, VOUT = 2 V p-p
100
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
–65
–70
–75
10
1
0.1
0.01
0.001
0.01
0.1
1
10
100
1
10
100
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 9. Output Impedance vs. Frequency; PWDN = (1,1)
Figure 6. Signal Feedthrough; PWDN = (0,0)
Rev. C | Page 6 of 16
AD8390
–50
–55
–60
–65
–70
–75
–45
–50
–55
–60
–65
–70
CREST FACTOR = 5.4
= V
PWDN(0,1); I
= V
EE
ADJ
CREST FACTOR = 5.4
PWDN(0,1); I
ADJ
EE
PWDN(1,0); I
ADJ
= V
EE
PWDN(0,1); I
ADJ
= NC
PWDN(1,0); I
ADJ
= V
EE
PWDN(0,1); I
ADJ
= NC
PWDN(1,1); I
= V
EE
ADJ
PWDN(1,1); I
= NC
= V
EE
ADJ
PWDN(1,0); I
ADJ
PWDN(1,1); I
= NC
= NC
ADJ
PWDN(1,0); I
ADJ
PWDN(1,1); I
18
= NC
ADJ
12
14
16
20
22
12
14
16
18
20
22
OUTPUT POWER (dBm)
OUTPUT POWER (dBm)
Figure 10. MTPR vs. Output Power;
970 kHz Empty Bin (26 kHz to 1.1 MHz)
Figure 13. MTPR vs. Output Power;
1.75 MHz Empty Bin (26 kHz to 2.2 MHz)
900
800
700
600
500
400
300
50
45
40
35
30
25
20
15
10
5
CREST FACTOR = 5.4
V
= ±12V
S
PWDN(1,1); I
= NC
ADJ
PWDN(1,0); I
= NC
ADJ
PWDN(1,1); I
ADJ
= V
EE
PWDN(0,1); I
= NC
ADJ
V
= ±5V
S
PWDN(1,0); I
ADJ
= V
EE
PWDN(0,1); I
ADJ
= V
EE
0
10
20
30
40
50
60
70
80
90
100
12
14
16
18
20
22
R
(Ω)
OUTPUT POWER (dBm)
LOAD
Figure 11. Power Consumption vs. Output Power
(Includes Output Power Delivered to Load)
Figure 14. Differential Output Swing vs. RLOAD
–50
–55
–60
–65
–70
–75
–80
–85
–90
–50
–55
–60
–65
–70
–75
–80
–85
–90
PWDN(0,1); I
= V
EE
ADJ
PWDN(0,1); I
= V
EE
ADJ
PWDN(0,1); I
= NC
ADJ
PWDN(0,1); I
ADJ
= NC
PWDN(1,1); I
PWDN(1,0); I
= NC
PWDN(1,1); I
PWDN(1,0); I
= NC
ADJ
ADJ
= NC
= NC
EE
ADJ
= V
ADJ
= V
PWDN(1,1); I
PWDN(1,1); I
PWDN(1,0); I
ADJ
= V
ADJ
EE
PWDN(1,0); I
= V
ADJ
EE
ADJ
EE
0.1
1
10
0.1
1
10
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 15. Total Harmonic Distortion vs. Frequency;
VS = 5 V, VOUT = 2 V p-p
Figure 12. Total Harmonic Distortion vs. Frequency;
VS = 12 V, VOUT = 2 V p-p
Rev. C | Page 7 of 16
AD8390
11
10
9
9
8
7
6
5
4
3
2
1
PWDN(1,1)
8
PWDN(1,1)
PWDN(1,0)
PWDN(0,1)
7
6
5
PWDN(1,0)
4
PWDN(0,1)
3
2
1
10
100
1k
10k
100k
1M
1
10
100
1k
10k
100k
1M
I
SERIES RESISTOR (Ω)
I
SERIES RESISTOR (Ω)
ADJ
ADJ
Figure 16. Quiescent Current vs. IADJ Resistor; VS = 12 V
Figure 19. Quiescent Current vs. IADJ Resistor; VS = 5 V
3
2
5.5
4.5
3.5
2.5
1.5
0.5
–0.5
3
2
5.5
4.5
3.5
2.5
1.5
0.5
–0.5
PWDN PINS
1
1
OUTPUT
OUTPUT
0
0
–1
–2
–3
–1
–2
–3
PWDN PINS
–2
0
2
4
6
8
10
–0.2 –0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
TIME (µs)
TIME (µs)
Figure 20. Power-Down Time;
PWDN = (1,1) to PWDN = (0,0)
Figure 17. Power-Up Time;
PWDN = (0,0) to PWDN = (1,1)
100
10
1
100
10
1.0
0.1
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 18. Voltage Noise (RTI)
Figure 21. Current Noise (RTI)
Rev. C | Page 8 of 16
AD8390
THEORY OF OPERATION
APPLICATIONS
CIRCUIT DEFINITIONS
R
F
Differential voltage refers to the difference between two node
voltages. For example, the output differential voltage (or output
differential-mode voltage) is defined as
V
CC
A
R
G
+IN
–OUT
I
ADJ
50kΩ
50kΩ
56kΩ
PWDN0
PWDN1
DGND
R
ADJ
C
VOUT,DM
=
V+OUT −V−OUT
)
(1)
V
EE
V
OCM
BYP
B
V+OUT and V–OUT refer to the voltages at the +OUT and –OUT
56kΩ
+OUT
terminals with respect to a common reference.
–IN
R
G
V
AD8390
EE
Common-mode voltage refers to the average of the two node
voltages. The output common-mode voltage is defined as
R
F
V+OUT +V−OUT
Figure 22. Functional Block Diagram
VOUT ,CM
=
(2)
2
The AD8390 is a true differential operational amplifier with
common-mode feedback. The AD8390 is functionally equivalent
to three op amps, as shown in Figure 22. Amplifiers A and B act
like a standard dual op amp in an inverting configuration that
requires four resistors to set the desired gain.
ANALYZING A BASIC APPLICATION CIRCUIT
The AD8390 uses high open-loop gain and negative feedback to
force its differential and common-mode output voltages in such
a way as to minimize the differential and common-mode error
voltages. The differential error voltage is defined as the voltage
between the differential inputs +IN and –IN, as shown in
Figure 23. For most purposes, this voltage can be assumed to be
zero. Similarly, the difference between the actual output
common-mode voltage and the voltage applied to VOCM can also
be assumed to be zero. Starting from these two assumptions, any
application circuit can be analyzed.
The third amplifier (C) maintains the common-mode voltage
(VOCM) at the output of the AD8390. VOCM is internally
generated, as shown in Figure 22. The common-mode feedback
amplifier (C) drives the noninverting terminals of A and B such
that the difference between the output common-mode voltage
and VOCM is always zero. This functionality forces the outputs to
sit at midsupply, which results in differential outputs of identical
amplitude and 180 degrees out of phase. The user also has the
option to externally drive the VOCM pin as an input to set the dc
output common-mode voltage. For details, see the Setting the
Output Common-Mode Voltage section.
R
F
R
G
+IN
–IN
–OUT
+OUT
+
–
V
IN,DM
V
R
V
OCM
L,DM
OUT,DM
+
R
G
–
R
F
Figure 23. Basic Applications Circuit
(IADJ Pin Not Connected, and PWDN0 and PWDN1 Held High)
SETTING THE CLOSED-LOOP GAIN
The differential-mode gain of the circuit in Figure 23 can be
described by
VOUT,DM
RF
RG
=
(3)
(4)
VIN,DM
CALCULATING INPUT IMPEDANCE
The input impedance of the circuit in Figure 23 between the
inputs (V+IN and V−IN) is simply
RIN,DM = 2 × RG
Rev. C | Page 9 of 16
AD8390
When IADJ is not connected, the bias current in the various
power modes is set to approximately 10 mA, 6.7 mA, and
3.8 mA for power modes PWDN1,0 = (1,1), (1,0), and (0,1),
respectively, as seen in Table 5. Setting IADJ = VEE for dual-supply
operation (or grounding the IADJ pin for single-supply opera-
tion) cuts the bias setting approximately in half for each mode.
SETTING THE OUTPUT COMMON-MODE VOLTAGE
By design, the AD8390’s VOCM pin is internally biased at a
voltage equal to the midsupply point (average value of the
voltages on VCC and VEE), eliminating the need for external
resistors. The high impedance nature of the VOCM pin, however,
allows the designer to force it to a desired level with an external
low impedance source. It should be noted that the VOCM pin is
not intended for use as an ac signal input.
A resistor (RADJ) between IADJ and ground for single-supply
operation, or IADJ and VEE for dual-supply operation, allows fine
bias adjustment between the bias levels preset by the PWDN
pins. Figure 16 and Figure 19 depict the effect of different RADJ
values on setting the bias levels.
The three configurations for the VOCM pin are floating with a
single supply, floating with dual supplies, and forcing the pin
with an external source. If not externally forcing the VOCM pin,
the designer must decouple it to ground with a 0.1 µF capacitor
in close proximity to the AD8390.
Table 5. PWDN Code Selection Guide
PWDN1
PWDN0
RADJ (Ω)
IQ (mA)
10.0
6.7
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
∞
∞
∞
∞
0
With dual equal supplies (for example, 12 V) such that the
midpoint of the supplies is nominally 0 V, the user may opt to
connect the VOCM pin directly to ground, thus eliminating the
need for an external decoupling capacitor.
3.8
0.67
5.2
POWER-DOWN FEATURES AND THE IADJ PIN
0
3.8
The AD8390 offers significant versatility in setting quiescent
bias levels for a particular application from full ON to full OFF.
This versatility gives the circuit designer the flexibility to maxi-
mize efficiency while maintaining optimal levels of performance.
0
2.5
0
0.57
ADSL and ADSL2+ Applications
The AD8390 line driver amplifier is an efficient class AB amplifier
that is ideal for driving xDSL signals. The AD8390 may be used
for driving ADSL or ADSL2+ modulated signals in either direc-
tion: upstream from CPE to the CO or downstream from the
CO to CPE.
Optimizing driver efficiency while delivering the required signal
level is accomplished with the AD8390 through the use of two
on-chip power management features: two PWDN pins used to
select one of four bias modes, and an IADJ pin used for additional
power management including fine bias adjustments.
ADSL and ADSL2+ Applications Circuit
PWDN Pins
Increased CO port density has made driver power efficiency an
important requirement in ADSL and ADSL2+ systems. The lar-
gest impact on efficiency is due to the need for back termina-
tion of the driver. In the simplest case, this is accomplished with
a pair of resistors, each equal to half the reflected line impedance,
in series with the outputs of the differential driver. In this scen-
ario, half the transmitted power is consumed by the back term-
ination resistors. This results in the need for higher turns ratio
transformers, which attenuate the receive signal and tend to be
more lossy. They also increase current requirements of the dri-
ver, effectively reducing headroom because the output devices
can no longer swing as close to the rail.
Two digitally programmable logic pins, PWDN1 and PWDN0,
may be used to select four different bias levels (see Table 5).
These levels start with full power if the IADJ pin is not connected.
The top bias level can also start at approximately half of full bias,
if the IADJ pin is connected to VEE or to ground in a single-supply
configuration, RADJ = 0. The bias level can be controlled with
CMOS logic levels (high = 1) applied to the PWDN1 and PWDN0
pins alone or in combination with the IADJ control pin. The
digital ground pin (DGND) is the logic ground reference for the
PWDN1 and PWDN0 pins. PWDN = (0,0) is the power-down
mode of the amplifier.
The AD8390 exhibits a low output impedance for PWDN1,0 =
(1,1), (1,0), and (0,1). At PWDN1,0 = (0,0), however, the output
impedance is undefined. The lowest power mode (0,0) of the
AD8390 alone may not be suitable for systems that rely on a
high impedance OFF state, such as multiplexing.
To solve this problem, it is common practice to use a combination
of negative and positive feedback to synthesize the output impe-
dance, thus decreasing the required ohmic value of the back
termination. Overall efficiency is improved because less power
is wasted in the back termination and a lower turns ratio trans-
former can be used without the need for increased supply rails.
The application circuit in Figure 24 depicts such an approach,
where the positive feedback, negative feedback, and back termi-
nation are provided by R2, R3, and RM, respectively.
IADJ Pin
The IADJ feature offers users significant flexibility in setting the
bias level of the AD8390 by allowing for fine tuning of the bias
setting. Use of the IADJ feature is not required for operation of
the AD8390.
Rev. C | Page 10 of 16
AD8390
R2
R3
V
CC
Table 6 shows a comparison of the results using the exact values,
the simplified approximation, and the closest 1% resistor values.
In this example, R1, AV, and k were chosen to be 1.0 kΩ, 10 kΩ,
and 0.1 kΩ, respectively.
0.1µF
10µF
0.1µF
R1
+IN
R
R
M
1:N
–OUT
+
It should be noted that decreasing the value of the back termi-
nation resistors attenuates the receive signal by approximately
1/k. However, advances in low noise receive amplifiers permit
k values as small as 0.1 to be commonly used.
V
R
V
OCM
L
OUT,DM
–
+OUT
R3
0.1µF
M
R1
–IN
R
ADJ
R2
The line impedance, turns ratio, and k factor specify the output
voltage and current requirements from the AD8390. To accom-
modate higher crest factors or lower supply rails, the turns ratio,
N, may have to be increased. Since higher turns ratios and smaller
k factors both attenuate the receive signal, a large increase in N
may require an increase in k to maintain the desired noise
performance. Any particular design process requires that these
trade-offs be visited.
V
EE
0.1µF
10µF
Figure 24. ADSL/ADSL2+ Application Circuit
Referring to Figure 24, the following describes how to calculate
the resistor values necessary to obtain the desired input imped-
ance, gain, and output impedance.
The differential input impedance to the circuit is simply 2R1.
As such, R1 is chosen by the designer to yield the desired input
impedance.
Table 6. Resistor Selection
Standard 1%
Approximate Resistor
Exact
When synthesizing the output impedance, a factor k is
introduced, which is used to express the ratio of the negative
feedback resistor to the positive feedback resistor by
Component
R1 (Ω)
R2 (Ω)
R3 (Ω)
RM (Ω)
Values
Calculation
Values
1000
2246.95
2022.25
5
1000
2222.22
2000
1000
2210
2000
4.99
R3
R2
1− k =
(5)
5
Actual AV
Actual k (Eq. 5)
10.000
0.1
9.889
0.1
10.138
0.095
Along with the turns ratio N, k is also used to define the value of
the back termination resistors RM. Commonly used values for k
are 0.1 to 0.25. A k value of 0.1 would result in back termination
resistors that are only 1/10 as large as those in the simplest case
described above. Lower values of k result in greater amounts of
positive feedback. Therefore, values much lower than 0.1 can
lead to instability and are generally not recommended.
MULTITONE POWER RATIO (MTPR)
Multitone power ratio is a commonly used figure of merit that
xDSL designers use to help describe system performance.
MTPR is the measured delta between the peak of a filled
frequency bin and the harmonic products that appear in an
intentionally empty frequency bin. Figure 25 illustrates this
principle. The plots in Figure 10 and Figure 13 show MTPR
performance in various power modes. All data were taken with
a circuit with a k factor of 0.1, a 1:1 turns ratio transformer, and
a waveform with a 5.4 peak-to-average ratio, also known as the
crest factor (CF).
RL
2×N 2
RM = k ×
(6)
This factor (k), along with R1, RM, and the desired gain (AV), is
then used to calculate the necessary values for R3 and R2.
R3 = AV ×R1× k + AV ×R1×
(
AV ×R1× k 2 + RM − k ×RM
)
10dB/DIV
(7)
The usually small value for RM allows a simplified approximation
for R3.
–70dBc
R3 ≅ R1×2× k × AV
(8)
(9)
R3
R2 =
1−k
Once RM, R3, and R2 are computed, the closest 1% resistors can
be chosen and the gain rechecked with the following equation:
R2×R3
RM +k×R2+R2−R3
CENTER 431.25kHz
1kHz/DIV
SPAN 10kHz
A =
(10)
V
(
)
×R1
Figure 25. MTPR Measurement
Rev. C | Page 11 of 16
AD8390
To obtain optimum thermal performance from the AD8390 in
either package, it is essential that the thermal pad be soldered to
a ground plane with minimal thermal resistance. This is par-
ticularly true for dense circuit designs with multiple integrated
circuits. Furthermore, the PCB should be designed in such a
manner as to draw the heat away from the ICs. Figure 26
illustrates the relationship between thermal resistance (°C/W)
and the copper area (mm2) for the AD8390ACP soldered down
to a 4-layer board with a given copper area.
LAYOUT, GROUNDING, AND BYPASSING
The first layout requirement is for a good solid ground plane
that covers as much of the board area around the AD8390 as
possible. The only exception to this is that the two input pins
should be kept a few millimeters from the ground plane, and
ground should be removed from inner layers and the opposite
side of the board under the input traces. This minimizes the
stray capacitance on these nodes and helps preserve the gain
flatness versus frequency.
Figure 26 can be used to help determine the copper board area
required for proper thermal management of the AD8390. The
power dissipation of the AD8390 can be computed using
Equation 11. This number can then be inserted into the
following equation to yield the required θJA:
The power supply pins should be bypassed as close as possible
to the device on a ground plane common with signal ground.
Good high frequency, ceramic chip capacitors should be used.
This bypassing should be done with a capacitance value of
0.01 μF to 0.1 μF for each supply. Low frequency bypassing
should be provided with 10 μF tantalum capacitors from each
supply to signal ground. The signal routing should be short and
direct to avoid parasitic effects, particularly on traces connected
to the amplifier inputs. Wherever there are complementary
signals, a symmetrical layout should be provided to the extent
possible to maximize the balance performance. When running
differential signals over a long distance, the traces on the PCB
should be close together.
TRISE
PAD8390
°C
W
θJA
=
=
(12)
where TRISE is the delta from the maximum expected ambient
temperature to the highest allowable die temperature. It is
generally recommended that the maximum die temperature be
limited to 125°C, and in no case should it be allowed to exceed
150°C.
POWER DISSIPATION AND THERMAL
MANAGEMENT
Using the θJA computed in Equation 12, Figure 26 can be used to
determine the minimum copper area required for proper thermal
dissipation of the AD8390.
The AD8390 was designed to be the most efficient class AB
ADSL/ADSL2+ line driver available. Figure 11 shows the total
power consumption (delivered line power and power consumed)
of the AD8390 driving ADSL signals at varying output powers
and power modes. To accurately determine the amount of
power dissipated by the AD8390, it is necessary to subtract the
power delivered to the load, matching losses, and transformer
losses as follows:
90
80
70
60
50
40
30
20
10
0
PAD8390 = Psupply,mW − Pload,mW − Plosses,mW
(11)
where:
P
P
P
supply,mW is the total supply power in mW drawn by the AD8390.
load,mW is the power delivered into a 100 Ω twisted-pair line in mW.
losses,mW is the power dissipated by the matching resistors and
1
10
100
Cu AREA (mm
1000
10000
2)
the transformer in mW.
Figure 26. Thermal Resistance vs. Copper Area
While this discussion focuses mainly on ADSL applications, the
same premise can be applied to determining the power dissipa-
tion of the AD8390 in any application.
Rev. C | Page 12 of 16
AD8390
OUTLINE DIMENSIONS
4.0
BSC SQ
0.60 MAX
16
PIN 1
INDICATOR
0.60 MAX
0.65 BSC
13
12
1
PIN 1
INDICATOR
2.25
2.10 SQ
1.95
TOP
VIEW
3.75
BSC SQ
BOTTOM
VIEW
0.75
0.60
0.50
4
9
8
5
0.25 MIN
1.95 BSC
0.80 MAX
0.65 TYP
12° MAX
0.05 MAX
0.02 NOM
1.00
0.85
0.80
0.35
0.28
0.25
0.20 REF
COPLANARITY
0.08
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VGGC
Figure 27. 4 × 4 mm 16-Lead Lead Frame Chip Scale Package [LFCSP]
(CP-16)
Dimensions shown in millimeters
0.197
0.096
0.189
16
1
9
8
0.077
0.236
BSC
0.154
BSC
TOP VIEW
0.090
BOTTOM VIEW
PIN 1
0.069
0.053
0.065
0.049
8°
0°
0.010
0.004
COPLANARITY
0.004
0.025
BSC
0.012
0.008
0.050
0.016
SEATING
PLANE
0.010
0.006
COMPLIANT TO JEDEC STANDARDS MO-137
Figure 28. 16-Lead Shrink Small Outline Package, Exposed Pad [QSOP/EP]
(RC-16)
Dimensions shown in inches
ORDERING GUIDE
Model
Temperature Range
Package Description
16-Lead LFCSP
16-Lead LFCSP
Package Option
AD8390ACP-R2
AD8390ACP-REEL
AD8390ACP-REEL7
AD8390ACP-EVAL
AD8390ARC
AD8390ARC-REEL
AD8390ARC-REEL7
AD8390ARC-EVAL
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
CP-16, 250 Piece Reel
CP-16, 13” Tape and Reel
CP-16, 7” Tape and Reel
LFCSP
16-Lead LFCSP
Evaluation Board
16-Lead QSOP/EP
16-Lead QSOP/EP
16-Lead QSOP/EP
Evaluation Board
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
RC-16
RC-16, 13” Tape and Reel
RC-16, 7” Tape and Reel
QSOP/EP
Rev. C | Page 13 of 16
AD8390
NOTES
Rev. C | Page 14 of 16
AD8390
NOTES
Rev. C | Page 15 of 16
AD8390
NOTES
©
2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C02694–0–9/04(C)
Rev. C | Page 16 of 16
相关型号：
AD8390ACPZ-R2
IC OP-AMP, 3000 uV OFFSET-MAX, PQCC16, 4 X 4 MM, MO-220-VGGC, LFCSP-16, Operational Amplifier
ADI
AD8390ACPZ-REEL
IC OP-AMP, 3000 uV OFFSET-MAX, PQCC16, 4 X 4 MM, MO-220-VGGC, LFCSP-16, Operational Amplifier
ADI
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