AD8398AACPZ-R7 [ADI]
Single Port VDSL2 Line Driver with Shutdown;
| 型号： | AD8398AACPZ-R7 |
| 厂家： | 
ADI |
| 描述： | Single Port VDSL2 Line Driver with Shutdown 驱动 接口集成电路 驱动器 |
| 文件： | 总12页 (文件大小：302K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Single Port VDSL2
Line Driver with Shutdown
AD8398A
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Voltage feedback
Wide output swing
18.4 V p-p differential, RLOAD, DIFF = 20 Ω from 12 V supply
High output current
Linear output current of 450 mA peak
Low distortion
−65 dBc for Profile 8b @ 20.4 dBm
−55 dBc for Profile 17a @ 14.5 dBm
High speed
12 NC
NC
−IN A
+IN A
GND
1
2
3
4
–
+
–
+
11 −IN B
10 +IN B
9
PD1
85 MHz bandwidth (AV DIFF = 5)
NC = NO CONNECT
Figure 1. Thermally Enhanced, 4 mm × 4 mm, 16-Lead LFCSP_WQ
APPLICATIONS
ADSL2+/VDSL2 CO/CPE line drivers
PLC line drivers
TYPICAL APPLICATION DIAGRAM
Consumer xDSL modems
Twisted pair line drivers
TIP
1/2
AD8398A
V
*
MID
RING
1/2
AD8398A
+
V
V
EE
CC
=
*V
MID
2
Figure 2. Typical VDSL2 Application
GENERAL DESCRIPTION
The AD8398A comprises two high speed, voltage feedback
operational amplifiers. When configured as a differential line
driver, the AD8398A is an ideal choice for ADSL2+, VDSL2, and
power line communications (PLC) applications. It has high
output current, high bandwidth, and fast slew rate, combined
with exceptional multitone power ratio (MTPR) and common-
mode stability. The AD8398A is available in a thermally enhanced
4 mm × 4 mm, 16-lead LFCSP.
The AD8398A incorporates power management functionality
via two CMOS-compatible control pins, PD0 and PD1. These
pins select one of four operating modes: full power, medium
power, low power, or complete power-down. In the power-down
mode, the quiescent current drops to 0.7 mA.
The AD8398A operates in the industrial temperature range of
−40°C to +85°C.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2008–2010 Analog Devices, Inc. All rights reserved.
AD8398A
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ..............................................6
Applications Information.................................................................8
Power Control Modes of Operation ...........................................8
Exposed Thermal Pad Connections ...........................................8
Power Supply Bypassing...............................................................8
Board Layout..................................................................................8
Multitone Power Ratio..................................................................9
Lightning and AC Power Fault....................................................9
Outline Dimensions....................................................................... 10
Ordering Guide .......................................................................... 10
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Typical Application Diagram.......................................................... 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
Thermal Resistance ...................................................................... 4
Maximum Power Dissipation ..................................................... 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
REVISION HISTORY
9/10—Rev. C to Rev. D
Change to General Description Section........................................ 1
3/10—Rev. B to Rev. C
Changes to Figure 14........................................................................ 9
12/09—Rev. A to Rev. B
Changes to Figure 13, Figure 14, and Figure 15 ........................... 9
10/09—Rev. Sp0 to Rev. A
Changed RLOAD to RLOAD, Diff Throughout........................................ 1
Changes to DC Performance, Differential Input Offset
Voltage Parameter, Table 1 .............................................................. 3
Changes to Figure 4.......................................................................... 5
Changes to Figure 8 and Figure 9................................................... 6
Changes to Exposed Thermal Pad Connections Section............ 8
11/08—Revision Sp0: Initial Version
Rev. D | Page 2 of 12
AD8398A
SPECIFICATIONS
VS = 12 V, 6 V at TA = 25°C, AV DIFF = 5, RLOAD, DIFF = 20 Ω, PD1 = 0, PD0 = 0, unless otherwise noted.
Table 1.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth
AV DIFF = 5, VOUT = 2 V peak, measured differentially
PD1 = 0, PD0 = 0
85
85
75
600
MHz
MHz
MHz
V/μs
PD1 = 0, PD0 = 1
PD1 = 1, PD0 = 0
Slew Rate
VOUT = 4 V peak, measured differentially
NOISE/DISTORTION PERFORMANCE
MTPR
Profile 8b at 20.4 dBm in VDSL2 application
Profile 17a at 14.5 dBm in VDSL2 application
PD1 = 1, PD0 = 1
f = 100 kHz
f = 100 kHz
−65
−55
−80
4.8
0.9
120
dBc
dBc
dBc
nV/√Hz
pA/√Hz
nV/√Hz
Off Isolation
Input Voltage Noise
Input Current Noise
Differential Output Voltage Noise
DC PERFORMANCE
f = 100 kHz in VDSL2 application
Differential Input Offset Voltage
Input Offset Voltage
Input Bias Current
−2
0.1
16
0.5
+2
55
1
mV
mV
μA
dB
Open-Loop Gain
63
Common-Mode Rejection
INPUT CHARACTERISTICS
Input Resistance
Measured differentially
f < 100 kHz
−100
−74
dB
1.9
MΩ
OUTPUT CHARACTERISTICS
Differential Swing
Linear Peak Output Current
POWER SUPPLY
17.6
18.4
450
V p-p
mA peak
VDSL2 at 20.4 dBm, MTPR = −65 dBc
Operating Range
Dual supply
6
V
Single supply
12
V
Supply Current
PD1 = 0, PD0 = 0
PD1 = 0, PD0 = 1
PD1 = 1, PD0 = 0
PD1 = 1, PD0 = 1
Measured differentially
29
20
12
33.2
22.9
13.3
0.7
37
mA
mA
mA
mA
dB
25.5
14.5
1.1
Power Supply Rejection
POWER-DOWN PINS
PD1, PD0 VIL
PD1, PD0 VIH
PD1, PD0 Bias Current
−94
−74
Referenced to GND
Referenced to GND
PD1, PD0 = 0 V
PD1, PD0 = 3 V
PD1, PD0 = (1, 1) − (0, 0)
PD1, PD0 = (0, 0) − (1, 1)
0.8
2
15
6
60
600
V
V
μA
μA
μs
μs
30
17
Enable Time
Disable Time
Rev. D | Page 3 of 12
AD8398A
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
MAXIMUM POWER DISSIPATION
Rating
The maximum safe power dissipation for the AD8398A is limited
by its junction temperature (TJ) on the die. The maximum safe
TJ of plastic encapsulated devices, as determined by the glass
transition temperature of the plastic, is 150°C. Temporarily
exceeding this limit may cause a shift in the parametric
performance due to a change in the stresses exerted on the
die by the package. Exceeding this limit for an extended period
can result in device failure.
Power Supplies (VCC − VEE)
Power Dissipation
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 10 sec)
Junction Temperature
13.2 V
(TJ MAX − TA)/θJA
−65°C to +125°C
−40°C to +85°C
300°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Figure 3 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 16-lead LFCSP_WQ
on a 4-layer board with six vias connecting the exposed pad to
the GND plane layer.
6
T
= 150°C
J
5
4
3
2
1
THERMAL RESISTANCE
θJA is specified with the device soldered on a JEDEC circuit
board and the thermal pad connected to the GND plane layer
using six vias.
Table 3. Thermal Resistance
Package Type
θJA
Unit
16-Lead LFCSP_WQ
35.6
°C/W
0
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
AMBIENT TEMPERATURE (°C)
Figure 3. Maximum Safe Power Dissipation vs. Ambient Temperature,
4-Layer JEDEC Board with Six Thermal Vias
ESD CAUTION
Rev. D | Page 4 of 12
AD8398A
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NC
−IN A
+IN A
GND
1
2
3
4
12 NC
11 −IN B
10 +IN B
AD8398A
9
PD1
TOP VIEW
(Not to Scale)
NOTES
1. NC = NO CONNECT
2. EXPOSED PADDLE (EPAD) IS
FLOATING, NOT ELECTRICALLY
CONNECTED INTERNALLY.
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 5, 6, 12, 15
NC
No Connect.
2
−IN A
Amplifier A Inverting Input.
3
4
+IN A
GND
Amplifier A Noninverting Input.
Ground.
7
8
VEE
PD0
Negative Power Supply Input.
Power Mode Control.
9
PD1
Power Mode Control.
10
11
13
14
16
EPAD
+IN B
−IN B
OUT B
VCC
OUT A
Exposed Paddle (EPAD)
Amplifier B Noninverting Input.
Amplifier B Inverting Input.
Amplifier B Output.
Positive Power Supply Input.
Amplifier A Output.
The exposed paddle is electrically isolated.
Rev. D | Page 5 of 12
AD8398A
TYPICAL PERFORMANCE CHARACTERISTICS
VCC = 6 V, VEE = −6 V, unless otherwise stated.
21
18
DIFFERENTIAL
15
12
9
1/2
AD8398A
6
3
V
*
COMMON-MODE
MID
R
= 20Ω
0
LOAD, DIFF
–3
–6
–9
–12
PD1 = 0, PD0 = 0
PD1 = 0, PD0 = 1
PD1 = 1, PD0 = 0
1/2
AD8398A
0.1
1
10
100
1000
+
V
V
EE
CC
=
*V
MID
2
FREQUENCY (MHz)
Figure 5. Small Signal Differential and Common-Mode Frequency Response;
AV DIFF = 5 (See the Application Circuit in Figure 8)
Figure 8. Typical Differential Application Circuit
RLOAD, DIFF = 20 Ω
18
DIFFERENTIAL
15
12
9
6
1/2
3
COMMON-MODE
0
–3
AD8398A
V
*
MID
R
= 20Ω
LOAD, DIFF
–6
–9
–12
1/2
AD8398A
PD1 = 0, PD0 = 0
PD1 = 0, PD0 = 1
PD1 = 1, PD0 = 0
–15
–18
–21
0.1
1
10
100
1000
+
V
V
EE
CC
=
*V
MID
FREQUENCY (MHz)
2
Figure 6. Small Signal Differential and Common-Mode Frequency Response
(See the Application Circuit in Figure 9)
Figure 9. Typical Differential Application Circuit with Positive Feedback
RLOAD, DIFF = 20 Ω
30
DIFFERENTIAL
20
10
0
TIP
1/2
AD8398A
PD1 = 0, PD0 = 0
PD1 = 0, PD0 = 1
PD1 = 1, PD0 = 0
–10
–20
V
*
MID
–30
–40
COMMON-MODE
–50
RING
1/2
AD8398A
–60
–70
+
0.1
1
10
100
1000
V
V
EE
CC
=
*V
MID
2
FREQUENCY (MHz)
Figure 10. Typical VDSL2 Application Circuit
Figure 7. Small Signal Differential and Common-Mode Frequency Response
(See the Application Circuit in Figure 10)
Rev. D | Page 6 of 12
AD8398A
1000
900
800
700
600
500
400
1000
100
10
VDSL2 PROFILE 17a
PD1 = 0, PD0 = 0
VDSL2 PROFILE 8b
PD1 = 0, PD0 = 1
1
0.01
10
12
14
16
18
20
0.1
1
10
100
OUTPUT POWER (dBm)
FREQUENCY (MHz)
Figure 11. Internal Power Dissipation vs. Output Power
Figure 12. Differential Output Voltage Noise vs. Frequency in a
Typical VDSL2 Application
Rev. D | Page 7 of 12
AD8398A
APPLICATIONS INFORMATION
POWER CONTROL MODES OF OPERATION
BOARD LAYOUT
As is the case with all high speed applications, careful attention
to printed circuit board (PCB) layout details prevents associated
board parasitics from becoming problematic. Proper RF design
technique is mandatory.
The AD8398A features four power modes: full power, medium
power, low power, and complete power-down. Two CMOS-
compatible logic pins (PD0 and PD1) select the power mode.
The power modes and associated logic states are listed in Table 5.
The PCB has a ground plane covering all unused portions of the
component side of the board to provide a low impedance return
path. Removing the ground plane on all layers from the area
near the input and output pins of the AD8398A reduces stray
capacitance.
Table 5. Power Modes
PD1 PD0 Power Mode
Total Supply Current (mA)
0
0
1
1
0
1
0
1
Full power
Medium power
Low power
33.2
22.9
13.3
0.7
Signal lines connecting the feedback and gain resistors should
be as short as possible to minimize the inductance and stray
capacitance associated with these traces. Place termination resistors
and loads as close as possible to their respective inputs and outputs.
Power-down
EXPOSED THERMAL PAD CONNECTIONS
To ensure adequate heat transfer away from the die, connect
the exposed thermal pad to a solid plane layer with low thermal
resistance. To maximize the operating life of the AD8398A, the
thermal design of the system should be kept below the junction
temperature of 125°C.
To minimize coupling (crosstalk) through the board, keep input
and output traces as far apart as possible. Wherever there are
complementary signals, provide a symmetrical layout to maximize
balanced performance.
Although it is electrically isolated, the thermal pad typically
connects to the ground plane layer.
POWER SUPPLY BYPASSING
The AD8398A typically operates on 6 V or +12 V supplies.
Power the AD8398A circuit with a well-regulated, properly
decoupled power supply. To minimize supply voltage ripple
and power dissipation, use high quality capacitors with low
equivalent series resistance (ESR), such as multilayer ceramic
capacitors (MLCCs). Place a decoupling 0.1 μF MLCC no
more than ⅛ inch away from each of the power supply pins.
In addition, a 10 μF tantalum capacitor is recommended to
provide good decoupling for lower frequency signals and to
supply current for fast, large signal changes at the AD8398A
outputs. Lay out bypass capacitors to keep return currents away
from the inputs of the amplifiers. This layout minimizes any
voltage drops that can develop due to ground currents flowing
through the ground plane.
Rev. D | Page 8 of 12
AD8398A
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
MULTITONE POWER RATIO
The discrete multitone (DMT) signal used in xDSL systems
carries data in discrete tones or bins that appear in the frequency
domain in evenly spaced 4.3125 kHz intervals. In applications
using this type of waveform, multitone power ratio (MTPR) is
a commonly used measure of linearity. Generally, designers are
concerned with two types of MTPR: in band and out of band.
In-band MTPR is defined as the measured difference from the
peak of one tone that is loaded with data to the peak of an adjacent
tone that is intentionally left empty. Out-of-band MTPR is
defined as the spurious emissions that occur in the receive bands.
Transmit band power and receive band MTPR are shown in
Figure 13, Figure 14, and Figure 15 for Profile 17a, Profile 8b,
and ADSL2+, respectively.
0
0.5
1.0
1.5
2.0
2.5
3.0
FREQUENCY (MHz)
Figure 15. MTPR of a Typical ADSL2+ DMT Test Signal,
VS = 6 V, Output Power = 20.4 dBm
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
LIGHTNING AND AC POWER FAULT
DSL line drivers are transformer-coupled to the twisted pair
telephone line. In this environment, the AD8398A may be
subject to large line transients resulting from events such as
lightning strikes or downed power lines. Additional circuitry
is required to protect the AD8398A from possible damage due
to these events.
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY (MHz)
Figure 13. MTPR of a Typical VDSL2 Profile 17a DMT Test Signal,
VS = 6 V, Output Power = 14.5 dBm
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
1
2
3
4
5
6
7
8
9
10
FREQUENCY (MHz)
Figure 14. MTPR of a Typical VDSL2 Profile 8b DMT Test Signal,
VS = 6 V, Output Power = 20.4 dBm
Rev. D | Page 9 of 12
AD8398A
OUTLINE DIMENSIONS
4.10
4.00 SQ
3.90
0.35
0.30
0.25
PIN 1
INDICATOR
PIN 1
INDICATOR
0.65
BSC
1
4
13
16
12
EXPOSED
PAD
2.40
2.35 SQ
2.30
9
8
5
0.20 MIN
0.45
0.40
0.35
TOP VIEW
BOTTOM VIEW
0.80
0.75
0.70
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD
Figure 16. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-16-20)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD8398AACPZ-R2
AD8398AACPZ-R7
AD8398AACPZ-RL
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option
CP-16-20
CP-16-20
16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
CP-16-20
1 Z = RoHS Compliant Part.
Rev. D | Page 10 of 12
AD8398A
NOTES
Rev. D | Page 11 of 12
AD8398A
NOTES
©2008–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07760-0-9/10(D)
Rev. D | Page 12 of 12
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