AD844JRZ-16-REEL [ADI]
60 MHz 2000 V Monolithic Op Amp; 60 MHz的2000 V单片运算放大器
| 型号： | AD844JRZ-16-REEL |
| 厂家： | 
ADI |
| 描述： | 60 MHz 2000 V Monolithic Op Amp |
| 文件： | 总20页 (文件大小：422K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
60 MHz 2000 V/μs
Monolithic Op Amp
AD844
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
Wide bandwidth
60 MHz at gain of −1
33 MHz at gain of −10
Slew rate: 2000 V/μs
NULL
–IN
1
2
3
4
8
7
6
5
NULL
+V
AD844
S
+IN
OUTPUT
TZ
–V
S
20 MHz full power bandwidth, 20 V p-p, RL = 500 Ω
Fast settling: 100 ns to 0.1% (10 V step)
Differential gain error: 0.03% at 4.4 MHz
Differential phase error: 0.16° at 4.4 MHz
Low offset voltage: 150 μV maximum (B Grade)
Low quiescent current: 6.5 mA
Available in tape and reel in accordance with
EIA-481-A standard
TOP VIEW
(Not to Scale)
Figure 1. 8-Lead PDIP (N) and 8-Lead CERDIP (Q) Packages
NC
1
2
3
4
5
6
7
8
16 NC
OFFSETNULL
15 OFFSETNULL
14 V+
–IN
NC
+IN
NC
V–
13 NC
12 OUTPUT
11 TZ
AD844
TOP VIEW
(Not to Scale)
APPLICATIONS
10 NC
NC
9
NC
Flash ADC input amplifiers
High speed current DAC interfaces
Video buffers and cable drivers
Pulse amplifiers
NC = NO CONNECT
Figure 2. 16-Lead SOIC (R) Package
GENERAL DESCRIPTION
The AD844A and AD844B are specified for the industrial
temperature range of −40°C to +85°C and are available in the
CERDIP (Q) package. The AD844A is also available in an 8-lead
PDIP (N). The AD844S is specified over the military temperature
range of −55°C to +125°C. It is available in the 8-lead CERDIP
(Q) package. A and S grade chips and devices processed to
MIL-STD-883B, Rev. C are also available.
The AD844 is a high speed monolithic operational amplifier
fabricated using the Analog Devices, Inc., junction isolated
complementary bipolar (CB) process. It combines high band-
width and very fast large signal response with excellent dc
performance. Although optimized for use in current-to-voltage
applications and as an inverting mode amplifier, it is also suitable
for use in many noninverting applications.
PRODUCT HIGHLIGHTS
The AD844 can be used in place of traditional op amps, but its
current feedback architecture results in much better ac perfor-
mance, high linearity, and an exceptionally clean pulse response.
1. The AD844 is a versatile, low cost component providing an
excellent combination of ac and dc performance.
2. It is essentially free from slew rate limitations. Rise and fall
times are essentially independent of output level.
This type of op amp provides a closed-loop bandwidth that is
determined primarily by the feedback resistor and is almost
independent of the closed-loop gain. The AD844 is free from
the slew rate limitations inherent in traditional op amps and
other current-feedback op amps. Peak output rate of change can
be over 2000 V/μs for a full 20 V output step. Settling time is
typically 100 ns to 0.1%, and essentially independent of gain.
The AD844 can drive 50 Ω loads to 2.5 V with low distortion
and is short-circuit protected to 80 mA.
3. The AD844 can be operated from 4.5 V to 18 V power
supplies and is capable of driving loads down to 50 Ω, as
well as driving very large capacitive loads using an external
network.
4. The offset voltage and input bias currents of the AD844 are
laser trimmed to minimize dc errors; VOS drift is typically 1
μV/°C and bias current drift is typically 9 nA/°C.
5. The AD844 exhibits excellent differential gain and
differential phase characteristics, making it suitable for a
variety of video applications with bandwidths up to 60 MHz.
6. The AD844 combines low distortion, low noise, and low
drift with wide bandwidth, making it outstanding as an
input amplifier for flash analog-to-digital converters (ADCs).
The AD844 is available in four performance grades and three
package options. In the 16-lead SOIC (RW) package, the AD844J
is specified for the commercial temperature range of 0°C to 70°C.
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©1989–2009 Analog Devices, Inc. All rights reserved.
AD844
TABLE OF CONTENTS
Features .............................................................................................. 1
Response as an Inverting Amplifier......................................... 12
Response as an I-V Converter.................................................. 13
Circuit Description of the AD844............................................ 13
Response as a Noninverting Amplifier.................................... 14
Noninverting Gain of 100 ......................................................... 14
Using the AD844 ............................................................................ 15
Board Layout............................................................................... 15
Input Impedance ........................................................................ 15
Driving Large Capacitive Loads............................................... 15
Settling Time............................................................................... 15
DC Error Calculation ................................................................ 16
Noise ............................................................................................ 16
Video Cable Driver Using 5 V Supplies................................ 16
High Speed DAC Buffer ............................................................ 17
20 MHz Variable Gain Amplifier............................................. 17
Outline Dimensions....................................................................... 19
Ordering Guide .......................................................................... 20
Applications....................................................................................... 1
Functional Block Diagrams............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Metallization Photograph............................................................ 5
ESD Caution.................................................................................. 5
Typical Performance Characteristics ............................................. 6
Inverting Gain-of-1 AC Characteristics.................................... 8
Inverting Gain-of-10 AC Characteristics.................................. 9
Inverting Gain-of-10 Pulse Response...................................... 10
Noninverting Gain-of-10 AC Characteristics ........................ 11
Understanding the AD844 ............................................................ 12
Open-Loop Behavior ................................................................. 12
REVISION HISTORY
1/03 Data Sheet changed from REV. D to REV. E.
2/09—Rev. E to Rev F
Updated Features...............................................................................1
Edit to TPC 18 ...................................................................................7
Edits to Figure 13 and Figure 14................................................... 13
Updated Outline Dimensions....................................................... 15
Updated Format..................................................................Universal
Changes to Features Section............................................................ 1
Changes to Differential Phase Error Parameter, Table 1............. 3
Changes to Figure 13........................................................................ 8
Changes to Figure 18........................................................................ 9
Changes to Figure 23 and Figure 24............................................. 11
Changes to Figure 42 and High Speed DAC Buffer Section..... 17
Updated Outline Dimensions....................................................... 19
Changes to Ordering Guide .......................................................... 20
11/01 Data Sheet changed from REV. C to REV. D.
Edits to Specifications ......................................................................2
Edits to Absolute Maximum Ratings..............................................3
Edits to Ordering Guide ...................................................................3
Rev. F | Page 2 of 20
AD844
SPECIFICATIONS
TA = 25°C and VS = 15 V dc, unless otherwise noted.
Table 1.
AD844J/AD844A
AD844B
AD844S
Typ
50
125
1
Parameter
Conditions
Min
Typ
50
75
1
Max
Min
Typ
50
75
1
Max
150
200
5
Min
Max
300
500
5
Unit
μV
μV
INPUT OFFSET VOLTAGE1
300
500
TMIN to TMAX
vs. Temperature
vs. Supply
μV/°C
5 V to 18 V
Initial
TMIN to TMAX
vs. Common Mode
Initial
TMIN to TMAX
4
4
20
35
4
4
10
10
4
4
20
20
μV/V
μV/V
VCM = 10 V
10
10
10
10
20
20
10
10
35
35
μV/V
μV/V
INPUT BIAS CURRENT
Negative Input Bias Current1
TMIN to TMAX
vs. Temperature
vs. Supply
200
800
9
450
1500
150
750
9
250
1100
15
200
1900
20
450
2500 nA
30
nA
nA/°C
5 V to 18 V
Initial
TMIN to TMAX
vs. Common Mode
Initial
TMIN to TMAX
Positive Input Bias Current1
TMIN to TMAX
vs. Temperature
vs. Supply
175
220
250
160
175
220
200
240
175
220
250
300
nA/V
nA/V
VCM = 10 V
90
90
110
150
200
500
7
90
160
200
400
1300 nA
15
nA/V
nA/V
nA
110
150
350
3
110
100
300
3
120
100
800
7
400
700
nA/°C
5 V to 18 V
Initial
TMIN to TMAX
vs. Common Mode
Initial
TMIN to TMAX
80
100
150
150
80
100
100
120
80
120
150
200
nA/V
nA/V
VCM = 10 V
90
130
90
130
120
190
90
140
150
200
nA/V
nA/V
INPUT CHARACTERISTICS
Input Resistance
Negative Input
Positive Input
Input Capacitance
Negative Input
Positive Input
50
10
65
50
10
65
50
10
65
Ω
MΩ
7
7
7
2
2
2
2
2
2
pF
pF
V
Input Common-Mode Voltage
Range
10
10
10
INPUT VOLTAGE NOISE
INPUT CURRENT NOISE
Negative Input
f ≥ 1 kHz
2
2
2
nV/√Hz
f ≥ 1 kHz
f ≥ 1 kHz
10
12
10
12
10
12
pV/√Hz
pV/√Hz
Positive Input
OPEN-LOOP TRANSRESISTANCE
VOUT = 10 V
RL = 500 Ω
2.2
1.3
3.0
2.0
4.5
2.8
1.6
3.0
2.0
4.5
2.2
1.3
3.0
1.6
4.5
MΩ
MΩ
pF
TMIN to TMAX
Transcapacitance
DIFFERENTIAL GAIN ERROR2
DIFFERENTIAL PHASE ERROR2
f = 4.4 MHz
f = 4.4 MHz
0.03
0.16
0.03
0.16
0.03
0.16
%
Degree
Rev. F | Page 3 of 20
AD844
AD844J/AD844A
AD844B
Typ
AD844S
Typ
Parameter
Conditions
Min
Typ
Max
Min
Max
Min
Max
Unit
FREQUENCY RESPONSE
Small Signal Bandwidth3, 4
Gain = −1
60
33
60
33
60
33
MHz
MHz
%
Gain = −10
TOTAL HARMONIC DISTORTION
f = 100 kHz,
2 V rms5
0.005
0.005
0.005
SETTLING TIME
10 V Output Step
Gain = −1, to 0.1%5
Gain = −10, to 0.1%6
2 V Output Step
15 V supplies
5 V supplies
100
100
100
100
100
100
ns
ns
Gain = −1, to 0.1%5
Gain = −10, to 0.1%6
OUTPUT SLEW RATE
110
100
110
100
110
100
ns
ns
Overdriven
input
1200 2000
1200 2000
1200 2000
V/ꢀs
FULL POWER BANDWIDTH
VOUT = 20 V p-p5
VOUT = 2 V p-p5
THD = 3%
VS = 15 V
VS = 5 V
20
20
20
20
20
20
MHz
MHz
OUTPUT CHARACTERISTICS
Voltage
Short-Circuit Current
TMIN to T MAX
Output Resistance
POWER SUPPLY
Operating Range
Quiescent Current
TMIN to TMAX
RL = 500 Ω
Open loop
10
11
80
60
15
10
11
80
60
15
10
11
80
60
15
V
mA
mA
Ω
4.5
18
7.5
8.5
4.5
18
7.5
8.5
4.5
18
7.5
8.5
V
mA
mA
6.5
7.5
6.5
7.5
6.5
7.5
1 Rated performance after a 5 minute warm-up at TA = 25°C.
2 Input signal 285 mV p-p carrier (40 IRE) riding on 0 mV to 642 mV (90 IRE) ramp. RL = 100 Ω; R1, R2 = 300 Ω.
3 For gain = −1, input signal = 0 dBm, CL = 10 pF, RL = 500 Ω, R1 = 500 Ω, and R2 = 500 Ω in Figure 29.
4 For gain = −10, input signal = 0 dBm, CL =10 pF, RL = 500 Ω, R1 = 500 Ω, and R2 = 50 Ω in Figure 29.
5 CL = 10 pF, RL = 500 Ω, R1 = 1 kΩ, R2 = 1 kΩ in Figure 29.
6 CL = 10 pF, RL = 500 Ω, R1 = 500 Ω, R2 = 50 Ω in Figure 29.
Rev. F | Page 4 of 20
AD844
ABSOLUTE MAXIMUM RATINGS
Table 2.
METALLIZATION PHOTOGRAPH
Contact factory for latest dimensions.
Parameter
Ratings
18 V
Supply Voltage
Power Dissipation1
Dimensions shown in inches and (millimeters).
1.1 W
Indefinite
VS
–IN
NULL
NULL
+V
S
Output Short-Circuit Duration
Input Common-Mode Voltage
Differential Input Voltage
Inverting Input Current
Continuous
6 V
5 mA
Transient
10 mA
0.076
(1.9)
Storage Temperature Range (Q)
Storage Temperature Range (N, RW)
Lead Temperature (Soldering, 60 sec)
ESD Rating
−65°C to +150°C
−65°C to +125°C
300°C
1000 V
1 28-lead PDIP package: θJA = 90°C/W.
8-lead CERDIP package: θJA = 110°C/W.
16-lead SOIC package: θJA = 100°C/W.
+IN
–V
TZ
OUTPUT
S
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
0.095
(2.4)
SUBSTRATE CONNECTED TO +V
S
Figure 3. Die Photograph
ESD CAUTION
Rev. F | Page 5 of 20
AD844
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C and VS = 15 V, unless otherwise noted.
20
15
10
5
70
T
= 25°C
A
60
50
40
30
0
0
5
10
15
20
0
5
10
15
20
SUPPLY VOLTAGE (±V)
SUPPLY VOLTAGE (±V)
Figure 4. −3 dB Bandwidth vs. Supply Voltage, R1 = R2 = 500 Ω
Figure 7. Noninverting Input Voltage Swing vs. Supply Voltage
20
–60
1V rms
R
A
= 500Ω
= 25°C
L
T
–70
–80
15
10
5
–90
–100
–110
SECOND HARMONIC
–120
THIRD HARMONIC
–130
0
0
5
10
15
20
100
1k
10k
100k
SUPPLY VOLTAGE (±V)
INPUT FREQUENCY (Hz)
Figure 5. Harmonic Distortion vs. Input Frequency, R1 = R2 = 1 kΩ
Figure 8. Output Voltage Swing vs. Supply Voltage
10
9
5
R
= ∞
L
4
3
2
1
0
R
= 500Ω
L
8
7
V
= ±15V
S
6
R
= 50Ω
L
V
= ±5V
S
5
4
–60 –40 –20
0
20
40
60
80
100 120 140
–50
0
50
100
150
TEMPERATURE (-°C)
TEMPERATURE (°C)
Figure 6. Transresistance vs. Temperature
Figure 9. Quiescent Supply Current vs. Temperature and Supply Voltage
Rev. F | Page 6 of 20
AD844
40
35
30
25
20
15
10
2
1
V
= ±15V
S
I
BP
0
V
= ±5V
S
–1
–2
I
BN
–60 –40 –20
0
20
40
60
80
100 120 140
–50
0
50
100
150
TEMPERATURE (-°C)
TEMPERATURE (°C)
Figure 12. –3 dB Bandwidth vs. Temperature, Gain = −1, R1 = R2 = 1 kΩ
Figure 10. Inverting Input Bias Current (IBN) and Noninverting Input Bias
Current (IBP) vs. Temperature
100
10
±5V SUPPLIES
1
0.1
0.01
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 11. Output Impedance vs. Frequency, Gain = −1, R1 = R2 = 1 kΩ
Rev. F | Page 7 of 20
AD844
INVERTING GAIN-OF-1 AC CHARACTERISTICS
+V
S
5V
4.7Ω
0.22µF
100
90
R1
R2
–
–IN
OUTPUT
AD844
+
R
C
L
L
10
0
0.22µF
4.7Ω
20ns
–V
S
Figure 16. Large Signal Pulse Response, Gain = −1, R1 = R2 = 1 kΩ
Figure 13. Inverting Amplifier, Gain of −1 (R1 = R2)
6
0
500nV
R1 = R2 = 500Ω
100
90
R1 = R2 = 1kΩ
–6
–12
–18
–24
10
0
20ns
100k
1M
10M
100M
Figure 17. Small Signal Pulse Response, Gain = −1, R1 = R2 = 1 kΩ
FREQUENCY (Hz)
Figure 14. Gain vs. Frequency for Gain = −1, RL = 500 Ω, CL = 0 pF
–180
–210
R1 = R2 = 500Ω
–240
–270
R1 = R2 = 1kΩ
–300
–330
0
25
50
FREQUENCY (MHz)
Figure 15. Phase vs. Frequency for Gain = −1, RL = 500 Ω, CL = 0 pF
Rev. F | Page 8 of 20
AD844
INVERTING GAIN-OF-10 AC CHARACTERISTICS
+V
–180
–210
–240
–270
–300
–330
S
4.7Ω
0.22µF
500Ω
R
= 500Ω
R
= 50Ω
L
L
50Ω
–
–IN
OUTPUT
AD844
+
R
C
L
L
0.22µF
4.7Ω
–V
S
0
25
50
FREQUENCY (MHz)
Figure 18. Gain of −10 Amplifier
Figure 20. Phase vs. Frequency, Gain = −10
26
20
14
8
R
= 500Ω
= 50Ω
L
L
R
2
–4
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 19. Gain vs. Frequency, Gain = −10
Rev. F | Page 9 of 20
AD844
INVERTING GAIN-OF-10 PULSE RESPONSE
5V
500nV
100
90
100
90
10
0
10
0
20ns
20ns
Figure 21. Large Signal Pulse Response, Gain = –10, RL = 500 Ω
Figure 22. Small Signal Pulse Response, Gain = −10, RL = 500 Ω
Rev. F | Page 10 of 20
AD844
NONINVERTING GAIN-OF-10 AC CHARACTERISTICS
4.7Ω
+V
S
2V
100ns
0.22µF
100
90
450Ω
50Ω
–
OUTPUT
AD844
+
–IN
0.22µF
R
L
C
L
4.7Ω
10
0
–V
S
Figure 23. Noninverting Gain of +10 Amplifier
Figure 26. Noninverting Amplifier Large Signal Pulse Response, Gain = +10,
RL = 500 Ω
26
20
14
8
200nV
50ns
100
90
R
= 50Ω
R = 500Ω
L
L
10
0
2
–4
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 24. Gain vs. Frequency, Gain = +10
Figure 27. Small Signal Pulse Response, Gain = +10, RL = 500 Ω
–180
–210
–240
–270
–300
–330
R
= 500Ω
R
= 50Ω
L
L
0
25
50
FREQUENCY (MHz)
Figure 25. Phase vs. Frequency, Gain = +10
Rev. F | Page 11 of 20
AD844
UNDERSTANDING THE AD844
RESPONSE AS AN INVERTING AMPLIFIER
The AD844 can be used in ways similar to a conventional op
amp while providing performance advantages in wideband
applications. However, there are important differences in the
internal structure that need to be understood to optimize the
performance of the AD844 op amp.
Figure 29 shows the connections for an inverting amplifier.
Unlike a conventional amplifier, the transient response and the
small signal bandwidth are determined primarily by the value of
the external feedback resistor, R1, rather than by the ratio of
R1/R2 as is customarily the case in an op amp application. This
is a direct result of the low impedance at the inverting input. As
with conventional op amps, the closed-loop gain is −R1/R2.
OPEN-LOOP BEHAVIOR
Figure 28 shows a current feedback amplifier reduced to essen-
tials. Sources of fixed dc errors, such as the inverting node bias
current and the offset voltage, are excluded from this model.
The most important parameter limiting the dc gain is the
transresistance, Rt, which is ideally infinite. A finite value of Rt
is analogous to the finite open-loop voltage gain in a conven-
tional op amp.
The closed-loop transresistance is the parallel sum of R1 and Rt.
Because R1 is generally in the range of 500 Ω to 2 kΩ and Rt is
about 3 MΩ, the closed-loop transresistance is only 0.02% to
0.07% lower than R1. This small error is often less than the
resistor tolerance.
When R1 is fairly large (above 5 kΩ) but still much less than Rt,
the closed-loop HF response is dominated by the time constant
R1 Ct. Under such conditions, the AD844 is overdamped and
provides only a fraction of its bandwidth potential. Because of
the absence of slew rate limitations under these conditions, the
circuit exhibits a simple single-pole response even under large
signal conditions.
The current applied to the inverting input node is replicated by
the current conveyor to flow in Resistor Rt. The voltage developed
across Rt is buffered by the unity gain voltage follower. Voltage
gain is the ratio Rt/RIN. With typical values of Rt = 3 MΩ and
RIN = 50 Ω, the voltage gain is about 60,000. The open-loop
current gain, another measure of gain that is determined by the
beta product of the transistors in the voltage follower stage (see
Figure 31), is typically 40,000.
In Figure 29, R3 is used to properly terminate the input if desired.
R3 in parallel with R2 gives the terminated resistance. As R1 is
lowered, the signal bandwidth increases, but the time constant
R1 Ct becomes comparable to higher order poles in the closed-
loop response. Therefore, the closed-loop response becomes
complex, and the pulse response shows overshoot. When R2
is much larger than the input resistance, RIN, at Pin 2, most of
the feedback current in R1 is delivered to this input, but as R2
becomes comparable to RIN, less of the feedback is absorbed at
Pin 2, resulting in a more heavily damped response. Consequently,
for low values of R2, it is possible to lower R1 without causing
instability in the closed-loop response. Table 3 lists combinations
of R1 and R2 and the resulting frequency response for the circuit
of Figure 29. Figure 16 shows the very clean and fast 10 V
pulse response of the AD844.
+1
I
R
C
t
IN
t
+1
R
I
IN
IN
Figure 28. Equivalent Schematic
The important parameters defining ac behavior are the
transcapacitance, Ct, and the external feedback resistor (not
shown). The time constant formed by these components is
analogous to the dominant pole of a conventional op amp and
thus cannot be reduced below a critical value if the closed-loop
system is to be stable. In practice, Ct is held to as low a value as
possible (typically 4.5 pF) so that the feedback resistor can be
maximized while maintaining a fast response. The finite RIN
also affects the closed-loop response in some applications.
R1
R2
V
IN
The open-loop ac gain is also best understood in terms of the
transimpedance rather than as an open-loop voltage gain. The
open-loop pole is formed by Rt in parallel with Ct. Because Ct is
typically 4.5 pF, the open-loop corner frequency occurs at about
12 kHz. However, this parameter is of little value in determining
the closed-loop response.
V
AD844
OUT
R3
OPTIONAL
R
C
L
L
Figure 29. Inverting Amplifier
Rev. F | Page 12 of 20
AD844
R1
Table 3. Gain vs. Bandwidth
I
SIG
Gain
R1
R2
BW (MHz)
GBW (MHz)
AD844
V
OUT
−1
−1
−2
−2
−5
−5
−10
−10
−20
−100
1 kΩ
500 Ω
2 kΩ
1 kΩ
5 kΩ
500 Ω
1 kΩ
500 Ω
1 kΩ
5 kΩ
1 kΩ
500 Ω
1 kΩ
500 Ω
1 kΩ
100 Ω
100 Ω
50 Ω
50 Ω
50 Ω
35
60
15
30
5.2
49
23
33
21
3.2
35
60
30
60
C
S
R
C
L
L
26
Figure 30. Current-to-Voltage Converter
245
230
330
420
320
CIRCUIT DESCRIPTION OF THE AD844
A simplified schematic is shown in Figure 31. The AD844 differs
from a conventional op amp in that the signal inputs have
radically different impedance. The noninverting input (Pin 3)
presents the usual high impedance. The voltage on this input is
transferred to the inverting input (Pin 2) with a low offset voltage,
ensured by the close matching of like polarity transistors operating
under essentially identical bias conditions. Laser trimming nulls
the residual offset voltage, down to a few tens of microvolts. The
inverting input is the common emitter node of a complementary
pair of grounded base stages and behaves as a current summing
node. In an ideal current feedback op amp, the input resistance
is zero. In the AD844, it is about 50 Ω.
RESPONSE AS AN I-V CONVERTER
The AD844 works well as the active element in an operational
current-to-voltage converter, used in conjunction with an exter-
nal scaling resistor, R1, in Figure 30. This analysis includes the
stray capacitance, CS, of the current source, which may be a
high speed DAC. Using a conventional op amp, this capacitance
forms a nuisance pole with R1 that destabilizes the closed-loop
response of the system. Most op amps are internally compensated
for the fastest response at unity gain, so the pole due to R1 and
CS reduces the already narrow phase margin of the system. For
example, if R1 is 2.5 kΩ, a CS of 15 pF places this pole at a fre-
quency of about 4 MHz, well within the response range of even a
medium speed operational amplifier. In a current feedback amp,
this nuisance pole is no longer determined by R1 but by the
input resistance, RIN. Because this is about 50 Ω for the AD844,
the same 15 pF forms a pole at 212 MHz and causes little
trouble. It can be shown that the response of this system is:
A current applied to the inverting input is transferred to a
complementary pair of unity-gain current mirrors that deliver
the same current to an internal node (Pin 5) at which the full
output voltage is generated. The unity-gain complementary
voltage follower then buffers this voltage and provides the load
driving power. This buffer is designed to drive low impedance
loads, such as terminated cables, and can deliver 50 mA into a
50 Ω load while maintaining low distortion, even when operating
at supply voltages of only 6 V. Current limiting (not shown)
ensures safe operation under short-circuited conditions.
K R1
VOUT = Isig
(
1+ sTd
)
(
1+ sTn
)
+V
7
S
where:
K is a factor very close to unity and represents the finite dc gain
of the amplifier.
I
B
Td is the dominant pole.
Tn is the nuisance pole.
3
2
5
6
OUTPUT
+IN
–IN
TZ
Rt
K =
Rt + R1
Td = KR1Ct
I
B
Tn = RINCS (assuming RIN << R1)
–V
S
4
Using typical values of R1 = 1 kΩ and Rt = 3 MΩ, K = 0.9997; in
other words, the gain error is only 0.03%. This is much less than
the scaling error of virtually all DACs and can be absorbed, if
necessary, by the trim needed in a precise system.
Figure 31. Simplified Schematic
In the AD844, Rt is fairly stable with temperature and supply
voltages, and consequently the effect of finite gain is negligible
unless high value feedback resistors are used. Because that
results in slower response times than are possible, the relatively
low value of Rt in the AD844 is rarely a significant source of error.
Rev. F | Page 13 of 20
AD844
NONINVERTING GAIN OF 100
It is important to understand that the low input impedance at
the inverting input is locally generated and does not depend on
feedback. This is very different from the virtual ground of a
conventional operational amplifier used in the current summing
mode, which is essentially an open circuit until the loop settles.
In the AD844, transient current at the input does not cause
voltage spikes at the summing node while the amplifier is
settling. Furthermore, all of the transient current is delivered
to the slewing (TZ) node (Pin 5) via a short signal path (the
grounded base stages and the wideband current mirrors).
The AD844 provides very clean pulse response at high
noninverting gains. Figure 32 shows a typical configuration
providing a gain of 100 with high input resistance. The feedback
resistor is kept as low as practicable to maximize bandwidth,
and a peaking capacitor (CPK) can optionally be added to
further extend the bandwidth. Figure 33 shows the small signal
response with CPK = 3 nF, RL = 500 Ω, and supply voltages of
either 5 V or 15 V. Gain bandwidth products of up to
900 MHz can be achieved in this way.
The current available to charge the capacitance (about 4.5 pF) at
the TZ node is always proportional to the input error current,
and the slew rate limitations associated with the large signal
response of the op amps do not occur. For this reason, the rise
and fall times are almost independent of signal level. In practice,
the input current eventually causes the mirrors to saturate.
When using 15 V supplies, this occurs at about 10 mA (or
2200 V/μs). Because signal currents are rarely this large,
classical slew rate limitations are absent.
The offset voltage of the AD844 is laser trimmed to the 50 μV
level and exhibits very low drift. In practice, there is an
additional offset term due to the bias current at the inverting
input (IBN), which flows in the feedback resistor (R1). This can
optionally be nulled by the trimming potentiometer shown in
Figure 32.
+V
S
4.7Ω
OFFSET
TRIM
This inherent advantage is lost if the voltage follower used
to buffer the output has slew rate limitations. The AD844 is
designed to avoid this problem, and as a result, the output
buffer exhibits a clean large signal transient response, free
from anomalous effects arising from internal saturation.
C
3nF
PK
R1
20Ω
499Ω
1
8
0.22µF
6
2
3
7
R2
4.99Ω
RESPONSE AS A NONINVERTING AMPLIFIER
AD844
Because current feedback amplifiers are asymmetrical with
regard to their two inputs, performance differs markedly in
noninverting and inverting modes. In noninverting modes, the
large signal high speed behavior of the AD844 deteriorates at
low gains because the biasing circuitry for the input system (not
shown in Figure 31) is not designed to provide high input
voltage slew rates.
V
R
IN
L
4
0.22µF
4.7Ω
–V
S
Figure 32. Noninverting Amplifier Gain = 100, Optional Offset Trim Is Shown
46
However, good results can be obtained with some care. The
noninverting input does not tolerate a large transient input; it
must be kept below 1 V for best results. Consequently, this
mode is better suited to high gain applications (greater than
×10). Figure 23 shows a noninverting amplifier with a gain of 10
and a bandwidth of 30 MHz. The transient response is shown in
Figure 26 and Figure 27. To increase the bandwidth at higher
gains, a capacitor can be added across R2 whose value is
approximately (R1/R2) × Ct.
V
= ±15V
= ±5V
S
40
34
28
22
16
V
S
100k
1M
FREQUENCY (Hz)
10M
20M
Figure 33. AC Response for Gain = 100, Configuration Shown in Figure 32
Rev. F | Page 14 of 20
AD844
USING THE AD844
BOARD LAYOUT
As with all high frequency circuits considerable care must be
used in the layout of the components surrounding the AD844.
A ground plane, to which the power supply decoupling capaci-
tors are connected by the shortest possible leads, is essential to
achieving clean pulse response. Even a continuous ground plane
exhibits finite voltage drops between points on the plane, and
this must be kept in mind when selecting the grounding points.
In general, decoupling capacitors should be taken to a point
close to the load (or output connector) because the load
currents flow in these capacitors at high frequencies. The +IN
and −IN circuits (for example, a termination resistor and Pin 3)
must be taken to a common point on the ground plane close to
the amplifier package.
V
6
OUT
AD844
5
C
L
750Ω
22pF
Figure 34. Feedforward Network for Large Capacitive Loads
5V
100
90
Use low impedance 0.22 μF capacitors (AVX SR305C224KAA
or equivalent) wherever ac coupling is required. Include either
ferrite beads and/or a small series resistance (approximately
4.7 Ω) in each supply line.
10
0
500ns
INPUT IMPEDANCE
Figure 35. Driving 1000 pF CL with Feedforward Network of Figure 34
At low frequencies, negative feedback keeps the resistance at the
inverting input close to zero. As the frequency increases, the
impedance looking into this input increases from near zero to
the open-loop input resistance, due to bandwidth limitations,
making the input seem inductive. If it is desired to keep the
input impedance flatter, a series RC network can be inserted
across the input. The resistor is chosen so that the parallel sum
of it and R2 equals the desired termination resistance. The capacit-
ance is set so that the pole determined by this RC network is
about half the bandwidth of the op amp. This network is not
important if the input resistor is much larger than the termination
used, or if frequencies are relatively low. In some cases, the
small peaking that occurs without the network can be of use in
extending the −3 dB bandwidth.
SETTLING TIME
Settling time is measured with the circuit of Figure 36. This
circuit employs a false summing node, clamped by the two
Schottky diodes, to create the error signal and limit the input
signal to the oscilloscope. For measuring settling time, the ratio
of R6/R5 is equal to R1/R2. For unity gain, R6 = R5 = 1 kΩ, and
RL = 500 Ω. For the gain of −10, R5 = 50 Ω, R6 = 500 Ω, and RL
was not used because the summing network loads the output
with approximately 275 Ω. Using this network in a unity-gain
configuration, settling time is 100 ns to 0.1% for a –5 V to +5 V
step with CL = 10 pF.
TO SCOPE
(TEK 7A11 FET PROBE)
DRIVING LARGE CAPACITIVE LOADS
R5
D1
R6
Capacitive drive capability is 100 pF without an external net-
work. With the addition of the network shown in Figure 34,
the capacitive drive can be extended to over 10,000 pF, limited
by internal power dissipation. With capacitive loads, the output
speed becomes a function of the overdriven output current limit.
Because this is roughly 100 mA, under these conditions, the
maximum slew rate into a 1000 pF load is 100 V/μs. Figure 35
shows the transient response of an inverting amplifier (R1 =
R2 = 1 kΩ) using the feedforward network shown in Figure 34,
driving a load of 1000 pF.
D2
R1
V
IN
R2
V
AD844
OUT
R3
R
C
L
L
NOTES
1. D1, D2 IN6263 OR EQUIVALENT SCHOTTKY DIODE.
Figure 36. Settling Time Test Fixture
Rev. F | Page 15 of 20
AD844
+5V
DC ERROR CALCULATION
2.2µF
2.2µF
Figure 37 shows a model of the dc error and noise sources for
the AD844. The inverting input bias current, IBN, flows in the
feedback resistor. IBP, the noninverting input bias current, flows
in the resistance at Pin 3 (RP), and the resulting voltage (plus
any offset voltage) appears at the inverting input. The total
error, VO, at the output is:
3
2
Z
= 50Ω
O
7
V
IN
50Ω
300Ω
300Ω
6
V
OUT
50Ω
R
4
L
50Ω
–5V
R1
R2
⎛
⎝
⎞
⎟
⎠
Figure 38. The AD844 as a Cable Driver
VO =
(
IBP RP + VOS + IBN RIN
)
1 +
+ IBN R1
⎜
Because IBN and IBP are unrelated both in sign and magnitude,
inserting a resistor in series with the noninverting input does
not necessarily reduce dc error and may actually increase it.
V
V
RF OUT
RF IN
IN
IN
IN
OUT
HP8753A
NETWORK
ANALYZER
CIRCUIT
UNDER
TEST
HP11850C
SPLITTER
OUT
V
OUT
OUT
EXT
TRIG
50Ω
R1
(TERMINATOR)
470Ω
SYNC OUT
HP3314A
STAIRCASE
GENERATOR
OUT
V
N
R
R2
IN
Figure 39. Differential Gain/Phase Test Setup
V
OS
I
I
BN
NN
0.3
0.2
0.1
0
IRE = 7.14mV
I
I
BP
NP
AD844
R
P
Figure 37. Offset Voltage and Noise Model for the AD844
–0.1
–0.2
NOISE
Noise sources can be modeled in a manner similar to the dc bias
currents, but the noise sources are INN, INP, VN, and the amplifier
induced noise at the output, VON, is:
–0.3
0
18
36
54
(IRE)
72
90
V
OUT
2
R1
R2
⎛
⎝
⎞
⎟
⎠
2
VON
=
((INP RP
)
+VN
)
1+
+
(
INN R1 2
)
2
Figure 40. Differential Phase for the Circuit of Figure 38
⎜
0.06
0.04
0.02
0
IRE = 7.14mV
Overall noise can be reduced by keeping all resistor values to a
minimum. With typical numbers, R1 = R2 = 1 kΩ, RP = 0 Ω,
VN = 2 nV/√Hz, INP = 10 pA/√Hz, INN = 12 pA/√Hz, and VON
calculates to 12 nV/√Hz. The current noise is dominant in this
case, because it is in most low gain applications.
VIDEO CABLE DRIVER USING 5 V SUPPLIES
The AD844 can be used to drive low impedance cables. Using
5 V supplies, a 100 Ω load can be driven to 2.5 V with low
distortion. Figure 38 shows an illustrative application that
provides a noninverting gain of +2, allowing the cable to be
reverse-terminated while delivering an overall gain of +1 to the
load. The −3 dB bandwidth of this circuit is typically 30 MHz.
Figure 39 shows a differential gain and phase test setup. In video
applications, differential-phase and differential-gain characteris-
tics are often important. Figure 40 shows the variation in phase as
the load voltage varies. Figure 41 shows the gain variation.
–0.02
–0.04
–0.06
0
18
36
54
72
90
V
(IRE)
OUT
Figure 41. Differential Gain for the Circuit of Figure 38
Rev. F | Page 16 of 20
AD844
+15V
–15V
1
2
24
23
22
21
20
19
18
17
16
15
14
13
MSB +15V (VCC
REFCOM
–15V (VEE
)
0.22µF*
0.22µF*
0.22µF*
0.22µF*
3
)
I
4
BPO
7
2
3
5
I
OUT
V
6
AD844
OUT
6
R
L
AD568
DIGITAL
INPUTS
4
R
I
7
ACOM
LCOM
SPAN
ANALOG
SUPPLY
GROUND
8
9
10
11
12
SPAN
GROUND
–5V
THCOM
DIGITAL
SUPPLY
100pF
LSB
V
TH
TOP VIEW
(Not to Scale)
*POWER SUPPLY BYPASS CAPACITORS.
Figure 42. High Speed DAC Amplifier
20 MHZ VARIABLE GAIN AMPLIFIER
HIGH SPEED DAC BUFFER
The AD844 is an excellent choice as an output amplifier for the
AD539 multiplier, in all of its connection modes. (See the
AD539 data sheet for full details.) Figure 44 shows a simple
multiplier providing the output:
The AD844 performs very well in applications requiring current-
to-voltage conversion. Figure 42 shows connections for use with
the AD568 current output DAC. In this application, the bipolar
offset is used so that the full-scale current is 5.12 mA, which
generates an output of 5.12 V using the 1 kΩ application resistor
on the AD568. Figure 43 shows the full-scale transient response.
Care is needed in power supply decoupling and grounding
techniques to achieve the full 12-bit accuracy and realize the
fast settling capabilities of the system. The AD568 data sheet
should be consulted for more complete details about its use.
VXVY
2V
VW = −
(1)
where VX is the gain control input, a positive voltage from 0 V
to 3.2 V (maximum), and VY is the signal voltage, nominally
2 V full scale but capable of operation up to 4.2 V.
The peak output in this configuration is thus 6.7 V. Using all
four of the internal application resistors provided on the AD539
in parallel results in a feedback resistance of 1.5 kΩ, at which
value the bandwidth of the AD844 is about 22 MHz, and is
essentially independent of VX. The gain at VX = 3.16 V is 4 dB.
2V
100
90
+V
S
TYP +6V
AT 15µA
10Ω
10Ω
0.22µF
0.22µF
10
0
INPUTS
V *
X
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
0V TO 3V
50ns
V *
Y
±2V FS
2
7
Figure 43. DAC Amplifier Full-Scale Transient Response
AD539
6
AD844
3nF
OUTPUT
TOP VIEW
4
3
V
(Not to Scale)
W
–V
V
Y
X
V
=
W
2V
0.22µF
INPUT
GND
9
10Ω
–V
TYP –6V
AT 15µA
S
0.22µF
10Ω
*V AND V INPUTS MAY OPTIONALLY BE TERMINATED;
X
Y
TYPICALLY BY USING A 50Ω OR 75Ω RESISTOR TO GROUND.
Figure 44. 20 MHz VGA Using the AD539
Rev. F | Page 17 of 20
AD844
4
–6
V
V
= 3.15V
= 1.0V
Figure 45 shows the small signal response for a 50 dB gain control
range (VX = 10 mV to 3.16 V). At small values of VX, capacitive
feedthrough on the PC board becomes troublesome and very
careful layout techniques are needed to minimize this problem.
A ground strip between the pins of the AD539 is helpful in this
regard. Figure 46 shows the response to a 2 V pulse on VY for
VX = 1 V, 2 V, and 3 V. For these results, a load resistor of 500 Ω
was used and the supplies were 9 V. The multiplier operates
from supplies between 4.5 V and 16.5 V.
X
X
–16
–26
–36
–46
–56
V
= 0.316V
= 0.10V
X
V
X
V
= 0.032V
X
Disconnecting Pin 9 and Pin 16 on the AD539 alters the
denominator in Equation 1 to 1 V, and the bandwidth is
approximately 10 MHz, with a maximum gain of 10 dB.
Using only Pin 9 or Pin 16 results in a denominator of 0.5 V,
a bandwidth of 5 MHz, and a maximum gain of 16 dB.
100k
1M
FREQUENCY (Hz)
10M
60M
Figure 45. VGA AC Response
1V
1V
50ns
100
90
10
0
Figure 46. VGA Transient Response with VX = 1 V, 2 V, and 3 V
Rev. F | Page 18 of 20
AD844
OUTLINE DIMENSIONS
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
8
1
5
4
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.210 (5.33)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
PLANE
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 47. 8-Lead Plastic Dual-in-Line Package [PDIP]
(N-8)
Dimensions shown in inches and (millimeters)
0.005 (0.13)
MIN
0.055 (1.40)
MAX
8
5
0.310 (7.87)
0.220 (5.59)
1
4
0.100 (2.54) BSC
0.405 (10.29) MAX
0.320 (8.13)
0.290 (7.37)
0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
MAX
0.150 (3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
0.023 (0.58)
0.014 (0.36)
15°
0°
0.070 (1.78)
0.030 (0.76)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 48. 8-Lead Ceramic Dual In-Line Package [CERDIP]
(Q-8)
Dimensions shown in inches and (millimeters)
Rev. F | Page 19 of 20
AD844
10.50 (0.4134)
10.10 (0.3976)
16
1
9
8
7.60 (0.2992)
7.40 (0.2913)
10.65 (0.4193)
10.00 (0.3937)
0.75 (0.0295)
0.25 (0.
0098)
1.27 (0.0500)
BSC
45°
2.65 (0.1043)
2.35 (0.0925)
0.30 (0.0118)
0.10 (0.0039)
8°
0°
COPLANARITY
0.10
SEATING
PLANE
0.51 (0.0201)
0.31 (0.0122)
1.27 (0.0500)
0.40 (0.0157)
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 49. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-16)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model
AD844AN
AD844ANZ1
AD844ACHIPS
AD844AQ
AD844BQ
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
Package Description
Package Option
N-8
N-8
Die
Q-8
8-Lead Plastic Dual In-Line Package [PDIP]
8-Lead Plastic Dual In-Line Package [PDIP]
8-Lead Ceramic Dual In-Line Package [CERDIP]
8-Lead Ceramic Dual In-Line Package [CERDIP]
16-Lead Standard Small Outline Package [SOIC_W]
16-Lead SOIC_W, 13”Tape and Reel
16-Lead SOIC_W, 7”Tape and Reel
16-Lead Standard Small Outline Package [SOIC_W]
16-Lead SOIC_W, 13”Tape and Reel
Q-8
AD844JR-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
Die
Q-8
Q-8
Q-8
AD844JR-16-REEL
AD844JR-16-REEL7
AD844JRZ-161
AD844JRZ-16-REEL1
AD844JRZ-16-REEL71
AD844SCHIPS
AD844SQ
0°C to 70°C
16-Lead SOIC_W, 7”Tape and Reel
−55°C to +125°C
−55°C to +125°C
−55°C to +125°C
−55°C to +125°C
8-Lead Ceramic Dual In-Line Package [CERDIP]
8-Lead Ceramic Dual In-Line Package [CERDIP]
8-Lead Ceramic Dual In-Line Package [CERDIP]
AD844SQ/883B
5962-8964401PA2
1 Z = RoHS Compliant Part.
2 Refer to the DESC drawing for tested specifications.
©1989–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00897-0-2/09(F)
Rev. F | Page 20 of 20
相关型号：
AD844SQ-883B
IC OP-AMP, 500 uV OFFSET-MAX, 60 MHz BAND WIDTH, CDIP8, CERDIP-8, Operational Amplifier
ADI
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