AD8510ARMZ [ADI]
Precision, Very Low Noise, Low Input Bias Current; 精密，极低噪声，低输入偏置电流
| 型号： | AD8510ARMZ |
| 厂家： | 
ADI |
| 描述： | Precision, Very Low Noise, Low Input Bias Current |
| 文件： | 总20页 (文件大小：435K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Precision, Very Low Noise, Low Input Bias Current,
Wide Bandwidth JFET Operational Amplifiers
AD8510/AD8512/AD8513
FEATURES
PIN CONFIGURATIONS
Fast settling time: 500 ns to 0.1%
Low offset voltage: 400 μV maximum
Low TCVOS: 1 μV/°C typical
Low input bias current: 25 pA typical at VS = 15 V
Dual-supply operation: 5 V to 15 V
Low noise: 8 nV/√Hz typical at f = 1 kHz
Low distortion: 0.0005%
NULL
–IN
1
2
3
4
8
7
6
5
NC
NULL
–IN
1
2
3
4
8
7
6
5
NC
AD8510
TOP VIEW
AD8510
TOP VIEW
V+
V+
+IN
OUT
NULL
+IN
OUT
NULL
(Not to Scale)
(Not to Scale)
V–
V–
NC = NO CONNECT
NC = NO CONNECT
Figure 1. 8-Lead MSOP (RM Suffix)
Figure 2. 8-Lead SOIC_N (R Suffix)
No phase reversal
Unity gain stable
OUT A
–IN A
+IN A
V–
1
2
3
4
8
7
6
5
V+
OUT A
–IN A
+IN A
V–
1
2
3
4
8
7
6
5
V+
AD8512
TOP VIEW
OUT B
–IN B
+IN B
AD8512
OUT B
–IN B
+IN B
TOP VIEW
(Not to Scale)
(Not to Scale)
APPLICATIONS
Instrumentation
Multipole filters
Precision current measurement
Photodiode amplifiers
Sensors
Figure 3. 8-Lead MSOP (RM Suffix)
Figure 4. 8-Lead SOIC_N (R Suffix)
OUT A
–IN A
+IN A
V+
1
2
3
4
5
6
7
14 OUT D
13 –IN D
12 +IN D
11 V–
OUT A
–IN A
+IN A
V+
1
2
3
4
5
6
7
14 OUT D
13 –IN D
12 +IN D
11 V–
AD8513
TOP VIEW
AD8513
TOP VIEW
Audio
(Not to Scale)
(Not to Scale)
+IN B
–IN B
OUT B
10 +IN C
+IN B
–IN B
OUT B
10 +IN C
9
8
–IN C
9
8
–IN C
OUT C
OUT C
Figure 5. 14-Lead SOIC_N (R Suffix)
Figure 6. 14-Lead TSSOP (RU Suffix)
GENERAL DESCRIPTION
The AD8510/AD8512/AD8513 are single-, dual-, and quad-
precision JFET amplifiers that feature low offset voltage, input
bias current, input voltage noise, and input current noise.
Fast slew rate and great stability with capacitive loads make the
AD8510/AD8512/AD8513 a perfect fit for high performance
filters. Low input bias currents, low offset, and low noise result
in a wide dynamic range of photodiode amplifier circuits. Low
noise and distortion, high output current, and excellent speed
make the AD8510/AD8512/AD8513 great choices for audio
applications.
The combination of low offsets, low noise, and very low input
bias currents makes these amplifiers especially suitable for high
impedance sensor amplification and precise current measurements
using shunts. The combination of dc precision, low noise, and
fast settling time results in superior accuracy in medical
instruments, electronic measurement, and automated test
equipment. Unlike many competitive amplifiers, the AD8510/
AD8512/AD8513 maintain their fast settling performance even
with substantial capacitive loads. Unlike many older JFET
amplifiers, the AD8510/AD8512/AD8513 do not suffer from
output phase reversal when input voltages exceed the maximum
common-mode voltage range.
The AD8510/AD8512 are both available in 8-lead narrow SOIC_N
and 8-lead MSOP packages. MSOP-packaged parts are only
available in tape and reel. The AD8513 is available in 14-lead
SOIC_N and TSSOP packages.
The AD8510/AD8512/AD8513 are specified over the −40°C to
+125°C extended industrial temperature range.
Rev. I
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2002–2009 Analog Devices, Inc. All rights reserved.
AD8510/AD8512/AD8513
TABLE OF CONTENTS
Features .............................................................................................. 1
Output Phase Reversal............................................................... 13
Total Harmonic Distortion (THD) + Noise .............................. 13
Total Noise Including Source Resistors................................... 13
Settling Time............................................................................... 14
Overload Recovery Time .......................................................... 14
Capacitive Load Drive ............................................................... 14
Open-Loop Gain and Phase Response.................................... 15
Precision Rectifiers..................................................................... 16
I-V Conversion Applications.................................................... 17
Outline Dimensions....................................................................... 19
Ordering Guide .......................................................................... 20
Applications....................................................................................... 1
Pin Configurations ........................................................................... 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics............................................................. 4
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Typical Performance Characteristics ............................................. 7
General Application Information................................................. 13
Input Overvoltage Protection ................................................... 13
REVISION HISTORY
2/09—Rev. H to Rev. I
9/03—Rev. B to Rev. C
Changes to Ordering Guide ............................................................4
Updated Figure 2 ............................................................................ 10
Changes to Input Overvoltage Protection Section .................... 10
Changes to Figure 10 and Figure 11............................................. 12
Changes to Photodiode Circuits Section .................................... 13
Changes to Figure 13 and Figure 14............................................. 13
Deleted Precision Current Monitoring Section ......................... 14
Updated Outline Dimensions....................................................... 15
Changes to Figure 25...................................................................... 10
Changes to Ordering Guide .......................................................... 20
10/07—Rev. G to Rev. H
Changes to Crosstalk Section........................................................ 18
Added Figure 58.............................................................................. 18
6/07—Rev. F to Rev. G
Changes to Figure 1 and Figure 2................................................... 1
Changes to Table 1 and Table 2....................................................... 3
Updated Outline Dimensions....................................................... 19
Changes to Ordering Guide .......................................................... 20
3/03—Rev. A to Rev. B
Updated Figure 5 ............................................................................ 11
Updated Outline Dimensions....................................................... 15
6/06—Rev. E to Rev. F
8/02—Rev. 0 to Rev. A
Changes to Figure 23........................................................................ 9
Updated Outline Dimensions....................................................... 19
Changes to Ordering Guide .......................................................... 20
Added AD8510 Model.......................................................Universal
Added Pin Configurations ...............................................................1
Changes to Specifications.................................................................2
Changes to Ordering Guide.............................................................4
Changes to TPC 2 and TPC 3..........................................................5
Added TPC 10 and TPC 12..............................................................6
Replaced TPC 20 ...............................................................................8
Replaced TPC 27 ...............................................................................9
Changes to General Application Information Section.............. 10
Changes to Figure 5........................................................................ 11
Changes to I-V Conversion Applications Section ..................... 13
Changes to Figure 13 and Figure 14............................................. 13
Changes to Figure 17...................................................................... 14
6/04—Rev. D to Rev. E
Changes to Format .............................................................Universal
Changes to Specifications................................................................ 3
Updated Outline Dimensions....................................................... 19
10/03—Rev. C to Rev. D
Added AD8513 Model.......................................................Universal
Changes to Specifications................................................................ 3
Added Figure 36 through Figure 40............................................. 10
Added Figure 55 and Figure 57..................................................... 17
Changes to Ordering Guide .......................................................... 20
Rev. I | Page 2 of 20
AD8510/AD8512/AD8513
SPECIFICATIONS
@ VS = 5 V, VCM = 0 V, TA = 25°C, unless otherwise noted.
Table 1.
Parameter
Symbol
VOS
Conditions
Min
Typ
0.08
0.1
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage (B Grade)1
0.4
0.8
0.9
1.8
75
0.7
7.5
50
mV
mV
mV
mV
pA
nA
nA
pA
nA
nA
−40°C < TA < +125°C
−40°C < TA < +125°C
Offset Voltage (A Grade)
Input Bias Current
VOS
IB
21
−40°C < TA < +85°C
−40°C < TA < +125°C
Input Offset Current
IOS
5
−40°C < TA < +85°C
−40°C < TA < +125°C
0.3
0.5
Input Capacitance
Differential
Common Mode
12.5
11.5
pF
pF
Input Voltage Range
Common-Mode Rejection Ratio
Large-Signal Voltage Gain
Offset Voltage Drift (B Grade)1
Offset Voltage Drift (A Grade)
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Output Voltage High
Output Voltage Low
Output Voltage High
Output Voltage Low
Output Current
−2.0
86
65
+2.5
V
dB
V/mV
μV/°C
μV/°C
CMRR
AVO
ΔVOS/ΔT
ΔVOS/ΔT
VCM = −2.0 V to +2.5 V
RL = 2 kΩ, VO = −3 V to +3 V
100
107
0.9
5
12
1.7
VOH
VOL
VOH
VOL
VOH
VOL
IOUT
RL = 10 kΩ
RL = 10 kΩ, −40°C < TA < +125°C
RL = 2 kΩ
RL = 2 kΩ, −40°C < TA < +125°C
RL = 600 Ω
RL = 600 Ω, −40°C < TA < +125°C
4.1
3.9
3.7
40
4.3
−4.9
4.2
−4.9
4.1
−4.8
54
V
V
V
V
V
V
mA
−4.7
−4.5
−4.2
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current/Amplifier
AD8510/AD8512/AD8513
AD8510/AD8512
PSRR
ISY
VS = 4.5 V to 18 V
86
130
2.0
dB
VO = 0 V
−40°C < TA < +125°C
−40°C < TA < +125°C
2.3
2.5
2.75
mA
mA
mA
AD8513
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
Settling Time
Total Harmonic Distortion (THD) + Noise
Phase Margin
SR
GBP
tS
THD + N
φM
RL = 2 kΩ
20
8
0.4
0.0005
44.5
V/μs
MHz
μs
To 0.1%, 0 V to 4 V step, G = +1
1 kHz, G = +1, RL = 2 kΩ
%
Degrees
NOISE PERFORMANCE
Voltage Noise Density
en
f = 10 Hz
f = 100 Hz
f = 1 kHz
f = 10 kHz
34
12
8.0
7.6
2.4
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
μV p-p
10
Peak-to-Peak Voltage Noise
en p-p
0.1 Hz to 10 Hz bandwidth
5.2
1 AD8510/AD8512 only.
Rev. I | Page 3 of 20
AD8510/AD8512/AD8513
ELECTRICAL CHARACTERISTICS
@ VS = 15 V, VCM = 0 V, TA = 25°C, unless otherwise noted.
Table 2.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage (B Grade)1
VOS
0.08
0.4
0.8
mV
mV
−40°C < TA < +125°C
−40°C < TA < +125°C
Offset Voltage (A Grade)
Input Bias Current
VOS
IB
0.1
25
1.0
1.8
80
0.7
10
75
0.3
0.5
mV
mV
pA
nA
nA
pA
nA
nA
−40°C < TA < +85°C
−40°C < TA < +125°C
Input Offset Current
IOS
6
−40°C < TA < +85°C
−40°C < TA < +125°C
Input Capacitance
Differential
Common Mode
12.5
11.5
pF
pF
Input Voltage Range
Common-Mode Rejection Ratio
Large-Signal Voltage Gain
−13.5
86
115
+13.0
V
CMRR
AVO
VCM = −12.5 V to +12.5 V
RL = 2 kΩ, VCM = 0 V,
108
196
dB
V/mV
VO = −13.5 V to +13.5 V
Offset Voltage Drift (B Grade)1
Offset Voltage Drift (A Grade)
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Output Voltage High
ΔVOS/ΔT
ΔVOS/ΔT
1.0
1.7
5
12
μV/°C
μV/°C
VOH
VOL
VOH
VOL
VOH
RL = 10 kΩ
RL = 10 kΩ, −40°C < TA < +125°C
RL = 2 kΩ
RL = 2 kΩ, −40°C < TA < +125°C
RL = 600 Ω
+14.0
+13.8
+14.2
−14.9
+14.1
–14.8
+13.9
V
V
V
V
V
V
−14.6
−14.5
Output Voltage Low
Output Voltage High
+13.5
+11.4
RL = 600 Ω, −40°C < TA < +125°C
RL = 600 Ω
RL = 600 Ω, −40°C < TA < +125°C
Output Voltage Low
VOL
IOUT
−14.3
70
−13.8
−12.1
V
V
mA
Output Current
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current/Amplifier
AD8510/AD8512/AD8513
AD8510/AD8512
PSRR
ISY
VS = 4.5 V to 18 V
86
dB
VO = 0 V
−40°C < TA < +125°C
−40°C < TA < +125°C
2.2
2.5
2.6
3.0
mA
mA
mA
AD8513
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
Settling Time
SR
GBP
tS
RL = 2 kΩ
20
8
0.5
0.9
0.0005
52
V/μs
MHz
μs
μs
%
To 0.1%, 0 V to 10 V step, G = +1
To 0.01%, 0 V to 10 V step, G = +1
1 kHz, G = +1, RL = 2 kΩ
Total Harmonic Distortion (THD) + Noise THD + N
Phase Margin φM
Degrees
Rev. I | Page 4 of 20
AD8510/AD8512/AD8513
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
NOISE PERFORMANCE
Voltage Noise Density
en
f = 10 Hz
f = 100 Hz
f = 1 kHz
f = 10 kHz
34
12
8.0
7.6
2.4
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
μV p-p
10
Peak-to-Peak Voltage Noise
en p-p
0.1 Hz to 10 Hz bandwidth
5.2
1 AD8510/AD8512 only.
Rev. I | Page 5 of 20
AD8510/AD8512/AD8513
ABSOLUTE MAXIMUM RATINGS
Table 3.
Table 4. Thermal Resistance
Package Type
1
θJA
θJC
45
43
36
35
Unit
°C/W
°C/W
°C/W
°C/W
Parameter
Rating
8-Lead MSOP (RM)
8-Lead SOIC_N (R)
14-Lead SOIC_N (R)
14-Lead TSSOP (RU)
210
158
120
180
Supply Voltage
18 V
Input Voltage
VS
Output Short-Circuit Duration to GND
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
Lead Temperature (Soldering, 10 sec)
Observe derating curves
−65°C to +150°C
−40°C to +125°C
−65°C to +150°C
300°C
1 θJA is specified for worst-case conditions, that is, θJA is specified for device
soldered in circuit board for surface-mount packages.
Electrostatic Discharge
(Human Body Model)
2000 V
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. I | Page 6 of 20
AD8510/AD8512/AD8513
TYPICAL PERFORMANCE CHARACTERISTICS
120
100k
10k
1k
V
= ±15V
SY
= 25°C
V
= ±5V, ±15V
SY
T
A
100
80
60
40
20
100
10
0
1
–0.5 –0.4 –0.3 –0.2 –0.1
0
0.1 0.2 0.3 0.4 0.5
–40 –25 –10
5
20
35
50
65
80
95 110 125
INPUT OFFSET VOLTAGE (mV)
TEMPERATURE (°C)
Figure 7. Input Offset Voltage Distribution
Figure 10. Input Bias Current vs. Temperature
30
25
20
1000
100
V
= ±15V
SY
B GRADE
±15V
15
10
10
1
±5V
5
0
0.1
0
1
2
3
4
5
6
–40 –25 –10
5
20
35
50
65
80
95 110 125
T V
C
(µV/°C)
OS
TEMPERATURE (°C)
Figure 11. Input Offset Current vs. Temperature
Figure 8. AD8510/AD8512 TCVOS Distribution
40
35
30
25
20
15
10
5
30
25
20
V
= ±15V
T
A
= 25°C
SY
A GRADE
15
10
5
0
0
8
13
18
23
28
30
0
1
2
3
4
5
6
SUPPLY VOLTAGE (V+ – V– )
T
C
V
OS
(µV/°C)
Figure 9. AD8510/AD8512 TCVOS Distribution
Figure 12. Input Bias Current vs. Supply Voltage
Rev. I | Page 7 of 20
AD8510/AD8512/AD8513
2.0
2.8
T
A
= 25°C
T
A
= 25°C
1.9
1.8
1.7
2.6
2.4
2.2
2.0
1.8
1.6
1.5
1.4
1.3
1.2
1.1
1.0
1.6
1.4
1.2
1.0
8
13
18
23
28
30
8
13
18
23
28
33
SUPPLY VOLTAGE (V+ – V–)
SUPPLY VOLTAGE (V+ – V–)
Figure 13. AD8512 Supply Current per Amplifier vs. Supply Voltage
Figure 16. AD8510 Supply Current vs. Supply Voltage
16
70
60
315
V
V
= ±15V
OL
SY
V
R
C
= ±15V
= 2.5kΩ
= 20pF
SCOPE
= 52°
SY
270
225
180
14
12
10
8
L
V
OH
50
40
30
20
10
Φ
M
135
90
45
6
V
V
OL
V
= ±5V
SY
0
0
–10
–20
–30
4
–45
OH
2
0
–90
–135
50M
0
10
20
30
40
50
60
70
80
10k
100k
1M
10M
LOAD CURRENT (mA)
FREQUENCY (Hz)
Figure 17. Open-Loop Gain and Phase vs. Frequency
Figure 14. AD8510/AD8512 Output Voltage vs. Load Current
2.50
2.25
2.00
1.75
1.50
2.50
2.25
±15V
±5V
2.00
±15V
1.75
±5V
1.50
1.25
1.00
1.25
1.00
–40 –25 –10
5
20
35 50
65
80
95 110 125
–40 –25 –10
5
20
35 50
65
80
95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 18. AD8510 Supply Current vs. Temperature
Figure 15. AD8512 Supply Current per Amplifier vs. Temperature
Rev. I | Page 8 of 20
AD8510/AD8512/AD8513
70
60
300
270
240
210
180
150
120
90
V
V
= ±15V
= 50mV
SY
IN
V
= ±15V, ±5V
SY
50
40
30
20
10
A
= 100
= 10
= 1
V
A
V
= 1
A
V
A
= 100
V
0
–10
–20
–30
A
V
60
A
V
= 10
30
0
100
1k
10k
1M
FREQUENCY (Hz)
10M
100M
100k
1k
10k
100k
FREQUENCY (Hz)
50M
1M
10M
Figure 19. Closed-Loop Gain vs. Frequency
Figure 22. Output Impedance vs. Frequency
1k
100
10
120
100
80
60
40
20
0
V
= ±5V TO ±15V
SY
V
= ±15V
SY
1
1
10
100
1k
10k
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 23. Voltage Noise Density vs. Frequency
Figure 20. CMRR vs. Frequency
120
100
V = ±15V
SY
V
= ±5V, ±15V
SY
80
60
–PSRR
+PSRR
40
20
0
–20
100
1k
10k
100k
1M
10M
100M
TIME (1s/DIV)
FREQUENCY (Hz)
Figure 21. PSRR vs. Frequency
Figure 24. 0.1 Hz to 10 Hz Input Voltage Noise
Rev. I | Page 9 of 20
AD8510/AD8512/AD8513
280
245
210
175
140
105
90
80
70
V
= ±5V TO ±15V
SY
V
R
= ±15V
= 2kΩ
SY
L
60
50
40
30
20
10
0
+OS
–OS
70
35
0
0
1
2
3
4
6
7
9
10
5
8
10k
10
1
100
LOAD CAPACITANCE (pF)
1k
FREQUENCY (Hz)
Figure 25. Voltage Noise Density vs. Frequency
Figure 28. Small-Signal Overshoot vs. Load Capacitance
70
60
50
40
30
20
10
0
315
270
V
R
C
= ±5V
= 2.5kΩ
= 20pF
SCOPE
= 44.5°
V
R
C
A
= ±15V
SY
SY
= 2kΩ
= 100pF
= 1
L
L
L
V
Φ
225
180
135
90
M
45
0
–10
–45
–20
–30
–90
–135
10k
100k
1M
10M
50M
TIME (1µs/DIV)
FREQUENCY (Hz)
Figure 26. Large-Signal Transient Response
Figure 29. Open-Loop Gain and Phase vs. Frequency
120
100
80
60
40
20
0
V
= ±5V
SY
V
= ±15V
SY
R
C
A
= 2kΩ
= 100pF
= 1
L
L
V
100k
FREQUENCY (Hz)
100
1k
10k
1M
10M
100M
TIME (100ns/DIV)
Figure 27. Small-Signal Transient Response
Figure 30. CMRR vs. Frequency
Rev. I | Page 10 of 20
AD8510/AD8512/AD8513
300
270
240
210
180
150
120
V
SY
V
IN
= ±5V
= 50mV
V
= ±5V
= 2kΩ
= 100pF
= 1
SY
R
C
A
L
L
V
A
V
= 1
A
V
= 100
90
60
A
V
= 10
30
0
100
1k
10k
100k
1M
10M
100M
TIME (100ns/DIV)
FREQUENCY (Hz)
Figure 34. Small-Signal Transient Response
Figure 31. Output Impedance vs. Frequency
100
90
V
R
= ±5V
= 2kΩ
V
= ±5V
SY
SY
L
80
70
60
50
40
+OS
–OS
30
20
10
0
1
10
100
LOAD CAPACITANCE (pF)
1k
10k
TIME (1s/DIV)
Figure 32. 0.1 Hz to 10 Hz Input Voltage Noise
Figure 35. Small-Signal Overshoot vs. Load Capacitance
100
90
80
70
60
50
40
30
20
10
V
= ±15V
S
V
= ±5V
= 2kΩ
= 100pF
= 1
SY
R
C
A
L
L
V
0
0
1
2
3
4
5
6
T
V
(µV/°C)
OS
TIME (1µs/DIV)
C
Figure 33. Large-Signal Transient Response
Figure 36. AD8513 TCVOS Distribution
Rev. I | Page 11 of 20
AD8510/AD8512/AD8513
120
100
80
16
14
12
10
8
V
= ±5V
S
V
V
V
= ±15V
SY
OL
OH
60
6
40
V
= ±5V
SY
V
V
OL
OH
4
20
2
0
0
0
1
2
3
4
5
6
0
20
30
40
50
60
70
80
10
T
V
(µV/°C)
OS
C
LOAD CURRENT (mA)
Figure 37. AD8513 TCVOS Distribution
Figure 39. AD8513 Output Voltage vs. Load Current
3.0
2.5
2.0
1.5
1.0
0.5
0
2.5
2.4
2.3
2.2
2.1
2.0
1.9
1.8
1.7
1.6
T
= 25°C
A
±15V
±5V
1.5
–40 –25 –10
5
20
35
50
65
80
95 110 125
8
18
23
28
33
13
TEMPERATURE (°C)
SUPPLY VOLTAGE (V+ – V–)
Figure 38. AD8513 Supply Current per Amplifier vs. Supply Voltage
Figure 40. AD8513 Supply Current per Amplifier vs. Temperature
Rev. I | Page 12 of 20
AD8510/AD8512/AD8513
GENERAL APPLICATION INFORMATION
INPUT OVERVOLTAGE PROTECTION
0.01
V
R
= ±5V
= 100kΩ
SY
L
The AD8510/AD8512/AD8513 have internal protective
circuitry that allows voltages as high as 0.7 V beyond the
supplies to be applied at the input of either terminal without
causing damage. For higher input voltages, a series resistor is
necessary to limit the input current. The resistor value can be
determined from the formula
BW = 22kHz
0.001
VIN −VS
≤ 5 mA
RS
With a very low offset current of <0.5 nA up to 125°C, higher
resistor values can be used in series with the inputs. A 5 kΩ
resistor protects the inputs from voltages as high as 25 V
beyond the supplies and adds less than 10 μV to the offset.
0.0001
20
100
1k
10k 20k
FREQUENCY (Hz)
Figure 42. THD + N vs. Frequency
TOTAL NOISE INCLUDING SOURCE RESISTORS
OUTPUT PHASE REVERSAL
The low input current noise and input bias current of the
AD8510/AD8512/AD8513 make them the ideal amplifiers for
circuits with substantial input source resistance. Input offset
voltage increases by less than 15 nV per 500 Ω of source
resistance at room temperature. The total noise density of the
circuit is
Phase reversal is a change of polarity in the transfer function of
the amplifier. This can occur when the voltage applied at the
input of an amplifier exceeds the maximum common-mode
voltage.
Phase reversal can cause permanent damage to the device and
can result in system lockups. The AD8510/AD8512/AD8513 do
not exhibit phase reversal when input voltages are beyond the
supplies.
2
2
enTOTAL
where:
=
en
+
in RS
)
+ 4kTRS
V
= ±5V
SY
en is the input voltage noise density of the parts.
in is the input current noise density of the parts.
RS is the source resistance at the noninverting terminal.
k is Boltzmann’s constant (1.38 × 10–23 J/K).
A
V
R
L
= 1
= 10kΩ
V
OUT
T is the ambient temperature in Kelvin (T = 273 + °C).
For RS < 3.9 kΩ, en dominates and enTOTAL ≈ en. The current noise
of the AD8510/AD8512/AD8513 is so low that its total density
does not become a significant term unless RS is greater than
165 MΩ, an impractical value for most applications.
V
IN
The total equivalent rms noise over a specific bandwidth is
expressed as
TIME (20µs/DIV)
enTOTAL = enTOTAL BW
Figure 41. No Phase Reversal
where BW is the bandwidth in hertz.
TOTAL HARMONIC DISTORTION (THD) + NOISE
Note that the previous analysis is valid for frequencies larger
than 150 Hz and assumes flat noise above 10 kHz. For lower
frequencies, flicker noise (1/f) must be considered.
The AD8510/AD8512/AD8513 have low THD and excellent gain
linearity, making these amplifiers great choices for precision
circuits with high closed-loop gain and for audio application
circuits. Figure 42 shows that the AD8510/AD8512/AD8513 have
approximately 0.0005% of total distortion when configured in
positive unity gain (the worst case) and driving a 100 kΩ load.
Rev. I | Page 13 of 20
AD8510/AD8512/AD8513
SETTLING TIME
V
A
R
= ±15V
= –100
= 10kΩ
SY
V
L
Settling time is the time it takes the output of the amplifier to
reach and remain within a percentage of its final value after a
pulse is applied at the input. The AD8510/AD8512/AD8513
settle to within 0.01% in less than 900 ns with a step of 0 V to
10 V in unity gain. This makes each of these parts an excellent
choice as a buffer at the output of DACs whose settling time is
typically less than 1 μs.
+15V
0V
0V
–200mV
In addition to the fast settling time and fast slew rate, low offset
voltage drift and input offset current maintain the full accuracy
of 12-bit converters over the entire operating temperature range.
TIME (2µs/DIV)
OVERLOAD RECOVERY TIME
Figure 44. Negative Overload Recovery
Overload recovery, also known as overdrive recovery, is the
time it takes the output of an amplifier to recover to its linear
region from a saturated condition. This recovery time is par-
ticularly important in applications where the amplifier must
amplify small signals in the presence of large transient voltages.
CAPACITIVE LOAD DRIVE
The AD8510/AD8512/AD8513 are unconditionally stable at all
gains in inverting and noninverting configurations. Each device
is capable of driving a capacitive load of up to 1000 pF without
oscillation in unity gain using the worst-case configuration.
Figure 43 shows the positive overload recovery of the AD8510/
AD8512/AD8513. The output recovers in approximately 200 ns
from a saturated condition.
However, as with most amplifiers, driving larger capacitive
loads in a unity gain configuration may cause excessive
overshoot and ringing, or even oscillation. A simple snubber
network significantly reduces the amount of overshoot and
ringing. The advantage of this configuration is that the output
swing of the amplifier is not reduced, because RS is outside the
feedback loop.
V
V
A
R
= ±15V
= 200mV
= –100
SY
IN
0V
V
L
= 10kΩ
–15V
V+
200mV
0V
2
7
6
V
OUT
AD8510
4
3
200mV
R
S
TIME (2µs/DIV)
C
S
C
L
Figure 43. Positive Overload Recovery
V–
Figure 45. Snubber Network Configuration
The negative overdrive recovery time shown in Figure 44 is less
than 200 ns.
In addition to the fast recovery time, the AD8510/AD8512/
AD8513 show excellent symmetry of the positive and negative
recovery times. This is an important feature for transient signal
rectification because the output signal is kept equally undistorted
throughout any given period.
Rev. I | Page 14 of 20
AD8510/AD8512/AD8513
Figure 46 shows a scope plot of the output of the AD8510/AD8512/
AD8513 in response to a 400 mV pulse. The circuit is configured in
positive unity gain (worst case) with a load experience of 500 pF.
OPEN-LOOP GAIN AND PHASE RESPONSE
In addition to their impressive low noise, low offset voltage, and
offset current, the AD8510/AD8512/AD8513 have excellent
loop gain and phase response even when driving large resistive
and capacitive loads.
V
= ±15V
= 500pF
=10kΩ
SY
C
L
R
L
Compared with Competitor A (see Figure 49) under the same
conditions, with a 2.5 kΩ load at the output, the AD8510/AD8512/
AD8513 have more than 8 MHz of bandwidth and a phase margin
of more than 52°.
Competitor A, on the other hand, has only 4.5 MHz of band-
width and 28° of phase margin under the same test conditions.
Even with a 1 nF capacitive load in parallel with the 2 kΩ load
at the output, the AD8510/AD8512/AD8513 show much better
response than Competitor A, whose phase margin is degraded
to less than 0, indicating oscillation.
TIME (1µs/DIV)
70
315
270
225
180
Figure 46. Capacitive Load Drive Without Snubber
V
R
C
= ±15V
= 2.5kΩ
= 0pF
SY
60
L
L
When the snubber circuit is used, the overshoot is reduced from
55% to less than 3% with the same load capacitance. Ringing is
virtually eliminated, as shown in Figure 47.
50
40
30
20
10
135
90
V
= ±15V
= 10kΩ
= 500pF
= 100Ω
= 1nF
SY
R
C
R
C
L
L
S
S
45
0
0
–10
–20
–30
–45
–90
–135
50M
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 48. Frequency Response of the AD8510/AD8512/AD8513
70
315
270
225
180
V
R
C
= ±15V
= 2.5kΩ
= 0pF
SY
TIME (1µs/DIV)
60
L
L
Figure 47. Capacitive Load with Snubber Network
50
40
30
20
10
Optimum values for RS and CS depend on the load capacitance
and input stray capacitance and are determined empirically.
Table 5 shows a few values that can be used as starting points.
135
90
Table 5. Optimum Values for Capacitive Loads
45
CLOAD
500 pF
2 nF
RS (Ω)
100
70
CS
0
0
–10
–20
–30
1 nF
100 pF
300 pF
–45
–90
5 nF
60
–135
50M
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 49. Frequency Response of Competitor A
Rev. I | Page 15 of 20
AD8510/AD8512/AD8513
PRECISION RECTIFIERS
Rectifying circuits are used in a multitude of applications. One
of the most popular uses is in the design of regulated power
supplies, where a rectifier circuit is used to convert an input
sinusoid to a unipolar output voltage.
However, there are some potential problems with amplifiers
used in this manner. When the input voltage (VIN) is negative,
the output is zero, and the magnitude of VIN is doubled at the
inputs of the op amp. If this voltage exceeds the power supply
voltage, it may permanently damage some amplifiers. In addition,
the op amp must come out of saturation when VIN is negative.
This delays the output signal because the amplifier requires
time to enter its linear region.
TIME (1ms/DIV)
Although the AD8510/AD8512/AD8513 have a very fast
overdrive recovery time, which makes them great choices for the
rectification of transient signals, the symmetry of the positive
and negative recovery times is also important to keep the output
signal undistorted.
Figure 51. Half-Wave Rectifier Signal (OUT A in Figure 50)
Figure 50 shows the test circuit of the rectifier. The first stage of
the circuit is a half-wave rectifier. When the sine wave applied at
the input is positive, the output follows the input response.
During the negative cycle of the input, the output tries to swing
negative to follow the input, but the power supply restrains it to
zero. In a similar fashion, the second stage is a follower during
the positive cycle of the sine wave and an inverter during the
negative cycle.
R2
R3
10kΩ
10kΩ
TIME (1ms/DIV)
Figure 52. Full-Wave Rectifier Signal (OUT B in Figure 50)
10V
V
IN
3V p-p
6
5
4
2/2
7
3
2
AD8512
8
1/2
OUT B
(FULL WAVE)
R1
1kΩ
8
1
AD8512
4
10V
OUT A
(HALF WAVE)
Figure 50. Half-Wave and Full-Wave Rectifiers
Rev. I | Page 16 of 20
AD8510/AD8512/AD8513
A typical value for Rd is 1000 MΩ. Because Rd >> R2, the
circuit behavior is not impacted by the effect of the junction
resistance. The maximum signal bandwidth is
I-V CONVERSION APPLICATIONS
Photodiode Circuits
Common applications for I-V conversion include photodiode
circuits where the amplifier is used to convert a current emitted
by a diode placed at the positive input terminal into an output
voltage.
ft
fMAX
=
2πR2Ct
where ft is the unity gain frequency of the amplifier.
The AD8510/AD8512/AD8513’s low input bias current, wide
bandwidth, and low noise make them each an excellent choice
for various photodiode applications, including fax machines,
fiber optic controls, motion sensors, and bar code readers.
Cf can be calculated by
Ct
Cf =
2πR2 ft
The circuit shown in Figure 53 uses a silicon diode with zero
bias voltage. This is known as a photovoltaic mode; this
configuration limits the overall noise and is suitable for
instrumentation applications.
where ft is the unity gain frequency of the op amp, and it achieves
a phase margin, φM, of approximately 45°.
A higher phase margin can be obtained by increasing the value
of Cf. Setting Cf to twice the previous value yields approximately
φM = 65° and a maximal flat frequency response, but it reduces the
maximum signal bandwidth by 50%.
Cf
R2
Using the previous parameters with a Cf ≈ 1 pF, the signal
bandwidth is approximately 2.6 MHz.
VEE
Signal Transmission Applications
4
2
One popular signal transmission method uses pulse-width
modulation. High data rates may require a fast comparator
rather than an op amp. However, the need for sharp, undistorted
signals may favor using a linear amplifier.
6
AD8510
3
Rd
Ct
7
VCC
The AD8510/AD8512/AD8513 make excellent voltage
comparators. In addition to a high slew rate, the AD8510/
AD8512/AD8513 have a very fast saturation recovery time. In
the absence of feedback, the amplifiers are in open-loop mode
(very high gain). In this mode of operation, they spend much of
their time in saturation.
Figure 53. Equivalent Preamplifier Photodiode Circuit
A larger signal bandwidth can be attained at the expense of
additional output noise. The total input capacitance (Ct)
consists of the sum of the diode capacitance (typically 3 pF to
4 pF) and the amplifier’s input capacitance (12 pF), which
includes external parasitic capacitance. Ct creates a pole in the
frequency response that can lead to an unstable system. To
ensure stability and optimize the bandwidth of the signal, a
capacitor is placed in the feedback loop of the circuit shown in
Figure 53. It creates a zero and yields a bandwidth whose corner
frequency is 1/(2π(R2Cf)).
The circuit shown in Figure 54 was used to compare two signals
of different frequencies, namely a 100 Hz sine wave and a 1 kHz
triangular wave. Figure 55 shows a scope plot of the resulting
output waveforms. A pull-up resistor (typically 5 kΩ) can be
connected from the output to VCC if the output voltage needs to
reach the positive rail. The trade-off is that power consumption
is higher.
The value of R2 can be determined by the ratio
+15V
V/ID
where:
3
7
6
V is the desired output voltage of the op amp.
V
OUT
ID is the diode current.
2
4
V1
For example, if ID is 100 μA and a 10 V output voltage is desired,
R2 should be 100 kΩ. Rd (see Figure 53) is a junction resistance
that drops typically by a factor of 2 for every 10°C increase in
temperature.
–15V
V2
Figure 54. Pulse-Width Modulator
Rev. I | Page 17 of 20
AD8510/AD8512/AD8513
The AD8510 single has two additional active terminals that are
not present on the AD8512 dual or AD8513 quad parts. These
pins are labeled “null” and are used for fine adjustment of the
input offset voltage. Although the guaranteed maximum offset
voltage at room temperature is 400 μV and over the −40°C to
+125°C range is 800 mV maximum, this offset voltage can be
reduced by adding a potentiometer to the null pins as shown in
Figure 58. With the 20 kꢀ potentiometer shown, the adjustment
range is approximately 3.5 mV. The potentiometer parallels
low value resistors in the drain circuit of the JFET differential
input pair and allows unbalancing of the drain currents to
change the offset voltage. If offset adjustment is not required,
these pins should be left unconnected.
TIME (2ms/DIV)
Caution should be used when adding adjusting potentiometers to
any op amp with this capability for several reasons. First, there is
gain from these nodes to the output; therefore, capacitive coupling
from noisy traces to these nodes will inject noise into the signal
path. Second, the temperature coefficient of the potentiometer
will not match the temperature coefficient of the internal resistors,
so the offset voltage drift with temperature will be slightly affected.
Third, this provision is for adjusting the offset voltage of the
op amp, not for adjusting the offset of the overall system. Although
it is tempting to decrease the value of the potentiometer to attain
more range, this will adversely affect the dc and ac parameters.
Instead, increase the potentiometer to 50 kΩ to decrease the
range if needed.
Figure 55. Pulse-Width Modulation
Crosstalk
Crosstalk, also known as channel separation, is a measure of
signal feedthrough from one channel to another on the same
IC. The AD8512/AD8513 have a channel separation of better
than −90 dB for frequencies up to 10 kHz and of better than
−50 dB for frequencies up to 10 MHz. Figure 57 shows the
typical channel separation behavior between Amplifier A
(driving amplifier) and each of the following: Amplifier B,
Amplifier C, and Amplifier D.
V
OUT
20kΩ
2.2kΩ
20kΩ
+V
S
V+
2
3
6
5
8
1
1
7
18V p-p
5
2
3
–
INPUT
+
7
6
OUTPUT
AD8510
4
5kΩ
5kΩ
V
IN
–V
V
S
OUT
10V
4
CROSSTALK = 20 log
V
TRIM RANGE IS
OS
IN
TYPICALLY ±3.5mV
Figure 56. Crosstalk Test Circuit
V–
0
–20
Figure 58. Optional Offset Nulling Circuit
–40
–60
CH B
CH D
CH C
–80
–100
–120
–140
–160
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 57. Channel Separation
Rev. I | Page 18 of 20
AD8510/AD8512/AD8513
OUTLINE DIMENSIONS
5.10
5.00
4.90
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
14
8
7
4.00 (0.1574)
3.80 (0.1497)
4.50
4.40
4.30
6.40
BSC
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
1
0.25 (0.0098)
0.10 (0.0040)
8°
0°
PIN 1
0.65
BSC
1.05
1.00
0.80
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
0.20
1.20
SEATING
PLANE
0.75
0.60
0.45
0.09
MAX
8°
0°
0.15
0.05
0.30
0.19
COMPLIANT TO JEDEC STANDARDS MS-012-AA
SEATING
PLANE
COPLANARITY
0.10
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 59. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-8)
Figure 61. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters and (inches)
Dimensions shown in millimeters
3.20
3.00
2.80
8.75 (0.3445)
8.55 (0.3366)
8
1
5
4
5.15
4.90
4.65
3.20
3.00
2.80
8
14
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
1
7
PIN 1
1.27 (0.0500)
BSC
0.65 BSC
0.50 (0.0197)
0.25 (0.0098)
45°
1.75 (0.0689)
1.35 (0.0531)
0.95
0.85
0.75
0.25 (0.0098)
0.10 (0.0039)
8°
0°
1.10 MAX
COPLANARITY
0.10
SEATING
PLANE
0.80
0.60
0.40
1.27 (0.0500)
0.40 (0.0157)
0.51 (0.0201)
0.31 (0.0122)
0.25 (0.0098)
0.17 (0.0067)
8°
0°
0.15
0.00
0.38
0.22
0.23
0.08
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MS-012-AB
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 62. 14-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-14)
Figure 60. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters and (inches)
Dimensions shown in millimeters
Rev. I | Page 19 of 20
AD8510/AD8512/AD8513
ORDERING GUIDE
Model
Temperature Range
Package Description
8-Lead MSOP
8-Lead MSOP
Package Option
RM-8
RM-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
Branding
B7A#
B7A#
AD8510ARMZ-REEL1
AD8510ARMZ1
AD8510AR
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead MSOP
AD8510ARZ1
AD8510ARZ-REEL1
AD8510ARZ-REEL71
AD8510BR
AD8510BR-REEL
AD8510BRZ1
AD8510BRZ-REEL1
AD8510BRZ-REEL71
AD8512ARMZ-REEL1
AD8512ARMZ1
AD8512AR
AD8512AR-REEL
AD8512AR-REEL7
AD8512ARZ1
AD8512ARZ-REEL1
AD8512ARZ-REEL71
AD8512BR
AD8512BR-REEL
AD8512BR-REEL7
AD8512BRZ1
AD8512BRZ-REEL1
AD8512BRZ-REEL71
AD8513AR
AD8513AR-REEL
AD8513AR-REEL7
AD8513ARZ1
AD8513ARZ-REEL1
AD8513ARZ-REEL71
AD8513ARU
AD8513ARU-REEL
AD8513ARUZ1
AD8513ARUZ-REEL1
R-8
R-8
RM-8
RM-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
B8A#
B8A#
8-Lead MSOP
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
R-8
R-14
R-14
R-14
R-14
R-14
R-14
RU-14
RU-14
RU-14
RU-14
1 Z = RoHS Compliant Part, # denotes RoHS compliant product may be top or bottom marked.
©2002–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02729-0-2/09(I)
Rev. I | Page 20 of 20
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