AD8546ARMZ [ADI]
22 μA, RRIO, CMOS, 18 V; 22 μA ， RRIO ， CMOS ， 18 V
| 型号： | AD8546ARMZ |
| 厂家： | 
ADI |
| 描述： | 22 μA, RRIO, CMOS, 18 V |
| 文件： | 总24页 (文件大小：682K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
22 μA, RRIO, CMOS, 18 V
Operational Amplifier
AD8546/AD8548
Data Sheet
FEATURES
PIN CONFIGURATIONS
Micropower at high voltage: 22 μA maximum
Low input bias current: 20 pA maximum
Gain bandwidth product: 240 kHz
Slew rate: 80 V/ms
OUT A
–IN A
+IN A
V–
1
2
3
4
8
7
6
5
V+
AD8546
OUT B
–IN B
+IN B
TOP VIEW
(Not to Scale)
Large signal voltage gain: 110 dB minimum
Single-supply operation: 2.7 V to 18 V
Dual-supply operation: 1.35 V to 9 V
Unity-gain stable
Figure 1. AD8546 (8-Lead MSOP)
OUT A
–IN A
+IN A
V+
1
2
3
4
5
6
7
14 OUT D
13 –IN D
12 +IN D
11 V–
AD8548
TOP VIEW
APPLICATIONS
(Not to Scale)
+IN B
–IN B
OUT B
10 +IN C
Portable medical equipment
Remote sensors
9
8
–IN C
OUT C
Transimpedance amplifiers
Current monitors
Figure 2. AD8548 (14-Lead SOIC_N)
4 mA to 20 mA loop drivers
Buffer/level shifting
Table 1. Micropower Op Amps1
GENERAL DESCRIPTION
The AD8546 and AD8548 are dual and quad micropower, high
input impedance amplifiers optimized for low power and wide
operating supply voltage range applications.
Supply Voltage
12 V to 18 V
AD8663
Amplifier
5 V
36 V
Single
AD8500
AD8505
AD8541
AD8603
ADA4505-1
AD8502
AD8506
AD8542
AD8607
ADA4505-2
AD8504
AD8508
AD8544
AD8609
ADA4505-4
The AD8546/AD8548 rail-to-rail input/output (RRIO) feature
provides increased dynamic range to drive low frequency data
converters, making these amplifiers ideal for dc gain and buffering
of sensor front ends or high impedance input sources used in
wireless or remote sensors or transmitters.
Dual
AD8546
AD8657
AD8667
OP281
OP295
ADA4062-2
The low supply current specification (22 μA) of the AD8546/
AD8548 over a wide operating voltage range of 2.7 V to 18 V
or dual supplies (±1.ꢀ5 V to ±± V) makes these amplifiers useful
for a variety of battery-powered, portable applications, such as
ECGs, pulse monitors, glucose meters, smoke and fire detectors,
vibration monitors, and backup battery sensors.
Quad
AD8548
AD8669
OP481
OP495
ADA4062-4
The AD8546/AD8548 are specified over the extended industrial
temperature range of −40°C to +125°C. The AD8546 is available
in an 8-lead MSOP package; the AD8548 is available in a 14-lead
SOIC_N package.
1 See www.analog.com for the latest selection of micropower op amps.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2011–2012 Analog Devices, Inc. All rights reserved.
AD8546/AD8548
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ..............................................7
Applications Information .............................................................. 17
Input Stage................................................................................... 17
Output Stage................................................................................ 18
Rail-to-Rail Input and Output.................................................. 18
Resistive Load ............................................................................. 18
Comparator Operation.............................................................. 19
4 mA to 20 mA Process Control Current Loop Transmitter .. 20
Outline Dimensions....................................................................... 21
Ordering Guide .......................................................................... 21
Applications....................................................................................... 1
Pin Configurations ........................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics—18 V Operation ............................. 3
Electrical Characteristics—10 V Operation ............................. 4
Electrical Characteristics—2.7 V Operation ............................ 5
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
REVISION HISTORY
4/12—Rev. A to Rev. B
Added AD8548 and 14-Lead SOIC..................................Universal
Changes to Product Title, Features Section, General
Changes to Figure 9, Figure 10, Figure 12, and Figure 13............8
Changes to Figure 22 and Figure 25 ............................................ 10
Changes to Figure 33...................................................................... 12
Changes to Figure 63 and Figure 64 ............................................ 18
Updated Outline Dimensions....................................................... 21
Added Figure 72 ............................................................................. 21
Changes to Ordering Guide.......................................................... 21
Description Section, and Table 1.................................................... 1
Added Figure 2; Renumbered Figures Sequentially..................... 1
Moved Electrical Characteristics—18 V Operation Section ...... 3
Changes to Table 2............................................................................ 3
Changes to Table 3............................................................................ 4
Moved Electrical Characteristics—2.7 V Operation Section ..... 5
Changes to Table 4............................................................................ 5
Changes to Table 6............................................................................ 6
Changes to Figure 4, Figure 5, Figure 7, and Figure 8 ................. 7
Deleted Figure 8 and Figure 11....................................................... 8
4/11—Rev. 0 to Rev. A
Changes to Product Title, Features Section, Applications
Section, General Description Section, and Table 1.......................1
1/11—Revision 0: Initial Version
Rev. B | Page 2 of 24
Data Sheet
AD8546/AD8548
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—18 V OPERATION
VSY = 18 V, VCM = VSY/2, TA = 25°C, unless otherwise noted.
Table 2.
Parameter
Symbol Test Conditions/Comments
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
VOS
VCM = 0 V to 18 V
VCM = 0.3 V to 17.7 V; −40°C ≤ TA ≤ +125°C
VCM = 0 V to 18 V; −40°C ≤ TA ≤ +125°C
3
7
12
mV
mV
mV
µV/°C
pA
nA
pA
nA
V
Offset Voltage Drift
Input Bias Current
ΔVOS/ΔT
IB
3
5
20
2.6
40
5.2
18
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
VCM = 0 V to 18 V
Input Offset Current
IOS
Input Voltage Range
Common-Mode Rejection Ratio
IVR
CMRR
0
74
95
dB
VCM = 0.3 V to 17.7 V; −40°C ≤ TA ≤ +125°C 68
dB
VCM = 0 V to 18 V; −40°C ≤ TA ≤ +125°C
RL = 100 kΩ; VO = 0.5 V to 17.5 V
−40°C ≤ TA ≤ +125°C
65
110
105
dB
dB
dB
GΩ
Large Signal Voltage Gain
AVO
RIN
125
10
Input Resistance
Input Capacitance
Differential Mode
Common Mode
CINDM
CINCM
3.5
10.5
pF
pF
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Short-Circuit Current
Closed-Loop Output Impedance
POWER SUPPLY
VOH
VOL
ISC
RL = 100 kΩ to VCM; −40°C ≤ TA ≤ +125°C
RL = 100 kΩ to VCM; −40°C ≤ TA ≤ +125°C
17.97
V
30
mV
mA
Ω
12
15
ZOUT
f = 1 kHz; AV = +1
Power Supply Rejection Ratio
PSRR
ISY
VSY = 2.7 V to 18 V
−40°C ≤ TA ≤ +125°C
IO = 0 mA
95
90
115
18
dB
dB
µA
µA
Supply Current per Amplifier
22
33
−40°C ≤ TA ≤ +125°C
DYNAMIC PERFORMANCE
Slew Rate
Settling Time to 0.1%
Gain Bandwidth Product
Phase Margin
Channel Separation
NOISE PERFORMANCE
Voltage Noise
SR
tS
GBP
ΦM
CS
RL = 1 MΩ; CL = 10 pF; AV = +1
VIN = 1 V step; RL = 100 kΩ; CL = 10 pF
RL = 1 MΩ; CL = 10 pF; AV = +1
RL = 1 MΩ; CL = 10 pF; AV = +1
f = 10 kHz; RL = 1 MΩ
80
15
240
60
105
V/ms
µs
kHz
Degrees
dB
en p-p
en
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 10 kHz
5
µV p-p
nV/√Hz
nV/√Hz
pA/√Hz
Voltage Noise Density
50
45
0.1
Current Noise Density
in
f = 1 kHz
Rev. B | Page 3 of 24
AD8546/AD8548
Data Sheet
ELECTRICAL CHARACTERISTICS—10 V OPERATION
VSY = 10 V, V CM = VSY/2, TA = 25°C, unless otherwise noted.
Table 3.
Parameter
Symbol Test Conditions/Comments
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
VOS
VCM = 0 V to 10 V
VCM = 0.3 V to 9.7 V; −40°C ≤ TA ≤ +125°C
VCM = 0 V to 10 V; −40°C ≤ TA ≤ +125°C
3
8
12
mV
mV
mV
µV/°C
pA
nA
pA
nA
V
Offset Voltage Drift
Input Bias Current
ΔVOS/ΔT
IB
3
2
15
2.6
30
5.2
10
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
Input Offset Current
IOS
Input Voltage Range
IVR
0
Common-Mode Rejection Ratio
CMRR
VCM = 0 V to 10 V
70
62
60
105
100
88
dB
dB
dB
dB
dB
GΩ
VCM = 0.3 V to 9.7 V; −40°C ≤ TA ≤ +125°C
VCM = 0 V to 10 V; −40°C ≤ TA ≤ +125°C
RL = 100 kΩ; VO = 0.5 V to 9.5 V
−40°C ≤ TA ≤ +125°C
Large Signal Voltage Gain
AVO
RIN
120
10
Input Resistance
Input Capacitance
Differential Mode
Common Mode
CINDM
CINCM
3.5
3.5
pF
pF
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Short-Circuit Current
Closed-Loop Output Impedance
POWER SUPPLY
VOH
VOL
ISC
RL = 100 kΩ to VCM; −40°C ≤ TA ≤ +125°C
RL = 100 kΩ to VCM; −40°C ≤ TA ≤ +125°C
9.98
V
20
mV
mA
Ω
11
15
ZOUT
f = 1 kHz; AV = +1
Power Supply Rejection Ratio
PSRR
ISY
VSY = 2.7 V to 18 V
−40°C ≤ TA ≤ +125°C
IO = 0 mA
95
90
115
18
dB
dB
µA
µA
Supply Current per Amplifier
22
33
−40°C ≤ TA ≤ +125°C
DYNAMIC PERFORMANCE
Slew Rate
Settling Time to 0.1%
Gain Bandwidth Product
Phase Margin
Channel Separation
NOISE PERFORMANCE
Voltage Noise
SR
tS
GBP
ΦM
CS
RL = 1 MΩ; CL = 10 pF; AV = +1
VIN = 1 V step; RL = 100 kΩ; CL = 10 pF
RL = 1 MΩ; CL = 10 pF; AV = +1
RL = 1 MΩ; CL = 10 pF; AV = +1
f = 10 kHz; RL = 1 MΩ
75
15
235
60
105
V/ms
µs
kHz
Degrees
dB
en p-p
en
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 10 kHz
5
µV p-p
nV/√Hz
nV/√Hz
pA/√Hz
Voltage Noise Density
50
45
0.1
Current Noise Density
in
f = 1 kHz
Rev. B | Page 4 of 24
Data Sheet
AD8546/AD8548
ELECTRICAL CHARACTERISTICS—2.7 V OPERATION
VSY = 2.7 V, V CM = VSY/2, TA = 25°C, unless otherwise noted.
Table 4.
Parameter
Symbol Test Conditions/Comments
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
VOS
VCM = 0 V to 2.7 V
VCM = 0.3 V to 2.4 V; −40°C ≤ TA ≤ +125°C
VCM = 0 V to 2.7 V; −40°C ≤ TA ≤ +125°C
3
4
12
mV
mV
mV
µV/°C
pA
nA
pA
nA
V
Offset Voltage Drift
Input Bias Current
ΔVOS/ΔT
IB
3
1
10
2.6
20
5.2
2.7
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
Input Offset Current
IOS
Input Voltage Range
IVR
0
Common-Mode Rejection Ratio
CMRR
VCM = 0 V to 2.7 V
60
58
49
97
90
75
dB
dB
dB
dB
dB
GΩ
VCM = 0.3 V to 2.4 V; −40°C ≤ TA ≤ +125°C
VCM = 0 V to 2.7 V; −40°C ≤ TA ≤ +125°C
RL = 100 kΩ; VO = 0.5 V to 2.2 V
−40°C ≤ TA ≤ +125°C
Large Signal Voltage Gain
AVO
RIN
115
10
Input Resistance
Input Capacitance
Differential Mode
Common Mode
CINDM
CINCM
3.5
3.5
pF
pF
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Short-Circuit Current
Closed-Loop Output Impedance
POWER SUPPLY
VOH
VOL
ISC
RL = 100 kΩ to VCM; −40°C ≤ TA ≤ +125°C
RL = 100 kΩ to VCM; −40°C ≤ TA ≤ +125°C
2.69
V
10
mV
mA
Ω
4
20
ZOUT
f = 1 kHz; AV = +1
Power Supply Rejection Ratio
PSRR
ISY
VSY = 2.7 V to 18 V
−40°C ≤ TA ≤ +125°C
IO = 0 mA
95
90
115
18
dB
dB
µA
µA
Supply Current per Amplifier
22
33
−40°C ≤ TA ≤ +125°C
DYNAMIC PERFORMANCE
Slew Rate
Settling Time to 0.1%
Gain Bandwidth Product
Phase Margin
Channel Separation
NOISE PERFORMANCE
Voltage Noise
SR
tS
GBP
ΦM
CS
RL = 1 MΩ; CL = 10 pF; AV = +1
VIN = 1 V step; RL = 100 kΩ; CL = 10 pF
RL = 1 MΩ; CL = 10 pF; AV = +1
RL = 1 MΩ; CL = 10 pF; AV = +1
f = 10 kHz; RL = 1 MΩ
50
20
190
60
105
V/ms
µs
kHz
Degrees
dB
en p-p
en
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 10 kHz
6
µV p-p
nV/√Hz
nV/√Hz
pA/√Hz
Voltage Noise Density
60
56
0.1
Current Noise Density
in
f = 1 kHz
Rev. B | Page 5 of 24
AD8546/AD8548
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 5.
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages using
a standard 4-layer board.
Parameter
Rating
Supply Voltage
Input Voltage
Input Current1
Differential Input Voltage
Output Short-Circuit Duration Indefinite
to GND
20.5 V
(V−) − 300 mV to (V+) + 300 mV
10 mA
VSY
Table 6. Thermal Resistance
Package Type
θJA
θJC
45
36
Unit
°C/W
°C/W
8-Lead MSOP (RM-8)
14-Lead SOIC_N (R-14)
142
115
Storage Temperature Range
−65°C to +150°C
Operating Temperature Range −40°C to +125°C
Junction Temperature Range
Lead Temperature
(Soldering, 60 sec)
−65°C to +150°C
300°C
ESD CAUTION
1 The input pins have clamp diodes to the power supply pins. Limit the input
current to 10 mA or less whenever input signals exceed the power supply
rail by 0.3 V.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. B | Page 6 of 24
Data Sheet
AD8546/AD8548
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
40
40
35
30
25
V
V
= 18V
SY
V
V
= 2.7V
= V /2
SY
SY
= V /2
CM
SY
35
30
25
CM
20
15
20
15
10
5
10
5
0
0
V
(mV)
V
(mV)
OS
OS
Figure 3. Input Offset Voltage Distribution
Figure 6. Input Offset Voltage Distribution
70
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
V
= 2.7V
V
= 18V
SY
SY
–40°C ≤ T ≤ +125°C
–40°C ≤ T ≤ +125°C
A
A
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
TCV (µV/°C)
OS
TCV (µV/°C)
OS
Figure 7. Input Offset Voltage Drift Distribution
Figure 4. Input Offset Voltage Drift Distribution
3.0
2.5
3.0
2.5
V
= 18V
V
= 2.7V
SY
SY
2.0
2.0
1.5
1.5
1.0
1.0
0.5
0.5
0
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
0
0.3
0.6
0.9
1.2
1.5
(V)
1.8
2.1
2.4
2.7
0
2
4
6
8
10
(V)
12
14
16
18
V
V
CM
CM
Figure 5. Input Offset Voltage vs. Common-Mode Voltage
Figure 8. Input Offset Voltage vs. Common-Mode Voltage
Rev. B | Page 7 of 24
AD8546/AD8548
Data Sheet
6
4
6
V
= 18V
V
= 2.7V
SY
SY
–40°C ≤ T ≤ +125°C
–40°C ≤ T ≤ +125°C
A
A
4
2
2
0
0
–2
–4
–6
–2
–4
–6
0
0.3
0.6
0.9
1.2
1.5
(V)
1.8
2.1
2.4
2.7
0
3
6
9
12
15
18
V
V
(V)
CM
CM
Figure 9. Input Offset Voltage vs. Common-Mode Voltage
Figure 12. Input Offset Voltage vs. Common-Mode Voltage
10000
1000
100
10
10000
1000
100
10
V
= 2.7V
SY
V
= 18V
SY
1
1
| I + |
| I + |
B
B
| I – |
| I – |
B
B
0.1
0.1
25
50
75
100
125
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 10. Input Bias Current vs. Temperature
Figure 13. Input Bias Current vs. Temperature
4
3
4
3
V
= 2.7V
V
= 18V
SY
SY
2
2
1
1
0
0
125°C
85°C
25°C
125°C
85°C
25°C
–1
–2
–3
–4
–1
–2
–3
–4
0
0.3
0.6
0.9
1.2
1.5
(V)
1.8
2.1
2.4
2.7
0
2
4
6
8
10
(V)
12
14
16
18
V
V
CM
CM
Figure 11. Input Bias Current vs. Common-Mode Voltage
Figure 14. Input Bias Current vs. Common-Mode Voltage
Rev. B | Page 8 of 24
Data Sheet
AD8546/AD8548
10
10
1
V
= 2.7V
V
= 18V
SY
SY
1
100m
10m
–40°C
+25°C
+85°C
+125°C
–40°C
+25°C
+85°C
+125°C
100m
10m
1m
1m
0.1m
0.01m
0.1m
0.01m
0.001
0.01
0.1
1
10
100
0.001
0.01
0.1
1
10
100
LOAD CURRENT (mA)
LOAD CURRENT (mA)
Figure 15. Output Voltage (VOH) to Supply Rail vs. Load Current
Figure 18. Output Voltage (VOH) to Supply Rail vs. Load Current
10
10
V
= 2.7V
V
= 18V
SY
SY
1
100m
10m
1
100m
10m
–40°C
+25°C
+85°C
+125°C
–40°C
+25°C
+85°C
+125°C
1m
1m
0.1m
0.01m
0.1m
0.01m
0.001
0.01
0.1
1
10
100
0.001
0.01
0.1
1
10
100
LOAD CURRENT (mA)
LOAD CURRENT (mA)
Figure 16. Output Voltage (VOL) to Supply Rail vs. Load Current
Figure 19. Output Voltage (VOL) to Supply Rail vs. Load Current
18.000
2.700
R
= 1MΩ
L
R
= 1MΩ
L
17.995
17.990
17.985
17.980
17.975
2.699
2.698
2.697
2.696
2.695
R
= 100kΩ
L
R
= 100kΩ
L
V
= 2.7V
V
= 18V
–25
SY
SY
–50
0
25
50
75
100
125
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 17. Output Voltage (VOH) vs. Temperature
Figure 20. Output Voltage (VOH) vs. Temperature
Rev. B | Page 9 of 24
AD8546/AD8548
Data Sheet
6
12
10
8
V
= 2.7V
V
= 18V
SY
SY
5
4
3
2
1
R
= 100kΩ
L
6
R
= 100kΩ
L
4
2
R
= 1MΩ
L
R
= 1MΩ
L
0
–50
0
–50
–25
0
25
50
75
100
125
–25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 21. Output Voltage (VOL) vs. Temperature
Figure 24. Output Voltage (VOL) vs. Temperature
35
30
25
20
15
10
5
35
30
25
20
15
10
5
V
= 2.7V
V
= 18V
SY
SY
–40°C
–40°C
+25°C
+85°C
+25°C
+85°C
+125°C
+125°C
0
0
0
0
3
6
9
12
15
18
0.3
0.6
0.9
1.2
V
1.5
(V)
1.8
2.1
2.4
2.7
V
(V)
CM
CM
Figure 22. Supply Current per Amplifier vs. Common-Mode Voltage
Figure 25. Supply Current per Amplifier vs. Common-Mode Voltage
35
30
25
20
15
60
50
V
V
= 2.7V
= 18V
SY
SY
40
30
20
10
0
10
–40°C
+25°C
5
+85°C
+125°C
0
0
3
6
9
12
15
18
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
V
(V)
SY
Figure 26. Supply Current per Amplifier vs. Temperature
Figure 23. Supply Current per Amplifier vs. Supply Voltage
Rev. B | Page 10 of 24
Data Sheet
AD8546/AD8548
135
90
135
60
60
40
V
R
= 2.7V
= 1MΩ
V
R
= 18V
SY
SY
PHASE
PHASE
= 1MΩ
L
L
90
40
45
45
20
20
GAIN
0
0
0
0
GAIN
–45
–90
–135
–45
–90
–135
–20
–20
–40
–60
C
C
= 10pF
C
C
= 10pF
L
L
L
L
–40
–60
= 100pF
= 100pF
1k
10k
100k
1M
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 27. Open-Loop Gain and Phase vs. Frequency
Figure 30. Open-Loop Gain and Phase vs. Frequency
60
60
V
= 2.7V
V
= 18V
SY
SY
A
= +100
A
= +100
V
V
40
20
40
20
A
A
= +10
= +1
A
A
= +10
= +1
V
V
V
V
0
0
–20
–40
–60
–20
–40
–60
100
1k
10k
100k
1M
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 28. Closed-Loop Gain vs. Frequency
Figure 31. Closed-Loop Gain vs. Frequency
1000
100
10
1000
100
10
A
= +100
A
= +100
V
V
A
= +10
A
= +10
V
V
A
= +1
A
= +1
V
V
V
= 2.7V
V
= 18V
SY
SY
1
1
100
1k
FREQUENCY (Hz)
10k
100k
100
1k
FREQUENCY (Hz)
10k
100k
Figure 29. Output Impedance vs. Frequency
Figure 32. Output Impedance vs. Frequency
Rev. B | Page 11 of 24
AD8546/AD8548
Data Sheet
140
140
120
100
80
V
V
= 2.7V
SY
CM
V
V
= 18V
= V /2
SY
= V /2
SY
SY
CM
120
100
80
60
40
20
0
60
40
20
0
100
100
1k
10k
100k
1M
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 33. CMRR vs. Frequency
Figure 36. CMRR vs. Frequency
100
80
60
40
20
0
100
80
60
40
20
0
V
= 18V
SY
V
= 2.7V
SY
PSRR+
PSRR–
PSRR+
PSRR–
100
1k
10k
100k
1M
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 34. PSRR vs. Frequency
Figure 37. PSRR vs. Frequency
70
70
60
50
40
30
20
10
0
V
V
= 18V
= 10mV p-p
V
V
R
= 2.7V
= 10mV p-p
= 1MΩ
SY
SY
IN
IN
60
50
40
30
20
10
0
R = 1MΩ
L
L
OS+
OS–
OS+
OS–
10
100
CAPACITANCE (pF)
1000
10
100
CAPACITANCE (pF)
1000
Figure 35. Small Signal Overshoot vs. Load Capacitance
Figure 38. Small Signal Overshoot vs. Load Capacitance
Rev. B | Page 12 of 24
Data Sheet
AD8546/AD8548
V
= ±1.35V
= +1
= 1MΩ
SY
V
= ±9V
= +1
= 1MΩ
= 100pF
SY
A
R
C
V
L
L
A
R
C
V
L
L
= 100pF
TIME (100µs/DIV)
TIME (100µs/DIV)
Figure 39. Large Signal Transient Response
Figure 42. Large Signal Transient Response
V
= ±1.35V
= +1
= 1MΩ
SY
V
= ±9V
= +1
= 1MΩ
= 100pF
SY
A
R
C
V
L
L
A
R
C
V
L
L
= 100pF
TIME (100µs/DIV)
TIME (100µs/DIV)
Figure 40. Small Signal Transient Response
Figure 43. Small Signal Transient Response
V
A
R
= ±9V
= –10
= 1MΩ
SY
0
–0.2
–0.4
V
L
INPUT
INPUT
0
–1
–2
V
A
R
= ±1.35V
= –10
= 1MΩ
SY
V
L
2
1
0
10
5
OUTPUT
OUTPUT
0
TIME (40µs/DIV)
TIME (40µs/DIV)
Figure 41. Positive Overload Recovery
Figure 44. Positive Overload Recovery
Rev. B | Page 13 of 24
AD8546/AD8548
Data Sheet
V
A
R
= ±1.35V
= –10
= 1MΩ
SY
V
A
R
= ±9V
= –10
= 1MΩ
SY
0.4
0.2
0
2
1
0
V
L
V
L
INPUT
INPUT
OUTPUT
OUTPUT
0
0
–1
–2
–5
–10
TIME (40µs/DIV)
TIME (40µs/DIV)
Figure 45. Negative Overload Recovery
Figure 48. Negative Overload Recovery
INPUT
INPUT
V
R
C
= 2.7V
= 100kΩ
= 10pF
V
R
C
= 18V
= 100kΩ
= 10pF
SY
SY
L
L
L
L
+5mV
0
+5mV
0
ERROR BAND
ERROR BAND
OUTPUT
OUTPUT
–5mV
–5mV
TIME (10µs/DIV)
TIME (10µs/DIV)
Figure 46. Positive Settling Time to 0.1%
Figure 49. Positive Settling Time to 0.1%
V
R
C
= 2.7V
= 100kΩ
= 10pF
V
R
C
= 18V
= 100kΩ
= 10pF
SY
SY
L
L
L
L
INPUT
INPUT
+5mV
0
+5mV
0
OUTPUT
OUTPUT
ERROR BAND
ERROR BAND
–5mV
–5mV
TIME (10µs/DIV)
TIME (10µs/DIV)
Figure 47. Negative Settling Time to 0.1%
Figure 50. Negative Settling Time to 0.1%
Rev. B | Page 14 of 24
Data Sheet
AD8546/AD8548
1000
1000
100
10
V
= 18V
V
= 2.7V
SY
SY
100
10
1
1
10
100
1k
10k
100k
1M
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 51. Voltage Noise Density vs. Frequency
Figure 54. Voltage Noise Density vs. Frequency
V
= 18V
V
= 2.7V
SY
SY
TIME (2s/DIV)
TIME (2s/DIV)
Figure 52. 0.1 Hz to 10 Hz Noise
Figure 55. 0.1 Hz to 10 Hz Noise
20
18
16
14
12
10
8
3.0
2.5
2.0
1.5
1.0
0.5
0
V
= 18V
= 17.9V
= 1MΩ
= +1
V
V
R
A
= 2.7V
= 2.6V
= 1MΩ
= +1
SY
SY
V
IN
IN
R
A
L
V
L
V
6
4
2
0
10
100
1k
10k
100k
1M
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 53. Output Swing vs. Frequency
Figure 56. Output Swing vs. Frequency
Rev. B | Page 15 of 24
AD8546/AD8548
Data Sheet
100
100
10
V
V
R
= 18V
= 0.5V rms
= 1MΩ
= +1
V
V
R
= 2.7V
= 0.2V rms
= 1MΩ
SY
IN
SY
IN
L
V
L
V
A
A
= +1
10
1
1
0.1
0.1
0.01
0.01
10
100
1k
10k
100k
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 57. THD + N vs. Frequency
Figure 59. THD + N vs. Frequency
0
–20
0
–20
1MΩ
V
R
A
= 18V
= 1MΩ
= –100
V
R
A
= 2.7V
= 1MΩ
= –100
SY
SY
1MΩ
10kΩ
L
V
L
V
10kΩ
R
L
R
–40
–40
L
V
V
V
V
V
= 1V p-p
= 5V p-p
= 10V p-p
= 15V p-p
= 17V p-p
IN
IN
IN
IN
IN
–60
–60
V
= 0.5V p-p
= 1.5V p-p
= 2.6V p-p
IN
–80
–80
V
V
IN
IN
–100
–120
–140
–100
–120
–140
100
1k
10k
FREQUENCY (Hz)
100k
100
1k
10k
FREQUENCY (Hz)
100k
Figure 58. Channel Separation vs. Frequency
Figure 60. Channel Separation vs. Frequency
Rev. B | Page 16 of 24
Data Sheet
AD8546/AD8548
APPLICATIONS INFORMATION
The AD8546/AD8548 are low input bias current, micropower
CMOS amplifiers that operate over a wide supply voltage range
of 2.7 V to 18 V. T he AD8546/AD8548 also employ unique input
and output stages to achieve rail-to-rail input and output ranges
with very low supply current.
drain impedances contributes to the offset voltage of the ampli-
fier. This problem is exacerbated at high temperatures due to the
decrease in the threshold voltage of the input transistors. See
Figure 9 and Figure 12 for typical performance data.
Current Source I1 drives the PMOS transistor pair. As the input
common-mode voltage approaches the upper rail, I1 is steered
away from the PMOS differential pair through the M5 transistor.
The bias voltage, VB1, controls the point where this transfer occurs.
INPUT STAGE
Figure 61 shows the simplified schematic of the AD8546/AD8548.
The input stage comprises two differential transistor pairs: an
NMOS pair (M1, M2) and a PMOS pair (M3, M4). The input
common-mode voltage determines which differential pair turns
on and is more active than the other.
M5 diverts the tail current into a current mirror consisting of the
M6 and M7 transistors. The output of the current mirror then
drives the NMOS transistor pair. Note that the activation of this
current mirror causes a slight increase in supply current at high
common-mode voltages (see Figure 22 and Figure 25).
The PMOS differential pair is active when the input voltage
approaches and reaches the lower supply rail. The NMOS differ-
ential pair is needed for input voltages up to and including the
upper supply rail. This topology allows the amplifier to maintain
a wide dynamic input voltage range and maximize signal swing to
both supply rails. For the greater part of the input common-mode
voltage range, the PMOS differential pair is active.
The AD8546/AD8548 achieve their high performance by using
low voltage MOS devices for their differential inputs. These low
voltage MOS devices offer excellent noise and bandwidth per unit
of current. Each differential input pair is protected by proprietary
regulation circuitry (not shown in Figure 61). The regulation
circuitry consists of a combination of active devices, which main-
tain the proper voltages across the input pairs during normal
operation, and passive clamping devices, which protect the
amplifier during fast transients. However, these passive clamping
devices begin to forward-bias as the common-mode voltage
approaches either power supply rail. This causes an increase in
the input bias current (see Figure 11 and Figure 14).
Differential pairs commonly exhibit different offset voltages.
The handoff from one pair to the other creates a step-like char-
acteristic that is visible in the VOS vs. VCM graphs (see Figure 5
and Figure 8). This characteristic is inherent in all rail-to-rail
amplifiers that use the dual differential pair topology. Therefore,
always choose a common-mode voltage that does not include the
region of handoff from one input differential pair to the other.
The input devices are also protected from large differential
input voltages by clamp diodes (D1 and D2). These diodes are
buffered from the inputs with two 10 kΩ resistors (R1 and R2).
The differential diodes turn on when the differential input voltage
exceeds approximately 600 mV; in this condition, the differential
input resistance drops to 20 kΩ.
Additional steps in the VOS vs. VCM graphs are also visible as the
input common-mode voltage approaches the power supply rails.
These changes are a result of the load transistors (M8, M9, M14,
and M15) running out of headroom. As the load transistors are
forced into the triode region of operation, the mismatch of their
V+
VB1
I1
M8
M9
M5
M10
M11
M3
M4
+IN x
–IN x
M16
M17
R1
R2
D1
D2
VB2
OUT x
M1 M2
M12
M14
M13
M15
M7
M6
V–
Figure 61. Simplified Schematic
Rev. B | Page 17 of 24
AD8546/AD8548
Data Sheet
OUTPUT STAGE
RESISTIVE LOAD
The AD8546/AD8548 feature a complementary output stage
consisting of the M16 and M17 transistors (see Figure 61). These
transistors are configured in a Class AB topology and are biased
by the voltage source, VB2. This topology allows the output voltage
to go within millivolts of the supply rails, achieving a rail-to-rail
output swing. The output voltage is limited by the output imped-
ance of the transistors, which are low RON MOS devices. The output
voltage swing is a function of the load current and can be estimated
using the output voltage to supply rail vs. load current graphs (see
Figure 15, Figure 16, Figure 18, and Figure 19).
The feedback resistor alters the load resistance that an amplifier
sees. Therefore, it is important to carefully select the value of the
feedback resistors used with the AD8546/AD8548. The amplifiers
are capable of driving resistive loads down to 100 kΩ. The Inverting
Op Amp Configuration section and the Noninverting Op Amp
Configuration section show how the feedback resistor changes
the actual load resistance seen at the output of the amplifier.
Inverting Op Amp Configuration
Figure 63 shows the AD8546/AD8548 in an inverting config-
uration with a resistive load, RL, at the output. The actual load
seen by the amplifier is the parallel combination of the feedback
resistor, R2, and the load, RL. For example, the combination of
a feedback resistor of 1 kΩ and a load of 1 MΩ results in an
equivalent load resistance of 999 Ω at the output. Because the
AD8546/AD8548 are incapable of driving such a heavy load,
performance degrades greatly.
RAIL-TO-RAIL INPUT AND OUTPUT
The AD8546/AD8548 feature rail-to-rail input and output with a
supply voltage from 2.7 V to 18 V. Figure 62 shows the input and
output waveforms of the AD8546/AD8548 configured as a unity-
gain buffer with a supply voltage of 9 V and a resistive load of
1 MΩ. With an input voltage of 9 V, the AD8546/AD8548 allow
the output to swing very close to both rails. Additionally, the
AD8546/AD8548 do not exhibit phase reversal.
To avoid loading the output, use a larger feedback resistor, but
consider the effect of resistor thermal noise on the overall circuit.
R2
V
= ±9V
SY
INPUT
OUTPUT
R
= 1MΩ
L
+V
SY
R1
V
IN
AD8546/
AD8548
V
OUT
R
L
–V
SY
R
= R || R2
L, EFF
L
Figure 63. Inverting Op Amp Configuration
Noninverting Op Amp Configuration
Figure 64 shows the AD8546/AD8548 in a noninverting config-
uration with a resistive load, RL, at the output. The actual load seen
by the amplifier is the parallel combination of R1 + R2 and RL.
R2
TIME (200µs/DIV)
Figure 62. Rail-to-Rail Input and Output
+V
SY
R1
AD8546/
AD8548
V
OUT
R
L
V
IN
–V
SY
R
= R || (R1 + R2)
L
L, EFF
Figure 64. Noninverting Op Amp Configuration
Rev. B | Page 18 of 24
Data Sheet
AD8546/AD8548
+V
SY
COMPARATOR OPERATION
An op amp is designed to operate in a closed-loop configuration
with feedback from its output to its inverting input. Figure 65
shows the AD8546 configured as a voltage follower with an input
voltage that is always kept at the midpoint of the power supplies.
The same configuration is applied to the unused channel. A1 and
A2 indicate the placement of ammeters to measure supply current.
ISY+ refers to the current flowing from the upper supply rail to the
op amp, and ISY− refers to the current flowing from the op amp
to the lower supply rail.
A1
I
+
SY
100kΩ
100kΩ
AD8546
V
OUT
1/2
A2
I
–
SY
+V
SY
–V
SY
Figure 67. Comparator Configuration A
A1
I
+
SY
+V
SY
100kΩ
100kΩ
AD8546
A1
I
+
SY
V
OUT
1/2
100kΩ
A2
I
–
SY
AD8546
V
OUT
1/2
–V
SY
100kΩ
A2
I
–
SY
Figure 65. Voltage Follower Configuration
As expected, Figure 66 shows that in normal operating condition,
the total current flowing into the op amp is equivalent to the total
current flowing out of the op amp, where ISY+ = ISY− = 36 μA for
the AD8546 at VSY = 18 V.
–V
SY
Figure 68. Comparator Configuration B
The AD8546/AD8548 have input devices that are protected
from large differential input voltages by Diode D1 and Diode D2
(see Figure 61). These diodes consist of substrate PNP bipolar
transistors and turn on when the differential input voltage
exceeds approximately 600 mV; however, these diodes also allow
a current path from the input to the lower supply rail, resulting
in an increase in the total supply current of the system. As shown
in Figure 69, both configurations yield the same result. At 18 V
of power supply, ISY+ remains at 36 μA per dual amplifier, but
ISY− increases to 140 μA in magnitude per dual amplifier.
160
40
35
30
25
20
15
I
I
–
+
SY
SY
10
5
140
120
100
0
0
2
4
6
8
10
(V)
12
14
16
18
V
SY
Figure 66. Supply Current vs. Supply Voltage (Voltage Follower)
I
I
–
+
SY
SY
80
60
40
20
0
In contrast to op amps, comparators are designed to work in an
open-loop configuration and to drive logic circuits. Although
op amps are different from comparators, occasionally an unused
section of a dual or quad op amp is used as a comparator to save
board space and cost; however, this is not recommended.
Figure 67 and Figure 68 show the AD8546 configured as a com-
parator, with 100 kΩ resistors in series with the input pins. The
unused channel is configured as a buffer with the input voltage
kept at the midpoint of the power supplies.
0
2
4
6
8
10
(V)
12
14
16
18
V
SY
Figure 69. Supply Current vs. Supply Voltage (AD8546 as a Comparator)
Rev. B | Page 19 of 24
AD8546/AD8548
Data Sheet
Note that 100 kΩ resistors are used in series with the input of
the op amp. If smaller resistor values are used, the supply current
of the system increases much more. For more information about
using op amps as comparators, see the AN-849 Application Note,
Using Op Amps as Comparators.
The AD8546 is an excellent choice due to its low supply current
of 33 μA per amplifier over temperature and supply voltage. The
current transmitter controls the current flowing in the loop, where
a zero-scale input signal is represented by 4 mA of current and a
full-scale input signal is represented by 20 mA. The transmitter
also floats from the control loop power supply, VDD, whereas signal
ground is in the receiver. The loop current is measured at the load
resistor, RL, at the receiver side.
4 mA TO 20 mA PROCESS CONTROL CURRENT
LOOP TRANSMITTER
A 2-wire current transmitter is often used in distributed control
systems and process control applications to transmit analog signals
between sensors and process controllers. Figure 70 shows a 4 mA
to 20 mA current loop transmitter.
With a zero-scale input, a current of VREF/RNULL flows through
R. This creates a current, ISENSE, that flows through the sense
resistor, as determined by the following equation:
ISENSE, MIN = (VREF × R)/(RNULL × RSENSE)
ADR125
V
REF
V
V
OUT
IN
With a full-scale input voltage, current flowing through R is
increased by the full-scale change in VIN/RSPAN. This creates an
increase in the current flowing through the sense resistor.
GND
R
NULL
1MΩ
1%
C2
C3
C4
C5
10µF 0.1µF
0.1µF 10µF
I
SENSE, DELTA = (Full-Scale Change in VIN × R)/(RSPAN × RSENSE
)
R
SPAN
200kΩ
1/2
AD8546
1%
V
Therefore,
Q1
IN
0V TO 5V
V
DD
18V
R4
3.3kΩ
ISENSE, MAX = ISENSE, MIN + ISENSE, DELTA
R1
68kΩ
1%
D1
4mA
TO
20mA
R3
1.2kΩ
When R >> RSENSE, the current through the load resistor at the
receiver side is almost equivalent to ISENSE
C1
390pF
.
R
100Ω
R2
2kΩ
1%
L
R
SENSE
100Ω
1%
Figure 70 shows a design for a full-scale input voltage of 5 V. At
0 V of input, the loop current is 3.5 mA, and at a full-scale input
of 5 V, the l o op current is 21 mA. This allows software calibration
to fine-tune the current loop to the 4 mA to 20 mA range.
NOTES
1. R1 + R2 = R´.
Figure 70. 4 mA to 20 mA Current Loop Transmitter
Together, the AD8546 and the ADR125 consume quiescent
current of only 160 µA, making 3.34 mA current available to
power additional signal conditioning circuitry or to power a
bridge circuit.
The transmitter is powered directly from the control loop
power supply, and the current in the loop carries signal from
4 mA to 20 mA. Thus, 4 mA establishes the baseline current
budget within which the circuit must operate.
Rev. B | Page 20 of 24
Data Sheet
AD8546/AD8548
OUTLINE DIMENSIONS
3.20
3.00
2.80
8
1
5
4
5.15
4.90
4.65
3.20
3.00
2.80
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.80
0.55
0.40
0.15
0.05
0.23
0.09
6°
0°
0.40
0.25
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 71. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
8.75 (0.3445)
8.55 (0.3366)
8
7
14
1
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
1.27 (0.0500)
0.50 (0.0197)
0.25 (0.0098)
45°
BSC
1.75 (0.0689)
1.35 (0.0531)
0.25 (0.0098)
0.10 (0.0039)
8°
0°
COPLANARITY
0.10
SEATING
PLANE
1.27 (0.0500)
0.40 (0.0157)
0.51 (0.0201)
0.31 (0.0122)
0.25 (0.0098)
0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012-AB
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 72. 14-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-14)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
RM-8
Branding
A2V
A2V
AD8546ARMZ
AD8546ARMZ-RL
AD8546ARMZ-R7
AD8548ARZ
AD8548ARZ-RL
AD8548ARZ-R7
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
14-Lead Standard Small Outline Package [SOIC_N]
14-Lead Standard Small Outline Package [SOIC_N]
14-Lead Standard Small Outline Package [SOIC_N]
RM-8
RM-8
R-14
R-14
R-14
A2V
1 Z = RoHS Compliant Part.
Rev. B | Page 21 of 24
AD8546/AD8548
NOTES
Data Sheet
Rev. B | Page 22 of 24
Data Sheet
NOTES
AD8546/AD8548
Rev. B | Page 23 of 24
AD8546/AD8548
NOTES
Data Sheet
©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09585-0-4/12(B)
Rev. B | Page 24 of 24
相关型号：
AD8551AN
IC OP-AMP, 10 uV OFFSET-MAX, 1 MHz BAND WIDTH, PDIP8, PLASTIC, DIP-8, Operational Amplifier
ADI
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