AD8574ARU [ADI]
Zero-Drift, Single-Supply, Rail-to-Rail Input/Output Operational Amplifiers; 零漂移，单电源，轨到轨输入/输出运算放大器
| 型号： | AD8574ARU |
| 厂家： | 
ADI |
| 描述： | Zero-Drift, Single-Supply, Rail-to-Rail Input/Output Operational Amplifiers |
| 文件： | 总19页 (文件大小：250K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Zero-Drift, Single-Supply, Rail-to-Rail
Input/Output Operational Amplifiers
a
AD8571/AD8572/AD8574
PIN CONFIGURATIONS
FEATURES
Low Offset Voltage: 1 V
8-Lead MSOP
(RM Suffix)
8-Lead SOIC
(R Suffix)
Input Offset Drift: 0.005 V/؇C
Rail-to-Rail Input and Output Swing
5 V/2.7 V Single-Supply Operation
High Gain, CMRR, PSRR: 130 dB
Ultralow Input Bias Current: 20 pA
Low Supply Current: 750 A/Op Amp
Overload Recovery Time: 50 s
No External Capacitors Required
NC
؊IN A
؉IN A
V؊
1
8
NC
1
2
3
4
NC
؊IN A
+IN A
V؊
8
7
6
5
NC
V+
OUT A
AD8571
V+
NC
4
5
AD8571
OUT A
NC
NC = NO CONNECT
NC = NO CONNECT
APPLICATIONS
Temperature Sensors
Pressure Sensors
Precision Current Sensing
Strain Gage Amplifiers
Medical Instrumentation
Thermocouple Amplifiers
8-Lead TSSOP
(RU Suffix)
8-Lead SOIC
(R Suffix)
1
8
5
OUT A
؊IN A
+IN A
V؊
V+
OUT B
؊IN B
+IN B
1
2
3
4
8
7
6
5
OUT A
؊IN A
+IN A
V؊
V+
AD8572
4
OUT B
؊IN B
+IN B
AD8572
GENERAL DESCRIPTION
This new family of amplifiers has ultralow offset, drift and bias
current. The AD8571, AD8572 and AD8574 are single, dual and
quad amplifiers featuring rail-to-rail input and output swings. All
are guaranteed to operate from 2.7 V to 5 V single supply.
14-Lead SOIC
(R Suffix)
14-Lead TSSOP
(RU Suffix)
The AD857x family provides the benefits previously found only in
expensive autozeroing or chopper-stabilized amplifiers. Using Analog
Devices’ new topology these new zero-drift amplifiers combine low
cost with high accuracy. (No external capacitors are required.) In
addition, using a patented spread-spectrum autozero technique, the
AD857x family virtually eliminates the intermodulation effects from
interaction of the chopping function with the signal frequency in ac
applications.
OUT A
؊IN A
؉IN A
V؉
؉N B
؊IN B
1
OUT D
؊IN D
؉IN D
V؊
؉IN C
؊IN C
OUT C
14
OUT A
OUT D
؊IN D
+IN D
V؊
1
2
3
4
5
6
7
14
13
12
11
10
9
؊IN A
+IN A
V+
AD8574
OUT B
7
8
AD8574
+IN B
؊IN B
OUT B
+IN C
؊IN C
OUT C
With an offset voltage of only 1 µV and drift of 0.005 µV/°C, the
AD8571 is perfectly suited for applications where error sources
cannot be tolerated. Position, and pressure sensors, medical
equipment, and strain gage amplifiers benefit greatly from nearly
zero drift over their operating temperature range. Many more
systems require the rail-to-rail input and output swings provided
by the AD857x family.
8
The AD857x family is specified for the extended industrial/automotive
(–40°C to +125°C) temperature range. The AD8571 single is
available in 8-lead MSOP and narrow 8-lead SOIC packages. The
AD8572 dual amplifier is available in 8-lead narrow SO and 8-lead
TSSOP surface mount packages. The AD8574 quad is available in
narrow 14-lead SOIC and 14-lead TSSOP packages.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1999
AD8571/AD8572/AD8574–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (VS = 5 V, VCM = 2.5 V, VO = 2.5 V, TA = 25؇C unless otherwise noted)
Parameter
Symbol
Conditions
Min
Typ Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
VOS
IB
1
5
µV
µV
pA
nA
pA
pA
V
–40°C ≤ TA ≤ +125°C
–40°C ≤ TA ≤ +125°C
–40°C ≤ TA ≤ +125°C
10
50
1.5
70
200
5
Input Bias Current
Input Offset Current
10
1.0
20
IOS
150
Input Voltage Range
0
Common-Mode Rejection Ratio
CMRR
AVO
VCM = 0 V to 5 V
120
115
125
120
140
130
145
135
dB
dB
dB
dB
µV/°C
–40°C ≤ TA ≤ +125°C
RL = 10 kΩ , VO = 0.3 V to 4.7 V
–40°C ≤ TA ≤ +125°C
–40°C ≤ TA ≤ +125°C
Large Signal Voltage Gain1
Offset Voltage Drift
∆VOS/∆T
0.005 0.04
OUTPUT CHARACTERISTICS
Output Voltage High
VOH
RL = 100 kΩ to GND
–40°C to +125°C
RL = 10 kΩ to GND
–40°C to +125°C
RL = 100 kΩ to V+
–40°C to +125°C
RL = 10 kΩ to V+
–40°C to +125°C
4.99
4.99
4.95
4.95
4.998
4.997
4.98
4.975
1
2
10
15
±50
±40
±30
±15
V
V
V
V
mV
mV
mV
mV
mA
mA
mA
mA
Output Voltage Low
VOL
10
10
30
30
Short Circuit Limit
Output Current
ISC
IO
±25
–40°C to +125°C
–40°C to +125°C
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
ISY
VS = 2.7 V to 5.5 V
–40°C ≤ TA ≤ +125°C
VO = 0 V
120
115
130
130
850
dB
dB
µA
µA
Supply Current/Amplifier
975
–40°C ≤ TA ≤ +125°C
1,000 1,075
DYNAMIC PERFORMANCE
Slew Rate
Overload Recovery Time
Gain Bandwidth Product
SR
RL = 10 kΩ
0.4
0.05 0.3
1.5
V/µs
ms
MHz
GBP
NOISE PERFORMANCE
Voltage Noise
en p–p
en p–p
en
0 Hz to 10 Hz
0 Hz to 1 Hz
f = 1 kHz
1.3
0.41
51
µV p–p
µV p–p
nV/√Hz
fA/√Hz
Voltage Noise Density
Current Noise Density
in
f = 10 Hz
2
NOTE
1Gain testing is highly dependent upon test bandwidth.
Specifications subject to change without notice.
–2–
REV. 0
AD8571/AD8572/AD8574
(V = 2.7 V, VCM = 1.35 V, VO = 1.35 V, TA = 25؇C unless otherwise noted)
ELECTRICAL CHARACTERISTICS
S
Parameter
Symbol
Conditions
Min
Typ Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
VOS
IB
1
5
µV
µV
pA
nA
pA
pA
V
–40°C ≤ TA ≤ +125°C
–40°C ≤ TA ≤ +125°C
–40°C ≤ TA ≤ +125°C
10
50
1.5
50
200
2.7
Input Bias Current
Input Offset Current
10
1.0
10
IOS
150
Input Voltage Range
0
Common-Mode Rejection Ratio
CMRR
AVO
VCM = 0 V to 2.7 V
115
110
110
105
130
130
140
130
dB
dB
dB
dB
µV/°C
–40°C ≤ TA ≤ +125°C
RL = 10 kΩ , VO = 0.3 V to 2.4 V
–40°C ≤ TA ≤ +125°C
–40°C ≤ TA ≤ +125°C
Large Signal Voltage Gain1
Offset Voltage Drift
∆VOS/∆T
0.005 0.04
OUTPUT CHARACTERISTICS
Output Voltage High
VOH
RL = 100 kΩ to GND
–40°C to +125°C
RL = 10 kΩ to GND
–40°C to +125°C
RL = 100 kΩ to V+
–40°C to +125°C
RL = 10 kΩ to V+
–40°C to +125°C
2.685 2.697
2.685 2.696
V
V
V
V
mV
mV
mV
mV
mA
mA
mA
mA
2.67
2.67
2.68
2.675
1
Output Voltage Low
VOL
10
10
20
20
2
10
15
Short Circuit Limit
Output Current
ISC
IO
±10
±15
±10
±10
±5
–40°C to +125°C
–40°C to +125°C
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
ISY
VS = 2.7 V to 5.5 V
–40°C ≤ TA ≤ +125°C
VO = 0 V
120
115
130
130
750
950
dB
dB
µA
µA
Supply Current/Amplifier
900
1,000
–40°C ≤ TA ≤ +125°C
DYNAMIC PERFORMANCE
Slew Rate
Overload Recovery Time
Gain Bandwidth Product
SR
RL = 10 kΩ
0.5
0.05
1
V/µs
ms
MHz
GBP
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
en p–p
en
in
0 Hz to 10 Hz
f = 1 kHz
f = 10 Hz
2.0
94
2
µV p–p
nV/√Hz
fA/√Hz
NOTE
1Gain testing is highly dependent upon test bandwidth.
Specifications subject to change without notice.
REV. 0
–3–
AD8571/AD8572/AD8574
ABSOLUTE MAXIMUM RATINGS1
1
Package Type
Unit
JA
JC
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . GND to VS + 0.3 V
Differential Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . ±5.0 V
ESD (Human Body Model) . . . . . . . . . . . . . . . . . . . . . 2,000 V
Output Short-Circuit Duration to GND . . . . . . . . . Indefinite
Storage Temperature Range
8-Lead MSOP (RM)
8-Lead TSSOP (RU)
8-Lead SOIC (R)
14-Lead TSSOP (RU)
14-Lead SOIC (R)
190
240
158
180
120
44
43
43
36
36
°C/W
°C/W
°C/W
°C/W
°C/W
RM, RU and R Packages . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range
AD8571A/AD8572A/AD8574A . . . . . . . . –40°C to +125°C
Junction Temperature Range
NOTE
1θJA is specified for worst-case conditions, i.e., θJA is specified for device in socket
for P-DIP packages, θJA is specified for device soldered in circuit board for
SOIC and TSSOP packages.
RM, RU and R Packages . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300°C
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
2Differential input voltage is limited to ±5.0 V or the supply voltage, whichever is less.
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Option
Model
Brand1
AD8571ARM2
AD8571AR
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
8-Lead MSOP
8-Lead SOIC
8-Lead TSSOP
8-Lead SOIC
14-Lead TSSOP
14-Lead SOIC
RM-8
SO-8
RU-8
SO-8
RU-14
SO-14
AJA
AD8572ARU3
AD8572AR
AD8574ARU3
AD8574AR
NOTES
1Due to package size limitations, these characters represent the part number.
2Available in reels only. 1,000 or 2,500 pieces per reel.
3Available in reels only. 2,500 pieces per reel.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8571/AD8572/AD8574 features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. 0
Typical Performance Characteristics–
AD8571/AD8572/AD8574
180
160
140
120
100
80
50
1,500
V
V
T
= 2.7V
S
V
T
= 5V
= 125؇C
S
V
T
= 5V
= 1.35V
S
CM
40
30
1,000
500
0
A
= ؊40؇C, +25؇C, +85؇C
= 25؇C
A
A
+85؇C
20
10
+25؇C
؊40؇C
؊500
0
60
؊1,000
؊1,500
؊2,000
؊10
؊20
؊30
40
20
0
5
5
0
1
2
3
4
0
1
2
3
4
؊2.5
؊1.5
؊0.5
0.5
1.5
2.5
COMMON-MODE VOLTAGE – V
OFFSET VOLTAGE – V
INPUT COMMON-MODE VOLTAGE – V
Figure 1. Input Offset Voltage
Distribution at 2.7 V
Figure 3. Input Bias Current vs.
Common-Mode Voltage
Figure 2. Input Bias Current vs.
Common-Mode Voltage
10k
180
160
140
120
100
80
12
V
V
T
= 5V
S
V
T
= 5V
= 25؇C
S
A
V
V
= 5V
= 2.5V
S
CM
= 2.5V
= 25؇C
CM
10
8
A
1k
100
10
T
= ؊40؇C TO +125؇C
A
6
SOURCE
SINK
60
4
2
0
40
1
20
0
0.1
؊2.5
؊1.5
؊0.5
0.5
1.5
2.5
1
LOAD CURRENT – mA
10
100
0
1
2
3
4
5
6
0.0001 0.001 0.01
0.1
OFFSET VOLTAGE – V
INPUT OFFSET DRIFT – nV/؇C
Figure 4. Input Offset Voltage
Distribution at 5 V
Figure 6. Output Voltage to Supply
Rail vs. Output Current at 5 V
Figure 5. Input Offset Voltage Drift
Distribution at 5 V
10k
1,000
1.0
V
T
= 2.7V
= 25؇C
S
A
V
V
= 2.5V
= 5V
CM
5V
S
0.8
1k
100
10
750
500
250
0
2.7V
0.6
SOURCE
SINK
0.4
0.2
0
1
0.1
1
10
100
0
0.0001 0.001 0.01
0.1
؊75 ؊50 ؊25
؊75 ؊50 ؊25
0
25 50 75 100 125 150
25 50 75 100 125 150
TEMPERATURE – ؇C
LOAD CURRENT – mA
TEMPERATURE – ؇C
Figure 7. Output Voltage to Supply
Rail vs. Output Current at 2.7 V
Figure 9. Supply Current vs.
Temperature
Figure 8. Bias Current vs. Temperature
REV. 0
–5–
AD8571/AD8572/AD8574
60
50
60
50
800
V
S
= 2.7V
= 0pF
=
T
= 25؇C
V
C
R
= 5V
= 0pF
=
A
S
C
R
L
L
700
600
500
400
300
200
100
0
L
L
40
0
40
0
30
45
30
45
20
90
20
90
10
135
180
225
270
10
135
180
225
270
0
0
؊10
؊20
؊30
؊40
؊10
؊20
؊30
؊40
10k
100k
1M
10M
100M
10k
100k
1M
10M
100M
0
1
2
3
4
5
6
FREQUENCY – Hz
FREQUENCY – Hz
SUPPLY VOLTAGE – V
Figure 11. Open-Loop Gain and
Phase Shift vs. Frequency at 2.7 V
Figure 12. Open-Loop Gain and
Phase Shift vs. Frequency at 5 V
Figure 10. Supply Current vs.
Supply Voltage
60
300
270
240
210
180
60
50
40
30
20
V
C
R
= 5V
= 0pF
= 2k⍀
V
C
R
= 2.7V
= 0pF
= 2k⍀
S
S
V
= 2.7V
50
40
30
20
S
L
L
L
L
A
V
= ؊100
= ؊10
A
= ؊100
= ؊10
V
A
A
V
V
10
0
150
120
90
60
30
0
10
0
A
= 100
V
A
= +1
A
= +1
V
V
؊10
؊20
؊30
؊40
؊10
؊20
؊30
؊40
A
= 10
V
A
= 1
V
100
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
10M
FREQUENCY – Hz
FREQUENCY – Hz
FREQUENCY – Hz
Figure 14. Closed Loop Gain vs.
Frequency at 5 V
Figure 15. Output Impedance vs.
Frequency at 2.7 V
Figure 13. Closed Loop Gain vs.
Frequency at 2.7 V
300
270
240
210
180
V
= 2.7V
= 300pF
= 2k⍀
= 1
V
= +5V
= 300pF
= 2k⍀
= 1
S
S
V
= 5V
S
C
R
A
C
R
A
L
L
V
L
L
V
150
120
90
60
30
0
A
= 100
V
A
= 10
V
500mV
2s
1V
5s
A
= 1
V
100
1k
10k
100k
1M
10M
FREQUENCY – Hz
Figure 17. Large Signal Transient
Response at 2.7 V
Figure 18. Large Signal Transient
Response at 5 V
Figure 16. Output Impedance vs.
Frequency at 5 V
–6–
REV. 0
AD8571/AD8572/AD8574
50
V
= ؎1.35V
= 50pF
=
S
V
= ؎2.5V
= 50pF
=
S
V
R
= ؎1.35V
= 2k⍀
S
C
R
A
45
40
35
30
25
20
15
10
5
L
L
V
C
R
A
L
L
V
L
T
= 25؇C
A
= 1
= 1
+OS
؊OS
50mV
5s
50mV
5s
0
10
100
1k
10k
CAPACITANCE – pF
Figure 21. Small Signal Overshoot
vs. Load Capacitance at 2.7 V
Figure 19. Small Signal Transient
Response at 2.7 V
Figure 20. Small Signal Transient
Response at 5 V
45
V
= ؎2.5V
= 2k⍀
= 25؇C
S
V
40
35
30
25
20
15
10
5
IN
0V
R
T
L
0V
V
A
IN
V
V
= ؎2.5V
= 200mV p-p
V
V
= ؎2.5V
= ؊200mV p-p
(RET TO GND)
= 0pF
= 10k⍀
= ؊100
S
S
IN
IN
(RET TO GND)
= 0pF
= 10k⍀
= ؊100
C
R
A
C
R
A
L
L
V
L
L
V
0V
+OS
؊OS
V
OUT
0V
V
OUT
20s
1V
20s
1V
BOTTOM SCALE: 1V/DIV
TOP SCALE: 200mV/DIV
BOTTOM SCALE: 1V/DIV
TOP SCALE: 200mV/DIV
0
10
100
1k
10k
CAPACITANCE – pF
Figure 24. Negative Overvoltage
Recovery
Figure 22. Small Signal Overshoot
vs. Load Capacitance at 5 V
Figure 23. Positive Overvoltage
Recovery
140
140
V
R
A
= ؎2.5V
= 2k⍀
= ؊100
S
V
= 5V
V
= 2.7V
S
S
L
120
100
80
60
40
20
0
120
100
80
V
V
= 60mV p-p
IN
60
40
1V
200s
20
0
100
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
10M
FREQUENCY – Hz
FREQUENCY – Hz
Figure 25. No Phase Reversal
Figure 27. CMRR vs. Frequency
at 5 V
Figure 26. CMRR vs. Frequency
at 2.7 V
REV. 0
–7–
AD8571/AD8572/AD8574
140
140
120
100
80
3.0
2.5
2.0
1.5
1.0
0.5
0
V
= ؎2.5V
V
= ؎1.35V
S
S
120
100
80
V
R
A
= ؎1.35V
= 2k⍀
= 1
S
L
V
THD+N < 1%
= 25؇C
T
A
+PSRR
60
60
+PSRR
؊PSRR
؊PSRR
40
40
20
0
20
0
100
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
FREQUENCY – Hz
FREQUENCY – Hz
FREQUENCY – Hz
Figure 28. PSRR vs. Frequency
at ±1.35 V
Figure 29. PSRR vs. Frequency
at ±2.5 V
Figure 30. Maximum Output Swing
vs. Frequency at 2.7 V
5.5
V
R
A
= ؎2.5V
= 2k⍀
= 1
S
V
A
= ؎2.5V
= 120,000
V
A
= ؎1.35V
= 120,000
S
S
5.0
4.5
4.0
3.5
3.0
L
V
V
V
THD+N < 1%
= 25؇C
T
A
0V
2.5
2.0
1.5
1.0
0.5
0
50mV
1s
50mV
1s
100
1k
10k
100k
1M
FREQUENCY – Hz
Figure 31. Maximum Output Swing
vs. Frequency at 5 V
Figure 32. 0.1 Hz to 10 Hz Noise
at 2.7 V
Figure 33. 0.1 Hz to 10 Hz Noise at 5 V
V
R
= 5V
= 0⍀
S
V
R
= 2.7V
= 0⍀
V
R
= 2.7V
= 0⍀
S
S
182
156
130
104
78
112
96
80
64
48
32
16
364
312
260
208
156
104
52
S
S
S
52
26
0
0.5
1.0
1.5
2.0
2.5
0
5
10
15
20
25
0
0.5
1.0
1.5
2.0
2.5
FREQUENCY – kHz
FREQUENCY – kHz
FREQUENCY – kHz
Figure 35. Voltage Noise Density at
2.7 V from 0 Hz to 25 kHz
Figure 36. Voltage Noise Density at
5 V from 0 Hz to 2.5 kHz
Figure 34. Voltage Noise Density at
2.7 V from 0 Hz to 2.5 kHz
–8–
REV. 0
AD8571/AD8572/AD8574
150
V
R
= 5V
= 0⍀
V
R
= 5V
= 0⍀
S
S
V
= 2.7V TO 5.5V
112
96
80
64
48
32
16
210
180
150
120
90
S
S
S
145
140
135
130
125
60
30
0
5
10
15
20
25
0
5
10
FREQUENCY – kHz
FREQUENCY – Hz
؊75 ؊50 ؊25
0
25 50 75 100 125 150
TEMPERATURE – ؇C
Figure 37. Voltage Noise Density
at 5 V from 0 Hz to 25 kHz
Figure 38. Voltage Noise Density
at 5 V from 0 Hz to 10 Hz
Figure 39. Power-Supply Rejection
vs. Temperature
50
100
250
V
= 2.7V
V = 5V
S
40
30
80
60
V = 5V
S
225
200
S
I
I
SC؊
SC؊
20
10
0
40
20
0
175
150
125
R
= 1k⍀
L
؊10
؊20
؊30
؊40
؊50
؊20
؊40
100
75
50
25
0
I
SC+
I
SC+
؊60
R
= 100k⍀
L
؊80
R
= 10k⍀
L
؊100
؊75 ؊50 ؊25
0
؊75 ؊50 ؊25
0
25 50 75 100 125 150
TEMPERATURE – ؇C
25 50 75 100 125 150
TEMPERATURE – ؇C
؊75 ؊50 ؊25
0
25 50 75 100 125 150
TEMPERATURE – ؇C
Figure 40. Output Short-Circuit
Current vs. Temperature
Figure 41. Output Short-Circuit
Current vs. Temperature
Figure 42. Output Voltage to
Supply Rail vs. Temperature
250
V
= 5V
225
200
S
175
150
125
R
= 1k⍀
L
100
75
50
25
0
R
= 100k⍀
L
R
= 10k⍀
L
؊75 ؊50 ؊25
0
25 50 75 100 125 150
TEMPERATURE – ؇C
Figure 43. Output Voltage to Supply
Rail vs. Temperature
REV. 0
–9–
AD8571/AD8572/AD8574
FUNCTIONAL DESCRIPTION
As noted in the previous section on amplifier architecture, each
AD857x op amp contains two internal amplifiers. One is used as
the primary amplifier, the other as an autocorrection, or nulling,
amplifier. Each amplifier has an associated input offset voltage
that can be modeled as a dc voltage source in series with the
noninverting input. In Figures 44 and 45 these are labeled as
VOSX, where x denotes the amplifier associated with the offset; A
for the nulling amplifier, B for the primary amplifier. The open-
loop gain for the +IN and –IN inputs of each amplifier is given
as AX. Both amplifiers also have a third voltage input with an
associated open-loop gain of BX.
The AD857x family are CMOS amplifiers that achieve their
high degree of precision through random frequency autozero
stabilization. The autocorrection topology allows the AD857x
to maintain its low offset voltage over a wide temperature range,
and the randomized autozero clock eliminates any intermodulation
distortion (IMD) errors at the amplifier’s output.
The AD857x can be run from a single supply voltage as low as
2.7 V. The extremely low offset voltage of 1 µV and no IMD
products allows the amplifier to be easily configured for high
gains without risk of excessive output voltage errors. This makes
the AD857x an ideal amplifier for applications requiring both dc
precision and low distortion for ac signals. The extremely small
temperature drift of 5 nV/°C ensures a minimum of offset voltage
error over its entire temperature range of –40°C to +125°C. These
combined features make the AD857x an excellent choice for a
variety of sensitive measurement and automotive applications.
There are two modes of operation determined by the action of
two sets of switches in the amplifier: An autozero phase and an
amplification phase.
Autozero Phase
In this phase, all φA switches are closed and all φB switches are
opened. Here, the nulling amplifier is taken out of the gain loop
by shorting its two inputs together. Of course, there is a degree of
offset voltage, shown as VOSA, inherent in the nulling amplifier,
which maintains a potential difference between the +IN and –IN
inputs. The nulling amplifier feedback loop is closed through φA2
Amplifier Architecture
Each AD857x op amp consists of two amplifiers, a main amplifier
and a secondary amplifier, used to correct the offset voltage of the
main amplifier. Both consist of a rail-to-rail input stage, allowing
the input common-mode voltage range to reach both supply rails.
The input stage consists of an NMOS differential pair operating
concurrently with a parallel PMOS differential pair. The outputs
from the differential input stages are combined in another gain
stage whose output is used to drive a rail-to-rail output stage.
and VOSA appears at the output of the nulling amp and on CM1
,
an internal capacitor in the AD857x. Mathematically, we can
express this in the time domain as:
VOA t = A V
t − B V
t
(1)
(2)
[ ]
OSA[ ] OA[ ]
A
A
which can be expressed as,
The wide voltage swing of the amplifier is achieved by using two
output transistors in a common-source configuration. The output
voltage range is limited by the drain-to-source resistance of these
transistors. As the amplifier is required to source or sink more
output current, the voltage drop across these transistors increases
due to their rds. Simply put, the output voltage will not swing as
close to the rail under heavy output current conditions as it will
with light output current. This is a characteristic of all rail-to-rail
output amplifiers. Figures 6 and 7 show how close the output
voltage can get to the rails with a given output current. The out-
put of the AD857x is short circuit protected to approximately
50 mA of current.
AAVOSA
t
[ ]
VOA t =
[ ]
1+ BA
This shows us that the offset voltage of the nulling amplifier
times a gain factor appears at the output of the nulling amplifier
and thus on the CM1 capacitor.
V
V
IN+
A
V
OUT
B
IN؊
B
B
⌽B
V
OA
C
M2
⌽B
V
OSA
+
⌽A
The AD857x amplifiers have exceptional gain, yielding greater
than 120 dB of open-loop gain with a load of 2 kΩ. Because the
output transistors are configured in a common-source configu-
ration, the gain of the output stage, and thus the open-loop gain
of the amplifier, is dependent on the load resistance. Open-loop
gain will decrease with smaller load resistances. This is another
characteristic of rail-to-rail output amplifiers.
A
V
A
NB
؊B
A
⌽A
C
M1
V
NA
Figure 44. Autozero Phase of the AD857x
Amplification Phase
Basic Autozero Amplifier Theory
Autocorrection amplifiers are not a new technology. Various IC
implementations have been available for over 15 years and some
improvements have been made over time. The AD857x design
offers a number of significant performance improvements over
older versions while attaining a very substantial reduction in
device cost. This section offers a simplified explanation of how
the AD857x is able to offer extremely low offset voltages and
high open-loop gains.
When the φB switches close and the φA switches open for the
amplification phase, this offset voltage remains on CM1 and
essentially corrects any error from the nulling amplifier. The
voltage across CM1 is designated as VNA. Let us also designate
VIN as the potential difference between the two inputs to the
primary amplifier, or VIN = (VIN+ – VIN–). Now the output of the
nulling amplifier can be expressed as:
VOA t = A V t −V
t
− B V
t
(3)
[ ] IN [ ] OSA[ ]
(
)
NA[ ]
A
A
–10–
REV. 0
AD8571/AD8572/AD8574
The AD857x architecture is optimized in such a way that
V
V
IN+
A
V
OUT
B
A
A = AB and BA = BB and BA >> 1. Also, the gain product to
IN؊
B
AABB is much greater than AB. These allow Equation 10 to be
B
⌽B
simplified to:
C
M2
⌽B
V
⌽A
OSA
+
V
OA
VOUT t ≈V t A B + A V +VOSB
OSA
(11)
(
)
[ ]
IN [ ]
A
A
A
V
A
NB
A
Most obvious is the gain product of both the primary and nulling
amplifiers. This AABA term is what gives the AD857x its extremely
high open-loop gain. To understand how VOSA and VOSB relate to
the overall effective input offset voltage of the complete amplifier,
we should set up the generic amplifier equation of:
؊B
A
⌽A
C
M1
V
NA
Figure 45. Output Phase of the Amplifier
VOUT = k × V +VOS, EFF
(12)
(
)
Because φA is now open and there is no place for CM1 to dis-
charge, the voltage VNA at the present time t is equal to the
voltage at the output of the nulling amp VOA at the time when
φA was closed. If we call the period of the autocorrection
switching frequency TS, then the amplifier switches between
phases every 0.5 ϫ TS. Therefore, in the amplification phase:
IN
Where k is the open-loop gain of an amplifier and VOS, EFF is its
effective offset voltage. Putting Equation 12 into the form of
Equation 11 gives us:
VOUT t ≈V t A B +VOS, EFF AABA
[ ] IN [ ]
(13)
A
A
1
And from here, it is easy to see that:
VNA t =V
[ ]
t − TS
(4)
NA
2
VOSA +VOSB
VOS, EFF
≈
(14)
And substituting Equation 4 and Equation 2 into Equation 3 yields:
BA
1
AABAVOSA t − TS
2
Thus, the offset voltages of both the primary and nulling ampli-
fiers are reduced by the gain factor BA. This takes a typical input
offset voltage from several millivolts down to an effective input
offset voltage of submicrovolts. This autocorrection scheme is
what makes the AD857x family of amplifiers among the most
precise amplifiers in the world.
(5)
VOA t = A V t + A V
t −
[ ] IN [ ] OSA[ ]
A
A
1+ BA
For the sake of simplification, let us assume that the autocorrection
frequency is much faster than any potential change in VOSA or
OSB. This is a good assumption since changes in offset voltage are
a function of temperature variation or long-term wear time, both of
which are much slower than the auto-zero clock frequency of the
AD857x. This effectively makes VOS time invariant and we can
rearrange Equation 5 and rewrite it as:
V
High Gain, CMRR, PSRR
Common-mode and power supply rejection are indications of the
amount of offset voltage an amplifier has as a result of a change in its
input common-mode or power supply voltages. As shown in the
previous section, the autocorrection architecture of the AD857x
allows it to quite effectively minimize offset voltages. The technique
also corrects for offset errors caused by common-mode voltage
swings and power supply variations. This results in superb CMRR
and PSRR figures in excess of 130 dB. Because the autocorrection
occurs continuously, these figures can be maintained across the
device’s entire temperature range, from –40°C to +125°C.
A 1+ B VOSA − AABAVOSA
(
)
A
A
VOA t = A V t +
[ ] IN [ ]
(6)
A
1+ BA
or,
VOSA
1+ BA
VOA t = A VIN t +
[ ] [ ]
A
(7)
Maximizing Performance Through Proper Layout
To achieve the maximum performance of the extremely high
input impedance and low offset voltage of the AD857x, care
should be taken in the circuit board layout. The PC board sur-
face must remain clean and free of moisture to avoid leakage
currents between adjacent traces. Surface coating of the circuit
board will reduce surface moisture and provide a humidity
barrier, reducing parasitic resistance on the board. The use of
guard rings around the amplifier inputs will further reduce leak-
age currents. Figure 46 shows how the guard ring should be
configured and Figure 47 shows the top view of how a surface
mount layout can be arranged. The guard ring does not need to
be a specific width, but it should form a continuous loop around
both inputs. By setting the guard ring voltage equal to the volt-
age at the noninverting input, parasitic capacitance is minimized
as well. For further reduction of leakage currents, components
can be mounted to the PC board using Teflon standoff insulators.
We can already get a feel for the autozeroing in action. Note the
OS term is reduced by a 1 + BA factor. This shows how the
nulling amplifier has greatly reduced its own offset voltage error
even before correcting the primary amplifier. Now the primary
amplifier output voltage is the voltage at the output of the
AD857x amplifier. It is equal to:
V
VOUT t = A V t +V
[ ] IN [ ]
In the amplification phase, VOA = VNB, so this can be rewritten as:
+ B V
B NB
(8)
(
)
B
OSB
VOSA
1+ BA
VOUT t = A V t + A V
[ ] IN [ ]
+ BB AA VIN t +
[ ]
B
B
OSB
(9)
Combining terms,
VOUT t =V t A + A B
AABBVOSA
1+ BA
+
+ ABVOSB
(
IN [ ]
)
[ ]
B
A
B
(10)
REV. 0
–11–
AD8571/AD8572/AD8574
R
F
R
1
V
V
OUT
OUT
V
V
IN
V
IN
OUT
AD8572
AD8572
V
IN
AD857x
R
= R
1
S
A
= 1 + (R /R )
F 1
V
NOTE: R SHOULD BE PLACED IN CLOSE PROXIMITY AND
S
V
IN
ALIGNMENT TO R TO BALANCE SEEBECK VOLTAGES
V
1
OUT
AD8572
Figure 49. Using Dummy Components to Cancel
Thermoelectric Voltage Errors
Figure 46. Guard Ring Layout and Connections to Reduce
PC Board Leakage Currents
1/f Noise Characteristics
Another advantage of autozero amplifiers is their ability to cancel
flicker noise. Flicker noise, also known as 1/f noise, is noise inher-
ent in the physics of semiconductor devices and increases 3 dB
for every octave decrease in frequency. The 1/f corner frequency
of an amplifier is the frequency at which the flicker noise is equal
to the broadband noise of the amplifier. At lower frequencies,
flicker noise dominates, causing higher degrees of error for sub-
Hertz frequencies or dc precision applications.
V+
R
R
2
1
AD8572
R
R
1
2
V
IN1
V
IN2
GUARD
RING
GUARD
RING
V
REF
V
REF
Because the AD857x amplifiers are self-correcting op amps,
they do not have increasing flicker noise at lower frequencies.
In essence, low frequency noise is treated as a slowly varying
offset error and is greatly reduced as a result of autocorrection.
The correction becomes more effective as the noise frequency
approaches dc, offsetting the tendency of the noise to increase
exponentially as frequency decreases. This allows the AD857x
to have lower noise near dc than standard low-noise amplifiers
that are susceptible to 1/f noise.
V؊
Figure 47. Top View of AD8572 SOIC Layout with
Guard Rings
Other potential sources of offset error are thermoelectric voltages
on the circuit board. This voltage, also called Seebeck voltage,
occurs at the junction of two dissimilar metals and is proportional
to the temperature of the junction. The most common metallic
junctions on a circuit board are solder-to-board trace and solder-
to-component lead. Figure 48 shows a cross-section diagram view
of the thermal voltage error sources. If the temperature of the PC
board at one end of the component (TA1) is different from the
temperature at the other end (TA2), the Seebeck voltages will not
be equal, resulting in a thermal voltage error.
Random Autozero Correction Eliminates Intermodulation
Distortion
The AD857x can be used as a conventional op amp for gains up
to 1 MHz. The autozero correction frequency of the device
continuously varies, based on a pseudo-random generator with a
uniform distribution from 2 kHz to 4 kHz. The randomization
of the autocorrection clock creates a continuous randomization
of intermodulation distortion (IMD) products, which show up
as simple broadband noise at the output of the amplifier. This
noise naturally combines with the amplifier’s voltage noise in a
root-squared-sum fashion, resulting in an output free of IMD.
Figure 50a shows the spectral output of an AD8572 with the
amplifier configured for unity gain and the input grounded. Figure
50b shows the spectral output with the amplifier configured for a
gain of 60 dB.
This thermocouple error can be reduced by using dummy com-
ponents to match the thermoelectric error source. Placing the
dummy component as close as possible to its partner will ensure
both Seebeck voltages are equal, thus canceling the thermo-
couple error. Maintaining a constant ambient temperature on
the circuit board will further reduce this error. The use of a
ground plane will help distribute heat throughout the board and
will also reduce EMI noise pickup.
COMPONENT
LEAD
SOLDER
V
V
SC2
SC1
+
SURFACE MOUNT
COMPONENT
+
؊
؊
V
V
TS2
TS1
+
+
؊
؊
PC BOARD
T
T
A2
A1
COPPER
TRACE
IF T = T , THEN
A1
A2
V
+ V
= V
+ V
TS1
SC1
TS2 SC2
Figure 48. Mismatch in Seebeck Voltages Causes a
Thermoelectric Voltage Error
–12–
REV. 0
AD8571/AD8572/AD8574
Broadband and External Resistor Noise Considerations
The total broadband noise output from any amplifier is primarily
a function of three types of noise: Input voltage noise from the
amplifier, input current noise from the amplifier and Johnson
noise from the external resistors used around the amplifier. Input
voltage noise, or en, is strictly a function of the amplifier used.
The Johnson noise from a resistor is a function of the resistance
and the temperature. Input current noise, or in, creates an equiva-
lent voltage noise proportional to the resistors used around the
amplifier. These noise sources are not correlated with each other
and their combined noise sums in a root-squared-sum fashion.
The full equation is given as:
0
؊20
؊40
؊60
؊80
V
A
= 5V
= 0dB
S
V
؊100
؊120
؊140
1
2
)
2
en, TOTAL = en2 + 4kTr + i r
؊160
(15)
(
s
n s
0
1
2
3
4
5
6
7
8
9
10
FREQUENCY – kHz
Where, en = The input voltage noise of the amplifier,
in = The input current noise of the amplifier,
Figure 50a. Spectral Analysis of AD857x Output in
Unity Gain Configuration
rs = Source resistance connected to the noninverting
terminal,
0
k = Boltzmann’s constant (1.38 ϫ 10-23 J/K)
T = Ambient temperature in Kelvin (K = 273.15 + °C)
V
= 5V
S
؊20
؊40
A
= 60dB
V
The input voltage noise density, en, of the AD857x is 51 nV/√Hz,
and the input noise, in , is 2 fA/√Hz. The en, TOTAL will be domi-
nated by input voltage noise provided the source resistance is less
than 172 kΩ. With source resistance greater than 172 kΩ, the
overall noise of the system will be dominated by the Johnson
noise of the resistor itself.
؊60
؊80
Because the input current noise of the AD857x is very small, in
does not become a dominant term unless rs is greater than 4 GΩ,
which is an impractical value of source resistance.
؊100
؊120
The total noise, en, TOTAL, is expressed in volts-per-square-root
Hertz, and the equivalent rms noise over a certain bandwidth
can be found as:
0
1
2
3
4
5
6
7
8
9
10
FREQUENCY – kHz
Figure 50b. Spectral Analysis of AD857x Output with
60 dB Gain
(16)
en = en, TOTAL × BW
Figure 51 shows the spectral output of an AD8572 configured
in a high gain (60 dB) with a 1 mV input signal applied. Note
the absence of any IMD products in the spectrum. The signal-
to-noise (SNR) ratio of the output signal is better than 60 dB,
or 0.1%.
Where BW is the bandwidth of interest in Hertz.
For a complete treatise on circuit noise analysis, please refer to the
1995 Linear Design Seminar book available from Analog Devices.
Output Overdrive Recovery
The AD857x amplifiers have an excellent overdrive recovery of
only 200 µs from either supply rail. This characteristic is particu-
larly difficult for autocorrection amplifiers, as the nulling ampli-
fier requires a substantial amount of time to error correct the
main amplifier back to a valid output. Figure 23 and Figure 24
show the positive and negative overdrive recovery time for the
AD857x.
0
V
= 5V
S
؊20
؊40
A
= 60dB
V
The output overdrive recovery for an autocorrection amplifier is
defined as the time it takes for the output to correct to its final
voltage from an overload state. It is measured by placing the
amplifier in a high gain configuration with an input signal that
forces the output voltage to the supply rail. The input voltage is
then stepped down to the linear region of the amplifier, usually
to half-way between the supplies. The time from the input signal
step-down to the output settling to within 100 µV of its final
value is the overdrive recovery time. Most competitors’ auto-
correction amplifiers require a number of autozero clock cycles
to recover from output overdrive and some can take several
milliseconds for the output to settle properly.
؊60
؊80
؊100
؊120
0
1
2
3
4
5
6
7
8
9
10
FREQUENCY – kHz
Figure 51. Spectral Analysis of AD857x in High Gain with
an Input Signal
REV. 0
–13–
AD8571/AD8572/AD8574
Input Overvoltage Protection
Although the snubber will not recover the loss of amplifier band-
width from the load capacitance, it will allow the amplifier to drive
larger values of capacitance while maintaining a minimum of over-
shoot and ringing. Figure 53 shows the output of an AD857x
driving a 1 nF capacitor with and without a snubber network.
Although the AD857x is a rail-to-rail input amplifier, care should
be taken to ensure that the potential difference between the inputs
does not exceed 5 V. Under normal operating conditions, the
amplifier will correct its output to ensure the two inputs are at
the same voltage. However, if the device is configured as a com-
parator, or is under some unusual operating condition, the input
voltages may be forced to different potentials. This could cause
excessive current to flow through internal diodes in the AD857x
used to protect the input stage against overvoltage.
10s
WITH
SNUBBER
If either input exceeds either supply rail by more than 0.3 V, large
amounts of current will begin to flow through the ESD protection
diodes in the amplifier. These diodes are connected between the
inputs and each supply rail to protect the input transistors against
an electrostatic discharge event and are normally reverse-biased.
However, if the input voltage exceeds the supply voltage, these
ESD diodes will become forward-biased. Without current-limiting,
excessive amounts of current could flow through these diodes
causing permanent damage to the device. If inputs are subject to
overvoltage, appropriate series resistors should be inserted to limit
the diode current to less than 2 mA maximum.
WITHOUT
SNUBBER
V
= 5V
LOAD
S
100mV
C
= 4.7nF
Figure 53. Overshoot and Ringing are Substantially
Reduced Using a Snubber Network
The optimum value for the resistor and capacitor is a function of
the load capacitance and is best determined empirically since actual
CLOAD will include stray capacitances and may differ substantially
from the nominal capacitive load. Table I shows some snubber
network values that can be used as starting points.
Output Phase Reversal
Output phase reversal occurs in some amplifiers when the input
common-mode voltage range is exceeded. As common-mode
voltage is moved outside of the common-mode range, the outputs
of these amplifiers will suddenly jump in the opposite direction to
the supply rail. This is the result of the differential input pair shut-
ting down, causing a radical shifting of internal voltages which
results in the erratic output behavior.
Table I. Snubber Network Values for Driving Capacitive Loads
CLOAD
RX
CX
The AD857x amplifier has been carefully designed to prevent
any output phase reversal, provided both inputs are maintained
within the supply voltages. If one or both inputs could exceed
either supply voltage, a resistor should be placed in series with
the input to limit the current to less than 2 mA. This will ensure
the output will not reverse its phase.
1 nF
4.7 nF
10 nF
200 Ω
60 Ω
20 Ω
1 nF
0.47 µF
10 µF
Power-Up Behavior
On power-up, the AD857x will settle to a valid output within 5 µs.
Figure 54a shows an oscilloscope photo of the output of the ampli-
fier along with the power supply voltage, and Figure 54b shows the
test circuit. With the amplifier configured for unity gain, the device
takes approximately 5 µs to settle to its final output voltage. This
turn-on response time is much faster than most other autocorrection
amplifiers, which can take hundreds of microseconds or longer for
their output to settle.
Capacitive Load Drive
The AD857x has excellent capacitive load-driving capabilities
and can safely drive up to 10 nF from a single 5 V supply.
Although the device is stable, capacitive loading will limit the
bandwidth of the amplifier. Capacitive loads will also increase
the amount of overshoot and ringing at the output. An R-C
snubber network, Figure 52, can be used to compensate the
amplifier against capacitive load ringing and overshoot.
5V
V
OUT
0V
V
AD857x
OUT
R
60⍀
X
V
IN
200mV p-p
C
4.7nF
L
C
X
0.47F
V+
0V
Figure 52. Snubber Network Configuration for Driving
Capacitive Loads
5s
1V
BOTTOM TRACE = 2V/DIV
TOP TRACE = 1V/DIV
Figure 54a. AD857x Output Behavior on Power-Up
–14–
REV. 0
AD8571/AD8572/AD8574
R
2
V
= 0V TO 5V
R
R
SY
1
V2
V1
100k⍀
100k⍀
V
OUT
3
AD857x
V
R
OUT
4
AD857x
R
R
R
R
R
R
4
3
2
1
2
1
IF
=
, THEN V
=
؋
(V1 ؊ V2) OUT
Figure 54b. AD857x Test Circuit for Turn-On Time
Figure 56. Using the AD857x as a Difference Amplifier
In an ideal difference amplifier, the ratio of the resistors are set
exactly equal to:
APPLICATIONS
A 5 V Precision Strain-Gage Circuit
R2 R4
R1 R3
The extremely low offset voltage of the AD8572 makes it an ideal
amplifier for any application requiring accuracy with high gains,
such as a weigh scale or strain-gage. Figure 55 shows a configuration
for a single supply, precision strain-gage measurement system.
AV
=
=
(19)
Which sets the output voltage of the system to:
VOUT = A V1−V2
(20)
A REF192 provides a 2.5 V precision reference voltage for A2.
The A2 amplifier boosts this voltage to provide a 4.0 V reference
for the top of the strain-gage resistor bridge. Q1 provides the cur-
rent drive for the 350 Ω bridge network. A1 is used to amplify the
output of the bridge with the full-scale output voltage equal to:
(
)
V
Due to finite component tolerance the ratio between the four
resistors will not be exactly equal, and any mismatch results in a
reduction of common-mode rejection from the system. Referring
to Figure 56, the exact common-mode rejection ratio can be
expressed as:
2 × R + R
(
)
1
2
(17)
RB
R1R4 + 2R2R4 + R2R3
CMRR =
(21)
2R1R4 − 2R2R3
Where RB is the resistance of the load cell. Using the values given
in Figure 55, the output voltage will linearly vary from 0 V with
no strain to 4 V under full strain.
In the 3 op amp instrumentation amplifier configuration shown
in Figure 57, the output difference amplifier is set to unity gain
with all four resistors equal in value. If the tolerance of the resis-
tors used in the circuit is given as δ, the worst-case CMRR of
the instrumentation amplifier will be:
2
5V
3
6
2.5V
REF192
1k⍀
Q1
2N2222
A2
1
2δ
4
OR
AD8572-B
CMRRMIN
=
(22)
EQUIVALENT
12k⍀
20k⍀
4.0V
AD8574-A
V2
R
R
R
2
1
100⍀
17.4k⍀
R
R
R
R
40mV
FULL-SCALE
V
A1
V
OUT
R
OUT
G
350⍀
LOAD
CELL
0V TO 4V
AD8572-A
AD8574-C
R
R
4
100⍀
R
3
R
TRIM
V1
17.4k⍀
NOTE:
AD8574-B
USE 0.1% TOLERANCE RESISTORS.
2R
(V1 ؊ V2)
V
= 1 +
OUT
Figure 55. A 5 V Precision Strain-Gage Amplifier
R
G
3 V Instrumentation Amplifier
Figure 57. A Discrete Instrumentation Amplifier
Configuration
The high common-mode rejection, high open-loop gain, and
operation down to 3 V of supply voltage makes the AD857x an
excellent choice of op amp for discrete single supply instrumenta-
tion amplifiers. The common-mode rejection ratio of the AD857x
is greater than 120 dB, but the CMRR of the system is also a
function of the external resistor tolerances. The gain of the differ-
ence amplifier shown in Figure 56 is given as:
Thus, using 1% tolerance resistors would result in a worst-case
system CMRR of 0.02, or 34 dB. Therefore either high precision
resistors or an additional trimming resistor, as shown in Figure 57,
should be used to achieve high common-mode rejection. The value
of this trimming resistor should be equal to the value of R multi-
plied by its tolerance. For example, using 10 kΩ resistors with 1%
tolerance would require a series trimming resistor equal to 100 Ω.
R4
R3 + R4
R1
R2
R2
R1
VOUT =V1
1+
−V2
(18)
REV. 0
–15–
AD8571/AD8572/AD8574
A High Accuracy Thermocouple Amplifier
Figure 60 shows the low-side monitor equivalent. In this circuit,
the input common-mode voltage to the AD8572 will be at or near
ground. Again, a 0.1 Ω resistor provides a voltage drop proportional
to the return current. The output voltage is given as:
Figure 58 shows a K-type thermocouple amplifier configuration
with cold-junction compensation. Even from a 5 V supply, the
AD8571 can provide enough accuracy to achieve a resolution
of better than 0.02°C from 0°C to 500°C. D1 is used as a tempera-
ture measuring device to correct the cold-junction error from
the thermocouple and should be placed as close as possible to
the two terminating junctions. With the thermocouple measuring
tip immersed in a zero-degree ice bath, R6 should be adjusted
until the output is at 0 V.
R2
R1
VOUT =V + −
× RSENSE × IL
(24)
For the component values shown in Figure 60, the output transfer
function decreases from V at –2.5 V/A.
Using the values shown in Figure 58, the output voltage will
track temperature at 10 mV/°C. For a wider range of tempera-
ture measurement, R9 can be decreased to 62 kΩ. This will
create a 5 mV/°C change at the output, allowing measurements
of up to 1000°C.
R
0.1⍀
SENSE
I
L
3V
V+
3V
0.1F
R
100⍀
1
3
2
8
1/2
1
AD8572
REF02EZ
5V
4
6
2
12V
S
G
M1
Si9433
0.1F
4
R
5
R
40.2k⍀
9
D
MONITOR
OUTPUT
124k⍀
R
1
R
10.7k⍀
1N4148
D1
2
2.49k⍀
5V
10F
+
0.1F
Figure 59. A High-Side Load Current Monitor
R
R
8
453⍀
2
2.74k⍀
2
3
–
+
–
+
8
K-TYPE
THERMOCOUPLE
40.7V/؇C
V+
1
R
200⍀
6
AD8571
4
R
2
2.49k⍀
0V TO 5V
(0؇C TO 500؇C)
R
4
5.62k⍀
R
3
V
OUT
53.6⍀
Q1
V+
Figure 58. A Precision K-Type Thermocouple Amplifier
with Cold-Junction Compensation
R
100⍀
Precision Current Meter
1
1/2 AD8572
R
0.1⍀
Because of its low input bias current and superb offset voltage at
single supply voltages, the AD857x is an excellent amplifier for
precision current monitoring. Its rail-to-rail input allows the
amplifier to be used as either a high-side or low-side current
monitor. Using both amplifiers in the AD8572 provides a simple
method to monitor both current supply and return paths for
load or fault detection.
SENSE
RETURN TO
GROUND
Figure 60. A Low-Side Load Current Monitor
Precision Voltage Comparator
The AD857x can be operated open-loop and used as a precision
comparator. The AD857x has less than 50 µV of offset voltage
when run in this configuration. The slight increase of offset
voltage stems from the fact that the autocorrection architecture
operates with lowest offset in a closed-loop configuration, that
is, one with negative feedback. With 50 mV of overdrive, the
device has a propagation delay of 15 µs on the rising edge and
8 µs on the falling edge.
Figure 59 shows a high-side current monitor configuration. Here,
the input common-mode voltage of the amplifier will be at or near
the positive supply voltage. The amplifier’s rail-to-rail input provides
a precise measurement, even with the input common-mode voltage
at the supply voltage. The CMOS input structure does not draw any
input bias current, ensuring a minimum of measurement error.
The 0.1 Ω resistor creates a voltage drop to the noninverting
input of the AD857x. The amplifier’s output is corrected until
this voltage appears at the inverting input. This creates a current
through R1, which in turn flows through R2. The Monitor Output
is given by:
Care should be taken to ensure the maximum differential volt-
age of the device is not exceeded. For more information, please
refer to the section on Input Overvoltage Protection.
RSENSE
Monitor Output = R2 ×
× IL
(23)
R1
Using the components shown in Figure 59, the Monitor Output
transfer function is 2.5 V/A.
–16–
REV. 0
AD8571/AD8572/AD8574
SPICE Model
The network around ECM1 creates the common-mode voltage
error, with CCM1 setting the corner frequency for the CMRR
roll-off. The power supply rejection error is created by the network
around EPS1, with CPS3 establishing the corner frequency for
the PSRR roll-off. The two current loops around nodes 80 and
81 are used to create a 51 nV/√Hz noise figure across RN2. All
three of these error sources are reflected to the input of the op
amp model through EOS. Finally, GSY is used to accurately
model the supply current versus supply voltage increase in
the AD857x.
The SPICE macro-model for the AD857x amplifier is given in
Listing 1. This model simulates the typical specifications for the
AD857x, and it can be downloaded from the Analog Devices
website at http://www.analog.com. The schematic of the
macro-model is shown in Figure 61.
Transistors M1 through M4 simulate the rail-to-rail input differ-
ential pairs in the AD857x amplifier. The EOS voltage source in
series with the noninverting input establishes not only the 1 µV
offset voltage, but is also used to establish common-mode and
power supply rejection ratios and input voltage noise. The differ-
ential voltages from nodes 14 to 16 and nodes 17 to 18 are reflected
to E1, which is used to simulate a secondary pole-zero combination
in the open-loop gain of the amplifier.
This macro-model has been designed to accurately simulate a
number of specifications exhibited by the AD857x amplifier,
and is one of the most true-to-life macro-models available for
any op amp. It is optimized for operation at 27°C. Although the
model will function at different temperatures, it may lose accuracy
with respect to the actual behavior of the AD857x.
The voltage at node 32 is then reflected to G1, which adds an
additional gain stage and, in conjunction with CF, establishes
the slew rate of the model at 0.5 V/µs. M5 and M6 are in a
common-source configuration, similar to the output stage of
the AD857x amplifier. EG1 and EG2 fix the quiescent current
in these two transistors at 100 µA, and also help accurately
simulate the VOUT vs. IOUT characteristic of the amplifier.
CCM1
99
R
CM1
21
+
22
R
D1
I1
9
ECM1
CM2
V1
؊
8
99
98
R
R
C8
80
81
C7
C2
10
+
18
R
17
VN1
R
HN
R
N2
N1
R
C3
C4
M1
R
M2
11
12
7
1
M3
M4
2
98
+
EOS
؊
99
CPS3
D2
V1
R
13
I2
99
CPS1
C1
C2
70
R
PS3
R
PS1
72
73
50
؊
0
GSY
EPS1
R
PS4
C1
+
R
PS2
14
16
71
R
R
C6
C5
98
CPS2
50
50
99
50
+
98
؊
EG1
C2
؊
EVP
M5
46
+
97
51
R
2
D3
D4
CF
31
32
30
45
+
E1
R
R
3
G1
1
+
47
؊
+
M6
EVN
؊
98
+
EG2
98
؊
98
EREF
؊
50
0
Figure 61. Schematic of the AD857x SPICE Macro-Model
REV. 0
–17–
AD8571/AD8572/AD8574
SPICE macro-model for the AD857x
* VOLTAGE NOISE REFERENCE OF 51nV/rt(Hz)
*
* AD8572 SPICE Macro-model
VN1 80 98 0
RN1 80 98 16.45E-3
HN 81 98 VN1 51
RN2 81 98 1
* Typical Values
* 7/99, Ver. 1.0
* TAM / ADSC
*
*
* Copyright 1999 by Analog Devices
*
* INTERNAL VOLTAGE REFERENCE
*
* Refer to “README.DOC” file for License
* Statement. Use of this model indicates
* your acceptance of the terms and
* provisions in the License Statement.
*
EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5
GSY 99 50 (99,50) 48E-6
EVP 97 98 (99,50) 0.5
EVN 51 98 (50,99) 0.5
*
* Node Assignments
* LHP ZERO AT 7MHz, POLE AT 50MHz
*
noninverting input
*
*
|
|
|
|
|
|
1
inverting input
E1 32 98 POLY(2) (4,6) (11,12) 0 .5814 .5814
*
|
|
|
|
|
2
positive supply
R2 32 33 3.7E+3
*
|
|
|
|
negative supply
R3 33 98 22.74E+3
*
|
|
|
output
|
|
C3 32 33 1E-12
*
*
*
* GAIN STAGE
.SUBCKT AD8572
99 50 45
*
*
G1 98 30 (33,98) 22.7E-6
R1 30 98 259.1E+6
* INPUT STAGE
*
CF 45 30 45.4E-12
M1
M2
4
6
7
2
8
8
8 PIX L=1E-6 W=355.3E-6
8 PIX L=1E-6 W=355.3E-6
D3 30 97 DX
D4 51 30 DX
M3 11 7 10 10 NIX L=1E-6 W=355.3E-6
M4 12 2 10 10 NIX L=1E-6 W=355.3E-6
RC1 4 14 9E+3
*
* OUTPUT STAGE
*
RC2 6 16 9E+3
M5 45 46 99 99 POX L=1E-6 W=1.111E-3
M6 45 47 50 50 NOX L=1E-6 W=1.6E-3
EG1 99 46 POLY(1) (98,30) 1.1936 1
EG2 47 50 POLY(1) (30,98) 1.2324 1
RC3 17 11 9E+3
RC4 18 12 9E+3
RC5 14 50 1E+3
RC6 16 50 1E+3
*
RC7 99 17 1E+3
RC8 99 18 1E+3
* MODELS
C1 14 16 30E-12
C2 17 18 30E-12
I1 99 8 100E-6
I2 10 50 100E-6
V1 99 9 0.3
*
.MODEL POX PMOS (LEVEL=2,KP=10E-6,
+ VTO=-1,LAMBDA=0.001,RD=8)
.MODEL NOX NMOS (LEVEL=2,KP=10E-6,
+ VTO=1,LAMBDA=0.001,RD=5)
.MODEL PIX PMOS (LEVEL=2,KP=100E-6,
+ VTO=-1,LAMBDA=0.01)
.MODEL NIX NMOS (LEVEL=2,KP=100E-6,
+ VTO=1,LAMBDA=0.01)
.MODEL DX D(IS=1E-14,RS=5)
.ENDS AD8572
V2 13 50 0.3
D1
D2 13 10 DX
EOS 1 POLY(3) (22,98) (73,98) (81,98)
+ 1E-6 1 1 1
8
9 DX
7
IOS
*
1
2 2.5E-12
* CMRR 120dB, ZERO AT 20Hz
*
ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5
RCM1 21 22 50E+6
CCM1 21 22 159E-12
RCM2 22 98 50
*
* PSRR=120dB, ZERO AT 1Hz
*
RPS1 70 0 1E+6
RPS2 71 0 1E+6
CPS1 99 70 1E-5
CPS2 50 71 1E-5
EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1
RPS3 72 73 15.9E+6
CPS3 72 73 10E-9
RPS4 73 98 16
–18–
REV. 0
AD8571/AD8572/AD8574
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead MSOP
(RM Suffix)
8-Lead SOIC
(R Suffix)
0.1968 (5.00)
0.1890 (4.80)
0.122 (3.10)
0.114 (2.90)
8
1
5
4
0.1574 (4.00)
0.1497 (3.80)
0.2440 (6.20)
0.2284 (5.80)
8
5
4
0.122 (3.10)
0.114 (2.90)
0.199 (5.05)
0.187 (4.75)
1
PIN 1
0.0688 (1.75)
0.0532 (1.35)
0.0196 (0.50)
0.0099 (0.25)
x 45°
0.0098 (0.25)
0.0040 (0.10)
PIN 1
0.0256 (0.65) BSC
0.120 (3.05)
0.112 (2.84)
0.120 (3.05)
0.112 (2.84)
8°
0°
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
SEATING
PLANE
0.0098 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.043 (1.09)
0.037 (0.94)
0.006 (0.15)
0.002 (0.05)
0.0160 (0.41)
33؇
0.018 (0.46)
0.008 (0.20)
27؇
0.028 (0.71)
0.016 (0.41)
0.011 (0.28)
0.003 (0.08)
SEATING
PLANE
8-Lead TSSOP
(RU Suffix)
14-Lead TSSOP
(RU Suffix)
0.122 (3.10)
0.114 (2.90)
0.201 (5.10)
0.193 (4.90)
14
8
7
8
5
1
1
4
PIN 1
PIN 1
0.0256 (0.65)
BSC
0.006 (0.15)
0.002 (0.05)
0.006 (0.15)
0.002 (0.05)
0.0433
(1.10)
MAX
0.0433
(1.10)
MAX
0.028 (0.70)
0.020 (0.50)
0.028 (0.70)
0.020 (0.50)
8؇
0؇
8؇
0؇
0.0118 (0.30)
0.0075 (0.19)
0.0118 (0.30)
0.0075 (0.19)
0.0256
(0.65)
BSC
SEATING
PLANE
SEATING
PLANE
0.0079 (0.20)
0.0035 (0.090)
0.0079 (0.20)
0.0035 (0.090)
14-Lead SOIC
(R Suffix)
0.3444 (8.75)
0.3367 (8.55)
14
8
7
0.1574 (4.00)
0.1497 (3.80)
0.2440 (6.20)
0.2284 (5.80)
1
0.0688 (1.75)
0.0532 (1.35)
PIN 1
0.0196 (0.50)
0.0099 (0.25)
x 45؇
0.0098 (0.25)
0.0040 (0.10)
8؇
0؇
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
SEATING
PLANE
0.0500 (1.27)
0.0160 (0.41)
0.0099 (0.25)
0.0075 (0.19)
REV. 0
–19–
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