AD8591ART-REEL [ADI]
CMOS Single-Supply, Rail-to-Rail Input/Output Operational Amplifiers with Shutdown; CMOS单电源，带有关断轨至轨输入/输出运算放大器
| 型号： | AD8591ART-REEL |
| 厂家： | 
ADI |
| 描述： | CMOS Single-Supply, Rail-to-Rail Input/Output Operational Amplifiers with Shutdown |
| 文件： | 总16页 (文件大小：408K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS Single-Supply, Rail-to-Rail Input/Output
Operational Amplifiers with Shutdown
AD8591/AD8592/AD8594
FEATURES
PIN CONFIGURATIONS
Single-supply operation: 2.5 V to 6 V
High output current: 250 mA
Extremely low shutdown supply current: 100 nA
Low supply current: 750 μA/Amp
Wide bandwidth: 3 MHz
OUT A
1
2
3
6
5
4
V+
AD8591
V–
SD
TOP VIEW
(Not to Scale)
+IN A
–IN A
Slew rate: 5 V/μs
Figure 1. 6-Lead SOT-23 (RJ Suffix)
No phase reversal
Very low input bias current
High impedance outputs when in shutdown mode
Unity-gain stable
OUT A
–IN A
+IN A
V–
1
2
3
4
5
10 V+
9
8
7
6
OUT B
–IN B
+IN B
SDB
AD8592
TOP VIEW
(Not to Scale)
SDA
APPLICATIONS
Figure 2. 10-Lead MSOP (RM Suffix)
Mobile communication handset audio
PC audio
PCMCIA/modem line driving
Battery-powered instrumentation
Data acquisition
OUT A
–IN A
+IN A
V+
1
2
3
4
5
6
7
8
16 OUT D
15 –IN D
14
+IN D
AD8594
13 V–
TOP VIEW
(Not to Scale)
+IN B
–IN B
OUT B
NC
12 +IN C
11 –IN C
10 OUT C
ASIC input or output amplifiers
LCD display reference level drivers
9
SD
NC = NO CONNECT
Figure 3. 16-Lead Narrow SOIC (R Suffix)
GENERAL DESCRIPTION
The AD8591, AD8592, and AD8594 are single, dual, and quad
rail-to-rail, input and output single-supply amplifiers featuring
250 mA output drive current and a power saving shutdown mode.
The AD8592 includes an independent shutdown function for
each amplifier. When both amplifiers are in shutdown mode,
the total supply current is reduced to less than 1 μA. The AD8591
and AD8594 include a single master shutdown function that
reduces the total supply current to less than 1 μA. All amplifier
outputs are in a high impedance state when in shutdown mode.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
OUT A
–IN A
+IN A
V+
OUT D
–IN D
+IN D
V–
AD8594
TOP VIEW
(Not to Scale)
+IN B
–IN B
OUT B
NC
+IN C
–IN C
OUT C
SD
NC = NO CONNECT
These amplifiers have very low input bias currents, making them
suitable for integrators and diode amplification. Outputs are stable
with virtually any capacitive load. Supply current is less than
750 μA per amplifier in active mode.
Figure 4. 16-Lead TSSOP (RU Suffix)
The AD8591, AD8592, and AD8594 are specified over the
industrial temperature range (−40°C to +85°C). The AD8591,
single, is available in the tiny 6-lead SOT-23 package. The AD8592,
dual, is available in the 10-lead surface-mount MSOP package. The
AD8594, quad, is available in 16-lead narrow SOIC and 16-lead
TSSOP packages.
Applications for these amplifiers include audio amplification for
portable computers, portable phone headsets, sound ports, sound
cards, and set-top boxes. The AD859x family is capable of driving
heavy capacitive loads, such as LCD panel reference levels.
The ability to swing rail to rail at both the input and output enables
designers to buffer CMOS DACs, ASICs, and other wide output
swing devices in single-supply systems.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2009 Analog Devices, Inc. All rights reserved.
AD8591/AD8592/AD8594
TABLE OF CONTENTS
Features .............................................................................................. 1
Output Short-Circuit Protection.............................................. 11
Power Dissipation....................................................................... 11
Capacitive Loading..................................................................... 12
PC98-Compliant Headphone/Speaker Amplifier.................. 12
Applications....................................................................................... 1
General Description......................................................................... 1
Pin Configurations ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics............................................................. 3
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Typical Performance Characteristics ............................................. 6
Theory of Operation ...................................................................... 11
Input Voltage Protection............................................................ 11
Output Phase Reversal............................................................... 11
A Combined Microphone and Speaker Amplifier for
Cellphone and Portable Headsets ............................................ 13
An Inexpensive Sample-and-Hold Circuit ............................. 13
Direct Access Arrangement for PCMCIA Modems
(Telephone Line Interface)........................................................ 14
Single-Supply Differential Line Driver.................................... 14
Outline Dimensions....................................................................... 15
Ordering Guide .......................................................................... 16
REVISION HISTORY
1/09—Rev. A to Rev. B
Updated Format..................................................................Universal
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 4
Deleted Spice Model for AD8591/AD8592/AD8594 Amplifiers
Sections ............................................................................................ 12
Changes to PC98-Compliant Headphone/Speaker Amplifier
Section and Figure 38..................................................................... 12
Changes to Figure 39...................................................................... 13
Changes to Figure 42 and Figure 43............................................. 14
Updated Outline Dimensions....................................................... 15
Changes to Ordering Guide .......................................................... 16
Rev. B | Page 2 of 16
AD8591/AD8592/AD8594
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VS = 2.7 V, VCM = 1.35 V, TA = 25°C, unless otherwise noted.
Table 1.
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
VOS
IB
25
30
50
60
25
30
2.7
mV
mV
pA
pA
pA
pA
V
dB
V/mV
μV/°C
fA/°C
fA/°C
−40°C < TA < +85°C
−40°C < TA < +85°C
−40°C < TA < +85°C
Input Bias Current
5
1
Input Offset Current
IOS
Input Voltage Range
Common-Mode Rejection Ratio
Large Signal Voltage Gain
Offset Voltage Drift
Bias Current Drift
Offset Current Drift
0
38
CMRR
AVO
ΔVOS/ΔT
ΔIB/ΔT
ΔIOS/ΔT
VCM = 0 V to 2.7 V
45
25
20
50
20
RL = 2 kΩ, VO = 0.3 V to 2.4 V
−40°C < TA < +85°C
−40°C < TA < +85°C
−40°C < TA < +85°C
OUTPUT CHARACTERISTICS
Output Voltage High
VOH
VOL
IL = 10 mA
−40°C to +85°C
IL = 10 mA
2.55
2.5
2.61
60
V
V
mV
mV
mA
Ω
Output Voltage Low
100
125
−40°C to +85°C
Output Current
Open-Loop Impedance
POWER SUPPLY
IOUT
ZOUT
250
60
f = 1 MHz, AV = 1
Power Supply Rejection Ratio
Supply Current per Amplifier
PSRR
ISY
VS = 2.5 V to 6 V
VO = 0 V
−40°C < TA < +85°C
All amplifiers shut down
−40°C < TA < +85°C
45
55
dB
1
1.25
1
mA
mA
μA
Supply Current Shutdown Mode
ISD
0.1
1
μA
ISD1
ISD2
Amplifier 1 shut down (AD8592)
Amplifier 2 shut down (AD8592)
1.4
1.4
mA
mA
SHUTDOWN INPUTS
Logic High Voltage
Logic Low Voltage
Logic Input Current
DYNAMIC PERFORMANCE
Slew Rate
Settling Time
Gain Bandwidth Product
Phase Margin
VINH
VINL
IIN
−40°C < TA < +85°C
−40°C < TA < +85°C
−40°C < TA < +85°C
1.6
V
V
μA
0.5
1
SR
tS
GBP
Φo
CS
RL = 2 kΩ
To 0.01%
3.5
1.4
2.2
67
V/μs
μs
MHz
Degrees
dB
Channel Separation
NOISE PERFORMANCE
Voltage Noise Density
f = 1 kHz, RL = 2 kΩ
65
en
in
f = 1 kHz
f = 10 kHz
f = 1 kHz
45
30
0.05
nV/√Hz
nV/√Hz
pA/√Hz
Current Noise Density
Rev. B | Page 3 of 16
AD8591/AD8592/AD8594
VS = 5.0 V, VCM = 2.5 V, TA = 25°C, unless otherwise noted.
Table 2.
Parameter
Symbol
Test Conditions
Min
Typ
2
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
VOS
IB
25
30
50
60
25
30
5
mV
mV
pA
pA
pA
pA
V
dB
V/mV
μV/°C
fA/°C
fA/°C
−40°C < TA < +85°C
−40°C < TA < +85°C
−40°C < TA < +85°C
Input Bias Current
5
Input Offset Current
IOS
1
Input Voltage Range
Common-Mode Rejection Ratio
Large Signal Voltage Gain
Offset Voltage Drift
Bias Current Drift
Offset Current Drift
0
38
15
CMRR
AVO
ΔVOS/ΔT
ΔIB/ΔT
ΔIOS/ΔT
VCM = 0 V to 5 V
47
30
20
50
20
RL = 2 kΩ, VO = 0.5 V to 4.5 V
−40°C < TA < +85°C
−40°C < TA < +85°C
−40°C < TA < +85°C
OUTPUT CHARACTERISTICS
Output Voltage High
VOH
VOL
IL = 10 mA
−40°C to +85°C
IL = 10 mA
4.9
4.85
4.94
50
V
V
mV
mV
mA
Ω
Output Voltage Low
100
125
−40°C to +85°C
Output Current
Open-Loop Impedance
POWER SUPPLY
IOUT
ZOUT
250
40
f = 1 MHz, AV = 1
Power Supply Rejection Ratio
Supply Current per Amplifier
PSRR
ISY
VS = 2.5 V to 6 V
VO = 0 V
−40°C < TA < +85°C
All amplifiers shut down
−40°C < TA < +85°C
45
55
dB
1.25
1.75
1
mA
mA
μA
Supply Current Shutdown Mode
ISD
0.1
1
μA
ISD1
ISD2
Amplifier 1 shut down (AD8592)
Amplifier 2 shut down (AD8592)
1.6
1.6
mA
mA
SHUTDOWN INPUTS
Logic High Voltage
Logic Low Voltage
Logic Input Current
DYNAMIC PERFORMANCE
Slew Rate
Full Power Bandwidth
Settling Time
Gain Bandwidth Product
Phase Margin
VINH
VINL
IIN
−40°C < TA < +85°C
−40°C < TA < +85°C
−40°C < TA < +85°C
2.4
V
V
μA
0.8
1
SR
BWP
tS
GBP
Φo
CS
RL = 2 kΩ
1% distortion
To 0.01%
5
V/μs
kHz
μs
MHz
Degrees
dB
325
1.6
3
70
65
Channel Separation
NOISE PERFORMANCE
Voltage Noise Density
f = 1 kHz, RL = 10 kΩ
en
in
f = 1 kHz
f = 10 kHz
f = 1 kHz
45
30
0.05
nV/√Hz
nV/√Hz
pA/√Hz
Current Noise Density
Rev. B | Page 4 of 16
AD8591/AD8592/AD8594
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 3.
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Parameter
Rating
Supply Voltage
6 V
Input Voltage
GND to VS
6 V
Table 4.
Package Type
Differential Input Voltage
Output Short-Circuit Duration to GND1
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
Lead Temperature (Soldering, 60 sec)
θJA
θJC
92
44
36
35
Unit
°C/W
°C/W
°C/W
°C/W
Observe Derating Curves
−65°C to +150°C
−40°C to +85°C
−65°C to +150°C
300°C
6-Lead SOT-23 (RJ)
10-Lead MSOP (RM)
16-Lead SOIC (R)
16-Lead TSSOP (RU)
230
200
120
180
1 For supplies less than 5 V, the differential input voltage is limited to the
supplies.
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. B | Page 5 of 16
AD8591/AD8592/AD8594
TYPICAL PERFORMANCE CHARACTERISTICS
1k
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
V
= 2.7V
= 25°C
T
= 25°C
S
A
A
T
100
10
1
SOURCE
SINK
0.1
0.01
0.1
1
10
100
1k
0.75
1.25
1.75
2.25
2.75 3.00
LOAD CURRENT (mA)
SUPPLY VOLTAGE (±V)
Figure 5. Output Voltage to Supply Rail vs. Load Current
Figure 8. Supply Current per Amplifier vs. Supply Voltage
–2
–3
–4
–5
–6
–7
–8
10k
1k
V
= 5V
= 25°C
S
A
V
V
= 5V
CM
S
T
= 2.5V
100
10
1
SINK
SOURCE
0.1
0.01
–50
–35
–15
5
25
45
65
85
0.1
1
10
100
1k
LOAD CURRENT (mA)
TEMPERATURE (°C)
Figure 6. Output Voltage to Supply Rail vs. Load Current
Figure 9. Input Offset Voltage vs. Temperature
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
8
7
6
5
4
3
2
V
V
= 2.7V, 5V
S
= V /2
CM
S
V
= 5V
S
V
= 2.7V
S
–40
–20
0
20
40
60
80
100
–50
–35
–15
5
25
45
65
85
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 10. Input Bias Current vs. Temperature
Figure 7. Supply Current per Amplifier vs. Temperature
Rev. B | Page 6 of 16
AD8591/AD8592/AD8594
80
60
40
20
0
4
3
V
= 5V
= NO LOAD
= 25°C
S
L
V
V
= 2.7V, 5V
S
R
= V /2
CM
S
T
A
45
90
2
135
180
1
0
–1
–2
–50
1k
10k
100k
1M
10M
100M
–35
–15
5
25
45
65
85
FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 11. Input Offset Current vs. Temperature
Figure 14. Open-Loop Gain and Phase vs. Frequency
8
7
6
5
4
3
2
1
5
V
= 2.7V
= 2kΩ
= 25°C
V
A
= 5V
= 25°C
S
L
S
R
T
T
A
V
= 2.5V p-p
IN
4
3
2
1
0
0
1
2
3
4
5
1k
10k
100k
1M
10M
COMMON-MODE VOLTAGE (V)
FREQUENCY (Hz)
Figure 15. Closed-Loop Output Voltage Swing vs. Frequency
Figure 12. Input Bias Current vs. Common-Mode Voltage
5
80
60
40
20
0
V
= 2.7V
V
= 5V
S
L
S
L
R
= NO LOAD
= 25°C
R
= 2kΩ
= 25°C
T
T
A
A
45
V
= 2.5V p-p
IN
4
3
2
1
0
90
135
180
1k
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 16. Closed-Loop Output Voltage Swing vs. Frequency
Figure 13. Open-Loop Gain and Phase vs. Frequency
Rev. B | Page 7 of 16
AD8591/AD8592/AD8594
200
140
120
100
80
V
T
= 5V
= 25°C
V
T
= 5V
= 25°C
S
A
S
A
180
160
140
120
100
80
A
= 10
V
–PSRR
+PSRR
60
40
20
A
= 1
V
60
0
40
–20
–40
–60
20
0
1k
10k
100k
1M
10M
100M
100
1k
10k
100k
1M
10M
10k
10k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 17. Closed-Loop Output Impedance vs. Frequency
Figure 20. Power Supply Rejection Ratio vs. Frequency
110
100
90
60
50
40
30
20
10
0
V
= 5V
S
A
V
= 2.5V
= 2kΩ
= 25°C
S
L
T
= 25°C
R
T
A
+OS
–OS
80
70
60
50
1k
10k
100k
1M
10M
10
100
1k
FREQUENCY (Hz)
CAPACITANCE (pF)
Figure 18. Common-Mode Rejection Ratio vs. Frequency
Figure 21. Small Signal Overshoot vs. Load Capacitance
140
120
100
80
60
50
40
30
20
10
0
V
T
= 2.5V
= 25°C
V
= 5V
= 2kΩ
= 25°C
S
A
S
L
R
T
A
–OS
60
+PSRR
–PSRR
+OS
40
20
0
–20
–40
–60
100
1k
10k
100k
1M
10M
10
100
1k
FREQUENCY (Hz)
CAPACITANCE (pF)
Figure 19. Power Supply Rejection Ratio vs. Frequency
Figure 22. Small Signal Overshoot vs. Load Capacitance
Rev. B | Page 8 of 16
AD8591/AD8592/AD8594
V
= ±2.5V
= +1
= 2kΩ
= 25°C
S
V
L
A
R
100
90
T
A
V
V
= ±1.35V
= ±50mV
= +1
S
IN
V
L
L
0V
A
R
C
= 2kΩ
= 300pF
= 25°C
T
A
10
0
500mV
500ns
500 ns/DIV
Figure 23. Small Signal Transient Response
Figure 26. Large Signal Transient Response
1V
10µs
100
90
V
V
= ±2.5V
= ±50mV
= +1
S
IN
V
L
L
0V
A
R
C
= 2kΩ
= 300pF
= 25°C
T
A
10
0
V
= ±2.5V
= +1
= +25°C
S
V
A
T
1V
A
500 ns/DIV
Figure 24. Small Signal Transient Response
Figure 27. No Phase Reversal
1
V
= 5V
= 25°C
V
= ±1.35V
= +1
= 2kΩ
= 25°C
S
A
S
V
L
T
A
R
100
90
T
A
0.1
10
0
500mV
500ns
0.01
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 25. Large Signal Transient Response
Figure 28. Current Noise Density vs. Frequency
Rev. B | Page 9 of 16
AD8591/AD8592/AD8594
600
500
400
300
200
100
0
V
A
= 5V
= +1000
= 25°C
V
V
= 2.7V
CM
= 25°C
A
S
S
= 1.35V
V
T
T
A
100
90
FREQUENCY = 1kHz
10
0
MARKER 41µV/√Hz
–14 –12 –10
–8
–6
–4
–2
0
2
4
6
INPUT OFFSET VOLTAGE (mV)
Figure 29. Voltage Noise Density vs. Frequency
Figure 31. Input Offset Voltage Distribution
600
500
400
300
200
100
0
V
A
= 5V
= +1000
= 25°C
S
V
V
T
= 5V
S
= 2.5V
V
CM
= 25°C
T
A
A
100
90
FREQUENCY = 10kHz
10
0
MARKER 25.9µV/√Hz
–14 –12 –10
–8
–6
–4
–2
0
2
4
6
INPUT OFFSET VOLTAGE (mV)
Figure 30. Voltage Noise Density vs. Frequency
Figure 32. Input Offset Voltage Distribution
Rev. B | Page 10 of 16
AD8591/AD8592/AD8594
THEORY OF OPERATION
The AD859x amplifiers are CMOS, high output drive, rail-to-
rail input and output single-supply amplifiers designed for low
cost and high output current drive. The parts include a power
saving shutdown function that makes the AD8591/AD8592/
AD8594 op amps ideal for portable multimedia and
telecommunications applications.
OUTPUT PHASE REVERSAL
The AD8591/AD8592/AD8594 are immune to output voltage
phase reversal with an input voltage within the supply voltages
of the device. However, if either of the inputs of the device exceeds
0.6 V outside of the supply rails, the output could exhibit phase
reversal. This is due to the ESD protection diodes becoming
forward-biased, thus causing the polarity of the input terminals
of the device to switch.
Figure 33 shows the simplified schematic for the AD8591/AD8592/
AD8594 amplifiers. Two input differential pairs, consisting of
an n-channel pair (M1, M2) and a p-channel pair (M3, M4),
provide a rail-to-rail input common-mode range. The outputs of
the input differential pairs are combined in a compound folded-
cascode stage that drives the input to a second differential pair
gain stage. The outputs of the second gain stage provide the gate
voltage drive to the rail-to-rail output stage.
The technique recommended in the Input Voltage Protection
section should be applied in applications where the possibility
of input voltages exceeding the supply voltages exists.
OUTPUT SHORT-CIRCUIT PROTECTION
To achieve high output current drive and rail-to-rail performance,
the outputs of the AD859x family do not have internal short-
circuit protection circuitry. Although these amplifiers are
designed to sink or source as much as 250 mA of output current,
shorting the output directly to the positive supply could damage or
destroy the device. To protect the output stage, limit the maximum
output current to 250 mA.
The rail-to-rail output stage consists of M15 and M16, which
are configured in a complementary common source configuration.
As with any rail-to-rail output amplifier, the gain of the output
stage, and thus the open-loop gain of the amplifier, is dependent
on the load resistance. In addition, the maximum output voltage
swing is directly proportional to the load current. The difference
between the maximum output voltage to the supply rails, known as
the dropout voltage, is determined by the on-channel resistance
of the AD8591/AD8592/AD8594 output transistors. The output
dropout voltage is given in Figure 5 and Figure 6.
By placing a resistor in series with the output of the amplifier,
as shown in Figure 34, the output current can be limited. The
minimum value for RX is
VSY
250 mA
RX ≥
(2)
100µA
V+
*
*
*
*
100µA
50µA
For a 5 V single-supply application, RX should be at least 20 Ω.
Because RX is inside the feedback loop, VOUT is not affected. The
trade-off in using RX is a slight reduction in output voltage
swing under heavy output current loads. RX also increases the
effective output impedance of the amplifier to RO + RX, where RO
is the output impedance of the device.
20µA
M11
INV
M337
M5
M12
M30
SD
M8
V
B2
M3
M1
M4
M15
M16
IN–
OUT
M2
M6
M7
IN+
+5V
V
M9
20µA
B3
M14
R
20Ω
V
X
IN
*
INV
V
AD8592
OUT
M340
M13
*
M10
M31
50µA
Figure 34. Output Short-Circuit Protection
V–
*ALL CURRENT SOURCES GO TO 0µA IN SHUTDOWN MODE.
POWER DISSIPATION
Figure 33. Simplified Schematic
Although the AD859x amplifiers are able to provide load
currents of up to 250 mA, proper attention should be given to
not exceeding the maximum junction temperature for the device.
The junction temperature equation is
INPUT VOLTAGE PROTECTION
Although not shown in the simplified schematic, ESD protection
diodes are connected from each input to each power supply rail.
These diodes are normally reverse-biased, but turn on if either
input voltage exceeds either supply rail by more than 0.6 V. If this
condition occurs, limit the input current to less than 5 mA.
This is done by placing a resistor in series with the input(s).
The minimum resistor value should be
TJ = PDISS × θJA + TA
where:
(3)
TJ is the AD859x junction temperature.
PDISS is the AD859x power dissipation.
θJA is the AD859x junction-to-ambient thermal resistance of the
package.
VIN,MAX
5 mA
RIN
≥
(1)
TA is the ambient temperature of the circuit.
Rev. B | Page 11 of 16
AD8591/AD8592/AD8594
In any application, the absolute maximum junction temperature
must be limited to 150°C. If the junction temperature is exceeded,
the device could suffer premature failure. If the output voltage
and output current are in phase, for example, with a purely resistive
load, the power dissipated by the AD859x can be found as
50mV
47nF LOAD
ONLY
PDISS = ILOAD × (VSY − VOUT
)
(4)
where:
ILOAD is the AD859x output load current.
VSY is the AD859x supply voltage.
VOUT is the output voltage.
SNUBBER
IN CIRCUIT
50mV
10µs
By calculating the power dissipation of the device and using the
thermal resistance value for a given package type, the maximum
allowable ambient temperature for an application can be found
using Equation 3.
Figure 37. Snubber Network Reduces Overshoot and Ringing
Caused by Driving Heavy Capacitive Loads
The optimum values for the snubber network should be
determined empirically based on the size of the capacitive load.
Table 5 shows a few sample snubber network values for a given
load capacitance.
CAPACITIVE LOADING
The AD859x exhibits excellent capacitive load driving capabilities
and can drive to 10 nF directly. Although the device is stable
with large capacitive loads, there is a decrease in amplifier
bandwidth as the capacitive load increases. Figure 35 shows
a graph of the AD8592 unity-gain bandwidth under various
capacitive loads.
Table 5. Snubber Networks for Large Capacitive Loads
Snubber Network
Load Capacitance, CL (nF)
RS (Ω)
300
30
CS (μF)
0.47
4.7
47
0.1
1
1
4.0
V
= ±2.5V
= 1kΩ
= 25°C
S
L
R
5
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
T
A
PC98-COMPLIANT HEADPHONE/SPEAKER
AMPLIFIER
Because of its high output current performance and shutdown
feature, the AD8592 makes an excellent amplifier for driving an
audio output jack in a computer application. Figure 38 shows
how the AD8592 can be interfaced with an AC’97 codec to
drive headphones or speakers.
+5V
+5V
0.01
0.1
1
10
100
25
38
AV
AV
DD1
DD2
C1
100µF
CAPACITIVE LOAD (nF)
R4
10
4
2
3
20Ω
U1-A
Figure 35. Unity-Gain Bandwidth vs. Capacitive Load
1
R2
2kΩ
NC
35
LINE_OUT_L
When driving heavy capacitive loads directly from the AD859x
output, a snubber network can be used to improve the transient
response. This network consists of a series RC connected from
the output of the amplifier to ground, placing it in parallel with
the capacitive load. The configuration is shown in Figure 36.
Although this network does not increase the bandwidth of the
amplifier, it significantly reduces the amount of overshoot, as
shown in Figure 37.
+5V
R1
5
AD1881A*
(AC’97)
100kΩ
6
C2
100µF
36
26
LINE_OUT_R
R5
20Ω
7
8
U1-B
AV
SS1
9
R3
2kΩ
+5V
U1 = AD8592
*ADDITIONAL PINS OMITTED FOR CLARITY.
V
AD8592
OUT
V
Figure 38. PC98-Compliant Headphone/Line Out Amplifier
R
5Ω
IN
S
100mV p-p
C
C
L
S
1µF
47nF
Figure 36. Configuration for Snubber Network to Compensate for Capacitive Loads
Rev. B | Page 12 of 16
AD8591/AD8592/AD8594
When headphones are plugged into the jack, the normalizing
contacts disconnect from the audio contacts. This allows the
voltage to the AD8592 shutdown pins to be pulled to 5 V,
activating the amplifiers. With no plug in the output jack, the
shutdown voltage is pulled to 100 mV through the R1 and R3 + R5
voltage divider. This powers the AD8592 down when it is not
needed, saving current from the power supply or battery.
A COMBINED MICROPHONE AND SPEAKER
AMPLIFIER FOR CELLPHONE AND PORTABLE
HEADSETS
The dual amplifiers in the AD8592 make an efficient design for
interfacing with a headset containing a microphone and speaker.
Figure 40 demonstrates a simple method for constructing an
interface to a codec.
If gain is required from the output amplifier, add four additional
resistors, as shown in Figure 39. The gain of the AD8592 can
be set as
R3
100kΩ
+5V
R1
2.2kΩ
C1
0.1µF
+5V
10
R2
10kΩ
R7
R6
2
3
NC
TO
AV
=
(5)
U1-A
CODEC
1
4
+5V
5
R7
1kΩ
+5V
R7
R8
MICROPHONE
AND SPEAKER
JACK
V
25
38
AV
AV
REF
10kΩ
100kΩ
DD1
DD2
FROM CODEC
+5V
6
C2
10µF
7
8
C1
100µF
R4
R4
35
10
LINE_OUT_L
U1-B
FROM CODEC
MONO OUT
(OR LEFT OUT)
2
3
20Ω
9
10kΩ
R6
10kΩ
U1-A
1
R2
2kΩ
NC
4
+5V
R1
U1 = AD8592
(RIGHT OUT)
R5
10kΩ
R6
10kΩ
5
100kΩ
(OPTIONAL)
27
VREF
Figure 40. Speaker/Microphone Headset Amplifier Circuit
6
C2
AD1881A*
(AC’97)
R5
20Ω
100µF
U1-A is used as a microphone preamplifier, where the gain of
the preamplifier is set as R3/R2. R1 is used to bias an electret
microphone, and C1 blocks any dc voltages from the amplifier.
U1-B is the speaker amplifier, and its gain is set at R5/R4. To
sum a stereo output, add R6, equal in value to R4.
7
8
R6
10kΩ
U1-B
9
R3
2kΩ
36
26
LINE_OUT_R
AV
SS1
R7
10kΩ
U1 = AD8592
R7
Using the same principle described in the PC98-Compliant
Headphone/Speaker Amplifier section, the normalizing contact
on the microphone/speaker jack can be used to put the AD8592
into shutdown when the headset is not plugged in. The AD8592
shutdown inputs can also be controlled with TTL- or CMOS-
compatible logic, allowing microphone or speaker muting, if
desired.
A
=
= 6dB WITH VALUES SHOWN
V
R6
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 39. PC98-Compliant Headphone/Line Out Amplifier with Gain
Input coupling capacitors are not required for either circuit
because the reference voltage is supplied from the AD1881A.
R4 and R5 help protect the AD8592 output in case the output
AN INEXPENSIVE SAMPLE-AND-HOLD CIRCUIT
jack or headphone wires accidentally are shorted to ground. The
output coupling capacitors, C1 and C2, block dc current from the
headphones and create a high-pass filter with a corner frequency of
The independent shutdown control of each amplifier in the
AD8592 allows a degree of flexibility in circuit design. One
particular application for which this feature is useful is in
designing a sample-and-hold circuit for data acquisition. Figure 41
shows a schematic of a simple, yet extremely effective, sample-
and-hold circuit using a single AD8592 and one capacitor.
1
f − 3dB =
(6)
(
)
2π C1 R4 + RL
where RL is the resistance of the headphones.
8
+5V
SAMPLE
AND HOLD
OUTPUT
9
2
3
10
U1-A
U1-B
+5V
6
1
7
4
C1
1nF
V
IN
5
U1 = AD8592
SAMPLE
CLOCK
Figure 41. An Efficient Sample-and-Hold Circuit
Rev. B | Page 13 of 16
AD8591/AD8592/AD8594
The U1-A amplifier is configured as a unity-gain buffer driving
a 1 nF capacitor. The input signal is connected to the noninverting
input, and the sample clock controls the shutdown for that
amplifier. When the sample clock is high, the U1-A amplifier is
active and the output follows VIN. When the sample clock goes
low, U1-A shuts down with the output of the amplifier going to
a high impedance state, holding the voltage on the C1 capacitor.
SINGLE-SUPPLY DIFFERENTIAL LINE DRIVER
Figure 43 shows a single-supply differential line driver circuit
that can drive a 600 Ω load with less than 0.7% distortion from
20 Hz to 15 kHz with an input signal of 4 V p-p and a single 5 V
supply. The design uses an AD8594 to mimic the performance
of a fully balanced transformer-based solution. However, this
design occupies much less board space, while maintaining low
distortion, and can operate down to dc. Like the transformer-based
design, either output can be shorted to ground for unbalanced
line driver applications without changing the circuit gain of 1.
The U1-B amplifier is used as a unity-gain buffer to prevent
loading on C1. Because of the low input bias current of the U1-B
CMOS input stage and the high impedance state of the U1-A
output in shutdown, there is little voltage droop from C1 during
the hold period. This circuit can be used with sample frequencies as
high as 500 kHz and as low as 1 Hz. By increasing the C1 value,
lower voltage droop is achieved for very low sample rates.
R3
10kΩ
C3
47µF
2
3
R5
50Ω
1
A2
V
O1
R6
10kΩ
R2
DIRECT ACCESS ARRANGEMENT FOR PCMCIA
MODEMS (TELEPHONE LINE INTERFACE)
10kΩ
R7
10kΩ
+5V
+5V
10
+5V
2
3
8
10
Figure 42 illustrates a 5 V transmit/receive telephone line
interface for 600 Ω systems. It allows full duplex transmission
of signals on a transformer-coupled 600 Ω line in a differential
manner. Amplifier A1 provides gain that can be adjusted to
meet the modem output drive requirements. Both A1 and A2
are configured to apply the largest possible signal on a single
supply to the transformer. Because of the high output current
drive and low dropout voltages of the AD8594, the largest signal
available on a single 5 V supply is approximately 4.5 V p-p into
a 600 Ω transmission system. Amplifier A3 is configured as a
difference amplifier for two reasons. It prevents the transmit
signal from interfering with the receive signal, and it extracts
the receive signal from the transmission line for amplification
by A4. The gain of A4 can be adjusted in the same manner as
the gain of A1 to meet the input signal requirements of the
modem. Standard resistor values permit the use of single
inline package (SIP) format resistor arrays. Couple this with
the 16-lead TSSOP or SOIC footprint of the AD8594, and this
circuit offers a compact, cost-effective solution.
C1
R8
1
22µF
R
600Ω
100kΩ
A1
L
A1
7
9
V
4
4
IN
C2
1µF
R9
100kΩ
R1
10kΩ
R11
10kΩ
R12
10kΩ
C4
47µF
R10
10kΩ
8
R14
50Ω
9
A2
V
O2
7
A1, A2 = 1/2 AD8592
R13
10kΩ
R3
R2
GAIN =
SET: R7, R10, R11 = R2
SET: R6, R12, R13 = R3
Figure 43. Low Noise, Single-Supply Differential Line Driver
R8 and R9 set up the common-mode output voltage equal to
half of the supply voltage. C1 is used to couple the input signal
and can be omitted if the dc voltage of the input is equal to half
of the supply voltage.
The circuit can also be configured to provide additional gain, if
desired. The gain of the circuit is
VOUT
VIN
R3
R2
AV
=
=
(7)
P1
Tx GAIN
where:
OUT = VO1 − VO2
ADJUST
R2
9.09kΩ
V
C1
0.1µF
TRANSMIT
TxA
R1
10kΩ
TO TELEPHONE
LINE
2kΩ
R2 = R7 = R10 = R11
R3 = R6 = R12 = R1
R3
360Ω
2
3
1
1:1
A1
9
R5
10kΩ
6.2V
6.2V
Z
SHUTDOWN
+5V
O
600Ω
T1
R6
10kΩ
9
6
5
MIDCOM
671-8005
R7
10kΩ
7
A2
R8
10kΩ
10µF
R9
R10
P2
Rx GAIN
ADJUST
10kΩ
10kΩ
9
RECEIVE
RxA
R13
R14
11
12
10kΩ 14.3kΩ
R11
10kΩ
10
A3
2kΩ
15
14
9
C2
0.1µF
R12
10kΩ
16
A4
A1, A2 = 1/4 AD8594
A3, A4 = 1/4 AD8594
Figure 42. Single-Supply Direct Access Arrangement for PCMCIA Modems
Rev. B | Page 14 of 16
AD8591/AD8592/AD8594
OUTLINE DIMENSIONS
2.90 BSC
6
1
5
2
4
3
2.80 BSC
1.60 BSC
PIN 1
INDICATOR
0.95 BSC
1.90
BSC
1.30
1.15
0.90
1.45 MAX
0.22
0.08
10°
4°
0°
0.60
0.45
0.30
0.50
0.30
0.15 MAX
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-178-AB
Figure 44. 6-Lead Small Outline Transistor Package [SOT-23]
(RJ-6)
Dimensions shown in millimeters
3.10
3.00
2.90
6
10
5.15
4.90
4.65
3.10
3.00
2.90
1
5
PIN 1
0.50 BSC
0.95
0.85
0.75
1.10 MAX
0.80
0.60
0.40
8°
0°
0.15
0.05
0.33
0.17
SEATING
PLANE
0.23
0.08
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 45. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
10.00 (0.3937)
9.80 (0.3858)
9
8
16
1
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
1.27 (0.0500)
0.50 (0.0197)
0.25 (0.0098)
45°
BSC
1.75 (0.0689)
1.35 (0.0531)
0.25 (0.0098)
0.10 (0.0039)
8°
0°
COPLANARITY
0.10
SEATING
PLANE
1.27 (0.0500)
0.40 (0.0157)
0.51 (0.0201)
0.31 (0.0122)
0.25 (0.0098)
0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012-AC
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 46. 16-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-16)
Dimensions shown in millimeters and (inches)
Rev. B | Page 15 of 16
AD8591/AD8592/AD8594
5.10
5.00
4.90
16
9
8
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 47. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
6-Lead SOT-23
6-Lead SOT-23
6-Lead SOT-23
6-Lead SOT-23
10-Lead MSOP
10-Lead MSOP
16-Lead SOIC_N
16-Lead SOIC_N
16-Lead SOIC_N
16-Lead SOIC_N
16-Lead SOIC_N
16-Lead SOIC_N
16-Lead TSSOP
16-Lead TSSOP
Package Option
RJ-6
RJ-6
RJ-6
RJ-6
Branding
A9A
A9A
A9A#
A9A#
AQA
AD8591ART-REEL
AD8591ART-REEL7
AD8591ARTZ-REEL1
AD8591ARTZ-REEL71
AD8592ARM-REEL
AD8592ARMZ-REEL1
AD8594AR
AD8594AR-REEL
AD8594AR-REEL7
AD8594ARZ1
AD8594ARZ-REEL1
AD8594ARZ-REEL71
AD8594ARU-REEL
AD8594ARUZ-REEL1
RM-10
RM-10
R-16
R-16
R-16
R-16
R-16
R-16
RU-16
RU-16
AQA#
1 Z = RoHS Compliant Part, # denotes RoHS compliant part may be top or bottom marked.
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D01106-0-1/09(B)
Rev. B | Page 16 of 16
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