AD8600CHIPS_技术文档

16-Channel, 8-Bit

Multiplying DAC

a

AD8600*

FUNCTIO NAL BLO CK D IAGRAM

FEATURES

16 Independently Addressable Voltage Outputs

Full-Scale Set by External Reference

2 µs Settling Tim e

Double Buffered 8-Bit Parallel Input

High Speed Data Load Rate

Data Readback

V

CC

RS

LD

R/W

DD1

DD2

REF

O0

O1

O2

O3

O4

O5

O6

O7

CS

EN

CONTROL

LOGIC

A3

A2

A1

A0

ADDRESS

DECODE

16 x 8

DAC

REGISTERS

16

Operates from Single +5 V

Optional ±6 V Supply Extends Output Range

8-BIT

DACS

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

O8

O9

16 x 8

INPUT

O10

O11

O12

O13

O14

O15

APPLICATIONS

Phased Array Ultrasound & Sonar

Pow er Level Setting

Receiver Gain Setting

Autom atic Test Equipm ent

LCD Clock Level Setting

REGISTERS

AD8600

D

V

EE

D

DACGND

GND2

GND1

At system power up or during fault recovery the reset (RS) pin

forces all DAC registers into the zero state which places zero

volts at all DAC outputs.

GENERAL D ESCRIP TIO N

T he AD8600 contains 16 independent voltage output digital-to-

analog converters that share a common external reference input

voltage. Each DAC has its own DAC register and input register

to allow double buffering. An 8-bit parallel data input, four ad-

dress pins, a CS select, a LD, EN, R/W, and RS provide the

digital interface.

T he AD8600 is offered in the PLCC-44 package. T he device is

designed and tested for operation over the extended industrial

temperature range of –40°C to +85°C.

V

LD•EN

R/W•CS•ADDR•EN

V

REF

V

DD2

DD1

T he AD8600 is constructed in a monolithic CBCMOS process

which optimizes use of CMOS for logic and bipolar for speed

and precision. T he digital-to-analog converter design uses volt-

age mode operation ideally suited to single supply operation.

V

CC

INPUT

REGISTER

R-2R

DAC

REGISTER

DB7...DB0

O

X

T he internal DAC voltage range is fixed at DACGND to V_REF

T he voltage buffers provide an output voltage range that ap-

proaches ground and extends to 1.0 V below V_CC. Changes in

reference voltage values and digital inputs will settle within

±1 LSB in 2 µs.

.

RS

D

GND2

DACGND

V

EE

D

GND1

R/W•CS•ADDRESS

Data is preloaded into the input registers one at a time after the

internal address decoder selects the input register. In the write

mode (R/W low) data is latched into the input register during

the positive edge of the EN pulse. Pulses as short as 40 ns can

be used to load the data. After changes have been submitted to

the input registers, the DAC registers are simultaneously up-

dated by a common load EN × LD strobe. T he new analog out-

put voltages simultaneously appear on all 16 outputs.

Figure 1. Equivalent DAC Channel

*P atent pending.

REV. 0

Inform ation furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assum ed by Analog Devices for its

use, nor for any infringem ents of patents or other rights of third parties

which m ay result from its use. No license is granted by im plication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norw ood. MA 02062-9106, U.S.A.

Tel: 617/ 329-4700 Fax: 617/ 326-8703

AD8600–SPECIFICATIONS

(@ V = V = V = +5 V ± 5%, V = 0 V, V = +2.500 V, –40°C ≤ T ≤ +85°C, unless otherwise noted)

SINGLE SUPPLY

DD1

DD2

CC

EE

REF

A

P aram eter

Sym bol Condition

Min

Typ

Max

Units

ST AT IC PERFORMANCE¹

Resolution

N

INL

8

–1

2.480

Bits

LSB

V

ppm/°C

LSB

kΩ

Relative Accuracy²

Differential Nonlinearity²

Full-Scale Voltage

Full-Scale T empco

Zero Scale Error

±1/2 +1

±1/4 +1

2.490 2.500

±20

+3.5

+5

DNL

V_FS

T CV_FS

V_ZSE

R_REF

Guaranteed Monotonic

Data = FF_H

Data = 00_H, RS = “0,” T _A= +25°C

Data = 00_H, RS = “0”

Data = AB_H

Reference Input Resistance

1.2

2

ANALOG OUT PUT

Output Voltage Range²

Output Current

OVR_SS

I_OUT

C_L

V_REF= +2.5 V

Data = 80_H

No Oscillation

0.000

2.500

V

mA

pF

±2

50

Capacitive Load

LOGIC INPUT S

Logic Input Low Voltage

Logic Input High Voltage

Logic Input Current

V_IL

V_IH

I_IL

0.8

V

µA

pF

2.4

10

Logic Input Capacitance³

C_IL

LOGIC OUT PUT S

Logic Out High Voltage

Logic Out Low Voltage

V_OH

V_OL

I_OH= –0.4 mA

I_OL= 1.6 mA

3.5

4

V

0.4

AC CHARACT ERIST ICS³

Slew Rate

SR

For ∆V_REFor FS Code Change

±1 LSB of Final Value, Full-Scale Data Change

±1 LSB of Final Value, ∆V_REF= 1 V, Data = FF_H

7

2

V/µs

µs

Voltage Output Settling T ime²t_S1

Voltage Output Settling T ime²t_S2

POWER SUPPLIES

Positive Supply Current

Logic Supply Currents

Power Dissipation

I_CC

V_IH= 5 V, V_IL= 0 V, No Load

∆V_CC= ±5%

24

35

0.1

175

0.007 %/%

5.25

7.0

mA

mW

I_DD1&2

P_DISS

PSS

120

Power Supply Sensitivity

Logic Power Supply Range

V_DDR

4.75

V_DD

V

Positive Power Supply Range³V_CCR

NOT ES

¹When V_REF= 2.500 V, 1 LSB = 9.76 mV.

²Single supply operation does not include the final 2 LSBs near analog ground. If this performance is critical, use a negative supply (V_EE

)

pin of at least –0.7 V to

–5.25 V. Note that for the INL measurement zero-scale voltage is extrapolated using codes 7 ₁₀to 80₁₀

.

³Guaranteed by design not subject to production test.

Specifications subject to change without notice.

–2–

REV. 0

AD8600

(@ V = V = V = +5 V ± 5%, V = –5 V ± 5%, V = +3.500 V, –40°C ≤ T ≤ +85°C, unless otherwise noted)

DUAL SUPPLY

DD1

DD2

CC

EE

REF

A

P aram eter

Sym bol Condition

Min

Typ

Max

Units

ST AT IC PERFORMANCE¹

Resolution

T otal Unadjusted Error

Relative Accuracy

Differential Nonlinearity

Full-Scale Voltage

Full-Scale Voltage Error

Full-Scale T empco

Zero Scale Error

Zero Scale T empco

Reference Input Resistance

Reference Input Capacitance²

N

T UE

INL

DNL

V_FS

V_FSE

T CV_FS

V_ZSE

T CV_ZS

R_REF

C_REF

8

–1

3.473

–1

Bits

LSB

V

LSB

ppm/°C

mV

LSB

µV/°C

kΩ

All Other DACs Loaded with Data = 55_H

±3/4

±1/2

±1/4

3.486

+1

3.500

+1

Guaranteed Monotonic

Data = FF_H, V_REF= +3.5 V

Data = 00_H, RS = “0,” T _A= +25°C

Data = 00_H, All Other DACs Data = 00_H

Data = 00_H, All Other DACs Data = 55_H

Data = 00_H, V_CC= +5 V, V_EE= –5 V

Data = AB_H

±20

±1

–2

–1

+2

+1

±1/2

±10

2

1.2

Data = AB_H

240

pF

ANALOG OUT PUT

Output Voltage Range

Output Voltage Range²

Output Current

OVR₁

OVR₂

I_OUT

C_L

V_REF= +3.5 V

V_CC= V_DD2= +7 V, V_EE= –0.7 V, V_REF= 5 V

Data = 80_H

No Oscillation

0.000

3.500

5.000

V

mA

pF

±2

50

Capacitive Load²

LOGIC INPUT S

Logic Input Low Voltage

Logic Input High Voltage

Logic Input Current

V_IL

V_IH

I_IL

0.8

V

µA

pF

2.4

3.5

10

Logic Input Capacitance²

C_IL

LOGIC OUT PUT S

Logic Out High Voltage

Logic Out Low Voltage

V_OH

V_OL

I_OH= –0.4 mA

I_OL= 1.6 mA

V

0.4

AC CHARACT ERIST ICS²

Reference In Bandwidth

Slew Rate

BW

SR

e_N

–3 dB Frequency, V_REF= 2.5 V_DC+ 0.1 V_AC

For ∆V_REFor FS Code Change

f = 1 kHz, V_REF= 0 V

Digital Inputs to DAC Outputs

±1 LSB of Final Value, FS Data Change

±1 LSB of Final Value, ∆V_REF= 1 V, Data = FF_H

500

4

kHz

V/µs

nV/√Hz

nVs

µs

7

Voltage Noise Density

Digital Feedthrough

46

10

1

FT

Voltage Output Settling T ime³t_S1

Voltage Output Settling T ime³t_S2

2

1

µs

POWER SUPPLIES

Positive Supply Current

Negative Supply Current

Logic Supply Currents

Power Dissipation⁴

Power Supply Sensitivity

Logic Power Supply Range

Pos Power Supply Range²

Neg Power Supply Range²

I_CC

I_EE

V_IH= 5 V, V_IL= 0 V, V_EE= –5 V, No Load

∆V_CC& ∆V_EE= ±5%

22

35

0.1

350

0.007

5.25

7.0

mA

mW

%/%

V

I_DD1&2

P_DISS

PSS

V_DDR

V_CCR

V_EER

225

4.75

V_DD

–5.25

V

0.0

NOT ES

¹When V_REF= +3.500 V, 1 LSB = 13.67 mV.

²Guaranteed by design not subject to production test.

³Settling time test is performed using R_L= 50 kΩ and C_L= 35 pF.

⁴Power Dissipation is calculated using 5 V × (I_DD+ | I_SS| + I_DD1+ I_DD2).

Specifications subject to change without notice.

REV. 0

–3–

AD8600

(@ V_DD1= V = V = +5 V ± 5%, V = –5 V, V = +3.500 V, –40°C ≤ T ≤ +85°C,

DD2

CC

EE

REF

A

unless otherwise noted)

ELECTRICAL CHARACTERISTICS

P aram eter

Sym bol

Condition

Min

Typ

Max

Units

INT ERFACE T IMING^{1, 2}

Clock (EN) Frequency

Clock (EN) High Pulse Width

Clock (EN) LowPulse Width

Data Setup T ime

Data Hold T ime

Address Setup T ime

Address Hold T ime

Valid Address to Data Valid

Load Enable Setup T ime

Load Enable Hold T ime

Read/Write to Clock (EN)

Read/Write to DataBus Hi-Z

Read/Write to DataBus Active

Clock (EN) to Read/Write

Clock (EN) to Chip Select

Chip Select to Clock (EN)

Chip Select to Data Valid

Chip Select to DataBus Hi-Z

Reset Pulse Width

f_CLK

t_CH

t_CL

t_DS

t_DH

t_AS

t_AH

t_AD

t_LS

Data Loading

12.5

MHz

ns

40

10

0

160

0

30

t_LH

t_RWC

t_RWZ

t_RWD

t_{T WH}

t_{T CH}

t_CSC

t_CSD

t_CSZ

t_RS

120

0

30

120

150

25

NOT ES

¹Guaranteed by design not subject to production test.

²All logic input signals have maximum rise and fall times of 2 ns.

Specifications subject to change without notice.

R/W

t_TWH

t_RWD

t_RWZ

t_DS

t_DH

HIGH -Z

HIGH-Z

DATA

ADDR

t_AS

t_AD

t_AH

ADDR

t_CH

EN

t_CSD

t_CSZ

EN

CS

t_TCH

t_CL

t_RWC

t_CSC

CS

Figure 2. Write Tim ing

Figure 3. Readback Tim ing

LD

EN

t_LS

t_LH

t_RS

RS

OUT

t_S1

Figure 4. Write to DAC Register & Voltage Output Settling

Tim ing (CS= High, Prevents Input Register Changes)

–4–

REV. 0

AD8600

ABSO LUTE MAXIMUM RATINGS

P IN D ESCRIP TIO N

(T _A= +25°C unless otherwise noted)

P in No.

Nam e

D escription

V_DD1(Digital Supply) to GND . . . . . . . . . . . . . . –0.3 V, +7 V

V_DD2(DAC Buffer/Driver Supply) . . . . . . . . . . . . –0.3 V, +7 V

V_CC(Analog Supply) to GND . . . . . . . . . . . . . . . –0.3 V, +7 V

V_EE(Analog Supply) to GND . . . . . . . . . . . . . . . +0.3 V, –7 V

1

2

NC

V_REF

No Connection

Reference input voltage common

to all DACs.

V_REFto GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V_CC+ 0.3 V

3

DACGND

DAC Analog Ground Return. Sets

analog zero-scale voltage.

Output Amplifier Positive Supply

Output Amplifier Negative Supply

DAC Channel Output No. 7

DAC Channel Output No. 6

DAC Channel Output No. 5

DAC Channel Output No. 4

DAC Channel Output No. 3

DAC Channel Output No. 2

DAC Channel Output No. 1

DAC Channel Output No. 0

Digital Logic Power Supply

Active Low Reset Input Pin

Data Bit Zero I/O (LSB)

Data Bit I/O

V_DD2to V_REF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V

V_OUTto GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V_CC

Short Circuit Duration

4

5

6

7

8

9

V_CC

V_EE

O7

O6

O5

O4

O3

O2

O1

V_OUTto GND or Power Supplies^{1 . . . . . . . . . . . . . . .}Continuous

Digital Input/Output Voltage to GND . . . –0.3 V, V_DD+ 0.3 V

T hermal Resistance–T heta Junction-to-Ambient (θ_JA)

PLCC-44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47°C/W

Package Power Dissipation . . . . . . . . . . . . . . . . (T_J– T _A)/θ_JA

Maximum Junction T emperature T_Jmax . . . . . . . . . . . 150°C

Operating T emperature Range . . . . . . . . . . . . –40°C to +85°C

Storage T emperature Range . . . . . . . . . . . . –65°C to +150°C

Lead T emperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

O0

V_DD1

RS

NOT E

¹No more than four outputs may be shorted to power or GND simultaneously.

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

A0

A1

A2

A3

R/W

EN

P IN CO NFIGURATIO N

Data Bit I/O

6

5

4

3

2

1

44 43 42 41 40

O6

O5

O4

O3

7

8

39 O9

38

Data Bit I/O

O10

Most Significant Data Bit I/O (MSB)

Address Bit Zero (LSB)

Address Bit

9

37 O11

36 O12

10

O2 11

O1 12

35

34

33

32

31

30

29

O13

O14

O15

DGND1

LD

AD8600

TOP VIEW

(Not to Scale)

Address Bit

Most Significant Addr Bit (MSB)

Read/Write Select Control Input

Active Low Enable Clock Strobe

Chip Select Input

13

14

O0

V_DD1

RS 15

DB0 16

DB1 17

CS

LD

CS

DAC Register Load Strobe

Digital Ground Input No. 1

DAC Channel Output No. 15

DAC Channel Output No. 14

DAC Channel Output No. 13

DAC Channel Output No. 12

DAC Channel Output No. 11

DAC Channel Output No. 10

DAC Channel Output No. 9

DAC Channel Output No. 8

Output Amplifier Negative Supply

Output Amplifier Positive Supply

Digital Ground Input No. 2

DAC Analog Supply Voltage

EN

DGND1

O15

O14

O13

O12

O11

O10

O9

O8

V_EE

V_CC

DGND2

V_DD2

18 19

21 22

24 25 26

28

27

20

23

NC = NO CONNECT

O RD ERING GUID E

P ackage

D escription

P ackage

O ption

Model

AD8600AP

Tem perature

–40°C to +85°C 44-Lead PLCC P-44A

AD8600Chips +25°C Die*

*For die specifications contact your local Analog Devices sales office.

T he AD8600 contains 5782 transistors.

CAUTIO N

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the AD8600 features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. 0

–5–

AD8600

TRANSFER EQ UATIO NS

O utput Voltage

D ecoded D AC Register

O_i= A

V

256

REF

O_i= D ×

where A is the decimal value of the decoded address bits A3,

A2, A1, A0 (LSB).

where i is the DAC channel number and D is the decimal value

of the DAC register data.

Address, CS, R/W and data inputs should be stable prior to acti-

vation of the active low EN input. Input registers are transpar-

ent when EN is low. When EN returns high, data is latched into

the decoded input register. When the load strobe LD and EN

pins are active low, all input register data is transferred to the

DAC registers. T he DAC registers are transparent while they

are enabled.

Table I. Truth Table

EN R/W CS LD RS

O peration

Write to DAC Register

Update DAC Register

Latches DAC Register

DAC Register T ransparent

–

X

L

H

L

–

L

+

L

H

L

+

L

Table II. Address D ecode Table

A3

(MSB)

A2

A1

A0

(LSB)

Addr

Code

(H ex)

D AC

Updated

Write to Input Register

Load Data to Input Register at

Decoded Address

Latches Data in Input Register at

Decoded Address

Latches Data in Input Register at

Decoded Address

(Binary)

L

+

L

+

H

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

7

O0

O1

O2

O3

O4

O5

O6

O7

Readback Input Registers

Input Register Readback (Data

Access)

Hi-Z Readback Disconnects from

Bus

Hi-Z on Data Bus

X

H

X

L

+

H

X

H

X

8

9

O8

O9

H

A

B

C

D

E

F

O10

O11

O12

O13

O14

O15

Reset

X

L

Clear All Registers to Zero,

V_OUT= 0 V

Latches All Registers to Zero

CS = Low; Input Register Ready

for R/W, DAC Register Latched

to Zero

X

L

X

H

L

H

+

NOT ES

¹+ symbol means positive edge of control input line.

²– symbol means negative edge of control input line.

–6–

REV. 0

Typical Performances Characteristics–AD8600

8

V

= +5V

= –5V

= 3.5V

CC

EE

DACs 00–07 SUPERIMPOSED

+1/2

0

3.50

3.49

3.48

3.47

V_CC= +5V

V_EE= –5V

V_REF= 3.5V

REF

4

0

V_CC= +5V

V_EE= –5V

V_REF= +3.5V

T_A= +25°C

–1/2

+1/2

0

–2

–4

DACs 08–015 SUPERIMPOSED

–1/2

0

64

128

192

256

–50 –25

0

25

50

75

100 125

–50 –25

0

25

50

75

100 125

DIGITAL INPUT CODE – Decimal

TEMPERATURE – °C

Figure 5. Linearity Error vs.

Digital Code

Figure 7. Zero-Scale Voltage vs.

Tem perature

Figure 6. Full-Scale Voltage vs.

Tem perature

100

4

3

V_CC= +5V

V_EE= –5V

V_REF= 0V

15

V_CC= +5V

V_EE= –5V

80

10

5

RS = 0

T

_A= +25°C

60

40

20

0

2

V_CC= +5V

V_EE= –5V

V_REF= 3.5V

–5

–10

–15

1

0

10

100

1k

10k

–4

–3 –2 –1

0

1

2

3

4

FREQUENCY – Hz

TIME – 250ns/DIV

V_OUT– Volts

Figure 8. Output Current vs.

Voltage

Figure 9. Full-Scale Settling Tim e

Figure 10. Voltage Noise Density vs.

Frequency

60

0

∆V

= 100mV p-p

CC

V_IN= 100mV p-p + 2.5V_DC

CODE = FF_H

T_A= +25°C

V

= 2V p-p + 1V

T = +25°C

IN

DC

A

–20

–40

RS = 0

= +25°C

CODE = 00

H

50

40

30

20

T

V

= –5V

A

EE

GAIN

0

–5

0

–45

–90

–60

–10

–15

PHASE

–80

–100

100

1k

10k

100k

1k

FREQUENCY – Hz

10

100

10k

100k

1k

10k

100k

1M

10M

FREQUENCY – Hz

Figure 11. Gain & Phase vs.

Frequency

Figure 12. AC Feedthrough vs.

Frequency

Figure 13. PSRR vs. Frequency

REV. 0

–7–

AD8600

5

4

20

19

18

17

16

15

V

= +5V

= –5V

= 3.5V

CC

EE

V

= +5V

= –5V

= 3.5V

CC

EE

3

REF

CODE = 00

H

2

χ + 3σ

χ − 3σ

REF

1

χ

0

–1

–2

–3

–4

–5

χ + 3σ

χ − 3σ

χ

0

200

400

600

800

1000 1200

–75 –50 –25

0

25

50

75 100 125

T = HOURS OF OPERATION AT +125°C

TEMPERATURE – °C

Figure 14. Supply Current vs. Tem perature

Figure 15. Output Voltage Drift

Accelerated by Burn-In

O per ation

Am plifier Section

T he AD8600 is a 16-channel voltage output, 8-bit digital to

analog converter. T he AD8600 operates from a single +5 V

supply, or for a wider output swing range, the part can operate

from dual supplies of ±5 V or ±6 V or a single supply of +7 V.

T he DACs are based upon a unique R-2R ladder structure*

that removes the possibility of current injection from the refer-

ence to ground during code switching. Each of the 8-bit DACs

has an output amplifier to provide 16 low impedance outputs.

With a single external reference, 16 independent dc output lev-

els can be programmed through a parallel digital interface. T he

interface includes 4 bits of address (A0–A3), 8 bits of data

(DB0–DB7), a read/write select pin (R/W), an enable clock

strobe (EN), a DAC register load strobe (LD), and a chip select

pin (CS). Additionally a reset pin (RS) is provided to asynchro-

nously reset all 16 DACs to 0 V output.

T he output of the DAC ladder is buffered by a rail-to-rail out-

put amplifier. T his amplifier is configured as a unity gain fol-

lower as shown in Figure 16. T he input stage of the amplifier

contains a PNP differential pair to provide low offset drift and

noise. T he output stage is shown in Figure 17. It employs

complementary bipolar transistors with their collectors con-

nected to the output to provide rail-to-rail operation. T he NPN

transistor enters into saturation as the output approaches the

negative rail. T hus, in single supply, the output low voltage is

limited by the saturation voltage of the transistor. For the tran-

sistors used in the AD8600, this is approximately 40 mV. T he

AD8600 was not designed to swing to the positive rail in con-

trast to some of ADI’s other DACs (for example, the AD8582).

T he output stage of the amplifier is actually capable of swinging

to the positive rail, but the input stage limits this swing to ap-

proximately 1.0 V below V_CC

.

D /A Conver ter Section

T he internal DAC is an 8-bit voltage mode device with an out-

put that swings from DACGND to the external reference volt-

age, V_REF. T he equivalent schematic of one of the DACs is

shown in Figure 16. T he DAC uses an R-2R ladder to ensure

accuracy and linearity over the full temperature range of the part.

The switches shown are actually N and P-channel MOSFET s to

allow maximum flexibility and range in the choice of reference

V

CC

V

OUT

V

REF

R

V

OUT

R

V

EE

R

TO 15

DACs

Figure 17. Equivalent Analog Output Circuit

During normal operation, the output stage can typically source

and sink ±1 mA of current. However, the actual short circuit

current is much higher. In fact, each DAC is capable of sourc-

ing 20 mA and sinking 8 mA during a short condition. T he

absolute maximum ratings state that, at most, four DACs can

be shorted simultaneously. T his restriction is due to current

densities in the metal traces. If the current density is too high,

voltage drops in the traces will cause a loss in linearity perfor-

mance for the other DACs in the package. T hus to ensure long-

term reliability, no more than four DACs should be shorted

simultaneously.

*R = 30kΩ

TYPICALLY

R

2R

DACGND

Figure 16. Equivalent Schem atic of Analog Channel

voltage. T he switches’ low ON resistance and matching is im-

portant in maintaining the accuracy of the R-2R ladder.

*Patent Pending.

–8–

REV. 0

AD8600

V

P ower Supply and Gr ounding Consider ations

CC

DD2

T he low power consumption of the AD8600 is a direct result of

circuit design optimizing using a CBCMOS process. T he over-

all power dissipation of 120 mW translates to a total supply cur-

rent of only 24 mA for 16 DACs. T hus, each DAC consumes

only 1.5 mA. Because the digital interface is comprised entirely

of CMOS logic, the power dissipation is dependent upon the

logic input levels. As expected for CMOS, the lowest power

dissipation is achieved when the input level is either close to

ground or +5 V. T hus, to minimize the power consumption,

CMOS logic should be used to interface to the AD8600.

ALL DIGITAL INPUTS

(A0–A3, DB0–DB7)

(R/W, CS, EN, LD, RS)

DGND1

V

REF

DACGND

T he AD8600 has multiple supply pins. V_CC(Pins 4 and 42) is

the output amplifiers’ positive supply, and V_EE(Pins 5 and 41)

the amplifiers’ negative supply. T he digital input circuitry is

powered by V_DD1(Pin 14), and finally the DAC register and R-

2R ladder switches are powered by V_DD2(Pin 44). T o minimize

noise feedthrough from the supplies, each supply pin should be

decoupled with a 0.1 µF ceramic capacitor close to the pin.

When applying power to the device, it is important for the digi-

tal supply, V_DD2, to power on before the reference voltage and

for V_REFto remain less than 0.3 V above V_DD2during normal

operation. Otherwise, an inherent diode will energize, and it

could damage the AD8600.

Figure 18. ESD Protection Diode Locations

Attention should be paid to the ground pins of the AD8600 to

ensure that noise is not introduced to the output. T he pin la-

beled DACGND (Pin 3) is actually the ground for the R-2R

ladder, and because of this, it is important to connect this pin to

a high quality analog ground. Ideally, the analog ground should

be an actual ground plane. T his helps create a low impedance,

low noise ground to maintain accuracy in the analog circuitry.

T he digital ground pins (DGND1 at Pin 32 and DGND2 at

Pin 43) provide the ground reference for the internal digital cir-

cuitry and latches. T he first thought may be to connect both of

these pins to the system digital ground. However, this is not the

best choice because of the high noise typically found on a

system’s digital ground. T his noise can feed through to the out-

put through the DAC’s ground pins. Instead, DGND1 and

DGND2 should be connected to the analog ground plane. T he

actual switching current in these pins is small and should not

degrade the analog ground.

In order to improve ESD resistance, the AD8600 has several

ESD protection diodes on its various pins. T hese diodes shunt

ESD energy to the power supplies and protect the sensitive ac-

tive circuitry. During normal operation, all the ESD diodes are

reversed biased and do not affect the part. However, if overvolt-

ages occur on the various inputs, these diodes will energize. If

the overvoltage is due to ESD, the electrical spike is typically

short enough so that the part is not damaged. However, if the

overvoltage is continuous and has sufficient current, the part

could be damaged. T o protect the part, it is important not to

forward bias any of the ESD protection diodes during normal

operation or during power up. Figure 18 shows the location of

these diodes. For example, the digital inputs have diodes con-

nected to V_CCand from DGND1. T hus, the voltage on any

digital input should never exceed the analog supply or drop be-

low ground, which is also indicated in the absolute maximum

ratings.

5 V O utput Swing

T he output swing is limited to 1.0 V below the positive supply.

T his gives a maximum output of +4.0 V on a +5 V supply. T o

increase the output range, the analog supply, V_CC, and the DAC

ladder supply, V_DD2, can be increased to +7 V. T his allows an

output of +5 V with a 5 V reference. V_DD1should remain at

+5 V to ensure that the input logic levels do not change.

Refer ence Input Consider ations

The AD8600 is designed for one reference to drive all 16 DACs.

T he reference pin (V_REF) is connected directly to the R-2R lad-

ders of each DAC. With 16 DACs in parallel, the input imped-

ance is typically 2 kΩ and a minimum of 1.2 kΩ. T he input

resistance is code dependent. T hus, the chosen reference device

must be able to drive this load. Some examples of +2.5 V refer-

ences that easily interface to the AD8600 are the REF43,

AD680, and AD780. T he unique architecture ensures that the

reference does not have to supply “shoot through” current,

which is a condition in some voltage mode DACs where the ref-

erence is momentarily connected to ground through the CMOS

switches. By eliminating this possibility, all 16 DACs in the

AD8600 can easily be driven from a single reference.

REV. 0

–9–

AD8600

Inter face Tim ing and Contr ol

T o load multiple input registers in the fastest time possible,

both R/W and CS should remain low, and the EN line be used

to “clock” in the data. As the write timing diagram shows, the

address should be updated at the same time as EN goes low.

Before EN returns high, valid data must be present for a time

equal to the data setup time (t_DS), and after EN returns high,

the data Hold T ime (t_DH) must be maintained. If these mini-

mum times are violated, invalid data may be latched into the in-

put register. T his cycle can be repeated 16 times to load all of

the DACs. T he fastest interface time is equal to the sum of the

low and high times (t_CLand t_CH) for the EN input, which gives a

minimum of 80 ns. Because the EN input is used to clock in

the data, it is often referred to as the clock input, and the timing

specifications give a maximum clock frequency of 12.5 MHz,

which is just the reciprocal of 80 ns.

T he AD8600 employs a double buffered DAC structure with

each DAC channel having a unique input register and DAC reg-

ister as shown in the diagram entitled “Equivalent DAC Chan-

nel” on the first page of the data sheet. T his structure allows

maximum flexibility in loading the DACs. For example, each

DAC can be updated independently, or, if desired, all 16 input

registers can be loaded, followed by a single LD strobe to up-

date all 16 DACs simultaneously. An additional feature is the

ability to read back from the input register to verify the DAC’s

data.

A0

A1

N1

A2

A3

N5

R/W

EN

CS

N2

N3

N4

After all the input registers have been loaded, a single load

strobe will transfer the contents of the input registers to the

DAC registers. EN must also be low during this time. If the

address or data on the inputs could change, then CS should be

high during this time to ensure that new data is not loaded into

an input register. Alternatively, a single DAC can be updated

by first loading its input register and then transferring that to the

DAC register without loading the other 15 input registers.

N6

R/W

CS

LD

EN

8

INPUT

REGISTER

DAC

REGISTER

R-2R

LADDER

D7–D0

8

READ BACK

T he final interface option is to read data from the DAC’s input

registers, which is accomplished by setting R/W high and bring-

ing CS low. Read back allows the microprocessor to verify that

correct data has been loaded into the DACs. During this time

EN and LD should be high. After a delay equal to t_RWD, the

data bus becomes active and the contents of the input register

are read back to the data pins, DB0–DB7. T he address can be

changed to look at the contents of all the input registers. Note

that after an address change, the valid data is not available for a

time equal to t_AD. T he delay time is due to the internal

readback buffers needing to charge up the data bus (measured

with a 35 pF load). T hese buffers are low power and do not

have high current to charge the bus quickly. When CS returns

high, the data pins assume a high impedance state and control

of the data lines or bus passes back to the microprocessor.

Figure 19. Logic Interface Circuit for DAC Channel 0

T he interface logic for a single DAC channel is shown in Figure

19. T his figure specifically shows the logic for Channel 0; how-

ever, by changing the address input configuration to gate N1,

the other 15 channels are achieved. All of the logic for the

AD8600 is level sensitive and not edge triggered. For example,

if all the control inputs (CS, R/W, EN, LD) are low, the input

and DAC registers are transparent and any change in the digital

inputs will immediately change the DAC’s R-2R ladder.

T able I details the different logic combinations and their effects.

Chip Select (CS), Enable (EN) and R/W must be low to write

the input register. During this time that all three are low, any

data on DB7–DB0 changes the contents of the input register.

T his data is not latched until either EN or CS returns high.

T he data setup and hold times shown in the timing diagrams

must be observed to ensure that the proper data is latched into

the input register.

–10–

REV. 0

AD8600

Unipolar O utput O per ation

Table IV. Bipolar Code Table

T he AD8600 is configured to give unipolar operation. T he full-

scale output voltage is equivalent to the reference input voltage

minus 1 LSB. T he output is dependent upon the digital code

and follows T able III. T he actual numbers given for the analog

output are calculated assuming a +2.5 V reference.

D AC

Binary Input

MSB

LSB Analog O utput

1 1 1 1 1 1 1 1 +2 V_REF(255/256) – V_REF= +2.49 V

1 0 0 0 0 0 0 1 +2 V_REF(129/256) – V_REF= +0.02 V

1 0 0 0 0 0 0 0 +2 V_REF(128/256) – V_REF= +0.00 V

0 1 1 1 1 1 1 1 +2 V_REF(127/256) – V_REF= –0.02 V

0 0 0 0 0 0 0 1 +2 V_REF(001/256) – V_REF= –2.48 V

0 0 0 0 0 0 0 0 +2 V_REF(000/256) – V_REF= –2.50 V

Table III. Unipolar Code Table

D AC

Binary Input

MSB

LSB

Analog O utput

1 1 1 1 1 1 1 1

1 0 0 0 0 0 0 1

1 0 0 0 0 0 0 0

0 1 1 1 1 1 1 1

0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0

+V_REF(255/256) = +2.49 V

+V_REF(129/256) = +1.26 V

+V_REF(128/256) = +1.25 V

+V_REF(127/256) = +1.24 V

+V_REF(001/256) = +0.01 V

+V_REF(000/256) = +0.00 V

Inter facing to the 68H C11 Micr ocontr oller

T he 68HC11 is a popular microcontroller from Motorola,

which is easily interfaced to the AD8600. T he connections be-

tween the two components are shown in Figure 21. Port C of

the 68HC11 is used as a bidirectional input/output data port to

write to and read from the AD8600. Port B is used for address-

ing and control information. T he bottom 4 LSBs of Port B are

the address, and the top 4 MSBs are the control lines (LD, CS,

EN, and R/W). T he microcode for the 68 HC11 is shown in

Figure 22. T he comments in the program explain the function

of each step. T hree routines are included in this listing: read

from the AD8600, write to the AD8600, and a continuous loop

that generates a saw-tooth waveform. T his loop is used in the

application below.

Bipolar O utput O per ation

T he AD8600 can be configured for bipolar operation with the

addition of an op amp for each output as shown in Figure 20.

T he output will now have a swing of ±V_REF, as detailed in T able

IV. T his modification is only needed on those channels that re-

quire bipolar outputs. For channels which only require unipolar

output, no external amplifier is needed. T he OP495 quad am-

plifier is chosen for the external amplifier because of its low

power, rail-to-rail output swing, and DC accuracy. Again, the

values calculated for the analog output are based upon an as-

sumed +2.5 V reference.

8

DB0–DB7

PC0–PC7

4

A0–A3

LD

PB0–PB3

PB4

AD8600

MOTOROLA

EN

PB5

PB6

PB7

V_REF

68HC11

R1

R/W

DGND1, DGND2

DACGND

10k

CS

GND

+5V

DIGITAL GROUND

ANALOG GROUND

1/4

OP495

V_REF

V_OUT

OUT

ø

Figure 21. Interfacing the 68HC11 to the AD8600

AD8600

–5V

Figure 20. Circuit for Bipolar Output Operation

REV. 0

–11–

AD8600

* This program contains subroutines to read and write

* to the AD8600 from the 68HC11. Additionally, a ramp

* program has been included, to continuously ramp the

* output giving a triangle wave output.

*

* The following connections need to be made:

*

68HC11

GND

PC0-PC7

PB0-PB3

PB4

PB5

PB6

PB7

AD8600

DGND1,2

DB0–DB7 respectively, data port

A0–A3 respectively, address port

LD

EN

R/W

CS

portc equ

portb equ

$1003

$1004

$1007

define port addresses

ddrc

*

equ

org

lds

$C000

#$CFFF

read

*

subroutine to read from AD8600

ldaa #$00

staa ddrc

initialize port c to 00000000

configures PC0-PC7 as inputs.

*

ldx

ldaa 0,x

adda #$70

#$00

points to DAC address in 68HC11 memory

put the address in the accumulator

add the control bits to the address

R/W, LD, EN are high, CS is low.

output control and address on port b.

*

staa portb

inx

ldaa portc

staa 0,x

points to memory location to store the data

read data from DAC

Store this data in memory at address “x”

*

ldy

#$1000

bset portb,y $f0

Set CS, LD, EN high

Return to BUFFALO

jmp

$e000

*

write lds

#$cfff

routine to write to AD8600

initialize port c to 11111111

configures PC0-PC7 as outputs.

ldaa #$ff

staa ddrc

*

ldx

ldaa 0,x

adda #$30

staa portb

#$00

points to DAC address in 68HC11 mem

puts the address in the accumulator

set CS, R/W low and LD, EN high

output to portb for control and address

*

inx

ldaa 0,x

staa portc

points to memory location to store the data

load the data into the accumulator

write the data to the DAC

ldy

#$1000

bclr portb,y $30

bset portb,y $b0

Set LD, EN low to latch data

Bring LD, EN, CS high, write is complete

jmp

$e000

Return to BUFFALO

*

ramp

lds

ldaa #$ff

#$cfff

routine to generate a triangle wave

configure port c as outputs

–12–

REV. 0

AD8600

staa ddrc

ldx #$00

ldaa 0,x

staa portb

*

set x to point to the DAC address

load the address from 68HC11 mem

set the address on portb

*

LD, CS, EN, R/W are all low for

transparent DAC loading

ldab #$ff

set accumulator b to 255

*

loop

ldaa #$00

staa portc

start the triangle wave at zero

write the data to the AD8600

*

load

inca

staa portc

cba

increase the data by one

send the new data to the AD8600

compare a to b

bne

jmp

load

loop

we haven’t reached 255 yet

we have reached 255, so start over

Figure 22. 68HC11 Microcode to Interface to the AD8600.

needs to be 1.25 V. In this application, the C1LO input is set at

the midscale voltage of 0.625 V, which is generated by a simple

voltage divider from the REF43. T he AD8600’s output is di-

vided in half, generating a 0 V to 1.25 V ramp, and then applied

to C1HI. T his ramp sweeps the gain from 0 dB to 40 dB.

Tim e D ependent Var iable Gain Am plifier Using the AD 600

T he AD8600 is ideal for generating a control signal to set the

gain of the AD600, a wideband, low noise variable gain ampli-

fier. T he AD600 (and similar parts such as the AD602 and

AD603) is often used in ultrasound applications, which require

the gain to vary with time. When a burst of ultrasound is ap-

plied, the reflections from near objects are much stronger than

from far objects. T o accurately resolve the far objects, the gain

must be greater than for the near objects. Additionally, the sig-

nals take longer to reach the ultrasound sensor when reflected

from a distant object. T hus, the gain must increase as the time

increases.

+5V

R1

10k

V_CC, V_DD1, V_DD2

Oø

13

0V – 1.25V

DIGITAL

AD8600

V_REF

CONTROL

R2

10k

C1

100pF

+5V

2

C1HI

16

V_POS

13

2

T he AD600 requires a dc voltage to adjust its gain over a

40 dB range. Since it is a dual, the two variable gain amplifiers

can be cascaded to achieve 80 dB of gain. T he AD8600 is used

to generate a ramped output to control the gain of the AD600.

T he slope of the ramp should correspond to the time delay

of the ultrasound signal. Since ultrasound applications often

require multiple channels, the AD8600 is ideal for this

application.

V_IN

(FROM

ULTRASOUND

SENSOR)

A1HI

V_OUT

14

AD600

A1OP

3

15

A1CM

+5V

A1LO

12

4

1

2

GAT1 C1LO

–5V

0.625V

4

6

REF43

+2.5V

R4

10k

R3

30k

T he circuit to achieve a time dependent variable gain amp is

shown in Figure 23. T he AD600’s gain is controlled by differ-

ential inputs, C1LO and C1HI, with a gain constant of

32 dB/V. T hus for 40 dB of gain, the differential control input

Figure 23. Ultrasound Am plifier with Digitally Controlled

Variable Gain

REV. 0

–13–

AD8600

T he functionality of this circuit is shown in the scope photo in

Figure 24 T he top trace is the control ramp, which goes from

0 V to 1.25 V. T he bottom trace is the output of the AD600.

T he input is actually a 12 mV p-p, 10 kHz sine wave. T hus, the

bottom trace shows the envelop of this waveform to illustrate

the increase in gain as time progresses. T his ramp was gener-

ated under control of the 68HC11 using the “ramp” subroutine

as mentioned above. T he slope of the ramp can easily be

lengthened by adding some delay in the loop, or the slope can

be increased by stepping by 2 or more LSBs instead of the cur-

rent 1 LSB changes.

Glitch Im pulse

A specification of interest in many DAC applications is the

glitch impulse. T his is the amount of energy contained in any

overshoot when a DAC changes at its major carry transition, in

other words, when the DAC switches from code 01111111 to

code 10000000. T his point is the most demanding because all

of the R-2R ladder switches are changing state. T he AD8600’s

glitch impulse is shown in Figure 25. Calculating the value of

the glitch is accomplished by calculating the area of the pulse,

which for the AD8600 is: Glitch Impulse = (1/2) × (100 mV) ×

(200 ns) = 10 nV sec.

GAIN

CONTROL

1V/DIV

V

OUT

50mV/DIV

AD600

OUTPUT

0.2V/DIV

200ns/DIV

200µs/DIV

Figure 24. Tim e Dependent Gain of the AD600

Figure 25. Glitch Im pulse

–14–

REV. 0

AD8600

O UTLINE D IMENSIO NS

D imensions shown in inches and (mm).

44-Lead P lastic Lead Chip Car r ier (P LCC) P ackage

(P -44A)

0.180 (4.57)

0.165 (4.19)

0.048 (1.21)

0.042 (1.07)

0.056 (1.42)

0.042 (1.07)

0.025 (0.63)

0.015 (0.38)

6

40

39

7

PIN 1

0.021 (0.53)

0.013 (0.33)

IDENTIFIER

0.048 (1.21)

0.042 (1.07)

0.63 (16.00)

0.59 (14.99)

0.032 (0.81)

TOP VIEW

0.026 (0.66)

0.050

(1.27)

BSC

29

28

17

18

0.020

(0.50)

R

0.040 (1.01)

0.025 (0.64)

0.656 (16.66)

0.650 (16.51)

SQ

0.110 (2.79)

0.085 (2.16)

0.695 (17.65)

0.685 (17.40)

REV. 0

–15–

AD8600

–16–

REV. 0


型号：	AD8600CHIPS
厂家：	ADI
描述：	16-Channel, 8-Bit Multiplying DAC 16通道， 8位乘法DAC
文件：	总16页 (文件大小：238K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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