AD8605ART-R2
更新时间：2024-10-29 02:21:47
品牌：ADI
描述：Precision Low noise CMOS Rail-to-Rail Input/Output Operational Amplifiers
概述
数据手册
替代型号AD8605ART-R2 概述
Precision Low noise CMOS Rail-to-Rail Input/Output Operational Amplifiers 精密，低噪声CMOS轨到轨输入/输出运算放大器
AD8605ART-R2 数据手册
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PDF下载Precision Low Noise CMOS Rail-to-Rail
Input/Output Operational Amplifiers
AD8605/AD8606/AD8608
FEATURES
APPLICATIONS
Low offset voltage: 65 µV maximum
Low input bias currents: 1 pA maximum
Hz
Low noise: 8 nV/√
Photodiode amplification
Battery-powered instrumentation
Multipole filters
Sensors
Barcode scanners
Audio
Wide bandwidth: 10 MHz
High open-loop gain: 120 dB
Unity gain stable
Single-supply operation: 2.7 V to 5.5 V
MicroCSP™
FUNCTIONAL BLOCK DIAGRAMS
GENERAL DESCRIPTION
The AD8605, AD8606, and AD86081 are single, dual, and quad
rail-to-rail input and output, single-supply amplifiers. They
feature very low offset voltage, low input voltage and current
noise, and wide signal bandwidth. They use Analog Devices’
patented DigiTrim® trimming technique, which achieves
superior precision without laser trimming.
OUT
V–
1
2
5
V+
V+
1
2
3
4
8
7
6
5
OUT A
–IN A
OUT B
–IN B
+IN B
AD8605
AD8608
+IN A
V–
–IN
3
4
+IN
Figure 1. 5-Lead SOT-23 (RT Suffix)
Figure 2. 8-Lead SOIC (R Suffix)
TOP VIEW
(BUMP SIDE DOWN)
The combination of low offsets, low noise, very low input bias
currents, and high speed makes these amplifiers useful in a
wide variety of applications. Filters, integrators, photodiode
amplifiers, and high impedance sensors all benefit from the
combination of performance features. Audio and other ac
applications benefit from the wide bandwidth and low
distortion. Applications for these amplifiers include optical
control loops, portable and loop-powered instrumentation,
and audio amplification for portable devices.
1
2
3
4
5
6
7
14
OUT D
OUT A
–IN A
+IN A
V+
OUT
1
V+
5
13 –IN D
12 +IN D
V–
2
AD8608
11
10
9
V–
+IN B
–IN B
OUT B
+IN C
–IN C
OUT C
+IN
3
–IN
4
8
AD8605 ONLY
Figure 3. 5-Bump MicroCSP
(CB Suffix)
Figure 4. 14-Lead SOIC (R Suffix)
The AD8605, AD8606, and AD8608 are specified over the
extended industrial temperature range (−40°C to +125°C). The
AD8605 single is available in the 5-lead SOT-23 and 5-bump
MicroCSP packages. The 5-bump MicroCSP offers the smallest
available footprint for any surface-mount operational amplifier.
The AD8606 dual is available in an 8-lead MSOP package and a
narrow SOIC surface-mount package. The AD8608 quad is
available in a 14-lead TSSOP and a narrow 14-lead SOIC
package. MicroCSP, SOT, MSOP, and TSSOP versions are
available in tape and reel only.
OUT A
OUT D
–IN D
+IN D
V–
+IN C
–IN C
OUT C
1
14
OUT A
V+
OUT B
–IN B
1
8
5
–IN A
+IN A
V+
+IN B
–IN B
–IN A
+IN A
V–
AD8606
AD8608
4
+IN B
8
7
OUT B
Figure 5. 8-Lead MSOP (RM Suffix)
Figure 6. 14-Lead TSSOP (RU Suffix)
1 Protected by U.S. Patent No. 5,969,657; other patents pending.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
AD8605/AD8606/AD8608
TABLE OF CONTENTS
5 V Electrical Specifications............................................................ 3
Channel Separation.................................................................... 14
Capacitive Load Drive ............................................................... 14
Light Sensitivity .......................................................................... 15
MicroCSP Assembly Considerations....................................... 15
I-V Conversion Applications ........................................................ 16
Photodiode Preamplifier Applications .................................... 16
Audio and PDA Applications ................................................... 16
Instrumentation Amplifiers ...................................................... 17
D/A Conversion ......................................................................... 17
Outline Dimensions....................................................................... 18
Ordering Guide .......................................................................... 19
2.7 V Electrical Specifications......................................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Typical Performance Characteristics ............................................. 7
Application Information................................................................ 13
Output Phase Reversal............................................................... 13
Maximum Power Dissipation ................................................... 13
Input Overvoltage Protection ................................................... 13
THD + Noise............................................................................... 13
Total Noise Including Source Resistors ................................... 14
REVISION HISTORY
5/04—Data Sheet Changed from Rev. C to Rev. D
3/03—Data Sheet Changed from Rev. A to Rev. B
Updated Format............................................................. Universal
Edit to Light Sensitivity Section ...............................................16
Updated Outline Dimensions...................................................19
Changes to Ordering Guide ......................................................20
Changes to Functional Block Diagram....................................... 1
Changes to Absolute Maximum Ratings.................................... 4
Changes to Ordering Guide ....................................................... 4
Changes to Figure 9 .................................................................... 13
Updated Outline Dimensions.................................................... 15
7/03—Data Sheet Changed from Rev. B to Rev. C
Changes to Features....................................................................... 1
Change to General Description ................................................... 1
Addition to Functional Block Diagrams .................................... 1
Addition to Absolute Maximum Ratings ................................... 4
Addition to Ordering Guide ........................................................ 4
Change to Equation In Maximum Power Dissipation
11/02—Data Sheet Changed from Rev. 0 to Rev. A
Change to Electrical Characteristics........................................... 2
Changes to Absolute Maximum Ratings.................................... 4
Changes Ordering Guide ............................................................. 4
Change to TPC 6 .......................................................................... 5
Updated Outline Dimensions.................................................... 15
Section........................................................................................11
Added Light Sensitivity Section.................................................12
Added New Figure 8 and Renumbered Subsequent Figures .13
Added New MicroCSP Assembly Considerations Section ....13
Changes to Figure 9.....................................................................13
Change to Equation in Photodiode Preamplifier
Applications Section ................................................................13
Changes to Figure 12...................................................................14
Change to Equation in D/A Conversion Section ....................14
Updated Outline Dimensions ...................................................15
Rev. D | Page 2 of 20
AD8605/AD8606/AD8608
5 V ELECTRICAL SPECIFICATIONS
Table 1. @ VS = 5 V, VCM = VS/2, TA = 25°C, unless otherwise noted.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
AD8605/AD8606
AD8608
VOS
VS = 3.5 V, VCM = 3 V
VS = 3.5 V, VCM = 2.7 V
VS = 5 V, VCM = 0 V to 5 V
−40°C < TA < +125°C
20
20
80
65
75
300
750
1
µV
µV
µV
µV
pA
pA
pA
pA
pA
pA
pA
pA
V
Input Bias Current
AD8605/AD8606
AD8605/AD8606
AD8608
AD8608
Input Offset Current
IB
0.2
−40°C < TA < +85°C
−40°C < TA < +125°C
−40°C < TA < +85°C
−40°C < TA < +125°C
50
250
100
300
0.5
20
IOS
0.1
−40°C < TA < +85°C
−40°C < TA < +125°C
75
5
Input Voltage Range
0
Common-Mode Rejection Ratio
CMRR
AVO
VCM = 0 V to 5 V
85
75
300
100
90
1,000
dB
dB
V/mV
−40°C < TA < +125°C
VO = 0.5 V to 4.5 V
RL = 2 kΩ, VCM = 0 V
Large Signal Voltage Gain
Offset Voltage Drift
AD8605/AD8606
AD8608
∆VOS/∆T
∆VOS/∆T
1
1.5
4.5
6.0
µV/°C
µV/°C
INPUT CAPACITANCE
Common-Mode Input Capacitance
Differential Input Capacitance
OUTPUT CHARACTERISTICS
Output Voltage High
8.8
2.59
pF
pF
VOH
IL = 1 mA
IL = 10 mA
4.96
4.7
4.98
4.79
V
V
−40°C < TA < +125°C
IL = 1 mA
IL= 10 mA
4.6
V
Output Voltage Low
VOL
20
170
40
210
290
mV
mV
mV
mA
Ω
−40°C < TA < +125°C
Output Current
Closed-Loop Output Impedance
POWER SUPPLY
IOUT
ZOUT
80
10
f = 1 MHz, AV = 1
Power Supply Rejection Ratio
AD8605/AD8606
AD8608
PSRR
VS = 2.7 V to 5.5 V
VS = 2.7 V to 5.5 V
−40°C < TA < +125°C
VO = 0 V
80
77
70
95
92
90
1
dB
dB
dB
mA
mA
Supply Current/Amplifier
ISY
1.2
1.4
−40°C < TA < +125°C
DYNAMIC PERFORMANCE
Slew Rate
Settling Time
Full Power Bandwidth
Gain Bandwidth Product
Phase Margin
SR
tS
BWP
GBP
RL = 2 kΩ
To 0.01%, 0 V to 2 V step
< 1% distortion
5
< 1
360
V/µs
µs
kHz
10
MHz
Degrees
65
ϕO
Rev. D | Page 3 of 20
AD8605/AD8606/AD8608
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
NOISE PERFORMANCE
Peak-to-Peak Noise
Voltage Noise Density
Voltage Noise Density
Current Noise Density
en p-p
en
f = 0.1 Hz to 10 Hz
f = 1 kHz
2.3
8
3.5
12
µV p-p
Hz
nV/√
nV/√
pA/√
en
f = 10 kHz
6.5
0.01
Hz
Hz
in
f = 1 kHz
Rev. D | Page 4 of 20
AD8605/AD8606/AD8608
2.7 V ELECTRICAL SPECIFICATIONS
Table 2. @ VS = 2.7 V, VCM = VS/2, TA = 25°C, unless otherwise noted.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
AD8605/AD8606
AD8608
VOS
VS = 3.5 V, VCM = 3 V
20
20
80
65
75
300
750
1
µV
µV
µV
µV
pA
pA
pA
pA
pA
pA
pA
pA
V
VS = 3.5 V, VCM = 2.7 V
VS = 2.7 V, VCM = 0 V to 2.7 V
−40°C < TA < +125°C
Input Bias Current
AD8605/AD8606
AD8605/AD8606
AD8608
AD8608
Input Offset Current
IB
0.2
−40°C < TA < +85°C
−40°C < TA < +125°C
−40°C < TA < +85°C
−40°C < TA < +125°C
50
250
100
300
0.5
20
IOS
0.1
−40°C < TA < +85°C
−40°C < TA < +125°C
75
Input Voltage Range
0
2.7
Common-Mode Rejection Ratio
CMRR
AVO
VCM = 0 V to 2.7 V
−40°C < TA < +125°C
RL = 2 kΩ, VO= 0.5 V to 2.2 V
80
70
110
95
85
350
dB
dB
V/mV
Large Signal Voltage Gain
Offset Voltage Drift
AD8605/AD8606
AD8608
∆VOS/∆T
∆VOS/∆T
1
1.5
4.5
6.0
µV/°C
µV/°C
INPUT CAPACITANCE
Common-Mode Input Capacitance
Differential Input Capacitance
OUTPUT CHARACTERISTICS
Output Voltage High
8.8
2.59
pF
pF
VOH
VOL
IL = 1 mA
−40°C < TA < +125°C
IL = 1 mA
2.6
2.6
2.66
25
V
V
mV
mV
mA
Ω
Output Voltage Low
40
50
−40°C < TA < +125°C
Output Current
Closed-Loop Output Impedance
POWER SUPPLY
IOUT
ZOUT
30
12
f = 1 MHz, AV = 1
Power Supply Rejection Ratio
AD8605/AD8606
AD8608
PSRR
ISY
VS = 2.7 V to 5.5 V
VS = 2.7 V to 5.5 V
−40°C < TA < +125°C
VO = 0 V
80
77
70
95
92
90
1.15
dB
dB
dB
mA
mA
Supply Current/Amplifier
1.4
1.5
−40°C < TA < +125°C
DYNAMIC PERFORMANCE
Slew Rate
Settling Time
Gain Bandwidth Product
Phase Margin
SR
tS
GBP
RL = 2 kΩ
To 0.01%, 0 V to 1 V step
5
< 0.5
9
V/µs
µs
MHz
Degrees
50
ϕO
NOISE PERFORMANCE
Peak-to-Peak Noise
Voltage Noise Density
Voltage Noise Density
Current Noise Density
en p-p
en
f = 0.1 Hz to 10 Hz
f = 1 kHz
2.3
8
3.5
12
µV p-p
Hz
nV/√
nV/√
pA/√
en
f = 10 kHz
6.5
0.01
Hz
in
f = 1 kHz
Hz
Rev. D | Page 5 of 20
AD8605/AD8606/AD8608
ABSOLUTE MAXIMUM RATINGS
Table 4. Package Type
Package Type
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
1
θJA
θJC
220
92
45
43
36
35
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
5-Bump MicroCSP (CB)
5-Lead SOT-23 (RT)
8-Lead MSOP (RM)
8-Lead SOIC (R)
14-Lead SOIC (R)
14-Lead TSSOP (RU)
220
230
210
158
120
180
Table 3.
Parameter
Rating
1 θJA is specified for worst-case conditions, i.e., θJA is specified for device in
socket for PDIP packages; θJA is specified for device soldered onto a circuit
board for surface-mount packages.
Supply Voltage
Input Voltage
Differential Input Voltage
6 V
GND to VS
6 V
Output Short-Circuit Duration
to GND
Observe Derating Curves
Storage Temperature Range
All Packages
Operating Temperature Range
AD8605/AD8606/AD8608
Junction Temperature Range
All Packages
−65°C to +150°C
−40°C to +125°C
−65°C to +150°C
300°C
Lead Temperature Range
(Soldering, 60 sec)
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. D | Page 6 of 20
AD8605/AD8606/AD8608
TYPICAL PERFORMANCE CHARACTERISTICS
300
200
100
0
4500
V
T
= 5V
= 25°C
V
T
V
= 5V
= 25°C
S
S
4000
3500
3000
2500
2000
1500
1000
500
A
A
= 0V TO 5V
CM
–100
–200
–300
0
–200
–100
0
100
200
300
–300
OFFSET VOLTAGE (mV)
COMMON-MODE VOLTAGE (V)
Figure 7. Input Offset Voltage Distribution
Figure 10. Input Offset Voltage vs. Common-Mode Voltage
(200 Units, 5 Wafer Lots, Including Process Skews)
24
20
16
12
8
360
320
280
240
200
160
120
80
V
T
V
= 5V
S
A
V
= ±2.5V
S
= –40°C TO +125°C
= 2.5V
CM
AD8605/AD8606
AD8608
4
40
0
0
0
0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8
TCVOS (mV/°C)
0
25
50
75
100
125
TEMPERATURE (°C)
Figure 8. AD8608 Input Offset Voltage Drift Distribution
Figure 11. Input Bias Current vs. Temperature
20
18
16
14
12
10
8
1k
100
10
V
T
V
= 5V
S
V
T
= 5V
= 25°C
S
A
= –40°C TO +125°C
A
= 2.5V
CM
SOURCE
SINK
6
1
4
2
0
0.1
0.001
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6
TCVOS (mV/°C)
0.01
0.1
LOAD CURRENT (mA)
1
10
Figure 9. AD8605/AD8606 Input Offset Voltage Drift Distribution
Figure 12. Output Voltage to Supply Rail vs. Load Current
Rev. D | Page 7 of 20
AD8605/AD8606/AD8608
5.000
6
5
4
3
2
1
0
V
@ 1mA LOAD
OH
4.950
V
= 5V
S
V
V
T
= 5V
= 4.9V p-p
= 25°C
S
4.900
4.850
4.800
4.750
4.700
IN
A
R
A
= 2k
= 1
Ω
L
V
V
@ 10mA LOAD
OH
1k
10k
100k
1M
10M
–40 –25 –10
5
20
35
50
65
80
95 110 125
FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 16. Closed-Loop Output Voltage Swing
Figure 13. Output Voltage Swing vs. Temperature
100
90
80
70
60
50
40
30
20
10
0
0.250
0.200
0.150
0.100
0.050
0
V
= ±2.5V
S
V
= 5V
S
V
@ 10mA LOAD
OH
A
= 100
V
A
= 10
A
= 1
V
V
V
@ 1mA LOAD
OH
1k
10k
100k
1M
10M
100M
–40 –25 –10
5
20
35
50
65
80
95 110 125
FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 17. Output Impedance vs. Frequency
Figure 14. Output Voltage Swing vs. Temperature
120
110
100
90
100
80
225
180
135
90
V
= ±2.5V
S
V
R
C
= ±2.5V
= 2kV
= 20pF
= 648
S
L
L
60
f
M
40
80
20
45
70
0
0
60
–20
–40
–60
–80
–100
–45
–90
–135
–180
–225
50
40
30
20
1k
10k
100k
1M
10M
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 18. Common-Mode Rejection Ratio vs. Frequency
Figure 15. Open-Loop Gain and Phase vs. Frequency
Rev. D | Page 8 of 20
AD8605/AD8606/AD8608
140
120
100
80
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
V
= 5V
S
60
40
20
0
–20
–40
–60
1k
10k
100k
1M
10M
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
FREQUENCY (Hz)
SUPPLY VOLTAGE (V)
Figure 19. PSRR vs. Frequency
Figure 22. Supply Current vs. Supply Voltage
45
40
35
30
25
20
15
10
5
V
S
= 5V
V
R
= 5V
=
= 25°C
= 1
S
L
T
A
A
V
+OS
–OS
0
10
100
1k
TIME (1s/DIV)
CAPACITANCE (pF)
Figure 20. Small Signal Overshoot vs. Load Capacitance
Figure 23. 0.1 Hz to 10 Hz Input Voltage Noise
2.0
V
= ±2.5V
= 10kΩ
= 200pF
= 1
S
R
C
A
L
L
V
1.5
V
= 2.7V
S
1.0
V
= 5V
S
0.5
0
–0.5
–1.0
–1.5
TIME (200ns/DIV)
–50 –35 –20
5
20
35
50
65
80
95 110 125
TEMPERATURE (°C)
Figure 21. Supply Current vs. Temperature
Figure 24. Small Signal Transient Response
Rev. D | Page 9 of 20
AD8605/AD8606/AD8608
36
32
28
24
20
16
12
8
V
= ±2.5V
= 10kΩ
= 200pF
= 1
S
V
= ±2.5V
S
R
C
A
L
L
V
4
TIME (400ns/DIV)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
FREQUENCY (kHz)
Figure 25. Large Signal Transient Response
Figure 28. Voltage Noise Density
53.6
46.9
40.2
33.5
26.8
20.1
13.4
6.7
V
R
A
= ±2.5V
= 10kΩ
= 100
S
V
= ±2.5V
S
L
+2.5V
V
V
= 50mV
IN
0V
0V
–50mV
0
TIME (400ns/DIV)
0
1
2
3
4
5
6
7
8
9
10
FREQUENCY (kHz)
Figure 26. Negative Overload Recovery
Figure 29. Voltage Noise Density
119.2
104.3
99.4
74.5
59.6
44.7
29.8
14.9
0
V
R
A
= ±2.5V
= 10kΩ
= 100
S
V
= ±2.5V
S
L
V
V
= 50mV
IN
+2.5V
0V
0V
–50mV
TIME (400ns/DIV)
0
10
20
30
40
50
60
70
80
90
100
FREQUENCY (Hz)
Figure 27. Positive Overload Recovery
Figure 30. Voltage Noise Density
Rev. D | Page 10 of 20
AD8605/AD8606/AD8608
1800
1600
1400
1200
1000
800
600
400
200
0
2.680
2.675
2.670
2.665
2.660
2.655
2.650
V
T
V
= 2.7V
= 25°C
S
V
= 2.7V
S
A
= 0V TO 2.7V
CM
V
@ 1mA LOAD
OH
–200
–100
0
100
200
300
–40 –25 –10
5
20
35
50
65 80
95 110 125
–300
OFFSET VOLTAGE (µV)
TEMPERATURE (°C)
Figure 31. Input Offset Voltage Distribution
Figure 34. Output Voltage Swing vs. Temperature
300
200
100
0
0.045
0.040
0.035
0.030
0.025
0.020
0.015
0.010
0.005
0
V
= 2.7V
S
= 25°C
V
= 2.7V
S
T
A
V
@ 1mA LOAD
OH
–100
–200
–300
0
0
0.9
1.8
2.7
–40 –25 –10
5
20
35
50
65 80
95 110 125
COMMON-MODE VOLTAGE (V)
TEMPERATURE (°C)
Figure 32. Input Offset Voltage vs. Common-Mode Voltage
(200 Units, 5 Wafer Lots, Including Process Skews)
Figure 35. Output Voltage Swing vs. Temperature
100
80
225
180
135
90
1k
100
10
V
R
C
= ±1.35V
= 2kΩ
= 20pF
V
T
= 2.7V
= 25°C
S
S
L
A
L
60
fM = 52.5°
40
20
45
SOURCE
0
0
SINK
–20
–40
–60
–80
–100
–45
–90
–135
1
–180
–225
0.1
0.001
10k
100k
1M
10M
100M
0.1
LOAD CURRENT (mA)
0.01
10
1
FREQUENCY (Hz)
Figure 36. Open-Loop Gain and Phase vs. Frequency
Figure 33. Output Voltage to Supply Rail vs. Load Current
Rev. D | Page 11 of 20
AD8605/AD8606/AD8608
3.0
V
= 2.7V
S
2.5
V
V
= 2.7V
S
= 2.6V p-p
= 25°C
IN
2.0
1.5
1.0
0.5
0
T
A
R
A
= 2kΩ
L
V
= 1
TIME (1s/DIV)
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 40. 0.1 Hz to 10 Hz Input Voltage Noise
Figure 37. Closed-Loop Output Voltage Swing vs. Frequency
100
90
80
70
60
50
40
30
20
10
0
V
= 1.35V
= 10kΩ
= 200pF
= 1
S
R
C
A
V
= ±1.35V
L
L
V
S
A
= 100
V
A
= 10
V
A
= 1
V
TIME (200ns/DIV)
10k
100k
1M
10M
100M
1k
FREQUENCY (Hz)
Figure 38. Output Impedance vs. Frequency
Figure 41. Small Signal Transient Response
60
50
40
30
20
10
0
V
= 1.35V
= 10kΩ
= 200pF
= 1
V
T
A
= 2.7V
= 25°C
= 1
S
S
A
R
C
A
L
L
V
V
–OS
+OS
10
100
1k
TIME (400ns/DIV)
CAPACITANCE (pF)
Figure 42. Large Signal Transient Response
Figure 39. Small Signal Overshoot vs. Load Capacitance
Rev. D | Page 12 of 20
AD8605/AD8606/AD8608
APPLICATION INFORMATION
OUTPUT PHASE REVERSAL
Figure 44 compares the maximum power dissipation with
temperature for the various AD8605 family packages.
Phase reversal is defined as a change in polarity at the output of
the amplifier when a voltage that exceeds the maximum input
common-mode voltage drives the input.
2.0
1.8
Phase reversal can cause permanent damage to the amplifier; it
may also cause system lockups in feedback loops. The AD8605
does not exhibit phase reversal even for inputs exceeding the
supply voltage by more than 2 V.
SOIC-14
1.6
1.4
SOIC-8
1.2
1.0
V
V
A
R
= ±2.5V
= 5V p-p
= 1
S
0.8
IN
V
OUT
SOT-23
0.6
TSSOP
0.4
V
L
= 10k
Ω
MSOP
0.2
V
IN
0
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 44. Maximum Power Dissipation vs. Temperature
INPUT OVERVOLTAGE PROTECTION
The AD8605 has internal protective circuitry. However, if the
voltage applied at either input exceeds the supplies by more
than 2.5 V, external resistors should be placed in series with the
inputs. The resistor values can be determined by the formula
TIME (4µs/DIV)
Figure 43. No Phase Reversal
MAXIMUM POWER DISSIPATION
VIN −VS
RS + 200Ω
≤ 5mA
Power dissipated in an IC causes the die temperature to
increase. This can affect the behavior of the IC and the
application circuit performance.
(
)
The remarkable low input offset current of the AD8605 (<1 pA)
allows the use of larger value resistors. With a 10 kΩ resistor at
the input, the output voltage has less than 10 nV of error
voltage. A 10 kΩ resistor has less than 13 nV/√ of thermal
noise at room temperature.
The absolute maximum junction temperature of the AD8605/
AD8606/AD8608 is 150°C. Exceeding this temperature could
cause damage or destruction of the device. The maximum
power dissipation of the amplifier is calculated according to
the following formula:
Hz
THD + NOISE
Total harmonic distortion is the ratio of the input signal in V
rms to the total harmonics in V rms throughout the spectrum.
Harmonic distortion adds errors to precision measurements
and adds unpleasant sonic artifacts to audio systems.
TJ −TA
θJA
PDISS
=
where:
TJ = junction temperature
TA = ambient temperature
The AD8605 has a low total harmonic distortion. Figure 45
shows that the AD8605 has less than 0.005% or −86 dB of THD
+ N over the entire audio frequency range. The AD8605 is
configured in positive unity gain, which is the worst case, and
with a load of 10 kΩ.
θJA = junction to-ambient-thermal resistance
Rev. D | Page 13 of 20
AD8605/AD8606/AD8608
0.1
The AD8606 has a channel separation of greater than −160 dB
up to frequencies of 1 MHz, allowing the two amplifiers to
amplify ac signals independently in most applications.
V
A
B
= 2.5V
= 1
= 22kHz
SY
V
W
0
–20
0.01
0.001
–40
–60
–80
–100
–120
–140
–160
–180
0.0001
20
100
1k
10k 20k
FREQUENCY (Hz)
Figure 45. THD + N
100
1k
10k
100k
1M
10M
100M
TOTAL NOISE INCLUDING SOURCE RESISTORS
FREQUENCY (Hz)
The low input current noise and input bias current of the
AD8605 make it the ideal amplifier for circuits with substantial
input source resistance such as photodiodes. Input offset voltage
increases by less than 0.5 nV per 1 kΩ of source resistance at
room temperature and increases to 10 nV at 85°C. The total
noise density of the circuit is
Figure 46. Channel Separation vs. Frequency
CAPACITIVE LOAD DRIVE
The AD8605 can drive large capacitive loads without oscillation.
Figure 47 shows the output of the AD8606 in response to a
200 mV input signal. In this case, the amplifier was configured
in positive unity gain, worst case for stability, while driving a
1,000 pF load at its output. Driving larger capacitive loads in
unity gain may require the use of additional circuitry.
2
2
en
=
en
+
(
inRS
)
+ 4kTRS
,
TOTAL
where:
en is the input voltage noise density of the AD8605
in is the input current noise density of the AD8605
RS is the source resistance at the noninverting terminal
k is Boltzmann’s constant (1.38 × 10−23 J/K)
V
= ±2.5V
= 1
S
A
R
C
V
L
L
= 10k
= 1
Ω
T is the ambient temperature in Kelvin (T = 273 + °C)
For example, with RS = 10 kΩ, the total voltage noise density is
Hz
roughly 15 nV/√
.
For RS < 3.9 kΩ, en dominates and en,TOTAL ≈ en.
The current noise of the AD8605 is so low that its total density
does not become a significant term unless RS is greater than
6 MΩ. The total equivalent rms noise over a specific bandwidth
is expressed as
TIME (10µs/DIV)
Figure 47. Capacitive Load Drive without Snubber
A snubber network, shown in Figure 48, helps reduce the signal
overshoot to a minimum and maintain stability. Although this
circuit does not recover the loss of bandwidth induced by large
capacitive loads, it greatly reduces the overshoot and ringing.
This method does not reduce the maximum output swing of
the amplifier.
En =
(
en,TOTAL
)
BW
where BW is the bandwidth in hertz.
Note that the analysis above is valid for frequencies greater than
100 Hz and assumes relatively flat noise, above 10 kHz. For
lower frequencies, flicker noise (1/f) must be considered.
Figure 49 shows a scope photograph of the output at the
snubber circuit. The overshoot is reduced from over 70% to
less than 5%, and the ringing is eliminated by the snubber.
Optimum values for RS and CS are determined experimentally.
CHANNEL SEPARATION
Channel separation, or inverse crosstalk, is a measure of the
signal feed from one amplifier (channel) to an other on the
same IC.
Rev. D | Page 14 of 20
AD8605/AD8606/AD8608
V+
shown in Figure 50 are not normal for most applications, i.e.,
even though direct sunlight can have intensities of 50 mW/cm2,
office ambient light can be as low as 0.1 mW/cm2.
4
2
3
200mV
When the MicroCSP package is assembled on the board with
the bump-side of the die facing the PCB, reflected light from the
PCB surface is incident on active silicon circuit areas and results
in the increased IB. No performance degradation occurs due to
illumination of the backside (substrate) of the AD8605ACB.
The AD8605ACB is particularly sensitive to incident light with
wavelengths in the near infrared range (NIR, 700 nm to 1000
nm). Photons in this waveband have a longer wavelength and
lower energy than photons in the visible (400 nm to 700 nm)
and near ultraviolet bands (NUV, 200 nm to 400 nm); therefore,
they can penetrate more deeply into the active silicon. Incident
light with wavelengths greater than 1100 nm has no photo-
electric effect on the AD8605ACB because silicon is trans-
parent to wave lengths in this range. The spectral content of
conventional light sources varies: sunlight has a broad spectral
range, with peak intensity in the visible band that falls off in the
NUV and NIR bands; fluorescent lamps have significant peaks
in the visible but not in the NUV or NIR bands.
1
AD8605
V
IN
R
R
C
L
S
L
8
C
S
V–
Figure 48. Snubber Network Configuration
V
= ±2.5V
= 1
Ω
Ω
= 1,000pF
= 700pF
S
A
R
R
C
C
V
L
S
L
S
= 10k
= 90
Efforts have been made at a product level to reduce the effect
of ambient light; the under bump metal (UBM) has been
designed to shield the sensitive circuit areas on the active side
(bump-side) of the die. However, if an application encounters
any light sensitivity with the AD8605ACB, shielding the bump
side of the MicroCSP package with opaque material should
eliminate this effect. Shielding can be accomplished using
materials such as silica filled liquid epoxies that are used in
flip chip underfill techniques.
TIME (10µs/DIV)
Figure 49. Capacitive Load Drive with Snubber
Table 5 summarizes a few optimum values for capacitive loads.
Table 5.
CL (pF)
RS (Ω)
100
70
CS (pF)
1,000
1,000
800
500
1,000
2,000
60
5000
4500
4000
3500
An alternate technique is to insert a series resistor inside the
feedback loop at the output of the amplifier. Typically, the value
of this resistor is approximately 100 Ω. This method also
reduces overshoot and ringing but causes a reduction in the
maximum output swing.
2
3mW/cm
3000
2500
LIGHT SENSITIVITY
2
2mW/cm
2000
1500
1000
The AD8605ACB (MicroCSP package option) is essentially
a silicon die with additional post fabrication dielectric and
intermetallic processing designed to contact solder bumps on
the active side of the chip. With this package type, the die is
exposed to ambient light and is subject to photoelectric effects.
Light sensitivity analysis of the AD8605ACB mounted on
standard PCB material reveals that only the input bias current
(IB) parameter is impacted when the package is illuminated
directly by high intensity light. No degradation in electrical
performance is observed due to illumination by low intensity
(0.1 mW/cm2) ambient light. Figure 50 shows that IB increases
with increasing wavelength and intensity of incident light;
IB can reach levels as high as 4500 pA at a light intensity of
3 mW/cm2 and a wavelength of 850 nm. The light intensities
2
1mW/cm
500
0
350
450
550
650
750
850
WAVELENGTH (nm)
Figure 50. AD8605ACB Input Bias Current Response to Direct Illumination of
Varying Intensity and Wavelength
MICROCSP ASSEMBLY CONSIDERATIONS
For detailed information on MicroCSP PCB assembly and
reliability, refer to ADI Application Note AN-617 on the ADI
website www.analog.com.
Rev. D | Page 15 of 20
AD8605/AD8606/AD8608
I-V CONVERSION APPLICATIONS
At room temperature, the AD8605 has an input bias current of
0.2 pA and an offset voltage of 100 µV. Typical values of RD are
in the range of 1 GΩ.
PHOTODIODE PREAMPLIFIER APPLICATIONS
The low offset voltage and input current of the AD8605 make it
an excellent choice for photodiode applications. In addition, the
low voltage and current noise make the amplifier ideal for
application circuits with high sensitivity.
For the circuit shown in Figure 9, the output error voltage is
approximately 100 µV at room temperature, increasing to about
1 mV at 85°C.
C
F
10pF
Where ft is the unity gain frequency of the amplifier, the
maximum achievable signal bandwidth is
R
10MΩ
F
ft
fMAX
=
PHOTODIODE
2πRFCT
+VOS–
C
50pF
D
AD8605
R
I
D
D
AUDIO AND PDA APPLICATIONS
V
OUT
The AD8605’s low distortion and wide dynamic range make it a
great choice for audio and PDA applications, including
microphone amplification and line output buffering.
Figure 51. Equivalent Circuit for Photodiode Preamp
Figure 52 shows a typical application circuit for headphone/line
out amplification.
The input bias current of the amplifier contributes an error
term that is proportional to the value of RF.
R1 and R2 are used to bias the input voltage at half the supply.
This maximizes the signal bandwidth range. C1 and C2 are used
to ac couple the input signal. C1 and R2 form a high-pass filter
whose corner frequency is 1/2πR1C1.
The offset voltage causes a dark current induced by the shunt
resistance of the diode RD. These error terms are combined at
the output of the amplifier. The error voltage is written as
⎛
⎜
⎝
⎞
⎟
⎟
⎠
RF
RD
The high output current of the AD8605 allows it to drive heavy
resistive loads.
⎜
EO = VOS 1+
+ RF IB
The circuit of Figure 52 was tested to drive a 16 W headphone.
The THD + N is maintained at approximately −60 dB
throughout the audio range.
Typically, RF is smaller than RD, thus RF/RD can be ignored.
5V
R1
10kΩ
C1
1µF
8
C3
R4
100µF
20Ω
3
2
R2
10kΩ
1/2
V1
500mV
AD8606
1
HEADPHONES
R3
1kΩ
4
5V
C2
1µF
8
C4
100µF
R6
20Ω
5
6
1/2
V2
500mV
AD8606
7
R5
1kΩ
4
Figure 52. Single-Supply Headphone/Speaker Amplifier
Rev. D | Page 16 of 20
AD8605/AD8606/AD8608
INSTRUMENTATION AMPLIFIERS
R
R
R
The low offset voltage and low noise of the AD8605 make it a
great amplifier for instrumentation applications.
V
REF
C
F
R
F
Difference amplifiers are widely used in high accuracy circuits
to improve the common-mode rejection ratio.
R2
R2
R2
V+
V
OS
Figure 53 shows a simple difference amplifier. The CMRR of the
circuit is plotted versus frequency. Figure 54 shows the
common-mode rejection for a unity gain configuration and for
a gain of 10.
AD8605
V–
Making (R4/R3) = (R2/R1) and choosing 0.01% tolerance yields
a CMRR of 74 dB and minimizes the gain error at the output.
Figure 55. Simplified Circuit of the DAC8143 with AD8605 Output Buffer
R1
1kΩ
R2
10kΩ
To optimize the performance of the DAC, insert a capacitor in
the feedback loop of the AD8605 to compensate the amplifier
from the pole introduced by the output capacitance of the DAC.
Typical values for CF are in the range of 10 pF to 30 pF; it can be
adjusted for the best frequency response. The total error at the
output of the op amp can be computed by the formula:
V1
5V
R4 R2
=
R3 R1
R2
R1
AD8605
V
OUT
V
=
(V2 – V1)
OUT
⎛
⎜
⎝
⎞
⎟
⎟
⎠
RF
Req
R3
1kΩ
R4
10kΩ
⎜
EO = VOS 1+
V2
where Req is the equivalent resistance seen at the output of the
DAC. As mentioned above, Req is code dependant and varies
with the input. A typical value for Req is 15 kΩ. Choosing a
feedback resistor of 10 kΩ yields an error of less than 200 µV.
Figure 53. Difference Amplifier, AV = 10
120
100
80
V
= ±2.5V
SY
A
= 10
V
Figure 56 shows the implementation of a dual-stage buffer at
the output of a DAC. The first stage is used as a buffer.
Capacitor C1, with Req, creates a low-pass filter and thus
provides phase lead to compensate for frequency response. The
second stage of the AD8606 is used to provide voltage gain at
the output of the buffer.
A
= 1
V
60
40
Grounding the positive input terminals in both stages reduces
errors due to the common-mode output voltage. Choosing R1,
R2, and R3 to match within 0.01% yields a CMRR of 74 dB and
maintains minimum gain error in the circuit.
20
0
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
R
R3
20kΩ
CS
15V
Figure 54. Difference Amplifier CMRR vs. Frequency
R2
10kΩ
C1
33pF
D/A CONVERSION
V
R
FB
DD
R1
10kΩ
The low input bias current and offset voltage of the AD8605
make it an excellent choice for buffering the output of a current
output DAC.
OUT1
V
AD7545
OUT
V
REF
R
AGND
V
P
IN
1/2
DB11
1/2
AD8606
AD8606
Figure 55 shows a typical implementation of the AD8605 at the
output of a 12-bit DAC.
R4
5kΩ10%
The DAC8143 output current is converted to a voltage by the
feedback resistor. The equivalent resistance at the output of the
DAC varies with the input code, as does the output capacitance.
Figure 56. Bipolar Operation
Rev. D | Page 17 of 20
AD8605/AD8606/AD8608
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
2.90 BSC
8
1
5
4
5
4
3
6.20 (0.2440)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
2.80 BSC
1.60 BSC
2
1.27 (0.0500)
BSC
0.50 (0.0196)
0.25 (0.0099)
PIN 1
× 45°
1.75 (0.0688)
1.35 (0.0532)
0.95 BSC
0.25 (0.0098)
0.10 (0.0040)
1.90
BSC
1.30
1.15
0.90
8°
0.51 (0.0201)
0.31 (0.0122)
0° 1.27 (0.0500)
COPLANARITY
0.10
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
0.40 (0.0157)
1.45 MAX
0.22
0.08
COMPLIANT TO JEDEC STANDARDS MS-012AA
10°
5°
0°
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
0.15 MAX
0.50
0.30
0.60
0.45
0.30
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-178AA
Figure 60. 8-Lead Standard Small Outline Package [SOIC] Narrow Body (R-8)
Figure 57. 5-Lead Small Outline Transistor Package [SOT-23] (RT-5)
5.10
5.00
4.90
8.75 (0.3445)
8.55 (0.3366)
14
1
8
7
4.00 (0.1575)
3.80 (0.1496)
6.20 (0.2441)
5.80 (0.2283)
14
8
7
4.50
4.40
4.30
6.40
BSC
1.27 (0.0500)
BSC
0.50 (0.0197)
0.25 (0.0098)
1.75 (0.0689)
1.35 (0.0531)
× 45°
0.25 (0.0098)
0.10 (0.0039)
1
8°
0°
PIN 1
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
1.27 (0.0500)
0.40 (0.0157)
COPLANARITY
0.10
0.25 (0.0098)
0.17 (0.0067)
0.65
BSC
1.05
1.00
0.80
0.20
0.09
1.20
MAX
0.75
0.60
0.45
COMPLIANT TO JEDEC STANDARDS MS-012AB
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
8°
0°
0.15
0.05
0.30
0.19
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153AB-1
Figure 58. 14-Lead Standard Small Outline Package [SOIC]
Narrow Body (R-14)
Figure 61. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14)
3.00
BSC
0.50 REF
0.94
0.90
0.86
0.37
0.36
0.35
8
5
4
SEATING
PLANE
4.90
BSC
3.00
BSC
BOTTOM VIEW
0.87
0.23
PIN 1
IDENTIFIER
0.18
0.14
1.33
1.29
1.25
TOP VIEW
PIN 1
0.50
(BALL SIDE DOWN)
0.65 BSC
0.21
1.10 MAX
0.15
0.00
0.17
0.14
0.12
0.80
0.60
0.40
0.20
8°
0°
0.50
0.38
0.22
0.23
0.08
COPLANARITY
0.10
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-187AA
Figure 59. 8-Lead Mini Small Outline Package [MSOP] (RM-8)
Figure 62. 5-Bump 2 × 1 × 2 Array MicroCSP [WLCSP] (CB-5)
Rev. D | Page 18 of 20
AD8605/AD8606/AD8608
ORDERING GUIDE
Model
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
5-Bump MicroCSP
5-Bump MicroCSP
5-Lead SOT-23
5-Lead SOT-23
5-Lead SOT-23
5-Lead SOT-23
5-Lead SOT-23
8-Lead MSOP
8-Lead MSOP
8-Lead SOIC
Package Option
CB-5
CB-5
RT-5
RT-5
RT-5
RT-5
RT-5
RM-8
RM-8
R-8
R-8
R-8
R-14
R-14
R-14
RU-14
RU-14
Branding
B3A
B3A
B3A
B3A
B3A
B3A
B3A
B6A
AD8605ACB-REEL
AD8605ACB-REEL7
AD8605ART-R2
AD8605ART-REEL
AD8605ART-REEL7
AD8605ARTZ-REEL1
AD8605ARTZ-REEL71
AD8606ARM-R2
AD8606ARM-REEL
AD8606AR
AD8606AR-REEL
AD8606AR-REEL7
AD8608AR
AD8608AR-REEL
AD8608AR-REEL7
AD8608ARU
B6A
8-Lead SOIC
8-Lead SOIC
14-Lead SOIC
14-Lead SOIC
14-Lead SOIC
14-Lead TSSOP
14-Lead TSSOP
AD8608ARU-REEL
1 Z = Pb-free part.
Rev. D | Page 19 of 20
AD8605/AD8606/AD8608
NOTES
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C02731-0-5/04(D)
Rev. D | Page 20 of 20
AD8605ART-R2 CAD模型
引脚图
封装焊盘图
AD8605ART-R2 替代型号
| 型号 | 制造商 | 描述 | 替代类型 | 文档 |
| AD8605ARTZ-REEL | ADI | Precision Low noise CMOS Rail-to-Rail Input/Output Operational Amplifiers | 功能相似 |
|
| AD8605ARTZ-REEL7 | ADI | Precision Low noise CMOS Rail-to-Rail Input/Output Operational Amplifiers | 功能相似 |
|
| AD8605ARTZ-R2 | ADI | Precision, Low Noise, CMOS, Rail-to-Rail, Input/Output Operational Amplifiers | 功能相似 |
|
AD8605ART-R2 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| AD8605ART-REEL | ADI | Precision Low noise CMOS Rail-to-Rail Input/Output Operational Amplifiers | 获取价格 |
|
| AD8605ART-REEL7 | ADI | Precision Low noise CMOS Rail-to-Rail Input/Output Operational Amplifiers | 获取价格 |
|
| AD8605ARTZ | ADI | Precision, Low Noise, CMOS, Rail-to-Rail, Input/Output Operational Amplifiers | 获取价格 |
|
| AD8605ARTZ-R2 | ADI | Precision, Low Noise, CMOS, Rail-to-Rail, Input/Output Operational Amplifiers | 获取价格 |
|
| AD8605ARTZ-REEL | ADI | Precision Low noise CMOS Rail-to-Rail Input/Output Operational Amplifiers | 获取价格 |
|
| AD8605ARTZ-REEL7 | ADI | Precision Low noise CMOS Rail-to-Rail Input/Output Operational Amplifiers | 获取价格 |
|
| AD8605_08 | ADI | Precision, Low Noise, CMOS, Rail-to-Rail, Input/Output Operational Amplifiers | 获取价格 |
|
| AD8605_15 | ADI | Precision, Low Noise, CMOS, Rail-to-Rail | 获取价格 |
|
| AD8606 | ADI | Precision Low noise CMOS Rail-to-Rail Input/Output Operational Amplifiers | 获取价格 |
|
| AD8606ACBZ-REEL | ADI | Precision, Low Noise, CMOS, Rail-to-Rail, Input/Output Operational Amplifiers | 获取价格 |
|
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