AD8659ACPZ-RL [ADI]
22 mu A, RRIO, CMOS,18 V Operational Amplifiers; 22亩， RRIO ， CMOS ， 18 V运算放大器
| 型号： | AD8659ACPZ-RL |
| 厂家： | 
ADI |
| 描述： | 22 mu A, RRIO, CMOS,18 V Operational Amplifiers |
| 文件： | 总24页 (文件大小：719K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
22 µA, RRIO, CMOS,18 V
Operational Amplifiers
AD8657/AD8659
Data Sheet
FEATURES
PIN CONNECTION DIAGRAMS
Micropower at high voltage (18 V): 22 μA maximum
Low offset voltage: 350 µV maximum
Low input bias current: 20 pA maximum
Gain bandwidth product: 230 kHz at AV = 100 typical
Unity-gain crossover: 230 kHz
OUT A
–IN A
+IN A
V–
1
2
3
4
8
7
6
5
V+
AD8657
OUT B
–IN B
+IN B
TOP VIEW
(Not to Scale)
Figure 1. AD8657 Pin Configuration, 8-Lead MSOP
−3 dB closed-loop bandwidth: 305 kHz
Single-supply operation: 2.7 V to 18 V
Dual-supply operation: 1.35 V to 9 V
Unity-gain stable
OUT A 1
–IN A 2
+IN A 3
V– 4
8 V+
AD8657
TOP VIEW
(Not to Scale)
7 OUT B
6 –IN B
5 +IN B
Excellent electromagnetic interference immunity
NOTES
APPLICATIONS
1. CONNECT THE EXPOSED PAD TO V– OR
LEAVE IT UNCONNECTED.
Portable operating systems
Current monitors
Figure 2. AD8657 Pin Configuration, 8-Lead LFCSP
4 mA to 20 mA loop drivers
Buffer/level shifting
Multipole filters
Remote/wireless sensors
Low power transimpedance amplifiers
Note: For AD8659 pin connections and for more information
about the pin connections for these products, see the Pin
Configurations and Function Descriptions section.
60
50
GENERAL DESCRIPTION
The AD8657/AD8659 are dual and quad micropower, precision,
rail-to-rail input/output amplifiers optimized for low power and
wide operating supply voltage range applications.
V
V
= 2.7V
= 18V
SY
SY
40
30
20
10
0
The AD8657/AD8659 operate from 2.7 V to 18 V with a typical
quiescent supply current of 18 μA. The devices use the Analog
Devices, Inc., patented DigiTrim® trimming technique, which
achieves low offset voltage. The AD8657/AD8659 also have
high immunity to electromagnetic interference.
The combination of low supply current, low offset voltage, very
low input bias current, wide supply range, and rail-to-rail input
and output make the AD8657/AD8659 ideal for current
monitoring in process and motor control applications. The
combination of precision specifications makes these devices
ideal for dc gain and buffering of sensor front ends or high
impedance input sources in wireless or remote sensors or
transmitters.
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
Figure 3. AD8657, Supply Current vs. Temperature
Table 1. Precision Micropower Op Amps (<250 µA)
Supply Voltage
5 V
12 V to 16 V 36 V
Single
AD8538
AD8603
ADA4051-1
AD8539
AD8607
ADA4051-2
AD8609
OP196
The AD8657/AD8659 are specified over the extended industrial
temperature range (−40°C to +125°C). The AD8657 is available in
an 8-lead MSOP package and an 8-lead LFCSP package; the
AD8659 is available in a 14-lead SOIC package and 16-lead
LFCSP package.
Dual
AD8657
AD8659
AD8622
ADA4091-2
ADA4096-2
AD8624
ADA4091-4
ADA4096-4
Quad
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2011–2012 Analog Devices, Inc. All rights reserved.
AD8657/AD8659
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ..............................................9
Applications Information .............................................................. 19
Input Stage................................................................................... 19
Output Stage................................................................................ 20
Rail to Rail................................................................................... 20
Resistive Load ............................................................................. 20
Comparator Operation—AD8657........................................... 21
EMI Rejection Ratio .................................................................. 22
Applications....................................................................................... 1
General Description ......................................................................... 1
Pin Connection Diagrams............................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics—18 V Operation ............................. 3
Electrical Characteristics—10 V Operation ............................. 4
Electrical Characteristics—2.7 V Operation ............................ 5
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
4 mA to 20 mA Process Control Current Loop Transmitter—
AD8657........................................................................................ 22
Outline Dimensions....................................................................... 23
Ordering Guide .......................................................................... 24
REVISION HISTORY
8/12—Rev. A to Rev. B
Change to Comparator Operation—AD8657 Heading ............ 21
Change to 4 mA to 20 mA Process Control Current Loop
Transmitter—AD8657 Section Heading and Changed
33 μA to 34 μA ................................................................................ 22
Updated Outline Dimensions....................................................... 24
Added Figure 81 and Figure 82 .................................................... 24
Changes to Ordering Guide.......................................................... 24
Added AD8659 ...................................................................Universal
Changes to Features Section............................................................ 1
Changes to Pin Connection Diagrams Section ............................ 1
Added Figure 3, Renumbered Figures Sequentially..................... 1
Changes to Table 1............................................................................ 1
Reordered Table 2 and Table 4........................................................ 3
Changes to Table 2............................................................................ 3
Changes to Table 3 ............................................................................ 4
Changes to Table 4............................................................................ 5
Changes to Table 6............................................................................ 6
Added Pin Configurations and Function Descriptions Section 7
Added Figure 4 and Figure 5........................................................... 7
Added Table 7, Renumbered Tables Sequentially ........................ 7
Added Figure 6 and Figure 7........................................................... 8
Added Table 8.................................................................................... 8
Changes to Figure 10 and Figure 13............................................... 9
Changes to Figure 14, Figure 15, Figure 17, and Figure 18....... 10
Changes to Figure 28 and Figure 31............................................. 12
Changes to Figure 32...................................................................... 13
Changes to Figure 39...................................................................... 14
Changes to Figure 63 and Figure 66............................................. 18
Moved Figure 68 ............................................................................. 19
Change to Inverting Op Amp Configuration Section Heading
and Changes to Figure 70 .............................................................. 20
Change to Noninverting Op Amp Configuration Heading and
Changes to Figure 71...................................................................... 20
3/11—Rev. 0 to Rev. A
Added LFCSP Package Information ........................... Throughout
Added Figure 2, Renumbered Subsequent Figures....................1
Changes to Table 2, Introductory Text; Input Characteristics,
Offset Voltage and Common-Mode Rejection Ratio Test
Conditions/Comments; and Dynamic Performance, Phase
Margin Values ....................................................................................3
Changes to Table 3, Introductory Text; Input Characteristics,
Offset Voltage and Common-Mode Rejection Ratio Test
Conditions/Comments.....................................................................4
Changes to Table 4, Introductory Text; Input Characteristics,
Offset Voltage and Common-Mode Rejection Ratio Test
Conditions/Comments.....................................................................5
Changes to Thermal Resistance Section and Table 5 ...................6
Updated Outline Dimensions....................................................... 21
Changes to Ordering Guide.......................................................... 21
1/11—Revision 0: Initial Version
Rev. B | Page 2 of 24
Data Sheet
AD8657/AD8659
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—18 V OPERATION
VSY = 18 V, VCM = VSY/2 V, TA = 25°C, unless otherwise specified.
Table 2.
Parameter
Symbol Test Conditions/Comments
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
VOS
VCM = 0 V to 18 V
350
1.8
2
16
20
2.9
40
5.8
18
µV
mV
mV
mV
pA
nA
pA
nA
V
VCM = 0.3 V to 17.7 V, −40°C ≤ TA ≤ +85°C
VCM = 0.3 V to 17.7 V, −40°C ≤ TA ≤ +125°C
VCM = 0 V to 18 V, −40°C ≤ TA ≤ +125°C
Input Bias Current
IB
5
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
Input Offset Current
IOS
Input Voltage Range
0
Common-Mode Rejection Ratio
CMRR
AVO
VCM = 0 V to 18 V
94
82
80
64
115
105
110
120
dB
dB
dB
dB
dB
dB
μV/°C
GΩ
pF
VCM = 0.3 V to 17.7 V, −40°C ≤ TA ≤ +85°C
VCM = 0.3 V to 17.7 V, −40°C ≤ TA ≤ +125°C
VCM = 0 V to 18 V, −40°C ≤ TA ≤ +125°C
RL = 100 kΩ, VO = 0.5 V to 17.5 V
−40°C ≤ TA ≤ +125°C
Large Signal Voltage Gain
Offset Voltage Drift
Input Resistance
Input Capacitance, Differential Mode
Input Capacitance, Common Mode
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Short-Circuit Current
Closed-Loop Output Impedance
POWER SUPPLY
ΔVOS/ΔT
RIN
CINDM
CINCM
2
10
11
3.5
pF
VOH
VOL
ISC
RL = 100 kΩ to VCM, −40°C ≤ TA ≤ +125°C
RL = 100 kΩ to VCM, −40°C ≤ TA ≤ +125°C
17.97
V
30
mV
mA
Ω
12
15
ZOUT
f = 1 kHz, AV = 1
Power Supply Rejection Ratio
PSRR
ISY
VSY = 2.7 V to 18 V
−40°C ≤ TA ≤ +125°C
IO = 0 mA
100
90
115
18
dB
dB
µA
µA
Supply Current per Amplifier
22
34
−40°C ≤ TA ≤ +125°C
DYNAMIC PERFORMANCE
Slew Rate
Settling Time to 0.1%
Unity-Gain Crossover
Phase Margin
Gain Bandwidth Product
−3 dB Closed-Loop Bandwidth
Channel Separation
EMI Rejection Ratio of +IN x
SR
tS
RL = 1 MΩ, CL = 10 pF, AV = 1
80
15
V/ms
µs
VIN = 1 V step, RL = 100 kΩ, CL = 10 pF
VIN = 10 mV p-p, RL = 1 MΩ, CL = 10 pF, AV = 1
VIN = 10 mV p-p, RL = 1 MΩ, CL = 10 pF, AV = 1
VIN = 10 mV p-p, RL = 1 MΩ, CL = 10 pF, AV = 100
VIN = 10 mV p-p, RL = 1 MΩ, CL = 10 pF, AV = 1
f = 10 kHz, RL = 1 MΩ
UGC
ΦM
GBP
f−3 dB
CS
230
60
230
305
95
kHz
Degrees
kHz
kHz
dB
EMIRR
VIN = 100 mVPEAK; f = 400 MHz, 900 MHz,
1800 MHz, 2400 MHz
90
dB
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
en p-p
en
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 10 kHz
5
µV p-p
nV/√Hz
nV/√Hz
pA/√Hz
50
45
0.1
Current Noise Density
in
f = 1 kHz
Rev. B | Page 3 of 24
AD8657/AD8659
Data Sheet
ELECTRICAL CHARACTERISTICS—10 V OPERATION
VSY = 10 V, VCM = VSY/2 V, TA = 25°C, unless otherwise specified.
Table 3.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
VOS
VCM = 0 V to 10 V
350
1.6
2
16
15
2.6
30
5.2
10
µV
mV
mV
mV
pA
nA
pA
nA
V
VCM = 0.3 V to 9.7 V, −40°C ≤ TA ≤ +85°C
VCM = 0.3 V to 9.7 V, −40°C ≤ TA ≤ +125°C
VCM = 0 V to 10 V, −40°C ≤ TA ≤ +125°C
Input Bias Current
IB
2
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
Input Offset Current
IOS
Input Voltage Range
0
Common-Mode Rejection Ratio
CMRR
AVO
VCM = 0 V to 10 V
88
76
75
59
108
100
105
120
dB
dB
dB
dB
dB
dB
μV/°C
GΩ
pF
VCM = 0.3 V to 9.7 V, −40°C ≤ TA ≤ +85°C
VCM = 0.3 V to 9.7 V, −40°C ≤ TA ≤ +125°C
VCM = 0 V to 10 V, −40°C ≤ TA ≤ +125°C
RL = 100 kΩ, VO = 0.5 V to 9.5 V
−40°C ≤ TA ≤ +125°C
Large Signal Voltage Gain
Offset Voltage Drift
Input Resistance
Input Capacitance, Differential Mode
Input Capacitance, Common Mode
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Short-Circuit Current
Closed-Loop Output Impedance
POWER SUPPLY
ΔVOS/ΔT
RIN
CINDM
CINCM
2
10
11
3.5
pF
VOH
VOL
ISC
RL = 100 kΩ to VCM, −40°C ≤ TA ≤ +125°C
RL = 100 kΩ to VCM, −40°C ≤ TA ≤ +125°C
9.98
V
20
mV
mA
Ω
11
15
ZOUT
f = 1 kHz, AV = 1
Power Supply Rejection Ratio
PSRR
ISY
VSY = 2.7 V to 18 V
−40°C ≤ TA ≤ +125°C
IO = 0 mA
100
90
115
18
dB
dB
µA
µA
Supply Current per Amplifier
22
34
−40°C ≤ TA ≤ +125°C
DYNAMIC PERFORMANCE
Slew Rate
Settling Time to 0.1%
Unity-Gain Crossover
Phase Margin
Gain Bandwidth Product
−3 dB Closed-Loop Bandwidth
Channel Separation
EMI Rejection Ratio of +IN x
SR
ts
RL = 1 MΩ, CL = 10 pF, AV = 1
75
15
V/ms
µs
VIN = 1 V step, RL = 100 kΩ, CL = 10 pF
VIN = 10 mV p-p, RL = 1 MΩ, CL = 10 pF, AV = 1
VIN = 10 mV p-p, RL = 1 MΩ, CL = 10 pF, AV = 1
VIN = 10 mV p-p, RL = 1 MΩ, CL = 10 pF, AV = 100
VIN = 10 mV p-p, RL = 1 MΩ, CL = 10 pF, AV = 1
f = 10 kHz, RL = 1 MΩ
UGC
ΦM
GBP
f−3 dB
CS
225
60
230
300
95
kHz
Degrees
kHz
kHz
dB
EMIRR
VIN = 100 mVPEAK; f = 400 MHz, 900 MHz,
1800 MHz, 2400 MHz
90
dB
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
en p-p
en
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 10 kHz
5
µV p-p
nV/√Hz
nV/√Hz
pA/√Hz
50
45
0.1
Current Noise Density
in
f = 1 kHz
Rev. B | Page 4 of 24
Data Sheet
AD8657/AD8659
ELECTRICAL CHARACTERISTICS—2.7 V OPERATION
VSY = 2.7 V, VCM = VSY/2 V, TA = 25°C, unless otherwise specified.
Table 4.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
VOS
VCM = 0 V to 2.7 V
350
1.2
2.5
16
10
2.6
20
µV
mV
mV
mV
pA
nA
pA
nA
V
VCM = 0.3 V to 2.4 V, −40°C ≤ TA ≤ +85°C
VCM = 0.3 V to 2.4 V, −40°C ≤ TA ≤ +125°C
VCM = 0 V to 2.7 V, −40°C ≤ TA ≤ +125°C
Input Bias Current
IB
1
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
Input Offset Current
IOS
5.2
2.7
Input Voltage Range
0
Common-Mode Rejection Ratio
CMRR
AVO
VCM = 0 V to 2.7 V
77
69
62
47
95
90
95
dB
dB
dB
dB
dB
dB
μV/°C
GΩ
pF
VCM = 0.3 V to 2.4 V, −40°C ≤ TA ≤ +85°C
VCM = 0.3 V to 2.4 V, −40°C ≤ TA ≤ +125°C
VCM = 0 V to 2.7 V, −40°C ≤ TA ≤ +125°C
RL = 100 kΩ, VO = 0.5 V to 2.2 V
−40°C ≤ TA ≤ +125°C
Large Signal Voltage Gain
105
Offset Voltage Drift
Input Resistance
Input Capacitance, Differential Mode CINDM
Input Capacitance, Common Mode
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Short-Circuit Current
Closed-Loop Output Impedance
POWER SUPPLY
ΔVOS/ΔT
RIN
2
10
11
3.5
CINCM
pF
VOH
VOL
ISC
RL = 100 kΩ to VCM, −40°C ≤ TA ≤ +125°C
RL = 100 kΩ to VCM, −40°C ≤ TA ≤ +125°C
2.69
V
10
mV
mA
Ω
4
20
ZOUT
f = 1 kHz, AV = 1
Power Supply Rejection Ratio
PSRR
ISY
VSY = 2.7 V to 18 V
−40°C ≤ TA ≤ +125°C
IO = 0 mA
100
90
115
18
dB
dB
µA
µA
Supply Current per Amplifier
22
34
−40°C ≤ TA ≤ +125°C
DYNAMIC PERFORMANCE
Slew Rate
Settling Time to 0.1%
Unity-Gain Crossover
Phase Margin
Gain Bandwidth Product
−3 dB Closed-Loop Bandwidth
Channel Separation
EMI Rejection Ratio of +IN x
SR
ts
RL = 1 MΩ, CL = 10 pF, AV = 1
50
20
V/ms
µs
VIN = 1 V step, RL = 100 kΩ, CL = 10 pF
VIN = 10 mV p-p, RL = 1 MΩ, CL = 10 pF, AV = 1
VIN = 10 mV p-p, RL = 1 MΩ, CL = 10 pF, AV = 1
VIN = 10 mV p-p, RL = 1 MΩ, CL = 10 pF, AV = 100
VIN = 10 mV p-p, RL = 1 MΩ, CL = 10 pF, AV = 1
f = 10 kHz, RL = 1 MΩ
UGC
ΦM
GBP
f−3 dB
CS
190
55
200
245
95
kHz
Degrees
kHz
kHz
dB
EMIRR
VIN = 100 mVPEAK; f = 400 MHz, 900 MHz,
1800 MHz, 2400 MHz
90
dB
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
en p-p
en
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 10 kHz
6
µV p-p
nV/√Hz
nV/√Hz
pA/√Hz
60
56
0.1
Current Noise Density
in
f = 1 kHz
Rev. B | Page 5 of 24
AD8657/AD8659
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 5.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages using a
standard 4-layer JEDEC board. The exposed pad (LFCSP
packages only) is soldered to the board.
Parameter
Rating
Supply Voltage
Input Voltage
Input Current1
Differential Input Voltage
Output Short-Circuit
Duration to GND
Temperature Ranges
Storage
Operating
Junction
Lead Temperature
(Soldering, 60 sec)
20.5 V
(V−) − 300 mV to (V+) + 300 mV
10 mA
VSY
Table 6. Thermal Resistance
Indefinite
Package Type
θJA
142
75
115
52
θJC
45
12
36
13
Unit
°C/W
°C/W
°C/W
°C/W
8-Lead MSOP (RM-8)
8-Lead LFCSP (CP-8-11)
14-Lead SOIC (R-14)
16-Lead LFCSP (CP-16-20)
−65°C to +150°C
−40°C to +125°C
−65°C to +150°C
300°C
ESD CAUTION
1 The input pins have clamp diodes to the power supply pins. Limit the input
current to 10 mA or less whenever input signals exceed the power supply
rail by 0.3 V.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. B | Page 6 of 24
Data Sheet
AD8657/AD8659
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
OUT A
–IN A
+IN A
V–
1
2
3
4
8
7
6
5
V+
OUT A 1
–IN A 2
+IN A 3
V– 4
8 V+
AD8657
OUT B
–IN B
+IN B
AD8657
TOP VIEW
(Not to Scale)
7 OUT B
6 –IN B
5 +IN B
TOP VIEW
(Not to Scale)
NOTES
1. CONNECT THE EXPOSED PAD TO V– OR
LEAVE IT UNCONNECTED.
Figure 4. AD8657 Pin Configuration, 8-Lead MSOP
Figure 5. AD8657 Pin Configuration, 8-Lead LFCSP
Table 7. Pin Function Descriptions, AD8657
Pin No.1
8-Lead MSOP 8-Lead LFCSP Mnemonic Description
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
OUT A
−IN A
+IN A
V−
+IN B
−IN B
OUT B
V+
Output Channel A.
Negative Input Channel A.
Positive Input Channel A.
Negative Supply Voltage.
Positive Input Channel B.
Negative Input Channel B.
Output Channel B.
Positive Supply Voltage.
Exposed Pad. For the AD8657 (8-lead LFCSP only), connect the exposed pad to V− or leave
it unconnected.
N/A
EP2
EPAD
1 N/A means not applicable.
2 The exposed pad is not shown in the pin configuration diagram.
Rev. B | Page 7 of 24
AD8657/AD8659
Data Sheet
OUT A
–IN A
+IN A
V+
1
2
3
4
5
6
7
14 OUT D
13 –IN D
12 +IN D
11 V–
–IN A
+IN A
V+
1
2
3
4
12 –IN D
11 +IN D
10 V–
AD8659
TOP VIEW
AD8659
(Not to Scale)
9
+IN C
+IN B
TOP VIEW
(Not to Scale)
+IN B
–IN B
OUT B
10 +IN C
9
8
–IN C
OUT C
NOTES
1. NIC = NO INTERNAL CONNECTION.
2. CONNECT THE EXPOSED PAD TO V– OR
LEAVE IT UNCONNECTED.
Figure 7. AD8659 Pin Configuration, 16-Lead LFCSP
Figure 6. AD8659 Pin Configuration, 14-Lead SOIC_N
Table 8. Pin Function Descriptions, AD8659
Pin No.1
14-Lead SOIC
16-Lead LFCSP
Mnemonic
OUT A
−IN A
+IN A
V−
+IN B
−IN B
OUT B
V+
OUT C
−IN C
+IN C
+IN D
−IN D
OUT D
NIC
Description
1
2
3
11
5
6
7
4
8
15
1
2
10
4
5
6
3
7
8
Output Channel A.
Negative Input Channel A.
Positive Input Channel A.
Negative Supply Voltage.
Positive Input Channel B.
Negative Input Channel B.
Output Channel B.
Positive Supply Voltage.
Output Channel C.
9
Negative Input Channel C.
Positive Input Channel C.
Positive Input Channel D.
Negative Input Channel D.
Output Channel D.
No Internal Connection.
No Internal Connection.
Exposed Pad. For the AD8659 (16-lead LFCSP only), connect the exposed pad to
V− or leave it unconnected.
10
12
13
14
N/A
N/A
N/A
9
11
12
14
13
16
EP2
NIC
EPAD2
1 N/A means not applicable.
2 The exposed pad is not shown in the pin configuration diagram.
Rev. B | Page 8 of 24
Data Sheet
AD8657/AD8659
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
160
160
140
120
100
80
V
V
= 2.7V
= V /2
SY
V
V
= 18V
= V /2
SY
SY
SY
140
120
100
80
CM
CM
60
60
40
40
20
20
0
0
V
(µV)
V
(µV)
OS
OS
Figure 8. Input Offset Voltage Distribution
Figure 11. Input Offset Voltage Distribution
18
16
14
12
10
8
20
18
16
14
12
10
8
V
= 2.7V
V
= 18V
SY
SY
–40°C ≤ T ≤ +125°C
–40°C ≤ T ≤ +125°C
A
A
6
6
4
4
2
2
0
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
TCV (µV/°C)
OS
TCV (µV/°C)
OS
Figure 9. Input Offset Voltage Drift Distribution
Figure 12. Input Offset Voltage Drift Distribution
350
250
150
50
350
250
V
= 18V
V
= 2.7V
SY
SY
150
50
–50
–150
–250
–50
–150
–250
–350
–350
0
0.3
0.6
0.9
1.2
V
1.5
(V)
1.8
2.1
2.4
2.7
0
2
4
6
8
10
(V)
12
14
16
18
V
CM
CM
Figure 10. Input Offset Voltage vs. Common-Mode Voltage
Figure 13. Input Offset Voltage vs. Common-Mode Voltage
Rev. B | Page 9 of 24
AD8657/AD8659
Data Sheet
3.0
3.0
2.5
V
= 2.7V
V
= 18V
SY
SY
2.5
2.0
–40°C ≤ T ≤ +85°C
–40°C < T < +85°C
A
A
2.0
1.5
1.5
1.0
1.0
0.5
0.5
0
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
0
0.3
0.6
0.9
1.2
1.5
(V)
1.8
2.1
2.4
2.7
18
0
2
4
6
8
10
(V)
12
14
16
V
V
CM
CM
Figure 14. Input Offset Voltage vs. Common-Mode Voltage
Figure 17. Input Offset Voltage vs. Common-Mode Voltage
6
6
4
V
= 18V
SY
V
= 2.7V
SY
4
2
–40°C ≤ T ≤ +125°C
A
–40°C ≤ T ≤ +125°C
A
2
0
0
–2
–4
–6
–2
–4
–6
0
0.3
0.6
0.9
1.2
1.5
(V)
1.8
2.1
2.4
2.7
0
2
4
6
8
10
(V)
12
14
16
18
V
CM
V
CM
Figure 15. Input Offset Voltage vs. Common-Mode Voltage
Figure 18. Input Offset Voltage vs. Common-Mode Voltage
10000
1000
100
10
10000
1000
100
10
V
= 2.7V
V
= 18V
SY
SY
│I +│
│I +│
B
B
│I –│
│I –│
B
B
1
1
0.1
0.1
25
50
75
100
125
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 16. Input Bias Current vs. Temperature
Figure 19. Input Bias Current vs. Temperature
Rev. B | Page 10 of 24
Data Sheet
AD8657/AD8659
4
4
3
V
= 2.7V
V
= 18V
SY
SY
3
2
2
1
1
0
0
125°C
85°C
25°C
125°C
85°C
25°C
–1
–2
–3
–4
–1
–2
–3
–4
0
0.3
0.6
0.9
1.2
1.5
(V)
1.8
2.1
2.4
2.7
0
2
4
6
8
10
(V)
12
14
16
18
V
V
CM
CM
Figure 20. Input Bias Current vs. Common-Mode Voltage
Figure 23. Input Bias Current vs. Common-Mode Voltage
10
1
10
1
V
= 2.7V
V
= 18V
SY
SY
–40°C
+25°C
+85°C
+125°C
–40°C
+25°C
+85°C
+125°C
100m
10m
1m
100m
10m
1m
0.1m
0.01m
0.1m
0.01m
0.001
0.01
0.1
1
10
100
0.001
0.01
0.1
1
10
100
LOAD CURRENT (mA)
LOAD CURRENT (mA)
Figure 21. Output Voltage (VOH) to Supply Rail vs. Load Current
Figure 24. Output Voltage (VOH) to Supply Rail vs. Load Current
10
10
V
= 2.7V
V
= 18V
SY
SY
1
100m
10m
1
100m
10m
–40°C
+25°C
+85°C
+125°C
–40°C
+25°C
+85°C
+125°C
1m
1m
0.1m
0.01m
0.1m
0.01m
0.001
0.01
0.1
1
10
100
0.001
0.01
0.1
1
10
100
LOAD CURRENT (mA)
LOAD CURRENT (mA)
Figure 22. Output Voltage (VOL) to Supply Rail vs. Load Current
Figure 25. Output Voltage (VOL) to Supply Rail vs. Load Current
Rev. B | Page 11 of 24
AD8657/AD8659
Data Sheet
2.700
2.699
2.698
2.697
2.696
18.000
17.995
17.990
17.985
17.980
17.975
R = 1MΩ
L
R
= 1MΩ
L
R
= 100kΩ
L
R
= 100kΩ
L
V
= 2.7V
V
= 18V
–25
SY
SY
2.695
–50
–50
0
25
50
75
100
125
–25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 26. Output Voltage (VOH) vs. Temperature
Figure 29. Output Voltage (VOH) vs. Temperature
12
10
8
12
10
8
V
= 2.7V
V
= 18V
SY
SY
R
= 100kΩ
L
6
6
4
4
R
= 100kΩ
L
2
2
R
= 1MΩ
L
R
= 1MΩ
L
0
–50
0
–50
–25
0
25
50
75
100
125
–25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 27. Output Voltage (VOL) vs. Temperature
Figure 30. Output Voltage (VOL) vs. Temperature
35
30
25
20
15
10
5
35
30
25
20
15
10
5
V
= 18V
SY
V
= 2.7V
SY
–40°C
+25°C
+85°C
+125°C
–40°C
+25°C
+85°C
+125°C
0
0
0
3
6
9
12
15
18
0
0.3
0.6
0.9
1.2
1.5
(V)
1.8
2.1
2.4
2.7
V
(V)
CM
V
CM
Figure 28. Supply Current vs. Common-Mode Voltage
Figure 31. Supply Current vs. Common-Mode Voltage
Rev. B | Page 12 of 24
Data Sheet
AD8657/AD8659
60
50
40
30
20
10
0
40
35
30
25
20
15
10
5
V
V
= 2.7V
= 18V
SY
SY
–40°C
+25°C
+85°C
+125°C
0
0
3
6
9
12
15
18
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
V
(V)
SY
Figure 35. Supply Current vs. Temperature
Figure 32. Supply Current vs. Supply Voltage
135
90
135
90
60
40
60
40
V
R
= 18V
= 1MΩ
SY
V
R
= 2.7V
= 1MΩ
SY
PHASE
PHASE
L
L
45
45
20
20
GAIN
0
0
0
0
GAIN
–45
–90
–135
–45
–90
–135
–20
–40
–60
–20
–40
–60
C
C
= 10pF
C
C
= 10pF
L
L
L
L
= 100pF
= 100pF
1k
10k
100k
1M
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 36. Open-Loop Gain and Phase vs. Frequency
Figure 33. Open-Loop Gain and Phase vs. Frequency
60
60
40
V
= 18V
V
= 2.7V
SY
SY
A
= 100
A
= 100
V
V
40
20
A
A
= 10
= 1
A
A
= 10
= 1
V
V
V
V
20
0
0
–20
–40
–60
–20
–40
–60
100
1k
10k
100k
1M
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 37. Closed-Loop Gain vs. Frequency
Figure 34. Closed-Loop Gain vs. Frequency
Rev. B | Page 13 of 24
AD8657/AD8659
Data Sheet
1000
1000
100
10
A
= 100
A = 100
V
V
A
= 10
A = 10
V
V
100
10
1
A
= 1
A = 1
V
V
V
= 2.7V
V
= 18V
SY
SY
1
100
1k
FREQUENCY (Hz)
10k
100k
100
1k
FREQUENCY (Hz)
10k
100k
Figure 38. Output Impedance vs. Frequency
Figure 41. Output Impedance vs. Frequency
140
120
100
80
140
120
100
80
V
V
= 18V
SY
V
V
= 2.7V
SY
= V /2
= V /2
CM
SY
CM
SY
60
60
40
40
20
20
0
100
0
100
1k
10k
100k
1M
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 42. CMRR vs. Frequency
Figure 39. CMRR vs. Frequency
100
80
60
40
20
0
100
V
= 18V
V
= 2.7V
SY
SY
80
60
40
20
0
PSRR+
PSRR–
PSRR+
PSRR–
100
1k
10k
100k
1M
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 43. PSRR vs. Frequency
Figure 40. PSRR vs. Frequency
Rev. B | Page 14 of 24
Data Sheet
AD8657/AD8659
70
70
60
50
40
30
20
10
0
V
V
R
= 2.7V
= 10mV p-p
= 1MΩ
V
V
R
= 18V
= 10mV p-p
= 1MΩ
SY
IN
SY
IN
OS+
OS–
OS+
OS–
60
50
40
30
20
10
0
L
L
10
100
CAPACITANCE (pF)
1000
10
100
CAPACITANCE (pF)
1000
Figure 44. Small Signal Overshoot vs. Load Capacitance
Figure 47. Small Signal Overshoot vs. Load Capacitance
V
= ±1.35V
SY
A
R
C
= 1
= 1MΩ
= 100pF
V
L
L
V
= ±9V
= 1
= 1MΩ
= 100pF
SY
A
R
C
V
L
L
TIME (100µs/DIV)
TIME (100µs/DIV)
Figure 45. Large Signal Transient Response
Figure 48. Large Signal Transient Response
V
= ±1.35V
= 1
= 1MΩ
= 100pF
SY
V
= ±9V
= 1
= 1MΩ
= 100pF
SY
A
R
C
V
L
L
A
R
C
V
L
L
TIME (100µs/DIV)
TIME (100µs/DIV)
Figure 46. Small Signal Transient Response
Figure 49. Small Signal Transient Response
Rev. B | Page 15 of 24
AD8657/AD8659
Data Sheet
V
A
R
= ±9V
= –10
= 1MΩ
SY
0
–0.2
–0.4
V
L
INPUT
INPUT
0
–1
–2
V
A
R
= ±1.35
= –10
= 1MΩ
SY
V
L
2
1
0
10
5
OUTPUT
OUTPUT
0
TIME (40µs/DIV)
TIME (40µs/DIV)
Figure 50. Positive Overload Recovery
Figure 53. Positive Overload Recovery
V
A
R
= ±9V
= –10
= 1MΩ
SY
0.4
0.2
0
2
1
0
V
L
INPUT
INPUT
OUTPUT
OUTPUT
0
0
V
A
R
= ±1.35V
= –10
= 1MΩ
SY
–1
–2
–5
–10
V
L
TIME (40µs/DIV)
TIME (40µs/DIV)
Figure 51. Negative Overload Recovery
Figure 54. Negative Overload Recovery
INPUT
INPUT
V
R
C
= 2.7V
= 100kΩ
= 10pF
V
R
C
= 18V
= 100kΩ
= 10pF
SY
SY
L
L
L
L
+5mV
0
+5mV
0
ERROR BAND
ERROR BAND
OUTPUT
OUTPUT
–5mV
–5mV
TIME (10µs/DIV)
TIME (10µs/DIV)
Figure 52. Positive Settling Time to 0.1%
Figure 55. Positive Settling Time to 0.1%
Rev. B | Page 16 of 24
Data Sheet
AD8657/AD8659
V
R
C
= 2.7V
= 100kΩ
= 10pF
V
R
C
=18V
= 100kΩ
= 10pF
SY
SY
L
L
L
L
INPUT
INPUT
+5mV
0
+5mV
0
OUTPUT
OUTPUT
ERROR BAND
ERROR BAND
–5mV
–5mV
TIME (10µs/DIV)
TIME (10µs/DIV)
Figure 56. Negative Settling Time to 0.1%
Figure 59. Negative Settling Time to 0.1%
1000
100
10
1000
100
10
V
= 2.7V
V
= 18V
SY
SY
1
1
10
100
1k
10k
100k
1M
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 57. Voltage Noise Density vs. Frequency
Figure 60. Voltage Noise Density vs. Frequency
V
= 2.7V
V
= 18V
SY
SY
TIME (2s/DIV)
TIME (2s/DIV)
Figure 58. 0.1 Hz to 10 Hz Noise
Figure 61. 0.1 Hz to 10 Hz Noise
Rev. B | Page 17 of 24
AD8657/AD8659
Data Sheet
20
18
16
14
12
10
8
3.0
2.5
2.0
1.5
1.0
0.5
0
V
V
R
A
= 18V
= 17.9V
= 1MΩ
= 1
V
V
R
= 2.7V
= 2.6V
= 1MΩ
= 1
SY
IN
SY
IN
L
V
L
V
A
6
4
2
0
10
100
1k
10k
100k
1M
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 65. Output Swing vs. Frequency
Figure 62. Output Swing vs. Frequency
100
10
10
V
V
R
A
= 18V
= 0.2V RMS
= 1MΩ
SY
IN
V
V
R
A
= 2.7V
= 0.2V RMS
= 1MΩ
= 1
SY
IN
L
V
= 1
L
V
1
1
0.1
0.1
0.01
0.01
0.001
10
100
1k
10k
100k
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 63. THD + N vs. Frequency
Figure 66. THD + N vs. Frequency
0
0
1MΩ
1MΩ
V
R
A
= 2.7V
= 1MΩ
= –100
10kΩ
V
R
A
= 18V
= 1MΩ
= –100
SY
SY
10kΩ
–20
–20
L
V
L
V
R
L
R
–40
–60
–40
–60
L
V
V
V
V
V
= 1V p-p
= 5V p-p
= 10V p-p
= 15V p-p
= 17V p-p
IN
IN
IN
IN
IN
V
V
V
= 0.5V p-p
= 1.5V p-p
= 2.6V p-p
IN
IN
IN
–80
–80
–100
–120
–140
–100
–120
–140
100
1k
10k
FREQUENCY (Hz)
100k
100
1k
10k
FREQUENCY (Hz)
100k
Figure 64. Channel Separation vs. Frequency
Figure 67. Channel Separation vs. Frequency
Rev. B | Page 18 of 24
Data Sheet
AD8657/AD8659
APPLICATIONS INFORMATION
V+
VB1
I1
M8
M9
M5
M10
M11
M3
M4
+IN x
–IN x
M16
M17
R1
R2
D1
D2
VB2
OUT x
M1 M2
M12
M14
M13
M15
M7
M6
V–
Figure 68. Simplified Schematic
The AD8657/AD8659 are low power, rail-to-rail input and output
precision CMOS amplifiers that operate over a wide supply
voltage range of 2.7 V to 18 V. The AD8657/AD8659 use the
Analog Devices DigiTrim technique to achieve a higher degree
of precision than is available from other CMOS amplifiers. The
DigiTrim technique is a method of trimming the offset voltage
of an amplifier after assembly. The advantage of post-package
trimming is that it corrects any shifts in offset voltage caused by
mechanical stresses of assembly.
These changes are a result of the load transistors (M8, M9, M14,
and M15) running out of headroom. As the load transistors are
forced into the triode region of operation, the mismatch of their
drain impedances contributes to the offset voltage of the amplifier.
This problem is exacerbated at high temperatures due to the
decrease in the threshold voltage of the input transistors (see
Figure 14, Figure 15, Figure 17, and Figure 18 for typical perfor-
mance data).
Current Source I1 drives the PMOS transistor pair. As the input
common-mode voltage approaches the upper rail, I1 is steered
away from the PMOS differential pair through the M5 transistor.
The bias voltage, VB1 (see Figure 68), controls the point where this
transfer occurs. M5 diverts the tail current into a current mirror
consisting of the M6 and M7 transistors. The output of the current
mirror then drives the NMOS pair. Note that the activation of
this current mirror causes a slight increase in supply current at
high common-mode voltages (see Figure 28 and Figure 31 for
more details).
The AD8657/AD8659 also employ unique input and output
stages to achieve a rail-to-rail input and output range with a
very low supply current.
INPUT STAGE
Figure 68 shows the simplified schematic of the AD8657/AD8659.
The input stage comprises two differential transistor pairs, an
NMOS pair (M1, M2) and a PMOS pair (M3, M4). The input
common-mode voltage determines which differential pair turns
on and is more active than the other.
The AD8657/AD8659 achieve their high performance by using
low voltage MOS devices for their differential inputs. These low
voltage MOS devices offer excellent noise and bandwidth per
unit of current. Each differential input pair is protected by proprie-
tary regulation circuitry (not shown in the simplified schematic).
The regulation circuitry consists of a combination of active
devices that maintain the proper voltages across the input pairs
during normal operation and passive clamping devices that protect
the amplifier during fast transients. However, these passive
clamping devices begin to forward bias as the common-mode
voltage approaches either power supply rail, thereby causing an
increase in the input bias current (see Figure 20 and Figure 23).
The PMOS differential pair is active when the input voltage
approaches and reaches the lower supply rail. The NMOS pair
is needed for input voltages up to and including the upper supply
rail. This topology allows the amplifier to maintain a wide
dynamic input voltage range and to maximize signal swing to
both supply rails.
For the majority of the input common-mode voltage range, the
PMOS differential pair is active. Differential pairs commonly
exhibit different offset voltages. The handoff from one pair to the
other creates a step-like characteristic that is visible in the VOS vs.
VCM graphs (see Figure 10 and Figure 13). This characteristic is
inherent in all rail-to-rail amplifiers that use the dual differential
pair topology. Therefore, always choose a common-mode voltage
that does not include the region of handoff from one input
differential pair to the other.
The input devices are also protected from large differential
input voltages by clamp diodes (D1 and D2). These diodes are
buffered from the inputs with two 10 kΩ resistors (R1 and R2).
The differential diodes turn on whenever the differential voltage
exceeds approximately 600 mV; in this condition, the differential
input resistance drops to 20 kΩ.
Additional steps in the VOS vs. VCM curves are also visible as the
input common-mode voltage approaches the power supply rails.
Rev. B | Page 19 of 24
AD8657/AD8659
Data Sheet
Inverting Op Amp Configuration
OUTPUT STAGE
Figure 70 shows the AD8657/AD8659 in an inverting configu-
ration with a resistive load, RL, at the output. The actual load
seen by the amplifier is the parallel combination of the feedback
resistor, R2, and load, RL. For example, the combination of a feed-
back resistor of 1 kΩ and a load of 1 MΩ results in an equivalent
load resistance of 999 Ω at the output. Because the AD8657/
AD8659 are incapable of driving such a heavy load, performance
degrades greatly.
The AD8657/AD8659 feature a complementary output stage
consisting of the M16 and M17 transistors. These transistors are
configured in Class AB topology and are biased by the voltage
source, VB2. This topology allows the output voltage to go
within millivolts of the supply rails, achieving a rail-to-rail output
swing. The output voltage is limited by the output impedance of the
transistors, which are low RON MOS devices. The output voltage
swing is a function of the load current and can be estimated using
the output voltage to the supply rail vs. load current diagrams (see
Figure 21, Figure 22, Figure 24, and Figure 25).
To avoid loading the output, use a larger feedback resistor, but
consider the resistor thermal noise effect on the overall circuit.
R2
RAIL TO RAIL
The AD8657/AD8659 feature rail-to-rail input and output with
a supply voltage from 2.7 V to 18 V. Figure 69 shows the input
and output waveforms of the AD8657/AD8659 configured as a
unity-gain buffer with a supply voltage of 9 V and a resistive
load of 1 MΩ. With an input voltage of 9 V, the AD8657/AD8659
allow the output to swing very close to both rails. Additionally,
they do not exhibit phase reversal.
+V
SY
R1
V
IN
AD8657/
AD8659
V
OUT
R
L
–V
SY
R
= R || R2
L, EFF
L
V
R
= ±9V
= 1MΩ
SY
INPUT
OUTPUT
Figure 70. Inverting Op Amp Configuration
L
Noninverting Op Amp Configuration
Figure 71 shows the AD8657/AD8659 in a noninverting configu-
ration with a resistive load, RL, at the output. The actual load seen
by the amplifier is the parallel combination of R1 + R2 and RL.
R2
+V
SY
R1
AD8657/
AD8659
V
OUT
R
L
V
IN
TIME (200µs/DIV)
Figure 69. Rail-to-Rail Input and Output
–V
SY
R
= R || (R1 + R2)
L, EFF
L
RESISTIVE LOAD
Figure 71. Noninverting Op Amp Configuration
The feedback resistor alters the load resistance that an amplifier
sees. It is, therefore, important to be aware of the value of feed-
back resistors chosen for use with the AD8657/AD8659. The
amplifiers are capable of driving resistive loads down to 100 kΩ.
The following two examples, inverting and noninverting
configurations, show how the feedback resistor changes the
actual load resistance seen at the output of the amplifier.
Rev. B | Page 20 of 24
Data Sheet
AD8657/AD8659
conduct whenever the differential input voltage exceeds approxi-
mately 600 mV; however, these diodes also allow a current path
from the input to the lower supply rail, thus resulting in an
increase in the total supply current of the system. As shown in
Figure 76, both configurations yield the same result. At 18 V of
power supply, ISY+ remains at 36 μA per dual amplifier, but ISY−
increases to 140 μA in magnitude per dual amplifier.
COMPARATOR OPERATION—AD8657
An op amp is designed to operate in a closed-loop configuration
with feedback from its output to its inverting input. Figure 72
shows the AD8657 configured as a voltage follower with an input
voltage that is always kept at midpoint of the power supplies.
The same configuration is applied to the unused channel. A1 and
A2 indicate the placement of ammeters to measure supply current.
ISY+ refers to the current flowing from the upper supply rail to
the op amp, and ISY− refers to the current flowing from the op
amp to the lower supply rail. As shown in Figure 73, as expected
in normal operating condition, the total current flowing into the
op amp is equivalent to the total current flowing out of the op amp,
where, ISY+ = ISY− = 36 μA for the dual AD8657 at VSY = 18 V.
+V
SY
A1
I
+
SY
100kΩ
100kΩ
AD8657
V
OUT
1/2
+V
SY
A2
I
–
SY
A1
I
+
SY
–V
SY
100kΩ
100kΩ
AD8657
Figure 74. Comparator A
V
OUT
1/2
+V
SY
A2
I
–
SY
A1
I
+
SY
100kΩ
–V
SY
AD8657
V
OUT
Figure 72. Voltage Follower
1/2
40
35
30
25
20
15
10
5
100kΩ
A2
I
–
SY
–V
SY
Figure 75. Comparator B
160
140
120
100
80
I
I
–
+
SY
SY
0
I
–
+
SY
0
2
4
6
8
10
(V)
12
14
16
18
I
SY
V
SY
60
Figure 73. Supply Current vs. Supply Voltage (Voltage Follower)
40
In contrast to op amps, comparators are designed to work in an
open-loop configuration and to drive logic circuits. Although
op amps are different from comparators, occasionally an unused
section of a dual op amp is used as a comparator to save board
space and cost; however, this is not recommended.
20
0
0
2
4
6
8
10
(V)
12
14
16
18
V
SY
Figure 76. Supply Current vs. Supply Voltage (AD8657 as a Comparator)
Figure 74 and Figure 75 show the AD8657 configured as a com-
parator, with 100 kΩ resistors in series with the input pins. Any
unused channels are configured as buffers with the input voltage
kept at the midpoint of the power supplies. The AD8657/AD8659
have input devices that are protected from large differential
input voltages by Diode D1 and Diode D2 (refer to Figure 68).
These diodes consist of substrate PNP bipolar transistors, and
Note that 100 kΩ resistors are used in series with the input of
the op amp. If smaller resistor values are used, the supply current of
the system increases much more. For more details on op amps as
comparators, refer to the AN-849 Application Note Using Op
Amps as Comparators.
Rev. B | Page 21 of 24
AD8657/AD8659
Data Sheet
which the circuit must operate. Using the AD8657 is an excellent
choice due to its low supply current of 34 μA per amplifier over
temperature and supply voltage. The current transmitter controls
the current flowing in the loop, where a zero-scale input signal
is represented by 4 mA of current and a full-scale input signal
is represented by 20 mA. The transmitter also floats from the
control loop power supply, VDD, while signal ground is in the
receiver. The loop current is measured at the load resistor, RL,
at the receiver side.
EMI REJECTION RATIO
Circuit performance is often adversely affected by high frequency
electromagnetic interference (EMI). In the event where signal
strength is low and transmission lines are long, an op amp must
accurately amplify the input signals. However, all op amp pins—
the noninverting input, inverting input, positive supply, negative
supply, and output pins—are susceptible to EMI signals. These
high frequency signals are coupled into an op amp by various
means such as conduction, near field radiation, or far field radi-
ation. For example, wires and PCB traces can act as antennas and
pick up high frequency EMI signals.
At a zero-scale input, a current of VREF/RNULL flows through R.
This creates a current flowing through the sense resistor, ISENSE
determined by the following equation (see Figure 78 for details):
SENSE, MIN = (VREF × R)/(RNULL × RSENSE
,
Precision op amps, such as the AD8657 and AD8659, do not
amplify EMI or RF signals because of their relatively low
bandwidth. However, due to the nonlinearities of the input
devices, op amps can rectify these out-of-band signals. When
these high frequency signals are rectified, they appear as a dc
offset at the output.
I
)
With a full-scale input voltage, current flowing through R is
increased by the full-scale change in VIN/RSPAN. This creates an
increase in the current flowing through the sense resistor.
ISENSE, DELTA = (Full-Scale Change in VIN × R)/(RSPAN × RSENSE
)
To describe the ability of the AD8657/AD8659 to perform as
intended in the presence of an electromagnetic energy, the
electromagnetic interference rejection ratio (EMIRR) of the
noninverting pin is specified in Table 2, Table 3, and Table 4 of
the Specifications section. A mathematical method of
measuring EMIRR is defined as follows:
Therefore
ISENSE, MAX = ISENSE, MIN + ISENSE, DELTA
When R >> RSENSE, the current through the load resistor at the
receiver side is almost equivalent to ISENSE
.
Figure 78 is designed for a full-scale input voltage of 5 V. At 0 V
of input, loop current is 3.5 mA; and at a full scale of 5 V, the
loop current is 21 mA. This allows software calibration to fine
tune the current loop to the 4 mA to 20 mA range.
EMIRR = 20 log (VIN_PEAK/ΔVOS)
140
120
100
80
The AD8657 and ADR125 both consume only 160 µA quiescent
current, making 3.34 mA current available to power additional
signal conditioning circuitry or to power a bridge circuit.
ADR125
V
REF
V
V
OUT
IN
GND
R
NULL
1MΩ
1%
C2
C3
C4
C5
60
10µF 0.1µF
0.1µF 10µF
40
V
V
= 100mV
PEAK
= 2.7V TO 18V
IN
R
SPAN
SY
200kΩ
1/2
AD8657
1%
V
Q1
IN
0V TO 5V
20
10M
V
100M
1G
10G
DD
18V
R4
3.3kΩ
R1
68kΩ
1%
FREQUENCY (Hz)
D1
4mA
TO
20mA
R3
1.2kΩ
Figure 77. EMIRR vs. Frequency
C1
390pF
R
R2
2kΩ
1%
L
4 mA TO 20 mA PROCESS CONTROL CURRENT
LOOP TRANSMITTER—AD8657
100Ω
R
SENSE
100Ω
1%
The 2-wire current transmitters are often used in distributed
control systems and process control applications to transmit
analog signals between sensors and process controllers. Figure 78
shows a 4 mA to 20 mA current loop transmitter.
NOTES
1. R1 + R2 = R´.
Figure 78. 4 mA to 20 mA Current Loop Transmitter
The transmitter powers directly from the control loop power
supply, and the current in the loop carries signal from 4 mA to
20 mA. Thus, 4 mA establishes the baseline current budget within
Rev. B | Page 22 of 24
Data Sheet
AD8657/AD8659
OUTLINE DIMENSIONS
3.20
3.00
2.80
8
1
5
4
5.15
4.90
4.65
3.20
3.00
2.80
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.80
0.55
0.40
0.15
0.05
0.23
0.09
6°
0°
0.40
0.25
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 79. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
2.44
2.34
2.24
3.10
3.00 SQ
0.50 BSC
2.90
8
5
PIN 1 INDEX
EXPOSED
PAD
1.70
1.60
1.50
AREA
0.50
0.40
0.30
4
1
PIN 1
INDICATOR
(R 0.15)
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION
0.80
0.75
0.70
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
SEATING
PLANE
0.30
0.25
0.20
0.203 REF
COMPLIANT TO JEDEC STANDARDS MO-229-WEED
Figure 80. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-8-11)
Dimensions shown in millimeters
Rev. B | Page 23 of 24
AD8657/AD8659
Data Sheet
8.75 (0.3445)
8.55 (0.3366)
8
7
14
1
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
1.27 (0.0500)
BSC
0.50 (0.0197)
0.25 (0.0098)
45°
1.75 (0.0689)
1.35 (0.0531)
0.25 (0.0098)
0.10 (0.0039)
8°
0°
COPLANARITY
0.10
SEATING
PLANE
1.27 (0.0500)
0.40 (0.0157)
0.51 (0.0201)
0.31 (0.0122)
0.25 (0.0098)
0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012-AB
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 81. 14-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-14)
Dimensions shown in millimeters and (inches)
4.10
4.00 SQ
3.90
0.35
0.30
0.25
PIN 1
INDICATOR
PIN 1
INDICATOR
13
16
0.65
BSC
1
4
12
EXPOSED
PAD
2.40
2.35 SQ
2.30
9
8
5
0.50
0.40
0.30
0.25 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGC-3.
Figure 82. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-16-20)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
Package Option
RM-8
RM-8
Branding
A2N
A2N
A2N
A2N
AD8657ARMZ
AD8657ARMZ-R7
AD8657ARMZ-RL
AD8657ACPZ-R7
AD8657ACPZ-RL
AD8659ARZ
AD8659ARZ-R7
AD8659ARZ-RL
AD8659ACPZ-R7
AD8659ACPZ-RL
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Lead Frame Chip Scale Package [LFCSP_WD]
8-Lead Lead Frame Chip Scale Package [LFCSP_WD]
14-Lead Standard Small Outline Package [SOIC_N]
14-Lead Standard Small Outline Package [SOIC_N]
14-Lead Standard Small Outline Package [SOIC_N]
16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
RM-8
CP-8-11
CP-8-11
R-14
R-14
R-14
A2N
CP-16-20
CP-16-20
1 Z = RoHS Compliant Part.
©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08804-0-8/12(B)
Rev. B | Page 24 of 24
相关型号：
©2020 ICPDF网 联系我们和版权申明