AD8698 [ADI]
Dual Precision, Rail-to-Rail Output Operational Amplifier; 双路精密，轨到轨输出运算放大器
| 型号： | AD8698 |
| 厂家： | 
ADI |
| 描述： | Dual Precision, Rail-to-Rail Output Operational Amplifier |
| 文件： | 总20页 (文件大小：309K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual Precision, Rail-to-Rail Output
Operational Amplifier
AD8698
FEATURES
CONNECTION DIAGRAMS
Low offset voltage: 100 µV max
Low offset voltage drift: 2 µV/°C max
Low input bias current: 700 pA max
Low noise: 8 nV/√Hz
High common-mode rejection: 118 dB min
Wide operating temperature: −40°C to +85°C
No phase reversal
8-Lead SOIC
(R-8)
8-Lead MSOP
(RM-8)
OUT A
–IN A
+IN A
V–
1
2
3
4
8
V+
OUT A
–IN A
+IN A
V–
1
2
3
4
8
7
6
5
V+
AD8698
AD8698
7
6
5
OUT B
–IN B
+IN B
OUT B
–IN B
+IN B
TOP VIEW
TOP VIEW
(Not to Scale)
(Not to Scale)
Figure 1.
APPLICATIONS
Photodiode amplifier
Sensors and controls
Multipole filters
Integrator
GENERAL DESCRIPTION
The AD8698 is a high precision, rail-to-rail output, low noise,
low input bias current operational amplifier. Offset voltage is a
respectable 100 µV max and drift over temperature is below
2 µV/°C, eliminating the need for manual offset trimming. The
AD8698 is ideal for high impedance sensors, minimizing offset
errors due to input bias and offset currents.
The rail-to-rail output maximizes dynamic range in a variety of
applications, such as photodiode amplifiers, DAC I/V
amplifiers, filters, and ADC input amplifiers.
The AD8698 dual amplifiers are offered in 8-lead MSOP and
narrow 8-lead SOIC packages. The MSOP version is available
in tape and reel only.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
AD8698
TABLE OF CONTENTS
Specifications .................................................................................... 3
Instrumentation Amplifier ....................................................... 15
Composite Amplifier................................................................. 15
Low Noise Applications ............................................................ 16
Driving ADCs............................................................................. 16
Using the AD8698 in Active Filter Designs ........................... 16
Outline Dimensions....................................................................... 17
Ordering Guide .......................................................................... 17
Absolute Maximum Ratings ........................................................... 5
Thermal Resistance...................................................................... 5
ESD Caution.................................................................................. 5
Typical Performance Characteristics............................................. 6
Applications .................................................................................... 14
Input Overvoltage Protection................................................... 14
Driving Capacitive Loads.......................................................... 14
REVISION HISTORY
4/04—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
AD8698
SPECIFICATIONS
VS = 15 V, VCM = 0 V (@TA = 25oC, unless otherwise noted.)
Table 1.
Parameter
Symbol Conditions
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
VOS
20
100
300
2
µV
µV
−40°C < TA < +85°C
−40°C < TA < +85°C
Offset Voltage Drift
Input Bias Current
0.6
µV/°C
pA
pA
pA
pA
V
∆VOS/∆T
IB
700
1500
700
1500
13.5
−40°C < TA < +85°C
Input Offset Current
IOS
−40°C < TA < +85°C
−40°C < TA < +85°C
VCM = 13.5 V
Input Voltage Range
IVR
−13.5V
118
Common-Mode Rejection Ratio
Large Signal Voltage Gain
Input Capacitance
CMRR
AVO
132
1450
6.5
dB
900
V/mV
pF
RL = 2 kΩ, VO = 13.5 V
CDIFF
CCM
4.6
pF
OUTPUT CHARACTERISTICS
Output Voltage Swing
(Ref. to GND)
(Ref. to GND)
VOH
VOH
VOL
VOL
14.85
14.6
14.93
14.8
V
V
V
V
IL = 1 mA, −40°C < TA < +85°C
IL = 5 mA, −40°C < TA < +85°C
IL = 1 mA, −40°C < TA < +85°C
IL = 5 mA, −40°C < TA < +85°C
−14.93
−14.82
−14.6
−14.5
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current
PSRR
ISY
2.5 V < VS < 15 V
VO = 0 V
114
2.5
132
2.8
dB
mA
mA
V
3.2
3.8
15
−40°C < TA < +85°C
−40°C < TA < +85°C
Supply Voltage
VS
DYNAMIC PERFORMANCE
Slew Rate
SR
0.4
1
V/µs
RL = 2 kΩ
Gain Bandwidth Product
Phase Margin
GBP
ØO
MHz
60
Degrees
NOISE PERFORMANCE
Input Noise Voltage
Input Voltage Noise Density
Input Voltage Noise Density
Current Noise Density
en p-p
en
0.1 Hz < f < 10 Hz
f = 10 Hz
0.6
15
8
µV p-p
nV/√Hz
nV/√Hz
pA/√Hz
en
f = 1 kHz
in
f = 1 kHz
0.2
Rev. 0 | Page 3 of 20
AD8698
VS = 2.5 V, VCM = 0 V (@TA = 25oC, unless otherwise noted.)
Table 2.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
VOS
20
100
µV
300
2
µV
−40°C < TA < +85°C
−40°C < TA < +85°C
Offset Voltage Drift
Input Bias Current
µV/°C
pA
pA
pA
pA
V
∆VOS/∆T
IB
700
1500
700
1500
+1.5
−40°C < TA < +85°C
Input Offset Current
IOS
−40°C < TA < +85°C
−40°C < TA < +85°C
VCM = 13.5 V
Input Voltage Range
IVR
−1.5
105
600
Common-Mode Rejection Ratio
Large Signal Voltage Gain
Input Capacitance
CMRR
AVO
120
1200
6.4
dB
V/mV
pF
RL = 2 kΩ, VO = 13.5 V
CDIFF
CCM
4.6
pF
OUTPUT CHARACTERISTICS
Output Voltage Swing
(Ref. to GND)
(Ref. to GND)
VOH
VOH
VOL
VOL
2.35
2.1
2.44
V
V
V
V
IL = 1 mA, −40°C < TA < +85°C
IL = 5 mA, −40°C < TA < +85°C
IL = 1 mA, −40°C < TA < +85°C
IL = 5 mA, TA = 25°C
2.29
−2.43
−2.15
−2.2
−1.9
−1.6
IL= 5mA, −40°C<TA<+85°C
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current
PSRR
ISY
2.5 V < VS < 15 V
VO = 0 V
114
2.5
132
2.3
dB
mA
mA
V
2.8
3.3
15
−40°C < TA < +85°C
−40°C < TA < +85°C
Supply Voltage
Vs
DYNAMIC PERFORMANCE
Slew Rate
SR
0.4
1
V/µs
RL = 2 kΩ
Gain Bandwidth Product
Phase Margin
GBP
Øo
MHz
60
Degrees
NOISE PERFORMANCE
Input Noise Voltage
Input Voltage Noise Density
Input Voltage Noise Density
Current Noise Density
en p-p
en
0.1 Hz < f < 10Hz
f = 10 Hz
0.6
15
8
µV p-p
nV/√Hz
nV/√Hz
pA/√Hz
en
f =1 kHz
in
f = 1 kHz
0.2
Rev. 0 | Page 4 of 20
AD8698
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 3.
θJA is specified for the worst-case conditions, i.e., θJA is specified
for devices soldered in circuit boards for surface-mount
packages.
Parameter
Rating
15 V
VS
Supply Voltage
Input Voltage
Differential Input Voltage
VS
Table 4. Thermal Resistance
Package Type
Output Short-Circuit Duration
to Gnd
Indefinite
Unit
θJA
210
158
θJC
45
43
Storage Temperature Range
R, RM Packages
Operating Temperature Range
−65°C to +150°C
MSOP-8 (RM)
SOIC-8 (R)
°C/W
°C/W
−40°C to +85°C
−65°C to +150°C
Junction Temperature Range
R, RM Packages
Lead Temperature Range
(Soldering, 60 Sec)
+300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 1000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 5 of 20
AD8698
TYPICAL PERFORMANCE CHARACTERISTICS
100
80
225
180
135
90
80
V
= ±15V
V
= ±15V
S
S
70
60
50
40
30
20
10
0
60
40
45
20
0
0
–45
–20
–40
–90
0
0.2
0.4
0.6
0.8
1.0
1.2
10k
100k
FREQUENCY (Hz)
1M
10M
TCV (µV/°C)
OS
Figure 2. Input Offset Voltage Drift Distribution
Figure 5. Open-Loop Gain and Phase vs. Frequency
80
70
60
50
40
30
20
10
0
50
40
V
= ±15V
V
= ±15V
S
S
A
= 100
= 10
= 1
V
30
20
A
V
10
0
A
V
–10
–20
–100 –80 –60 –40 –20
0
20
(µV)
40
60
80 100
1k
10k
100k
1M
10M
V
FREQUENCY (Hz)
OS
Figure 3. Offset Voltage Distribution
Figure 6. Closed-Loop Gain vs. Frequency
70
60
50
40
30
20
10
0
60
45
30
15
V
= ±15V
V
S
= ±15V
S
A
= 100
V
A
= 10
V
A
V
= 1
0
10
–400 –320 –240 –160 –80
0
80 160 240 320 400
(pA)
100
1k
10k
100k
1M
FREQUENCY (Hz)
I
B
Figure 4. Input Bias Distribution
Figure 7. Output Impedance vs. Frequency
Rev. 0 | Page 6 of 20
AD8698
V
V
C
= ±15V
= 4V p-p
= 1nF
S
IN
0
L
V
V
IN
–200
15
OUT
V
= ±15V
= 200mV p-p
= –100
S
0
V
IN
A
V
TIME (100µs/DIV)
TIME (10µs/DIV)
Figure 8. Large Signal Transient Response
Figure 11. Positive Overvoltage Recovery
V
= ±15V
= 200mV p-p
= 1nF
V
V
A
= ±15V
S
S
V
= 200mV
IN
IN
200
C
= –100
L
V
V
IN
0
0
–15
V
OUT
TIME (100µs/DIV)
TIME (400µs/DIV)
Figure 9. Small Signal Transient Response
Figure 12. Negative Overvoltage Recovery
50
120
100
80
60
40
20
0
V
V
A
= ±15V
= 200mV
= 1
V
= ±15V
S
IN
V
S
30
20
10
0
0
500
1000
1500
2000
2500
3000
1k
10k
100k
1M
10M
CAPACITIVE LOAD (pF)
FREQUENCY (Hz)
Figure 10. Overshoot vs. Load Capacitance
Figure 13. CMRR vs. Frequency
Rev. 0 | Page 7 of 20
AD8698
100
80
60
40
20
100
10
1
V
= ±15V
S
V
= ±15V
S
+PSRR
–PSRR
0
10
0.1
0.1
100
1k
10k
100k
1M
1
10
100
1k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 17. Current Noise Density vs. Frequency
Figure 14. PSRR vs. Frequency
20
10
–I
SC
V
S
= ±15V
V = ±15V
S
0
–10
–20
–30
–40
+I
SC
–60
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
TIME (1s/DIV)
Figure 18. Short-Circuit Current vs. Temperature
Figure 15. Input Voltage Noise
14.96
14.95
14.94
14.93
14.92
14.91
14.90
14.89
14.88
14.87
100
V
= ±15V
S
V
= ±15V
= 1mA
S
I
L
10
V
OH
–V
OL
1
0.1
–60
–40
–20
0
20
40
60
80
100
1
10
100
1k
TEMPERATURE (°C)
FREQUENCY (Hz)
Figure 16. Voltage Noise Density vs. Frequency
Figure 19. Output Swing vs. Temperature
Rev. 0 | Page 8 of 20
AD8698
14.90
14.85
14.80
14.75
14.70
14.65
14.60
140
138
136
134
132
130
V
= ±15V
= 5mA
V = ±15V
S
S
I
L
V
OH
–V
OL
–60
–40
–20
0
20
40
60
80
100
100
100
–60
–40
–20
0
20
40
60
80
100
100
20
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 20. Output Voltage Swing vs. Temperature
Figure 23. PSRR vs. Temperature
30
20
100
50
V
= ±15V
S
V
= ±15V
S
10
0
0
–10
–20
–30
–50
–100
–60
–40
–20
0
20
40
60
80
–60
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 21. ∆ Offset Voltage vs. Temperature
Figure 24. ∆ Input Bias Current vs. Temperature
155
150
145
140
135
130
125
120
6
5
4
3
2
1
0
V
= ±15V
S
V
= ±15V
S
V
OL
V
OH
15
–60
–40
–20
0
20
40
60
80
0
5
10
LOAD CURRENT (mA)
TEMPERATURE (°C)
Figure 22. CMRR vs. Temperature
Figure 25. ∆ Output Voltage Swing from Rails vs. Load Current
Rev. 0 | Page 9 of 20
AD8698
3.5
100
80
225
180
135
90
V
= ±2.5V
S
V
= ±15V
S
3.0
2.5
2.0
1.5
60
40
45
20
0
0
–45
–90
–20
–40
–60
–40
–20
0
20
40
60
80
100
10k
100k
FREQUENCY (Hz)
1M
10M
TEMPERATURE (°C)
Figure 26. Supply Current vs. Temperature
Figure 29. Open-Loop Gain and Phase vs. Frequency
0
–20
60
45
30
15
0
V
= ±15V
V = ±2.5V
S
S
–40
–60
A
= 10
–80
V
A
= 100
V
–100
–120
–140
A
= 1
V
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 27. Channel Separation
Figure 30. Output Impedance vs. Frequency
70
60
50
40
30
20
10
0
V
= ±2.5V
S
V
V
C
= ±2.5V
S
= 2V p-p
= 1nF
IN
L
0
–100 –80 –60 –40 –20
0
20
V)
40
60
80 100
V
(µ
OS
TIME (100µs/DIV)
Figure 28. Offset Voltage Distribution
Figure 31. Large Signal Transient Response
Rev. 0 | Page 10 of 20
AD8698
V
V
A
= ±2.5V
S
V
V
C
= ±2.5V
= 200mV p-p
= 1nF
S
= 200mV p-p
= –100
IN
200
IN
V
L
V
IN
0
0
–2.5
V
OUT
TIME (100
µ
s/DIV)
TIME (4µs/DIV)
Figure 32. Small Signal Transient Response
Figure 35. Negative Overvoltage Recovery
50
40
30
20
10
0
120
100
80
60
40
20
0
V
V
A
= ±2.5V
= 200mV
= 1
V
= ±2.5V
S
IN
V
S
0
500
1000
1500
2000
2500
3000
1k
10k
100k
1M
10M
CAPACITIVE LOAD (pF)
FREQUENCY (Hz)
Figure 33. Overshoot vs. Load Capacitance
Figure 36. CMRR vs. Frequency
100
80
60
40
20
0
V
= ±2.5V
S
0
V
IN
–200
2.5
+PSRR
–PSRR
V
OUT
0
V
V
= ±2.5V
= 200mV p-p
= –100
S
IN
A
V
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
TIME (4µs/DIV)
Figure 37. PSRR vs. Frequency
Figure 34. Positive Overvoltage Recovery
Rev. 0 | Page 11 of 20
AD8698
20
30
20
–I
SC
V
= ±2.5V
S
V
= ±2.5V
S
10
10
0
0
–10
–20
–10
–20
–30
+I
SC
–30
–60
–40
–20
0
20
40
60
80
100
100
100
–60
–40
–20
0
20
40
60
80
100
100
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 38. Short-Circuit Current vs. Temperature
Figure 41. ∆ Offset Voltage vs. Temperature
134
132
130
128
126
124
2.46
2.45
2.44
2.43
2.42
2.41
2.40
2.39
V
= ±2.5V
= 1mA
S
V
= ±2.5V
S
I
L
V
OH
–V
OL
2.38
–60
–40
–20
0
20
40
60
80
–60
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 39. Output Swing vs. Temperature
Figure 42. CMRR vs. Temperature
2.5
2.3
2.1
1.9
1.7
–20
–30
–40
–50
–60
–70
–80
V
= ±2.5V
= 5mA
S
V
= ±2.5V
S
I
L
V
OH
–V
OL
1.5
–60
–40
–20
0
20
40
60
80
–60
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 43. ∆ Input Bias Current vs. Temperature
Figure 40. Output Voltage Swing vs. Temperature
Rev. 0 | Page 12 of 20
AD8698
3.0
2.5
2.0
1.5
1.0
0.5
0
2500
2000
1500
1000
500
V
= ±2.5V
S
V
OL
V
OH
0
0
5
10
15
20
25
30
35
0
5
10
LOAD CURRENT (mA)
15
20
SUPPLY VOLTAGE (V)
Figure 47. Supply Current vs. Supply Voltage
Figure 44. ∆ Output Voltage Swing from Rails vs. Load Current
3.0
2.5
2.0
1.5
1.0
0.5
0
–20
V
= ±2.5V
S
V
= ±2.5V
S
–40
–60
–80
–100
–120
–140
0
–60
–40
–20
0
20
40
60
80
100
1k
10k
100k
1M
10M
TEMPERATURE (°C)
FREQUENCY (Hz)
Figure 45. Supply Current vs. Temperature
Figure 48. Channel Separation
V
V
= ±5V
S
= 11.4V p-p
IN
TIME (400µs/DIV)
Figure 46. No Phase Reversal
Rev. 0 | Page 13 of 20
AD8698
V
= ±15V
= 68nF
= 30Ω
= 5nF
= 1
S
APPLICATIONS
INPUT OVERVOLTAGE PROTECTION
C
R
C
A
L
S
S
V
The AD8698 has internal protective circuitry which allows
voltages at either input to exceed the supply voltage. However,
if voltages applied at either input exceed the supply voltage by
more than 2 V, it is recommended to use a resistor in series
with the inputs to limit the input current and prevent damaging
the device.
The value of the resistor can be calculated from the following
formula:
VIN −VS
≤5mA
TIME (10µs/DIV)
RS +500
Figure 50. Compensated Capacitive Load Drive with Snubber
DRIVING CAPACITIVE LOADS
The snubber network consists of a simple RC network
whose values are determined empirically.
The AD8698 is stable even when driving heavy capacitive
loads in any configuration. Although the AD8698 will safely
drive capacitive loads well over 10 nF, it is recommended to
use external compensation should the amplifier be subjected
to driving a load exceeding 50 nF. This is particularly
important in positive unity gain configurations, the worst
case for stability. Figure 49 shows the output of the AD8698
with a 68 nF load in response to a 400 mV signal at its
positive input; the overshoot is less than 25% without any
external compensation. Using a simple “snubber” network
reduces the overshoot to less than 10% as shown in
Figure 50.
V–
V+
R
S
C
L
+
–
C
S
400mV
Figure 51. Snubber Network
Table 5 provides a few starting values for optimum
compensation.
Table 5. Compensation Values
V
C
A
= ±15V
= 68nF
= 1
S
L
V
CL (nF)
CS (nF)
RS (Ω)
20
47
7
5
3
68
30
100
50
The use of the snubber network does not recover the loss of
bandwidth incurred by the load capacitance. The AD8698
maintains a unity gain bandwidth of 1 MHz with load
capacitances of up to 1 nF.
TIME (10µs/DIV)
Figure 49. Heavy Capacitive Load Drive without Compensation
Rev. 0 | Page 14 of 20
AD8698
10M
1M
R1
1kΩ
R2
10kΩ
V1
V+
V–
R3
9kΩ
1/2 AD8698
R4
2kΩ
V+
V–
100k
10k
1k
OP184
R5
10kΩ
R3
9kΩ
V–
V+
R1
9.8kΩ
R7
V2
400Ω
1/2 AD8698
1
10
100
LOAD CAPACITANCE (nF)
Figure 53. Three Op Amp In-Amp
Figure 52. Unity Gain Bandwidth vs. Load Capacitance
COMPOSITE AMPLIFIER
Figure 52 shows the unity gain bandwidth as a function of load
capacitance.
The dc accuracy of the AD8698 and the ac performance of the
OP184 are combined in the circuit shown in Figure 54. The
composite amplifier provides a higher bandwidth, a lower offset
voltage, and a higher loop, thereby reducing the gain error
substantially.
INSTRUMENTATION AMPLIFIER
Instrumentation amplifiers are used in applications requiring
precision, accuracy, and high CMRR. One popular application
is signal conditioning in process control, test automation, and
measurement instrumentation, where the amplifier is used to
amplify small signals.
The circuit shown exhibits a total output rms noise of less than
500 µV, corresponding to less than 3 mV of peak-to-peak noise
over approximately a 3 MHz bandwidth. Cf is used to minimize
peaking.
The triple op amp implementation uses the AD8698 at the
front end with the OP184 for optimum accuracy.
The circuit has an inverting gain of 10. In applications with
higher closed-loop gains, Cf is necessary to maintain a
sufficient phase margin and ensure stability. This results in a
narrower closed-loop bandwidth.
The circuit in Figure 53 enjoys a high overall gain, excellent dc
performance, high CMRR, as well as the benefit of an output
that swings to the supplies.
R2
10kΩ
The CMRR of the in-amp will be limited by the choice of
resistor tolerance. R5 is an optional potentiometer that can be
used to calibrate the circuit for maximum gain. R7 can be
trimmed for optimum CMRR.
R1
1kΩ
Cf
20pF
V
IN
V–
V+
The output voltage is given by:
V–
V+
OP184
2R3 R2
1/2 AD8698
⎛
⎝
⎞⎛
⎟⎜
⎠⎝
⎞
⎟
⎠
VO =VIN 1+
⎜
R4
R1
Figure 54. Composite Amplifier Circuit
Rev. 0 | Page 15 of 20
AD8698
If a higher gain is desired, the corner frequency should be
chosen accordingly. For example, if the amplifier is configured
with a gain of 10, the corner frequency of the filter should not
be more than 10 kHz.
LOW NOISE APPLICATIONS
In some applications, it is critical to minimize the noise, and
although the AD8698 has a low noise of typically 8 nV/√Hz at
1 kHz, paralleling the two amplifiers within the same package
reduces the total noise referred to the input to approximately
5.5 nV/√Hz. This simple technique is depicted in Figure 55.
An example of an active filter is the Sallen Key. This topology
gives the user the flexibility of implementing a low-pass or a
high-pass filter by simply interchanging the resistors and the
capacitors.
V
IN
V+
V–
R3
100Ω
In the high-pass filter of Figure 56, the damping factor Q is set
to 1/√2 for a maximally flat response (Butterworth).
R1
1kΩ
R2
10kΩ
The gain is unity and the bandwidth is 10 kHz with the values
shown.
V
OUT
C1
R1
1nF
11kΩ
V–
V+
V
IN
R5
100Ω
C2
1nF
R3
1kΩ
V+
V–
R4
10kΩ
R2
22kΩ
Figure 55. Paralleling Amplifiers
DRIVING ADCs
Figure 56. Two Pole High-Pass Filter
The AD8698 can drive extremely heavy capacitive loads
C1
2nF
R1
11kΩ
without any compensation. Sometimes capacitors are placed at
the output of the amplifier to absorb transient currents while
the op amp is interfaced with the ADC. Most op amps need a
small resistor with the output to isolate the load capacitance.
V
IN
R2
11kΩ
V+
This results in a loss of bandwidth and slows the amplifier
down substantially. However, the AD8698 maintains a unity
gain bandwidth of 1 MHz with loads of up to 1 nF, as shown in
Figure 52.
V–
C2
1nF
Figure 57. Two Pole Low-Pass Filter
USING THE AD8698 IN ACTIVE FILTER DESIGNS
The circuit of Figure 57 has a bandwidth of 10 kHz and a
maximally flat response. In this case, the damping factor is
controlled by the ratio of the capacitors and the gain is unity.
The AD8698 is recommended for unity gain filter designs with
a corner frequency of up to 100 kHz, one tenth of the op amp’s
unity gain bandwidth.
Rev. 0 | Page 16 of 20
AD8698
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2440)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
0.50 (0.0196)
0.25 (0.0099)
× 45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0.51 (0.0201)
0.31 (0.0122)
0° 1.27 (0.0500)
COPLANARITY
0.10
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 58. 8-Lead Small Outline IC [SOIC] (R-8)—Dimensions shown in millimeters
3.00
BSC
8
5
4
4.90
BSC
3.00
BSC
PIN 1
0.65 BSC
1.10 MAX
0.15
0.00
0.80
0.60
0.40
8°
0°
0.38
0.22
0.23
0.08
COPLANARITY
0.10
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-187AA
Figure 59. 8-Lead Small Outline IC [SOIC] (RM-8)—Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Package
Package Description
Package Option
Branding
AD8698ARM-R2
AD8698ARM-REEL
AD8698AR
AD8698AR-REEL
AD8698AR-REEL7
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
MSOP
MSOP
SOIC
SOIC
SOIC
RM-8
RM-8
R-8
R-8
R-8
A02
A02
Rev. 0 | Page 17 of 20
AD8698
NOTES
Rev. 0 | Page 18 of 20
AD8698
NOTES
Rev. 0 | Page 19 of 20
AD8698
NOTES
©
2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04807-0-4/04(0)
Rev. 0 | Page 20 of 20
相关型号：
AD8698ARMZ-R2
IC DUAL OP-AMP, 300 uV OFFSET-MAX, 1 MHz BAND WIDTH, PDSO8, MO-187AA, MSOP-8, Operational Amplifier
ADI
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