AD8801AR [ADI]
Octal 8-Bit TrimDAC with Power Shutdown; 八路8位TrimDAC与功耗关断模式型号: | AD8801AR |
厂家: | ADI |
描述: | Octal 8-Bit TrimDAC with Power Shutdown |
文件: | 总16页 (文件大小:215K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Octal 8-Bit TrimDAC
with Power Shutdown
a
AD8801/AD8803
FEATURES
FUNCTIO NAL BLO CK D IAGRAM
Low Cost
(D ACs 2–7 O m itted for Clar ity)
Replaces Eight Potentiom eters
Eight Individually Program m able Outputs
Three-Wire Serial Input
Pow er Shutdow n ≤ 25 W Including IDD and IREF
Midscale Preset, AD8801
V
REFH
V
REFL
AD8801/AD8803
V
REFH
8
8-BIT
V
V
O1
DAC 1
DD
OUT
LATCH
V
REFL
Separate VREFL Range Setting, AD8803
+3 V to +5 V Single Supply Operation
RS
CK
GND
8
1
DAC
SELECT
.
.
.
.
.
.
APPLICATIONS
Autom atic Adjustm ent
Trim m er Potentiom eter Replacem ent
Video and Audio Equipm ent Gain and Offset Adjustm ent
Portable and Battery Operated Equipm ent
8
ADDRESS
3
11-BIT
SERIAL
LATCH
D
8
SDI
RS
CK
CLK
V
REFH
8-BIT
LATCH
8
8
CS
V
O8
DAC 8 OUT
GENERAL D ESCRIP TIO N
V
REFL
8
CK RS
T he AD8801/AD8803 provides eight digitally controlled dc
voltage outputs. This potentiometer divider TrimDAC® allows
replacement of the mechanical trimmer function in new designs.
The AD8801/AD8803 is ideal for dc voltage adjustment
applications.
RS
SHDN
Easily programmed by serial interfaced microcontroller ports,
the AD8801 with its midscale preset is ideal for potentiometer
replacement where adjustments start at a nominal value. Appli-
cations such as gain control of video amplifiers, voltage con-
trolled frequencies and bandwidths in video equipment,
geometric correction and automatic adjustment in CRT com-
puter graphic displays are a few of the many applications ideally
suited for these parts. T he AD8803 provides independent con-
trol of both the top and bottom end of the potentiometer divider
allowing a separate zero-scale voltage setting determined by the
VREFL pin. T his is helpful for maximizing the resolution of de-
vices with a limited allowable voltage control range.
Internally the AD8801/AD8803 contain eight voltage output
digital-to-analog converters, sharing a common reference volt-
age input.
Each DAC has its own DAC register that holds its output state.
T hese DAC registers are updated from an internal serial-to-par-
allel shift register that is loaded from a standard three-wire serial
input digital interface. Eleven data bits make up the data word
clocked into the serial input register. T his data word is decoded
where the first 3 bits determine the address of the DAC register
to be loaded with the last 8 bits of data. T he AD8801/AD8803
consumes only 5 µA from 5 V power supplies. In addition, in
shutdown mode reference input current consumption is also re-
duced to 5 µA while saving the DAC latch settings for use after
return to normal operation.
T he AD8801/AD8803 is available in 16-pin plastic DIP and the
1.5 mm height SO-16 surface mount packages.
See the AD 8802/AD 8804 for a twelve channel ver sion of this pr oduct.
Tr im D AC is a r egister ed tr adem ar k of Analog D evices, Inc.
REV. A
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norw ood. MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
(V = +3 V ؎ 10% or +5 V ؎ 10%, VREFH = +V , VREFL = 0 V, –40؇C
DD
DD
≤ T ≤ +85؇C unless otherwise noted)
A
AD8801/AD8803–SPECIFICATIONS
P aram eter
Sym bol
Conditions
Min
Typ1
Max
Units
ST AT IC ACCURACY
Specifications Apply to All DACs
Resolution
Integral Nonlinearity Error
Differential Nonlinearity
Full-Scale Error
Zero-Code Error
DAC Output Resistance
Output Resistance Match
N
8
–1.5
–1
–4
–0.5
3
Bits
LSB
LSB
LSB
LSB
kΩ
INL
DNL
GFSE
VZSE
ROUT
∆R/RO
±1/2
±1/4
–2.8
±0.1
5
+1.5
+1
+0.5
+0.5
8
Guaranteed Monotonic
1
%
REFERENCE INPUT
Voltage Range2
VREFH
VREFL
RREFH
CREF0
CREF1
0
0
VDD
VDD
V
V
kΩ
pF
pF
Pin Available on AD8803 Only
Digital Inputs = 55H, VREFH = VDD
Digital Inputs All Zeros
Input Resistance
2
25
25
Reference Input Capacitance3
Digital Inputs All Ones
DIGIT AL INPUT S
Logic High
Logic Low
Logic High
Logic Low
VIH
VIL
VIH
VIL
IIL
VDD = +5 V
VDD = +5 V
VDD = +3 V
VDD = +3 V
2.4
2.1
V
V
V
V
µA
pF
0.8
0.6
±1
Input Current
VIN = 0 V or +5 V
Input Capacitance3
CIL
5
POWER SUPPLIES4
Power Supply Range
Supply Current (CMOS)
Supply Current (T T L)
Shutdown Current
VDD Range
IDD
IDD
2.7
5.5
5
4
V
µA
mA
µA
VIH = VDD or VIL = 0 V
VIH = 2.4 V or VIL = 0.8 V, VDD= +5.5 V
SHDN = 0
0.01
1
0.01
IREFH
5
Power Dissipation
Power Supply Sensitivity
Power Supply Sensitivity
PDISS
PSRR
PSRR
VIH = VDD or VIL = 0 V, VDD = +5.5 V
VDD = 5 V ± 10%, VREFH = +4.5 V
VDD = 3 V ± 10%, VREFH = +2.7 V
27.5
0.001 0.002
0.01
µW
%/%
%/%
DYNAMIC PERFORMANCE3
VOUT Settling Time (Positive or Negative) tS
±1/2 LSB Error Band
See Note 5, f = 100 kHz
0.6
50
µs
dB
Crosstalk
CT
SWIT CHING CHARACT ERIST ICS3, 6
Input Clock Pulse Width
Data Setup T ime
Data Hold T ime
CS Setup T ime
CS High Pulse Width
Reset Pulse Width
CLK Rise to CS Rise Hold T ime
CS Rise to Next Rising Clock
tCH, tCL
tDS
tDH
tCSS
tCSW
tRS
tCSH
tCS1
Clock Level High or Low
15
5
5
10
10
60
15
10
ns
ns
ns
ns
ns
ns
ns
ns
NOT ES
1T ypical values represent average readings measured at +25 °C.
2VREFH can be any value between GND and VDD, for the AD8803 VREFL can be any value between GND and VDD
.
3Guaranteed by design and not subject to production test.
4Digital Input voltages VIN = 0 V or VDD for CMOS condition. DAC outputs unloaded. PDISS is calculated from (IDD × VDD ).
5Measured at a VOUT pin where an adjacent VOUT pin is making a full-scale voltage change.
6See timing diagram for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of VDD) and timed from a voltage
level of 1.6 V.
Specifications subject to change without notice.
–2–
REV. A
AD8801/AD8803
O RD ERING GUID E
ABSO LUTE MAXIMUM RATINGS
(T A = +25°C, unless otherwise noted)
P ackage
D escription O ption
P ackage
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3, +8 V
VREFX to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, VDD
Outputs (Ox) to GND . . . . . . . . . . . . . . . . . . . . . . . . 0 V, VDD
Digital Input Voltage to GND . . . . . . . . . . . . . . . . . . 0 V, VDD
Operating T emperature Range . . . . . . . . . . . . . –40°C to +85°C
Maximum Junction T emperature (TJ MAX) . . . . . . . . +150°C
Storage T emperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead T emperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C
Package Power Dissipation . . . . . . . . . . . . . (TJ MAX – TA)/θJA
T hermal Resistance θJA,
Model
FTN
Tem perature
AD8801AN
AD8801AR
AD8803AN
AD8803AR
RS
RS
–40°C to +85°C PDIP-16
–40°C to +85°C SO-16
REFL –40°C to +85°C PDIP-16
REFL –40°C to +85°C SO-16
N-16
R-16A
N-16
R-16A
AD 8803 P IN D ESCRIP TIO NS
P in Nam e D escription
SOIC (SO-16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
P-DIP (N-16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57°C/W
1
2
3
4
5
6
VREFH Common High-Side DAC Reference Input
O1
O2
O3
O4
DAC Output # 1, Addr = 0002
DAC Output # 2, Addr = 0012
DAC Output # 3, Addr = 0102
DAC Output # 4, Addr = 0112
AD 8801 P IN D ESCRIP TIO NS
P in Nam e D escription
1
2
3
4
5
6
VREFH Common DAC Reference Input
O1
O2
O3
O4
DAC Output # 1, Addr = 0002
DAC Output # 2, Addr = 0012
DAC Output # 3, Addr = 0102
DAC Output # 4, Addr = 0112
SHDN Reference inputs open circuit, active low, all
DAC outputs open circuit. DAC latch settings
maintained.
7
CS
Chip Select Input, active low. When CS returns
high, data in the serial input register is decoded
based on the address bits and loaded into the tar-
get DAC register.
SHDN Reference input open circuit, active low, all
DAC outputs open circuit. DAC latch settings
maintained.
8
9
GND
VREFL
Ground
7
CS
Chip Select Input, active low. When CS returns
high, data in the serial input register is decoded
based on the address bits and loaded into the tar-
get DAC register.
Common Low-Side DAC Reference Input
Serial Clock Input, Positive Edge T riggered
Serial Data Input
10 CLK
11 SDI
12 O5
13 O6
14 O7
15 O8
16 VDD
8
9
GND Ground
CLK Serial Clock Input, Positive Edge T riggered
DAC Output # 5, Addr = 1002
DAC Output # 6, Addr = 1012
DAC Output # 7, Addr = 1102
DAC Output # 8, Addr = 1112
10 SDI
11 O5
12 O6
13 O7
14 O8
15 RS
Serial Data Input
DAC Output # 5, Addr = 1002
DAC Output # 6, Addr = 1012
DAC Output # 7, Addr = 1102
DAC Output # 8, Addr = 1112
Positive power supply, specified for operation at
both +3 V and +5 V.
Asynchronous preset to midscale output setting,
active low. Loads all DAC latches with 80H.
P IN CO NFIGURATIO NS
16 VDD
Positive power supply, specified for operation at
both +3 V and +5 V.
16
15
16
15
1
2
1
2
V
V
V
V
DD
REFH
DD
REFH
O1
O1
O8
O7
O6
RS
3
4
5
6
7
8
14
13
3
4
5
6
7
8
14
13
O2
O3
O4
O8
O2
O3
O4
AD8801
TOP VIEW
(Not to Scale)
AD8803
TOP VIEW
(Not to Scale)
O7
12 O6
12 O5
11
10
9
11
10
9
O5
SDI
SHDN
SHDN
SDI
CLK
CLK
CS
CS
GND
GND
V
REFL
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although these devices feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
–3–
AD8801/AD8803
OCTAL 8-BIT TRIMDAC, WITH SHUTDOWN
following address assignments for the ADDR decode which de-
termines the location of DAC register receiving the serial regis-
ter data in bits B7 through B0:
1
SDI
A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
DAC # = A2 × 4 + A1 × 2 + A0 + 1
CLK
DAC outputs can be changed one at a time in random se-
quence. The fast serial-data loading of 33 MHz makes it possible
to load all eight DACs in as little time as 3 µs (12 × 8 × 30 ns).
T he exact timing requirements are shown in Figure 2.
1
DAC REGISTER LOAD
CS
0
+5V
V
OUT
0V
T he AD8801 offers a midscale preset activated by the RS pin
simplifying initial setting conditions at first power up. T he
AD8803 has both a VREFH and a VREFL pin to establish indepen-
dent positive full-scale and zero-scale settings to optimize reso-
lution. Both parts offer a power shutdown SHDN that places
the DAC structure in a zero power consumption state resulting
in only leakage currents being consumed from the power supply,
VREF inputs, and all 8 outputs. In shutdown mode the DACx
latch settings are maintained. When returning to operational
mode from power shutdown the DAC outputs return to their
previous voltage settings.
Figure 2a. Tim ing Diagram
DETAIL SERIAL DATA INPUT TIMING (RS = "1")
SDI
(DATA
IN)
1
0
A
X
OR D
A OR D
X X
X
tDS
tDH
tCH
tCS1
1
0
CLK
tCL
tCSH
tCSS
1
0
TO OTHER DACS
tCSW
tS
CS
P CH
V
REFH
+5V
0V
±1 LSB
N CH
MSB
V
OUT
O
X
2R
±1 LSB ERROR BAND
R
R
Figure 2b. Detail Tim ing Diagram
DAC
REGISTER
RESET TIMING
D7
2R
tRS
1
D6
D0
RS
0
tS
. .
. .
. .
.
.
.
+5V
V
OUT
±1 LSB
2.5V
±1 LSB ERROR BAND
2R
2R
LSB
Figure 2c. Reset Tim ing Diagram
GND
Table I. Serial-D ata Word Form at
D ATA
V
REFL
AD D R
Figure 3. AD8801/AD8803 Equivalent Trim DAC Circuit
B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
P RO GRAMMING TH E O UTP UT VO LTAGE
MSB
LSB MSB
LSB
T he output voltage range is determined by the external refer-
ence connected to VREFH and VREFL pins. See Figure 3 for a
simplified diagram of the equivalent DAC circuit. In the case of
the AD8801, its VREFL is internally connected to GND and
therefore cannot be offset. VREFH can be tied to VDD and VREFL
can be tied to GND establishing a basic rail-to-rail voltage out-
put programming range. Other output ranges are established by
the use of different external voltage references. T he general
transfer equation that determines the programmed output
voltage is:
210 29
28 27
26
25
24
23
22
21
20
O P ERATIO N
T he AD8801/AD8803 provides eight channels of programmable
voltage output adjustment capability. Changing the programmed
output voltage of each T rimDAC is accomplished by clocking in
an 11-bit serial data word into the SDI (Serial Data Input) pin.
T he format of this data word is three address bits, MSB first,
followed by eight data bits, MSB first. T able I provides the se-
rial register data word format. T he AD8801/AD8803 has the
VO (Dx) = (Dx)/256 × (VREFH – VREFL) + VREFL
(1)
where Dx is the data contained in the 8-bit DACx latch.
–4–
REV. A
AD8801/AD8803
For example, when VREFH = +5 V and VREFL = 0 V the follow-
ing output voltages will be generated for the following codes:
D IGITAL INTERFACING
T he AD8801/AD8803 contains a standard three-wire serial in-
put control interface. T he three inputs are clock (CLK), CS and
serial data input (SDI). T he positive-edge sensitive CLK input
requires clean transitions to avoid clocking incorrect data into
the serial input register. Standard logic families work well. If
mechanical switches are used for product evaluation, they
should be debounced by a flip-flop or other suitable means. Fig-
ure 4 block diagram shows more detail of the internal digital cir-
cuitry. When CS is taken active low, the clock can load data into
the serial register on each positive clock edge, see T able II.
D
VO X
O utput State
(VREFH = +5 V, VREFL = 0 V)
255
128
1
4.98 V
2.50 V
0.02 V
0.00 V
Full-Scale
Half-Scale (Midscale Reset Value)
1 LSB
Zero-Scale
0
REFERENCE INP UTS (VREFH , VREFL
)
T he reference input pins set the output voltage range of all eight
DACs. In the case of the AD8801 only the VREFH pin is avail-
able to establish a user designed full-scale output voltage. T he
external reference voltage can be any value between 0 and VDD
but must not exceed the VDD supply voltage. In the case of the
AD8803, which has access to the VREFL which establishes the
zero-scale output voltage, any voltage can be applied between
0 V and VDD. VREFL can be smaller or larger in voltage than
VREFH since the DAC design uses fully bidirectional switches as
shown in Figure 3. T he input resistance to the DAC has a code
dependent variation that has a nominal worst case measured at
55H, which is approximately 2 kΩ. When VREFH is greater than
Table II. Input Logic Control Truth Table
CS
CLK
Register Activity
1
0
X
P
No effect.
Shifts Serial Register one bit loading the
next bit in from the SDI pin.
P
X
Data is transferred from the serial register
to the decoded DAC register. See Figure 5.
NOT E: P = positive edge, X = don’t care.
T he data setup and data hold times in the specification table
determine the data valid time requirements. T he last 11 bits of
the data word entered into the serial register are held when CS
returns high. At the same time CS goes high it gates the address
decoder which enables one of the eight positive edge triggered
DAC registers, see Figure 5 detail.
VREFL, the REFL reference must be able to sink current out of
the DAC ladder, while the REFH reference is sourcing current
into the DAC ladder. T he DAC design minimizes reference
glitch current maintaining minimum interference between DAC
channels during code changes.
DAC 1
D AC O UTP UTS (O 1–O 8)
DAC 2
CS
.
ADDR
.
T he eight DAC outputs present a constant output resistance of
approximately 5 kΩ independent of code setting. T he distribu-
tion of ROUT from DAC to DAC typically matches within ±1%.
However, device to device matching is process lot dependent
having a ±20% variation. T he change in ROUT with temperature
has a 500 ppm/°C temperature coefficient. During power shut-
down all eight outputs are open circuited.
DECODE
.
DAC 8
SERIAL
CLK
REGISTER
SDI
Figure 5. Equivalent Control Logic
The target DAC register is loaded with the last eight bits of the se-
rial data word completing one DAC update. Eight separate 11-bit
data words must be clocked in to change all eight output settings.
CS
AD8801/AD8803
V
DD
V
REFH
All digital inputs are protected with a series input resistor and
parallel Zener ESD structure shown in Figure 6. T his applies to
digital input pins CS, SDI, RS, SHDN, CLK.
CLK
DAC
D7
D0
O1
O2
O3
1
DAC
REG
#1
EN
ADDR
DEC
D10
D9
D8
100Ω
R
O4
O5
O6
O7
O8
LOGIC
D7
. . .
. . .
. . .
..
..
..
SER
REG
.
.
.
D7
D0
Figure 6. Equivalent ESD Protection Circuit
SDI
D
D0
DAC
8
DAC
REG
#8
Digital inputs can be driven by voltages exceeding the AD8801/
AD8803 VDD value. T his allows 5 V logic to interface directly to
the part when it is operated at 3 V.
8
R
SHDN
V
REFL
GND
RS
(AD8801 ONLY) (AD8803 ONLY)
Figure 4. Block Diagram
REV. A
–5–
AD8801/AD8803–Typical Performance Characteristics
1
0.75
0.5
200
150
100
50
V
V
V
= +5V
DD
V
V
V
= +5V
DD
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
= +2V
= 0V
REFH
REFL
= +5V
= 0V
REFH
REFL
ALL OTHER DACS SET
TO ZERO SCALE
T
= +25°C
A
0.25
0
–0.25
–0.5
–0.75
–1
0
0
32
64
96
128
160
192
224
256
0
32
64
96
128
160
192
224
256
CODE – Decimal
CODE – Decimal
Figure 7. INL vs. Code
Figure 10. Input Reference Current vs. Code
1
0.75
0.5
10k
V
= +5V
= +5V
V
V
= +5.5V
= 0V
DD
DD
V
REFH
V
REFL
REF
T
= –40°C, +25°C, +85°C
= 0V
A
1k
0.25
0
V
V
= +5.5V
DD
100
= +5.5V
REF
–0.25
–0.5
–0.75
–1
10
0
0
64
128
192
256
–55
–35
–15
5
25
45
65
85
105
125
CODE – Decimal
TEMPERATURE – °C
Figure 11. Shutdown Current vs. Tem perature
Figure 8. Differential Nonlinearity Error vs. Code
100k
1200
V
DD
= +5.5V
V
V
V
= +4.5V
= +4.5V
1080
DD
LOGIC = +2.4V
ALL DIGITAL PINS
TIED TOGETHER
10k
1k
REF
960
840
= 0V
REFL
T
= +25°C
A
SS = 2446 PCS
100
10
720
600
480
260
240
120
0
V
DD
= +5.5V
1
LOGIC = +5.5V
ALL DIGITAL PINS
TIED TOGETHER
0.1
0.01
0.001
–55
–35
–15
5
25
45
65
85
105
125
–3.4 –3.3 –3.2 –3.1 –3.0 –2.9 –2.8 –2.7 –2.6 –2.5
TOTAL UNADJUSTED ERROR – LSB
TEMPERATURE – °C
Figure 12. Supply Current vs. Tem perature
Figure 9. Total Unadjusted Error Histogram
REV. A
–6–
AD8801/AD8803
100
10
T
= +25°C
A
ALL DIGITAL INPUTS
TIED TOGETHER
OUTPUT1: OO → FF
H
H
V
V
= +5V
DD
100
90
= +2V
REF
f = 500kHz
1.0
V
DD
= +5V
0.1
10
0.01
0.001
0.0001
0%
V
= +3V
DD
TIME – 0.2µs/DIV
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
LOGIC INPUT VOLTAGE – Volts
Figure 13. Supply Current vs. Logic Input Voltage
Figure 16. Adjacent Channel Clock Feedthrough
80
OUTPUT1: 7F → 80
H
H
V
V
= +5V ±0.5V
V
V
= +5V
= +2V
DD
P
DD
60
100
90
= +2V
REFH
REF
CODE = 80
H
OUT1
10mV/DIV
T
= +25°C
A
40
20
CS
5V/DIV
10
0%
TIME – 0.2µs/DIV
0
10
100
1k
FREQUENCY – Hz
10k
100k
Figure 17. Midscale Transition
Figure 14. Power Supply Rejection vs. Frequency
0.01
0.005
0
V
V
= +4.5V
DD
V
V
= +5V
DD
= +4.5V
REF
= +2V
REF
SS = 162 PCS
= 0V
100
90
V
REFL
2V
0V
OUT1
10
5V
0V
0%
CS
–0.005
–0.01
TIME – 1µs/DIV
0
150
300
450
600
HOURS OF OPERATION AT 150°C
Figure 18. Zero-Scale Error Accelerated by Burn-In
Figure 15. Large-Signal Settling Tim e
REV. A
–7–
AD8801/AD8803
1.0
0.5
0.04
V
V
= +4.5V
DD
V
V
= +4.5V
DD
= +4.5V
REF
= +4.5V
REF
CODE = 55
H
SS = 162 PCS
x + 2σ
SS = 162 PCS
0.02
0
x + 2σ
x
x
0
x – 2σ
x – 2σ
–0.5
–1.0
–0.02
–0.04
0
150
300
450
600
0
150
300
450
600
HOURS OF OPERATION AT 150°C
HOURS OF OPERATION AT 150°C
Figure 20. REF Input Resistance Accelerated by Burn-In
Figure 19. Full-Scale Error Accelerated by Burn-In
+5V
AP P LICATIO NS
Supply Bypassing
Precision analog products, such as the AD8801/AD8803, re-
quire a well filtered power source. Since the AD8801/AD8803
operate from a single +3 V to +5 V supply, it seems convenient
to simply tap into the digital logic power supply. Unfortunately,
the logic supply is often a switch-mode design, which generates
noise in the 20 kHz to 1 MHz range. In addition, fast logic gates
can generate glitches hundred of millivolts in amplitude due to
wiring resistances and inductances.
V
DD
AD8801/
AD8803
+
10µF
0.1µF
DGND
If possible, the AD8801/AD8803 should be powered directly
from the system power supply. T his arrangement, shown in Fig-
ure 21, will isolate the analog section from the logic switching
transients. Even if a separate power supply trace is not available,
however, generous supply bypassing will reduce supply-line in-
duced errors. Local supply bypassing consisting of a 10 µF tan-
talum electrolytic in parallel with a 0.1 µF ceramic capacitor is
recommended (Figure 22).
Figure 22. Recom m ended Supply Bypassing for the
AD8801/AD8803
Buffer ing the AD 8801/AD 8803 O utput
In many cases, the nominal 5 kΩ output impedance of the
AD8801/AD8803 is sufficient to drive succeeding circuitry. If a
lower output impedance is required, an external amplifier can
be added. Several examples are shown in Figure 23. One ampli-
fier of an OP291 is used as a simple buffer to reduce the output
resistance of DAC A. T he OP291 was chosen primarily for its
rail-to-rail input and output operation, but it also offers opera-
tion to less than 3 V, low offset voltage, and low supply current.
TTL/CMOS
LOGIC
CIRCUITS
+
AD8801/
AD8803
10µF
TANT
0.1µF
T he next two DACs, B and C, are configured in a summing ar-
rangement where DAC C provides the coarse output voltage
setting and DAC B can be used for fine adjustment. T he inser-
tion of R1 in series with DAC B attenuates its contribution to
the voltage sum node at the DAC C output.
+5V
POWER SUPPLY
Figure 21. Use Separate Traces to Reduce Power Supply
Noise
–8–
REV. A
AD8801/AD8803
+5V
Micr ocom puter Inter faces
T he AD8801/AD8803 serial data input provides an easy inter-
face to a variety of single-chip microcomputers (µCs). Many µCs
have a built-in serial data capability that can be used for com-
municating with the DAC. In cases where no serial port is pro-
vided, or it is being used for some other purpose (such as an
RS-232 communications interface), the AD8801/AD8803 can
easily be addressed in software.
V
V
DD
REFH
OP291
V
H
SIMPLE BUFFER
0V TO 5V
V
L
V
H
V
L
R1
Eleven data bits are required to load a value into the AD8801/
AD8803 (3 bits for the DAC address and 8 bits for the DAC
value). If more than 11 bits are transmitted before the Chip Se-
lect input goes high, the extra (i.e., the most-significant) bits are
ignored. T his feature is valuable because most µCs only transmit
data in 8-bit increments. T hus, the µC will send 16 bits to the
DAC instead of 11 bits. T he AD8801/AD8803 will only re-
spond to the last 11 bits clocked into the SDI input, however, so
the serial data interface is not affected.
100kΩ
V
SUMMER CIRCUIT
WITH FINE TRIM
ADJUSTMENT
H
V
L
AD8801/
AD8803
V
REFL GND
DIGITAL INTERFACING
OMITTED FOR CLARITY
Figure 23. Buffering the AD8801/AD8803 Output
An 8051 µC Inter face
Incr easing O utput Voltage Swing
A typical interface between the AD8801/AD8803 and an 8051
µC is shown in Figure 25. T his interface uses the 8051’s internal
serial port. T he serial port is programmed for Mode 0 opera-
tion, which functions as a simple 8-bit shift register. T he 8051’s
Port3.0 pin functions as the serial data output, while Port3.1
serves as the serial clock.
An external amplifier can also be used to extend the output volt-
age swing beyond the power supply rails of the AD8801/AD8803.
T his technique permits an easy digital interface for the DAC,
while expanding the output swing to take advantage of higher
voltage external power supplies. For example, DAC A of Fig-
ure 24 is configured to swing from –5 V to +5 V. T he actual
output voltage is given by:
+5V
+
0.1µF
10µF
RF
RS
D
VOUT = 1 +
×
× 5 V – 5 V
(
)
256
V
V
DD REFH
AD8801
Where D is the DAC input value (i.e., 0 to 255). T his circuit
can be combined with the “fine/coarse” circuit of Figure 23 if,
for example, a very accurate adjustment around 0 V is desired.
RxD P3.0
SDI
SBUF
SERIAL DATA SHIFT REGISTER
SHIFT CLOCK
O1
O2
O3
O4
O5
O6
O7
O8
TxD
P3.1
P1.3
P1.2
P1.1
SCLK
RESET
SHDN
CS
8051 µC
+5V
R
R
F
S
100kΩ
100kΩ
+5V
V
REFH
V
DD
1.3 1.2 1.1
PORT 1
–5V TO +4.98V
GND
A
OP191
–5V
AD8801/
AD8803
Figure 25. Interfacing the 8051 µC to an AD8801/AD8803,
Using the Serial Port
+12V
OP193
B
When data is written to the Serial Buffer Register (SBUF, at
Special Function Register location 99H), the data is automati-
cally converted to serial format and clocked out via Port3.0 and
Port3.1. After 8 bits have been transmitted, the T ransmit Inter-
rupt flag (SCON.1) is set and the next 8 bits can be transmitted.
0V TO +10V
V
REFL
GND
100kΩ
100kΩ
T he AD8801 and AD8803 require the Chip Select to go low at
the beginning of the serial data transfer. In addition, the SCLK
input must be high when the Chip Select input goes high at the
end of the transfer. T he 8051’s serial clock meets this require-
ment, since Port3.1 both begins and ends the serial data in the
high state.
Figure 24. Increasing Output Voltage Swing
DAC B of Figure 24 is in a noninverting gain of two configura-
tion, which increases the available output swing to +10 V. T he
feedback resistors can be adjusted to provide any scaling of the
output voltage, within the limits of the external op amp power
supplies.
Softwar e for the 8051 Inter face
A software routine for the AD8801/AD8803 to 8051 interface is
shown in Listing 1. T he routine transfers the 8-bit data stored at
data memory location DAC_VALUE to the AD8801/AD8803
DAC addressed by the contents of location DAC_ADDR.
REV. A
–9–
AD8801/AD8803
;
; T his subroutine loads an AD8801/AD8803 DAC from an 8051 microcomputer,
; using the 8051’s serial port in MODE 0 (Shift Register Mode).
; T he DAC value is stored at location DAC_VAL
; T he DAC address is stored at location DAC_ADDR
;
; Variable declarations
;
PORT 1
DAT A
DAT A
DAT A
DAT A
DAT A
DAT A
90H
40H
41H
042H
043H
44H
;SFR register for port 1
;DAC Value
;DAC Address
;high byte of 16-bit answer
;low byte of answer
;
DAC_VALUE
DAC_ADDR
SHIFT 1
SHIFT 2
SHIFT _COUNT
;
ORG
CLR
100H
SCON.7
;arbitrary start
;set serial
DO_8801:
CLR
SCON.6
; data mode 0
CLR
SCON.5
CLR
ORL
CLR
MOV
ACALL
MOV
JNB
SCON.1
PORT 1.1,# 00001110B
PORT 1.1
;clr transmit flag
;/RS, /SHDN, /CS high
;set the /CS low
;put DAC value in shift register
;
;send the address byte
;wait until 8 bits are sent
;clear the serial transmit flag
;send the DAC value
;
SHIFT 1,DAC_ADDR
BYT ESWAP
SBUF,SHIFT 2
SCON.1,ADDR_WAIT
SCON.1
SHIFT 1,DAC_VALUE
BYT ESWAP
SBUF,SHIFT 2
SCON.1,VALU_WAIT
SCON.1
ADDR_WAIT :
VALU_WAIT :
CLR
MOV
ACALL
MOV
JNB
CLR
SET B
RET
;
;wait again
;clear serial flag
;/CS high, latch data
; into AD8801
PORT 1.1
;
BYT ESWAP:
SWAP_LOOP:
MOV
MOV
RLC
MOV
MOV
RRC
MOV
DJNZ
RET
SHIFT _COUNT ,# 8
A,SHIFT 1
A
SHIFT 1,A
A,SHIFT 2
A
;Shift 8 bits
;Get source byte
;Rotate MSB to carry
;Save new source byte
;Get destination byte
;Move carry to MSB
;Save
SHIFT 2,A
SHIFT _COUNT ,SWAP_LOOP
;Done?
END
Listing 1. Software for the 8051 to AD8801/AD8803 Serial Port Interface
–10–
REV. A
AD8801/AD8803
T he subroutine begins by setting appropriate bits in the Serial
Control register to configure the serial port for Mode 0 opera-
tion. Next the DAC’s Chip Select input is set low to enable the
AD8801/AD8803. T he DAC address is obtained from memory
location DAC_ADDR, adjusted to compensate for the 8051’s
serial data format, and moved to the serial buffer register. At
this point, serial data transmission begins automatically. When
all 8 bits have been sent, the T ransmit Interrupt bit is set, and
the subroutine then proceeds to send the DAC value stored at
location DAC_VALUE. Finally the Chip Select input is re-
turned high, causing the appropriate AD8801/AD8803 output
voltage to change, and the subroutine ends.
T he BYT ESWAP routine in Listing 1 is convenient because the
DAC data can be calculated in normal LSB form. For example,
producing a ramp voltage on a DAC is simply a matter of re-
peatedly incrementing the DAC_VALUE location and calling
the LD_8801 subroutine.
If the µC’s hardware serial port is being used for other purposes,
the AD8801/AD8803 can be loaded by using the parallel port.
A typical parallel interface is shown in Figure 26. T he serial data
is transmitted to the DAC via the 8051’s Port1.7 output, while
Port1.6 acts as the serial clock.
Software for the interface of Figure 26 is contained in Listing 2. The
subroutine will send the value stored at location DAC_VALUE to
the AD8801/AD8803 DAC addressed by location DAC_ADDR.
T he program begins by setting the AD8801/AD8803’s Serial
Clock and Chip Select inputs high, then setting Chip Select low
to start the serial interface process. T he DAC address is loaded
into the accumulator and three Rotate Right shifts are per-
formed. T his places the DAC address in the 3 MSBs of the ac-
cumulator. T he address is then sent to the AD8801/AD8803 via
the SEND_SERIAL subroutine. Next, the DAC value is loaded
into the accumulator and sent to the AD8801/AD8803. Finally,
the Chip Select input is set high to complete the data transfer.
T he 8051 sends data out of its shift register LSB first, while the
AD8801/AD8803 require data MSB first. T he subroutine there-
fore includes a BYT ESWAP subroutine to reformat the data.
T his routine transfers the MSB-first byte at location SHIFT 1 to
an LSB-first byte at location SHIFT 2. T he routine rotates the
MSB of the first byte into the carry with a Rotate Left Carry in-
struction, then rotates the carry into the MSB of the second byte
with a Rotate Right Carry instruction. After 8 loops, SHIFT 2
contains the data in the proper format.
; T his 8051 µC subroutine loads an AD8801 or AD8803 DAC with an 8-bit value,
; using the 8051’s parallel port # 1.
; T he DAC value is stored at location DAC_VALUE
; T he DAC address is stored at location DAC_ADDR
;
; Variable declarations
PORT 1
DAT A
DAT A
DAT A
DAT A
;
90H
40H
41H
43H
;SFR register for port 1
;DAC Value
;DAC Address (0 through 7)
;COUNT LOOPS
DAC_VALUE
DAC_ADDR
LOOPCOUNT
ORG
ORL
CLR
MOV
MOV
RR
100H
;arbitrary start
LD_8803:
PORT 1,# 11110000B
PORT 1.5
LOOPCOUNT ,# 3
A,DAC_ADDR
A
;set CLK, /CS and /SHDN high,
;Set Chip Select low
;Address is 3 bits
; Get DAC address
; Rotate the DAC
RR
RR
A
A
;address to the Most
;Significant Bits (MSBs)
;Send the address
ACALL
MOV
MOV
ACALL
SET B
RET
SEND_SERIAL
LOOPCOUNT ,# 8
A,DAC_VALUE
SEND_SERIAL
PORT 1.5
;Do 8 bits of data
;Send the data
;Set /CS high
;DONE
SEND_SERIAL:
RLC
MOV
CLR
A
;Move next bit to carry
;Move data to SDI
;Pulse the
PORT 1.7,C
PORT 1.6
SET B
DJNZ
RET ;
END
PORT 1.6
LOOPCOUNT ,SEND_SERIAL
; CLK input
;Loop if not done
Listing 2. Software for the 8051 to AD8801/AD8803 Parallel Port Interface
REV. A
–11–
AD8801/AD8803
+5V
MC68HC11
*
AD8801/
AD8803*
MOSI
(PD3)
(PD4) SCK
SDI
V
V
REFH
DD
8051 µC
CLK
AD8803
O1
P1.7
P1.6
P1.5
P1.4
CS
SDI
SS
PC0
PC1
(PD5)
O2
O3
O4
O5
O6
O7
O8
CLK
SHDN
CS
RS (AD8801 ONLY)
SHDN
*ADDITIONAL PINS OMITTED FOR CLARITY
1.7 1.6 1.5 1.4
PORT 1
V
GND REFL
Figure 27. An AD8801/AD8803-to-MC68HC11 Interface
A software routine for loading the AD8801/AD8803 from a
68HC11 evaluation board is shown in Listing 3. First, the
MC68HC11 is configured for SPI operation. Bits CPHA and
CPOL define the SPI mode wherein the serial clock (SCK) is
high at the beginning and end of transmission, and data is valid
on the rising edge of SCK. T his mode matches the requirements
of the AD8801/AD8803. After the registers are saved on the
stack, the DAC value and address are transferred to RAM and
the AD8801/AD8803’s CS is driven low. Next, the DAC’s ad-
dress byte is transferred to the SPDR register, which automati-
cally initiates the SPI data transfer. T he program tests the SPIF
bit and loops until the data transfer is complete. T hen the DAC
value is sent to the SPI. When transmission of the second byte is
complete, CS is driven high to load the new data and address
into the AD8801/AD8803.
Figure 26. An AD8801/AD8803-8051 µC Interface Using
Parallel Port 1
Unlike the serial port interface of Figure 25, the parallel port in-
terface only transmits 11 bits to the AD8801/AD8803. Also, the
BYT ESWAP subroutine is not required for the parallel inter-
face, because data can be shifted out MSB first. However, the
results of the two interface methods are exactly identical. In
most cases, the decision on which method to use will be deter-
mined by whether or not the serial data port is available for
communication with the AD8801/AD8803.
An MC68H C11-to-AD 8801/AD 8803 Inter face
Like the 8051, the MC68HC11 includes a dedicated serial data
port (labeled SPI). T he SPI port provides an easy interface to
the AD8801/AD8803 (Figure 27). T he interface uses three lines
of Port D for the serial data, and one or two lines from Port C
to control the SHDN and RS (AD8801 only) inputs.
–12–
REV. A
AD8801/AD8803
*
* AD8801/AD8803 to M68HC11 Interface Assembly Program
*
* M68HC11 Register definitions
*
PORT C
*
EQU
$1003
Port C control register
“0,0,0,0;0,0,RS/, SHDN/”
Port C data direction
Port D data register
“0,0,/CS,CLK;SDI,0,0,0”
Port D data direction
SPI control register
“SPIE,SPE,DWOM,MST R;CPOL,CPHA,SPR1,SPR0”
SPI status register
“SPIF,WCOL,0,MODF;0,0,0,0”
DDRC
PORT D
*
DDRD
SPCR
*
SPSR
*
SPDR
*
EQU
EQU
$1007
$1008
EQU
EQU
$1009
$1028
EQU
EQU
$1029
$102A
SPI data register; Read-Buffer; Write-Shifter
* SDI RAM variables:
SDI1 is encoded from 0 (Hex) to 7 (Hex)
SDI2 is encoded from 00 (Hex) to FF (Hex)
AD8801/3 requires two 8-bit loads; upper 5 bits
of SDI1 are ignored. AD8801/3 address bits in last
three LSBs of SDI1.
*
*
*
*
*
SDI1
SDI2
EQU
EQU
$00
$01
SDI packed byte 1 “0,0,0,0;0,A2,A1,A0”
SDI packed byte 2 “DB7,DB6,DB5,DB4;DB3,DB2,DB1,DB0”
*
* Main Program
*
ORG
LDS
$C000
# $CFFF
Start of user’s RAM in EVB
T op of C page RAM
INIT
*
* Initialize Port C Outputs
*
LDAA
# $03
0,0,0,0;0,0,1,1
*
/RS-Hi, /SHDN-Hi
ST AA
LDAA
PORT C
# $03
Initialize Port C Outputs
0,0,0,0;0,0,1,1
ST AA
DDRC
/RS and /SHDN are now enabled as outputs
*
* Initialize Port D Outputs
*
LDAA
# $20
0,0,1,0;0,0,0,0
*
/CS-Hi,/CLK-Lo,SDI-Lo
Initialize Port D Outputs
0,0,1,1;1,0,0,0
ST AA
LDAA
PORT D
# $38
ST AA
DDRD
/CS,CLK, and SDI are now enabled as outputs
*
* Initialize SPI Interface
*
LDAA
# $53
ST AA
SPCR
SPI is Master,CPHA=0,CPOL=0,Clk rate=E/32
*
* Call update subroutine
*
BSR
JMP
UPDAT E
$E000
Xfer 2 8-bit words to AD8402
Restart BUFFALO
*
* Subroutine UPDAT E
*
UPDAT E
PSHX
Save registers X, Y, and A
REV. A
–13–
AD8801/AD8803
PSHY
PSHA
*
* Enter Contents of SDI1 Data Register
*
LDAA
ST AA
$0000
SDI1
Hi-byte data loaded from memory
SDI1 = data in location 0000H
*
* Enter Contents of SDI2 Data Register
*
LDAA
ST AA
$0001
SDI2
Low-byte data loaded from memory
SDI2 = Data in location 0001H
*
LDX
LDY
# SDI1
# $1000
Stack pointer at 1st byte to send via SDI
Stack pointer at on-chip registers
*
* Reset AD8801 to one-half scale (AD8803 does not have a Reset input)
*
BCLR
BSET
PORT C,Y $02
PORT C,Y $02
Assert /RS
De-assert /RS
*
* Get AD8801/03 ready for data input
*
BCLR
PORT D,Y $20
Assert /CS
*
T FRLP
LDAA
ST AA
0,X
SPDR
Get a byte to transfer via SPI
Write SDI data reg to start xfer
*
WAIT
LDAA
BPL
SPSR
WAIT
Loop to wait for SPIF
SPIF is the MSB of SPSR
(when SPIF is set, SPSR is negated)
Increment counter to next byte for xfer
Are we done yet ?
*
INX
CPX
BNE
# SDI2+1
T FRLP
If not, xfer the second byte
*
* Update AD8801 output
*
BSET
PORT D,Y $20
Latch register & update AD8801
*
PULA
PULY
PULX
RT S
When done, restore registers X, Y & A
** Return to Main Program **
Listing 3. AD8801/AD8803 to MC68HC11 Interface Program Source Code
–14–
REV. A
AD8801/AD8803
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
16-P in P lastic D IP P ackage (N-16)
0.840 (21.33)
0.745 (18.93)
16
9
8
0.280 (7.11)
0.240 (6.10)
1
0.325 (8.25)
0.300 (7.62)
0.195 (4.95)
0.115 (2.93)
0.060 (1.52)
0.015 (0.38)
PIN 1
0.210 (5.33)
MAX
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
0.070 (1.77)
0.045 (1.15)
SEATING
PLANE
0.022 (0.558)
0.014 (0.356)
0.100
(2.54)
BSC
16-P in Nar r ow Body SO IC Package (R-16A)
16
1
9
8
0.1574 (4.00)
0.1497 (3.80)
PIN 1
0.2440 (6.20)
0.2284 (5.80)
0.3937 (10.00)
0.3859 (9.80)
0.0196 (0.50)
0.0099 (0.25)
x 45°
0.0688 (1.75)
0.0532 (1.35)
8°
0°
0.0098 (0.25)
0.0040 (0.10)
0.0500 (1.27)
0.0160 (0.41)
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
0.0099 (0.25)
0.0075 (0.19)
REV. A
–15–
–16–
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