AD9026AD [ADI]
IC 1-CH 12-BIT FLASH METHOD ADC, PARALLEL ACCESS, CDIP28, 0.600 INCH, HERMETIC SEALED, CERAMIC, DIP-28, Analog to Digital Converter;
| 型号： | AD9026AD |
| 厂家： | 
ADI |
| 描述： | IC 1-CH 12-BIT FLASH METHOD ADC, PARALLEL ACCESS, CDIP28, 0.600 INCH, HERMETIC SEALED, CERAMIC, DIP-28, Analog to Digital Converter CD 转换器 |
| 文件： | 总16页 (文件大小：507K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Speed 12-Bit
Monolithic A/D Converters
a
AD9026/AD9027
FEATURES
FUNCTIONAL BLOCK DIAGRAM
25.6 MSPS and 31 MSPS Grades
On-Chip T/H and Reference
1.65 Watt Power Dissipation
75 dBc Spurious-Free Dynamic Range
TTL and ECL Logic Versions
AD9026/AD9027
5-BIT
ANALOG
INPUT
T/H
12
DIGITAL
ERROR
CORRECTION
ADC
DAC
**
DIGITAL
OUTPUTS
5-BIT
ADC
ENCODE
+5V
APPLICATIONS
16
T/H
*ENCODE
DAC
–5.2V
GND
Cellular Base Stations
Communications Receivers
Radar Receivers
+2V
REF
4-BIT
8
T/H
ADC
Spectrum Analyzers
Electro-optics
Medical Imaging
**AD9026 DIGITAL OUTPUTS: TTL
AD9027 DIGITAL OUTPUTS: ECL
*AD9027 ONLY
PRODUCT DESCRIPTION
PRODUCT HIGHLIGHTS
The AD9026 and AD9027 are high speed, high performance,
monolithic 12-bit analog-to-digital converters. All necessary
functions, including track-and-hold (T/H) and reference are
included on chip to provide complete conversion solutions. The
AD9026 features TTL logic for digital inputs and outputs; the
AD9027 uses ECL logic including differential ECL encode.
Both the TTL and ECL converters are available at 25.6 Msps
(A grade) and 31 Msps (B grade) production tested encode
rates.
1. At 31 Msps (B grade devices) conversion rate, the converters
can digitize 15 MHz of spectrum.
2. On-chip T/H provides > 70 dB spurious-free dynamic range
over entire Nyquist band.
3. On-chip reference sets a 2.048 V p-p input voltage range
centered at 0 V.
4. AD9026 outputs connect directly to TTL logic; no ECL-to-
TTL chips required.
The on-chip T/H has a 150 MHz input bandwidth and is de-
signed to provide good dynamic performance for input frequen-
cies above Nyquist. This feature is necessary for IF-to-digital
conversion applications in which the A/D converter is used in
an undersampling mode. In addition, wide spurious-free dy-
namic range over the entire Nyquist bandwidth makes the
AD9026 and AD9027 well suited for multichannel transceiver
applications; both 31 Msps converters can digitize bandwidths
up to 15 MHz.
5. AD9027 ECL outputs offer lowest noise alternative for sys-
tem designs that prefer reduced output voltage swings.
The AD9026 and AD9027 are built on a trench isolated bipolar
process and use an innovative multipass architecture (see Func-
tional Block Diagram). Both parts are packaged in a 28-pin
ceramic DIP; the custom cofired ceramic package forms a multi-
layer substrate to which internal bypass capacitors and the ADC
die are attached. Both the AD9026 and the AD9027 are speci-
fied to operate over the industrial (–25°C to +85°C measured
at case) temperature range.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
AD9026/AD9027–SPECIFICATIONS
(+V = +5 V, –V = –5.2 V unless otherwise noted)
DC SPECIFICATIONS
S
S
Test
AD9026AD/BD
AD9027AD/BD
Parameter
Temp
Level
Min
Typ
Max
Min
Typ
Max
Units
RESOLUTION
12
12
Bits
DC ACCURACY
No Missing Codes
Offset Error
Full
+25°C
Full
+25°C
Full
+25°C
VI
I
VI
I
VI
V
Guaranteed
Guaranteed
5
25
5
25
mV
15
0.5
0.5
0.7
35
15
0.5
0.5
0.7
35
mV
Gain Error
5.0
5.5
5.0
5.5
% FS
% FS
LSB rms
Thermal Noise1
ANALOG INPUT
Input Voltage Range
Input Resistance
±1.024
300
7
±1.024
300
7
V
Full
IV
V
225
2
375
225
375
Ω
Input Capacitance
+25°C
pF
ENCODE INPUT
Logic Compatibility
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Input Capacitance
TTL
ECL
Full
VI
VI
VI
VI
V
–1.1
V
V
µA
µA
pF
Full
0.8
20
20
–1.5
10
10
Full
7
7
4
3
3
4
Full
+25°C
DIGITAL OUTPUTS2
Logic Compatibility
Logic “1” Voltage
Logic “0” Voltage
Output Coding
TTL
ECL
Full
Full
VI
VI
2.4
–1.1
V
V
0.5
–1.5
Offset Binary
Offset Binary
POWER SUPPLY
+VS Supply Voltage
+VS Supply Current
–VS Supply Voltage
–VS Supply Current
Power Dissipation3
Power Supply
Full
Full
Full
Full
Full
VI
VI
VI
I
4.75
–5.45
5.0
5.25
142
–4.95
248
2.0
4.75
–5.45
5.0
5.25
130
–4.95
260
2.0
V
mA
V
mA
W
120
–5.2
205
1.65
110
–5.2
215
1.65
VI
Rejection Ratio (PSRR)4
Full
VI
20
55
20
55
mV/V
NOTES
1ANALOG INPUT is connected to ground.
2AD9026AD/BD: outputs sourcing 1 mA when VOH is measured and sinking 2 mA when VOL is measured. AD9027 outputs are terminated with 2 kΩ resistors to –VS.
3Does not include power dissipated in termination resistors.
4+VS and –VS varied independently ±5% from nominal; PSRR in specification table is either PSRR (+VS) or PSRR (–VS), whichever is worse.
Specifications subject to change without notice.
SWITCHING SPECIFICATIONS
(+VS = +5 V; –VS = –5.2 V; Encode = 25.6 MSPS for A Grade Parts; Encode = 31.0 MSPS for B Grade Parts unless otherwise noted)
Test
AD9026AD
AD9026BD
AD9027AD
AD9027BD
Parameter (Conditions)
Temp Level Min Typ Max
Min Typ Max Min Typ
Max Min Typ Max
Units
Maximum Conversion Rate
Minimum Conversion Rate
Aperture Delay (tA)
Aperture Uncertainty (Jitter) +25°C
ENCODE Pulse Width High +25°C IV
ENCODE Pulse Width Low +25°C IV
Full
+25°C
+25°C
VI
V
V
25.6
31
25.6
31
4
MSPS
MSPS
ns
ps rms
ns
ns
ns
4
3
2
4
3
2
4
3
2
3
2
V
14
14
13
14
14
13
14
14
10
14
14
10
Output Delay (tOD
)
Full
IV
23
23
18
18
Specifications subject to change without notice.
–2–
REV. 0
AD9026/AD9027
(+V = +5 V; –V = –5.2 V; Encode = 25.6 MSPS (50% duty cycle) for A Grade Parts; Encode = 31.0 MSPS
(50% duty cycle) for B Grade Parts unless otherwise noted)
AC SPECIFICATIONS
S
S
Test
AD9026AD
AD9026BD
Min Typ Max
AD9027AD
Min Typ Max
AD9027BD
Min Typ Max Units
Parameter (Conditions)
Temp Level Min Typ Max
AC ACCURACY
Differential Nonlinearity
+25°C I
0.25 0.75
1.0
1.2 2.5
1.25 3.0
0.4
1.2
0.75
1.0
0.25 0.75
1.0
1.2 2.5
1.25 3.0
0.4 0.75 LSB
1.0 LSB
1.2 2.5 LSB
1.25 3.0 LSB
Full
VI
Integral Nonlinearity
+25°C I
2.5
Full
VI
1.25 3.0
ANALOG INPUT BANDWIDTH +25°C
V
V
V
150
10
150
10
150
10
150
10
MHz
ns
TRANSIENT RESPONSE
+25°C
+25°C
OVERVOLTAGE RECOVERY
10
10
10
10
ns
SFDR1
Analog Input @ 1.2 MHz
+25°C
Full
+25°C
Full
+25°C
Full
I
VI
I
VI
I
VI
70
68
70
68
70
68
77
75
76
74
75
73
70
68
70
68
65
63
77
75
75
73
72
70
70
68
70
68
70
68
77
75
76
74
75
73
70
68
70
68
70
68
77
75
76
74
74
72
dBc
dBc
dBc
dBc
dBc
dBc
9.6 MHz
13.4 MHz
SINAD2
Analog Input @ 1.2 MHz
+25°C
Full
+25°C
Full
+25°C
Full
I
VI
I
VI
I
VI
61
60
60
59
59
58
65
64
64
63
63
62
60
59
59
58
57
56
63
62
62
61
61
60
62
61
61
60
61
60
65
64
65
64
64
63
61
60
60
59
60
59
65
64
64
63
64
63
dB
dB
dB
dB
dB
dB
9.6 MHz
13.4 MHz
SNR3
Analog Input @ 1.2 MHz
+25°C
Full
+25°C
Full
+25°C
Full
I
VI
I
VI
I
VI
62
61
61
60
60
59
65
64
64
63
63
62
61
60
60
59
59
58
64
63
63
62
62
61
63
62
62
61
62
61
65
64
65
64
65
64
62
61
61
60
61
60
65
64
65
64
65
64
dB
dB
dB
dB
dB
dB
9.6 MHz
13.4 MHz
Two-Tone IMD Rejection4
F1 = 8.1 MHz; F2 = 9.6 MHz +25°C
I
I
75
68
83
75
75
68
83
75
75
68
85
75
75
68
85
75
dBc
dBc
Two-Tone SFDR5
F1 = 8.1 MHz; F2 = 9.6 MHz +25°C
NOTES
1Analog Input signal power at –1 dBFS; spurious-free dynamic range (SFDR) is the ratio of the signal level to worst spur, usually limited by harmonics.
2Analog Input signal power at –1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics.
3Analog Input signal power at –1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first five harmonics removed).
4Both input tones at –7 dBFS; two tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst 3rd order intermod product.
5Both input tones at –7 dBFS; two tone spurious-free dynamic range (SFDR) is the ratio of either tone to the worst spurious signal.
Specifications subject to change without notice.
1
WAFER TEST LIMITS
(+VS = +5 V, –VS = –5.2 V unless otherwise noted)
AD9026CHIPS
Typ
AD9027CHIPS
Typ
Parameter
Min
Max
Min
Max
Units
POWER SUPPLY
+VS Supply Current
–VS Supply Current
100
160
140
246
90
180
128
258
mA
mA
ENCODE INPUT
Logic “1” Current
Logic “0” Current
20
20
10
10
µA
µA
ANALOG INPUT
Input Resistance
225
375
225
375
Ω
DC ACCURACY
Offset Error
–20
20
–20
20
mV
Gain Error
–4.5
4.5
–4.5
4.5
% FS
No Missing Codes
Differential Nonlinearity
Guaranteed
Guaranteed
–0.65
0.65
–0.65
0.65
LSB
NOTES
1Electrical test is performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice.
2Die substrate is connected to –VS.
REV. 0
–3–
AD9026/AD9027
ABSOLUTE MAXIMUM RATINGS1
DIE PHOTO/ PAD LABELS
Parameter
Min
Max Units
ELECTRICAL
+VS
–VS
Analog Input
0
–6
–1.5
+6
0
+1.5
V
V
V
GROUND
D11 (MSB)
D10
Digital Inputs
+V
S
AD9026 (TTL Logic)
AD9027 (ECL Logic)
Digital Output Current
AD9026 (TTL Logic)
AD9027 (ECL Logic)
0
–VS
+VS
0
V
V
GROUND
ENCODE
D9
D8
12
12
mA
mA
ENVIRONMENTAL2
Operating Temperature Range (Case) –25
Maximum Junction Temperature
Lead Temperature (Soldering, 10 sec)
Storage Temperature Range (Ambient) –65
D7
D6
+85 °C
+175 °C
+300 °C
+150 °C
GROUND
ENCODE
D5
D4
D0 (LSB)
NOTES
1Absolute maximum ratings are limiting values to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.
2Typical thermal impedances for “D” package (custom ceramic 28-pin DIP):
θJC = 14oC/W; θJA = 34oC/W
AD9026/AD9027 CUSTOM PACKAGE
EXPLANATION OF TEST LEVELS
Test Level
CUSTOM 28-PIN COFIRED CERAMIC
MULTILAYER DUAL INLINE PACKAGE.
(TOP LAYER METALLIZATION SHOWN)
I. 100% Production Tested.
II. 100% production tested at +25oC, and sample tested at
specified temperatures. AC testing done on sample basis.
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
C1
–V
S
III. Sample Tested Only.
3
IV. Parameter is guaranteed by design and characterization
testing.
+V
S
4
C2
5
–V
S
V. Parameter is a typical value only.
VI. All devices are 100% production tested at +25oC; sample
tested at temperature extremes.
6
7
U1
8
DIE LAYOUT AND MECHANICAL INFORMATION
9
Die Dimensions . . . . . . . . . . . . . . . . . 205 × 228 × 21 (±1) mils
Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 × 4 mils
Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Aluminum
Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –VS
Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4,336
Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oxynitride
Die Attach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Silver Filled
Bond Wire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold
10
11
12
13
14
C4 C3
C5
+V
–V
S
GND
S
NOTES:
C1 & C4 ARE –V SUPPLY DECOUPLING CAPS.
S
C2 & C5 ARE +V SUPPLY DECOUPLING CAPS.
S
C3 IS A BYPASS CAP FOR INTERNAL DAC REFERENCE.
U1 SUBSTRATE IS TIED TO –V
.
S
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9026/AD9027 features ESD protection circuitry, permanent damage may occur
on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. 0
AD9026/AD9027
PIN DESIGNATIONS
PIN DESCRIPTIONS
Pin
No.
D3
D2
1
2
28
D3
D2
1
2
28
GND
GND
Name
Function
27 –V
27 –V
S
S
D1
3
26 +V
D1
3
26 +V
S
S
1–3
4
D3–D1
D0 (LSB)
NC
Digital Output Bits.
D0 (LSB)
4
25
24
23
22
21
20
19
18
17
16
D0 (LSB)
ENCODE
NC
4
25
24
23
22
21
20
19
18
17
16
D4
D4
Digital Output Bit (Least Significant Bit).
No connection internally on AD9026.
5
5
NC
D5
D5
5*
6
6
+V
S
D6
D6
AD9026
AD9027
GND
ENCODE
GND
7
GND
7
D7
D7
ENCODE Complement of encode clock input on
TOP VIEW
TOP VIEW
8
8
D8
ENCODE
GND
D8
AD9027.
(Not to Scale)
(Not to Scale)
9
9
D9
D9
6*
+VS
+5 V power supply on AD9026.
No connection internally on the AD9027.
Ground.
+V
S
10
11
12
10
11
12
+V
S
D10
D10
NC
GND
AIN
GND
AIN
D11 (MSB)
BYPASS
GND
D11 (MSB)
BYPASS
GND
7
8
GND
–V 13
–V 13
S
ENCODE Encode Clock Input. Conversion initiated
on rising edge of clock.
S
+V
14
15 –V
+V 14
S
15 –V
S
S
S
9
GND
+VS
Ground.
NC = NO CONNECT
NC = NO CONNECT
BYPASS (PIN 17) SHOULD BE CONNECTED TO –V (PIN 15) THROUGH 0.1µF CAP
S
10
11
12
13
14
15
16
17
18
+5 V power supply.
Ground.
GND
AIN
ORDERING GUIDE
Temperature
Analog Input.
–VS
–5.2 V power supply.
+5 V power supply.
–5.2 V power supply.
Ground.
+VS
Model
Range
Package Description
–VS
AD9026AD
–25°C to +85°C
(Case)
28-Pin 600 mil Hermetic
Ceramic DIP (DH-28)
28-Pin 600 mil Hermetic
Ceramic DIP (DH-28)
Unpackaged Die
GND
BYPASS
Connect to –VS through 0.1 µF capacitor.
AD9026BD
–25°C to +85°C
(Case)
D11 (MSB) Digital Output Bit (Most Significant Bit).
AD9026CHIPS
AD9026/PCB-T
19–25 D10–D4
Digital output bits.
+5 V power supply.
–5.2 V power supply.
Ground.
Evaluation Board with
AD9026BD
26
27
28
+VS
–VS
AD9027AD
AD9027BD
–25°C to +85°C
(Case)
–25°C to +85°C
(Case)
28-Pin 600 mil Hermetic
Ceramic DIP (DH-28)
28-Pin 600 mil Hermetic
Ceramic DIP (DH-28)
Unpackaged Die
Evaluation Board with
AD9027BD
GND
*Pin descriptions for the AD9026 and AD9027 are identical with the exception
of Pins 5 and 6.
AD9027CHIPS
AD9027/PCB-E
AD9026 Basic Hook-Up
AD9027 Basic Hook-Up
TTL
OUTPUTS
ECL
OUTPUTS
D0 (LSB)
D0 (LSB)
D3
D3
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AD9026
AD9027
–5.2V
+5V
2
–5.2V
+5V
2
3
3
4
4
NC
5
ENCODE
NC
5
D4
+5V
D4
6
6
DIFFERENTIAL
ECL
7
7
ENCODE
TTL LOGIC LEVELS
8
8
ENCODE
9
9
D11 (MSB)
D11 (MSB)
+5V
10
11
12
13
14
+5V
10
11
12
13
14
ANALOG
ANALOG
INPUT 2.048 V
INPUT 2.048 V
PP
PP
–5.2V
–5.2V
–5.2V
+5V
–5.2V
+5V
1. ALL DECOUPLING/BYPASS CAPACITORS ARE 0.1µF
2. NC = NOT CONNECTED
1. ALL DECOUPLING/BYPASS CAPACITORS ARE 0.1µF
2. NC = NOT CONNECTED
3. TERMINATE ECL OUTPUTS WITH 2kΩ to –5.2V
REV. 0
–5–
AD9026/AD9027
DEFINITION OF SPECIFICATIONS
Analog Bandwidth
Overvoltage Recovery Time
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
The amount of time required for the converter to recover to
0.2% accuracy after an analog input signal 150% of full scale is
reduced to midscale.
Aperture Delay
Power Supply Rejection Ratio
The delay between the 50% point of the rising edge of the
ENCODE command and the instant at which the analog input
is sampled.
The ratio of a change in input offset voltage to a change in
power supply voltage.
Signal-to-Noise-and-Distortion (SINAD)
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, including harmonics but excluding dc.
Differential Nonlinearity
The deviation of any code from an ideal 1 LSB step.
Signal-to-Noise Ratio (Without Harmonics)
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, excluding the first five harmonics and dc.
Harmonic Distortion
The ratio of the rms signal amplitude to the rms value of the
worst harmonic component.
Spurious-Free Dynamic Range
Integral Nonlinearity
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious compo-
nent may or may not be a harmonic.
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line”
determined by a least square curve fit.
Transient Response
Minimum Conversion Rate
The time required for the converter to achieve 0.2% accuracy when
a one-half full-scale step function is applied to the analog input.
The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone to the rms value
of the worst third order intermodulation product.
Maximum Conversion Rate
The encode rate at which parametric testing is performed.
Output Propagation Delay
Two-Tone SFDR
The delay between the 50% point of the rising edge of ENCODE
command and the time when all output data bits are within
valid logic levels.
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product.
EQUIVALENT CIRCUITS
+V
+V
S
S
+V
+V
S
S
100
11k
12k
ENCODE
180
ANALOG
INPUT
D11 – D0
900
120
5pF
–V
S
–V
–V
S
S
Analog Input Stage
AD9026 Encode Input
AD9026 Output Stage
1200
BYPASS
3400
3400
ENCODE
ENCODE
50
–V
S
D11 – D0
20pF
–V
–V
S
–V
S
S
Bypass
AD9027 Encode Input
AD9027 Output Stage
–6–
REV. 0
AD9026/AD9027
Typical AD9026 Performance
0
100
90
80
70
60
50
40
30
20
10
0
ENCODE = 31 MSPS
AIN = 13.4 MHz
SNR = 61 dB
SFDR = 78 dBc
–20
ENCODE = 25.6 MSPS
AIN = 12.6 MHz
–40
–60
ENCODE = 31 MSPS
AIN = 14.75 MHz
–80
–100
dc
3.1
6.2
9.3
12.4
15.5
–60
–50
–40
–30
–20
–10
0
10
FREQUENCY – MHz
ANALOG INPUT POWER LEVEL – dBm
Figure 1. Single Tone at 13.4 MHz
Figure 4. SFDR vs. Analog Input Level
100
90
80
70
60
50
40
30
20
10
0
0
ENCODE = 31 MSPS
ENCODE = 31 MSPS
AIN = 8.1, 9.6 MHz
SFDR = 72 dBc
–20
–40
–60
–80
–100
–60
–50
–40
–30
–20
–10
0
10
dc
3.1
6.2
9.3
12.4
15.5
ANALOG INPUT POWER LEVEL – dBm
FREQUENCY – MHz
Figure 5. Two-Tone SFDR vs. Analog Input Level
Figure 2. Two Tones @ 8.1 MHz & 9.6 MHz
0
0
ENCODE = 31 MSPS
AIN = 40 MHz
ENCODE = 31 MSPS
AIN = 8.1, 13.4 MHz
SFDR = 75 dBc
–20
–20
–40
–40
–60
–60
–80
–80
–100
–100
dc
3.1
6.2
9.3
12.4
15.5
dc
3.1
6.2
9.3
12.4
15.5
FREQUENCY – MHz
FREQUENCY – MHz
Figure 6. Undersampling a 40 MHz Input Tone
Figure 3. Two Tones @ 8.1 MHz & 13.4 MHz
REV. 0
–7–
AD9026/AD9027
Typical AD9027 Performance
0
100
90
80
70
60
50
40
30
20
10
0
ENCODE = 31 MSPS
AIN = 14.75 MHz
ENCODE = 31 MSPS
AIN = 13.4 MHz
SNR = 62 dB
–20
–40
SFDR = 73 dBc
–60
–80
–100
–60
–50
–40
–30
–20
–10
0
10
dc
3.1
6.2
9.3
12.4
15.5
ANALOG INPUT POWER LEVEL – dBm
FREQUENCY – MHz
Figure 7. Single Tone at 13.4 MHz
Figure 10. SFDR vs. Analog Input Level
100
0
–20
90
80
70
60
50
40
30
20
10
0
ENCODE = 31 MSPS
ENCODE = 31 MSPS
AIN = 8.1, 9.6 MHz
SFDR = 71 dBc
–40
–60
–80
–100
–60
–50
–40
–30
–20
–10
0
10
dc
3.1
6.2
9.3
12.4
15.5
ANALOG INPUT POWER LEVEL – dBm
FREQUENCY – MHz
Figure 8. Two Tones @ 8.1 MHz & 9.6 MHz
Figure 11. Two-Tone SFDR vs. Analog Input Level
0
0
ENCODE = 31 MSPS
AIN = 8.1, 13.4 MHz
SFDR = 73 dBc
–20
–40
ENCODE = 31 MSPS
AIN = 40 MHz
–20
–40
–60
–60
–80
–80
–100
–100
dc
3.1
6.2
9.3
12.4
15.5
dc
3.1
6.2
9.3
12.4
15.5
FREQUENCY – MHz
FREQUENCY – MHz
Figure 12. Undersampling a 40 MHz Input Tone
Figure 9. Two Tones @ 8.1 MHz & 13.4 MHz
–8–
REV. 0
AD9026/AD9027
Typical AD9027 Performance
Typical AD9026 Performance
90
80
70
60
50
40
30
90
ENCODE = 31 MSPS
ENCODE = 31 MSPS
HARMONICS
80
70
60
50
40
30
HARMONICS
SNR
SNR
1
2
4
10
20
40
100
1
2
4
10
20
40
100
ANALOG INPUT FREQUENCY – MHz
ANALOG INPUT FREQUENCY – MHz
Figure 13. Noise and Distortion vs. AIN Frequency
Figure 16. Noise and Distortion vs. AIN Frequency
80
80
ENCODE = 31 MSPS
ENCODE = 31 MSPS
75
75
70
70
SFDR
SFDR
65
60
65
60
SNR
55
SNR
55
50
45
40
50
45
40
35
40
45
50
55
60
65
35
40
45
50
55
60
65
ENCODE DUTY CYCLE – %
ENCODE DUTY CYCLE – %
Figure 17. SNR, SFDR vs. Encode Duty Cycle
Figure 14. SNR , SFDR vs. Encode Duty Cycle
0
0
ENCODE = 25.6 MSPS
–20
ENCODE = 25.6 MSPS
AIN = 21.4 MHz
–20
–40
AIN = 21.4 MHz
–40
–60
–80
–60
–80
–100
–100
dc
2.56
5.12
7.68
10.24
12.8
dc
2.56
5.12
7.68
10.24
12.8
FREQUENCY – MHz
FREQUENCY – MHz
Figure 15. Undersampling a 21.4 MHz Input Tone
Figure 18. Undersampling a 21.4 MHz Input Tone
REV. 0
–9–
AD9026/AD9027
AD9026/AD9027
180
5-BIT
ADC
ANALOG
INPUT
T/H
1
12
DIGITAL
ERROR
CORRECTION
**ECL/
TTL
5-BIT
ADC
120
ENCODE
DAC
+5V
*ENCODE
DAC
16
T/H
2
–5.2V
GND
+2V
REF
4-BIT
ADC
T/H
8
3
*AD9027 ONLY
**AD9026 OUTPUTS: TTL
AD9027 OUTPUTS: ECL
Figure 19. AD9026/AD9027 Functional Block Diagram
THEORY OF OPERATION
The AD9026/AD9027 analog-to-digital converters (ADCs)
employ a three-pass subranging architecture and digital error
correction. This combination of design techniques ensures 12-
bit accuracy at relatively low power.
Internally, the encode clock is delayed and gated to generate all
of the timing necessary for data conversion. The allocation of
hold and acquisition time for the first track-and-hold is critical
and is affected by the duty cycle of the encode clock. Perfor-
mance is optimized for encode duty cycles of 50%. Duty cycle
variations that exceed 50 ± 5% will negatively impact perfor-
mance at 31 Msps (see Performance Curves for detail).
As shown in Figure 19, analog input signals are immediately at-
tenuated through a resistor divider and applied directly to the
sampling bridge of a track-and-hold (T/H). The rising edge of
the ENCODE pulse places this first track-and-hold, T/H1, into
hold mode. The held value of T/H1 is applied to a 5-bit flash
ADC. The 5-bit converter resolves the most significant bits
(MSBs) of the held analog voltage. These five bits are recon-
structed by a 5-bit digital-to-analog converter (DAC) and sub-
tracted from T/H1’s output to form a residual signal. Note that
the reconstruction DAC has a resolution of 5 bits but must
maintain 12-bit accuracy.
Operation at encode rates less than 4 Msps is not recom-
mended. At these low encodes, the internal T/Hs will droop out
of error correction range and cease to function properly. For
the same reason, burst mode operation at the ENCODE pin is
not recommended. If burst mode is required, gate the digital
output data instead of the encode to the ADC; do not leave the
ENCODE pin in a static “logic high” state.
Encoding the AD9026
A second track-and-hold, T/H2, holds the amplified residue signal
while it is encoded by a second 5-bit flash ADC. These five bits
are reconstructed and subtracted from T/H2’s output to form a
second residual signal. A third and final track-and-hold, T/H3,
precedes a gain stage which in turn drives a 4-bit flash ADC.
Care should be taken when selecting drive logic for this single-
ended TTL-compatible input. Fast, clean, symmetrical output
swings with low jitter will yield optimal performance.
Gates from the “LS” logic family are not recommended because
of their extreme differences in rising versus falling characteristics.
Digital error correction logic corrects and aligns the data from
the three flash converters and presents the result as a 12-bit par-
allel digital word. In the case of the AD9026, the digital output
stage provides TTL logic levels; the AD9027 parallel output
provides ECL logic levels.
“AC” logic on the other hand, is too fast with excessive drive
capability, and tends to couple clock noise into the converter’s
first T/H stage. “AS” logic offers the best compromise of the
TTL families evaluated, but optimal performance was achieved
with AD969X family of TTL comparators (see AD9026/PCB-T
schematic).
APPLYING THE AD9026/AD9027
Timing
Encoding the AD9027
Conversion is initiated by asserting a logic “high” state on the
ENCODE command for both the AD9026 and AD9027 con-
verters, as shown in Figure 20. The digital output data which
corresponds to a given encode rising edge is available after two
A differential ECL encode is required for the AD9027: EN-
CODE (Pin 8), ENCODE (Pin 5). This signal should be
“clean” and fast, with a minimum amount of jitter. Such a sig-
nal may be generated by using a spectrally pure low phase noise
sine wave to drive an AD96687 ECL comparator (see AD9027/
PCB-E schematic).
pipeline delays and one propagation delay
.
N
Analog Input
The analog input (Pin 12) voltage range is nominally ±1.024 V.
The range is set with an internal voltage reference and cannot be
adjusted by the user. The input resistance is 300 Ω, and the
analog small signal bandwidth is 150 MHz, making the AD9026
and AD9027 suitable for undersampling applications. Sample
FFTs of 40 MHz large signal inputs can be found in the Perfor-
mance section (Figures 6, 12).
ANALOG
IN
N+1
ta
N+2
ta = 3ns TYPICAL
tOD
ENCODE
tOD = 13–23ns (AD9026); 10–18ns (AD9027)
N–2 N–1
DATA
OUTPUT
N–3
N
Figure 20. Timing Diagram
–10–
REV. 0
AD9026/AD9027
AD9027 should be bypassed individually. The bypass pin (BY-
PASS Pin 17) should be connected to the –VS supply (Pin 15)
through a 0.1 µF chip capacitor as close to the part as possible.
+V
S
10µF
R
R
F
G =
G
R
IN
AD9027
0.1µF
100–130Ω
7
Multilayer boards allow designers to lay out signal traces with-
out interrupting the ground plane and provide low impedance
return paths. In systems with dedicated analog and digital
grounds, all grounds for the AD9026 and AD9027 should be
connected to the analog ground plane.
3
2
ANALOG
INPUT
AD9631/32
4
6
R
F
R
G
V
IN
0.1µF
In systems using multilayer boards, dedicated power planes are
recommended to provide low impedance connections for device
power. Sockets limit dynamic performance and are not recom-
mended for use with the AD9026 or AD9027.
R
TERM
10µF
–V
S
Figure 21. Low Distortion Drive Circuit for AD9026/AD9027
EVALUATING PERFORMANCE OF THE AD9026/AD9027
Noise Performance
Driving the Analog Input
High speed, wide bandwidth ADCs such as the AD9026 and
AD9027 are optimized for dynamic performance over a wide
range of analog input frequencies. Due to this wide input band-
width, for a given analog input voltage there will be a range of
output codes that may occur. This is caused by unavoidable
circuit noise within the wideband circuits of the ADC. If a dc
signal is applied to the ADC and several thousand outputs are
recorded, a distribution of codes such as that shown in the his-
togram may result (Figure 22).
Special care must be taken to ensure that the analog input signal
is not compromised before it reaches the ADC. Any required
filtering should be done as close to the AD9026/AD9027 as
possible, and away from any digital lines.
In systems that have impedance matching problems or require
gain before the converter, a low noise, low distortion, wideband
op amp may be used. Typically this amplifier will degrade over-
all performance, but this degradation will be minimal if the cor-
rect amplifier is selected.
The correct code appears most of the time, but adjacent codes
also appear with reduced probability. If a normal probability
density curve is fitted to this Gaussian distribution of codes, the
standard deviation will be equal to the equivalent input rms
noise of the ADC. The rms input noise may also be approxi-
mated by converting the signal-to-noise ratio (SNR), as mea-
sured by a low frequency FFT, to an equivalent input noise.
This method is accurate only if the SNR performance is domi-
nated by random thermal noise (the low frequency SNR without
harmonics is the best measure); 63 dB equates to 1 LSB rms for
a 2 V p-p (0.707 V rms) input signal.
Figure 21 shows the ultralow distortion, wide bandwidth AD9631
driving an AD9027 converter at a gain of –1. This amplifier/
ADC combination maintains >70 dB harmonic distortion over
the Nyquist band. The low output impedance of the AD9631
also reduces drive circuitry sensitivity to the small current spikes
that can come from an ADC’s internal track-and-hold.
Power Supplies
The power supplies of the AD9026 and AD9027 should be iso-
lated from the supplies used for noisy devices (digital logic espe-
cially) to reduce the amount of noise coupled into the ADC.
For optimum performance, linear supplies ensure that switching
noise from the supplies does not introduce distortion products
during the encoding process. If switching supplies must be
used, decoupling recommendations should be observed.
ONE STANDARD
DEVIATION = RMS
NOISE LEVEL
Layout Information
Preserving the accuracy and dynamic performance of the
AD9026 and AD9027 requires that designers pay special atten-
tion to layout of the printed circuit board.
Analog paths should be kept as short as possible and be properly
terminated to avoid reflections. The analog input connection
should be kept away from digital signal paths; this reduces the
amount of digital switching noise that is capacitively coupled
into the analog section. Digital signal paths should also be kept
short, and run lengths should be matched to avoid propagation
delay mismatch. The AD9026 and AD9027 outputs should be
buffered or latched close to the device (<2 cm). This prevents
load transients which may feed back into the device.
X–3
X–2
X–1
X
X + 1
X + 2
X + 3
OUTPUT CODE
Figure 22. ADC Equivalent Input Noise
In high speed circuits, layout of the ground is critical. A single
low impedance ground plane on the component side of the
board is the minimum requirement (an internal ground plane is
preferred). Power supplies should be capacitively coupled to
the ground plane with high quality 0.1 µF chip capacitors to re-
duce noise in the circuit. All power pins of the AD9026 and
The AD9027 has approximately 0.7 LSB of rms input noise
which would predict a noise-limited SNR of 66 dB. Since the
actual SNR of the AD9027 is 65 dB for a 1.2 MHz input, ther-
mal noise alone does not limit the SNR performance of the de-
vice. Differential nonlinearities, aperture uncertainty, and
digital switching noise account for the additional degradation in
SNR as measured at the ADC output.
REV. 0
–11–
AD9026/AD9027
Two-tone intermodulation distortion rejection was also charac-
terized on the AD9026 and AD9027. Two tones, each at
–7 dBFS, were varied in frequency to determine flatness of IMD
rejection across the Nyquist band. A “Two-Tone SFDR” speci-
fication was created to distinguish between the typical level of
IMD products and other spurious levels. In most cases, second
order terms and direct harmonics limited Two-Tone SFDR on
these converters. Third order products were typically >80 dBc
(dBc indicates strength relative to the carrier), while first and
second order products were >72 dBc (Figures 2, 3, 5, 8, 9,
and 11).
Performance curves illustrate SNR vs. input frequency for the
AD9026 and AD9027 at encode rates of 31 Msps (Figures 13,
16). Because the AD9026 TTL converter has larger digital out-
put voltage swings, it tends to have slightly worse noise perfor-
mance than its ECL counterpart.
For a fixed analog input frequency, reducing the encode rate
on the AD9026 actually improves SNR (note specifications at
31 Msps vs. 25.6 Msps). This improvement results because the
rms noise coupled to internal circuits decreases as the time be-
tween samples increases.
Performance in the Frequency Domain
Performance Over Temperature
The AD9026 and AD9027 were designed to minimize harmonic
distortion over the entire Nyquist bandwidth. Performance
curves are included which illustrate >70 dB spurious-free dy-
namic range (SFDR) for –1 dBFS signals from dc to 15 MHz
(Figures 13 and 16).
Signal-to-noise ratio (SNR) is typically flat over the specified
operating temperature range for both the AD9026 and AD9027
across the entire Nyquist band.
Spurious-free dynamic range (SFDR) for a given input fre-
quency varies by a few dB over the rated operating temperature
range as indicated in the specification table.
Typically, the spurious levels generated by tones near full scale
are dominated by low order harmonics generated in the con-
verter’s first track-and-hold. As the strength of the analog input
signal is reduced, there is actually a slight increase in spurious-
free dynamic range relative to the carrier. At approximately
–7 dBFS the SFDR decreases linearly as input power is reduced
(Figures 4 and 10).
Harmonic distortion consistently increases with input frequency
at the maximum operating temperature of +85°C measured at
device case. For example, the SFDR of the ADC may vary from
a low of 71 dBc (13.4 MHz analog in), to a high of 80 dBc
(1.2 MHz analog in) at +85°C.
U3
74AS574
H40DMC
J3
U2
AD9698R
SMA
J1
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
1D
2D
3D
4D
5D
6D
7D
8D
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
1
11
5
ENCODE
INPUT
2
R8–R12
&
R14–R20
ARE 1kΩ
CLK
U5
AD9713B
6
3
R1
51
CLK
12
4
9
D11
D10
D9
5
R8
R9
D0
D1
D2
D3
2
3
4
5
(MSB)
6
7
R10
D8
R4
7.5k
8
D7
R11
24
20
9
R SET
REF OUT
D6
CK
OE
1
10
11
12
13
14
15
16
17
18
19
20
D5
11
D4
19
18
R3
20
CON AMP IN
U1
AD9026
U4
74AS574
CON AMP OUT
1
2
3
4
25
24
23
22
21
20
19
18
17
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
R12
R14
D4
D4
D5
1D
2D
3D
4D
5D
6D
7D
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
6
7
D3
D2
D1
17
16
14
D5
REF IN
D3
D2
D1
D0
C5
0.1µF
U2
AD9698R
14
4
R15
D6
D6
8
R16
IOUT
D7
D7
9
D0 (LSB)
–5.2V
R17
D8
D8
10
11
14
20
8
3
R18
R5
51
D9
IOUT
ENCODE
D9
13
16
SMA
J2
R19
D10
D10
D11
12
SMA
J4
ANALOG
INPUT
R20
(MSB) D11
BYPASS
8D
AIN
(LSB)
CK
RC
OUT
OE
1
R7
62
J5
J6
J7
–5.2V
11
+5V
C4
0.1µF
R6
51
26
LE
GND
–5.2V
Figure 23. AD9026 Evaluation Board Schematic (AD9026/PCB-T)
–12–
REV. 0
AD9026/AD9027
J5
J6
J7
RC OUTPUT
J4
C 1 6
U3
C7
+5V
GND
-5.2V
C2
C3
R6
R5
R8
R9
R10
R11
C 5
C 1 5
U1
J1
R1
C 2 2
R3
C 1 9
C 8
C17
C5
C9
U4
C 2 1
R12
R14
R15
R16
R17
R18
R19
R20
ENCODE
INPUT
U 2
U 5
R4
C 1 4
C11
C12
ANALOG
INPUT
C4
C20
R7
C18
J3
J2
C13
AD9026 EVALUATION BOARD
Figure 24. AD9026/PCB-T Top Side
J5
J6
J7
U3
C7
J4
C2
C3
R6
R8
R9
R5
C 1 6
R10
C 5
C 1 5
R11
U1
R1
C 2 2
J1
R3
C 1 9
C 8
C17
C5
C9
U4
C 2 1
R12
R14
R15
R16
R17
R18
R19
R20
U 2
U 5
C 1 4
R4
C11
C12
C20
C4
C18
J3
J2
R7
C13
Figure 25. AD9026/PCB-T Bottom Side
REV. 0
–13–
AD9026/AD9027
5
8
7
2
U101
AD96687
5
RZ100
6PT–5.2
160/260
B8
D8B
D8
U200
AD96687
SMA
ECLEN
5
2
3 4
REF
1
8
2
4
R101
49.9
7
12
1
9
15
16
C37DRPF
J200
1
2
3
4
4
DUT 1
AD9027
B9
D9B
D9
U200
AD96687
10
REF
U101
1
2
3
4
5
6
7
8
9
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
DRB
D4B
D5B
D6B
D7B
D8B
D9B
D10B
D11B
GND
13
5
AD96687
B3
B2
B1
B0
GND
–5.2V
+5V
B4
D3
D2
D1
12
–V
S
9
15
16
8
7
2
1
+V
S
5
6
B10
REF
D10B
D10
RZ101
6PT–5.2
160/260
U201
AD96687
10
D0 (LSB)
D4
D5
D6
D7
7
8
ENCODE
13
B5
4
2
3
4
5
NC
NC
B6
9
12
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
GND
9
15
16
GND
B7
B11
REF
D11B
D11
U201
AD96687
ENCODE
GND
B8
D8
D9
10
E100
ENC
E101
GND
B9
13
5
E102
10
11
12
13
14
+V
S
+5V
D10
D11 (MSB)
BYPASS
GND
B10
B11
SMA
AIN
D0B
D1B
D2B
D3B
GND
C102
0.1µF
GND
AIN
GND
8
7
2
1
B6
D6B
D6
U202
AD96687
AIN
REF
–V
S
R102
62
GND
–5.2V
+5V
4
+V
S
–5.2V
–V
S
–5.2V
DR
D4
12
9
15
16
B7
D7B
D7
U202
AD96687
D5
D6
10
REF
D7
D8
13
5
+5V
–5.2V
BJ100
VC1
D9
D10
D11
+5V
8
7
2
1
C100
10µF
B4
R200
3.9k
D4B
D4
U203
AD96687
R202
3k
REF
ECL
TTL
4
BJ104
BJ101
R203
2k
R201
1.3k
12
–5.2V
9
15
16
D0
D1
D2
D3
B5
D5B
D5
U203
AD96687
REFU
REF
VE1
10
REF
C200
0.1µF
C101
10µF
13
5
8
7
2
1
B2
D2B
D2
U204
AD96687
REF
U207
AD9712
RZ103
10PB–5.2
2k
RZ102
6PB–5.2
2k
4
DRB
28
1
2
12
26
2
3
2
3
4
5
6
9
15
16
B4
B5
B3
D3B
D3
B3
B2
B1
B0
LE
U204
AD96687
4
5
10
(MSB) D11
BIT 1
BIT 2
REF
B6
B7
D10
D9
D8
13
5
6
7
20
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
BIT 10
BIT 11
BIT 12
BG
CIN
3
B8
B9
19
18
17
24
4
5
8
9
8
7
2
1
R204
20
D7
D6
B0
D0B
D0
B10
B11
U205
AD96687
COUT
REF
RS
6
7
10
REF
D5
D4
4
8
9
C202
0.1µF
D3
D2
12
10
11
9
15
16
–5.2V
R207
7.5k
D1
B1
D1B
D1
U205
AD96687
(LSB) D0
10
REF
SMA
RCOUT
13
14
16
R206
51
12
13
5
E200
R205
51
9
15
8
7
2
1
ENC
DRB
U206
AD96687
U206
AD96687
10
REF
DR
REF
16
C201
0.1µF
4
Figure 26. AD9027 Evaluation Board Schematic (AD9027/PCB-E)
–14–
REV. 0
AD9026/AD9027
C200 C125
U206
RZ206
E200
BCOM
a
AD9027
E101
ENCODE
INPUT
ECLEN
EVALUATION BOARD
RZ101
1994
USA
©
E102
E100
C114
48280(B)
MICROPHONE
C126 U203
–5.2V
RZ203
RZ202
C101
J200
TO ANTENNA ™
VE1
R101
C115
U202
DUT 1
C127
RZ103
C112
C122
RECONSTRUCT
C116
C128
U101
OUTPUT
U200
U207
RZ201
RZ208
RZ100
ANALOG
INPUT
C117
C129
GND
U201
R207
AIN
C102
C105
RCOUT
C104
C134
C103
C124
E2
E1
R204
C118
C130
U205
U204
U102
RZ205
R205
VC1
C100
R206
R105
+5V
C113
RZ102
C133
C119
C123
AINA
R200
R201
RZ204
ECL
REFV
BUFFERED
ANALOG
INPUT
R202
R203
C120
BB/GH/KB
7/21/94
C201
TTL
Figure 27. AD9027/PCB-E Top Side
C200 C125
U206
RZ206
E200
E101
RZ101
E102
E100
C114
C126 U203
RZ203
RZ202
ECLEN
J200
VE1 C101
R101
C122
C115
C127
DUT 1
U202
RZ103
C112
C116
C128
U101
U200
U207
RZ201
RZ208
RZ100
C 1 3 8
C117
C129
U201
AIN
R207
C 1 3 1
C 1 3 7
C102
C105
C104
C134
RCOUT
C103
C124
E2
E1
R204
C118
C130
U205
C 1 3 5
U102
C 2 0 2
C 1 3 6
RZ205
R205
VC1
C100
R206
R105
C113
RZ102
C133
C119
C123
AINA
U204
C120
R200
R201
RZ204
ECL
REFV
R202
R203
C201
TTL
Figure 28. AD9027PCB-E Bottom Side
REV. 0
–15–
AD9026/AD9027
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
15
28
0.595 ± 0.010
(15.11 ± 0.25)
1
14
PIN 1
IDENTIFIERS
1.400 ± 0.014
(35.56 ± 0.35)
0.2 ± 0.024
(5.08 ± 0.61)
0.010 ± 0.002
(0.25 ± 0.05)
0.150
(3.81)
MIN
0.050 ± 0.010
(1.27 ± 0.25)
0.600 (15.24) REF
0.100 (2.54)
TYP
0.018 ± 0.002
(0.46 ± 0.05)
SEATING
PLANE
0.05 (1.27)
TYP
–16–
REV. 0
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