AD9122_技术文档

Dual, 16-Bit, 1200 MSPS,

TxDAC+^®Digital-to-Analog Converter

AD9122

FEATURES

GENERAL DESCRIPTION

Flexible LVDS interface allows word, byte, or nibble load

Single-carrier W-CDMA ACLR = 82 dBc @ 122.88 MHz IF

The AD9122 is a dual 16-bit, high dynamic range, digital-to-

analog converter (DAC) that provides a sample rate of 1200 MSPS,

Analog output: adjustable 8.7 mA to 31.7 mA, R_L= 25 Ω to 50 Ω

Novel 2×/4×/8× interpolator/complex modulator allows

carrier placement anywhere in the DAC bandwidth

Digital gain and phase adjustment for sideband suppression

Multiple chip synchronization interfaces

High performance, low noise PLL clock multiplier

Digital inverse sinc filter

Flexible LVDS interface allows word, byte, or nibble load

Low power: 1.5 W @ 1.2 GSPS, 800 mW @ 500 MSPS, full

operating conditions

permitting a multicarrier generation up to the Nyquist frequency.

It includes features optimized for direct conversion transmit

applications, including complex digital modulation, and gain and

offset compensation. The DAC outputs are optimized to interface

seamlessly with analog quadrature modulators, such as the

ADL537x F-MOD series from Analog Devices, Inc. A 4-wire

serial port interface provides for programming/readback of many

internal parameters. Full-scale output current can be programmed

over a range of 8.7 mA to 31.7 mA. The AD9122 comes in a

72-lead LFCSP.

72-lead, exposed paddle LFCSP

PRODUCT HIGHLIGHTS

1. Ultralow noise and intermodulation distortion (IMD)

enable high quality synthesis of wideband signals from

baseband to high intermediate frequencies.

2. A proprietary DAC output switching technique enhances

dynamic performance.

APPLICATIONS

Wireless infrastructure

W-CDMA, CDMA2000, TD-SCDMA, WiMAX, GSM, LTE

Digital high or low IF synthesis

Transmit diversity

Wideband communications: LMDS/MMDS, point-to-point

3. The current outputs are easily configured for various

single-ended or differential circuit topologies.

4. Flexible LVDS digital interface allows the standard 32-wire

bus to be reduced to ½ or ¼ of the width.

TYPICAL SIGNAL CHAIN

COMPLEX BASEBAND

DC

COMPLEX IF

RF

f

LO – f

IF

I DAC

2

2/4

SIN

DIGITAL

ANTIALIASING

FILTER

PA

BASEBAND

AQM

LO

PROCESSOR

COS

Q DAC

NOTES

1. AQM = ANALOG QUADRATURE MODULATOR.

Figure 1.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD9122

TABLE OF CONTENTS

Features .............................................................................................. 1

NCO Modulation ....................................................................... 37

Datapath Configuration ............................................................ 37

Determining Interpolation Filter Modes ................................ 38

Datapath Configuration Example............................................ 39

Data Rates vs. Interpolation Modes......................................... 40

Coarse Modulation Mixing Sequences.................................... 40

Quadrature Phase Correction................................................... 41

DC Offset Correction ................................................................ 41

Inverse Sinc Filter....................................................................... 41

DAC Input Clock Configurations................................................ 42

DAC Input Clock Configurations............................................ 42

Analog Outputs............................................................................... 44

Transmit DAC Operation.......................................................... 44

Auxiliary DAC Operation......................................................... 45

Baseband Filter Implementation.............................................. 46

Driving the ADL5375-15 .......................................................... 46

Reducing LO Leakage and Unwanted Sidebands .................. 47

Device Power Dissipation.............................................................. 48

Temperature Sensor ................................................................... 49

Multichip Synchronization............................................................ 50

Synchronization with Clock Multiplication............................... 50

Synchronization with Direct Clocking.................................... 51

Data Rate Mode Synchronization ............................................ 51

FIFO Rate Mode Synchronization ........................................... 52

Additional Synchronization Features ...................................... 52

Interrupt Request Operation ........................................................ 54

Interrupt Service Routine.......................................................... 54

Interface Timing Validation.......................................................... 55

SED Operation............................................................................ 55

SED Example .............................................................................. 55

Outline Dimensions....................................................................... 56

Ordering Guide .......................................................................... 56

Applications....................................................................................... 1

General Description......................................................................... 1

Product Highlights ........................................................................... 1

Typical Signal Chain......................................................................... 1

Revision History ............................................................................... 2

Functional Block Diagram .............................................................. 3

Specifications..................................................................................... 4

DC Specifications ......................................................................... 4

Digital Specifications ................................................................... 5

Digital Input Data Timing Specifications ................................. 5

AC Specifications.......................................................................... 6

Absolute Maximum Ratings............................................................ 7

Thermal Resistance ...................................................................... 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Typical Performance Characteristics ........................................... 10

Terminology .................................................................................... 16

Theory of Operation ...................................................................... 17

Serial Port Operation................................................................. 17

Data Format ................................................................................ 17

Serial Port Pin Descriptions...................................................... 17

Serial Port Options..................................................................... 18

Device Configuration Register Map and Descriptions ......... 19

LVDS Input Data Ports .................................................................. 31

Word Interface Mode................................................................. 31

Byte Interface Mode ................................................................... 31

Nibble Interface Mode ............................................................... 31

FIFO Operation.......................................................................... 31

Interface Timing......................................................................... 33

Digital Datapath.............................................................................. 34

Premodulation ............................................................................ 34

Interpolation Filters ................................................................... 34

REVISION HISTORY

9/09—Revision 0: Initial Version

Rev. 0 | Page 2 of 56

AD9122

FUNCTIONAL BLOCK DIAGRAM

IOUT1P

IOUT1N

16

1.2G

AUX

DAC 1

16-BIT

16

D15P—D15N

I OFFSET

f

/2

PRE

MOD

NCO

AND

MOD

DATA

10

INV

SINC

DAC CLK

FIFO

HB1

HB2

HB3

Q OFFSET

16

D0P—D0N

DCI

IOUT2P

IOUT2N

16

1.2G

FRAME

AUX

DAC 1

16-BIT

REF

REFIO

FSADJ

10

AND

BIAS

INTERNAL CLOCK TIMING AND CONTROL LOGIC

DAC CLK_SEL

PLL CONTROL

DAC_CLK

DACCLKP

DACCLKN

CLK

0

RCVR

SERIAL

INPUT/OUTPUT

PORT

SYNC

PROGRAMMING

REGISTERS

POWER-ON

RESET

MULTICHIP

SYNCHRONIZATION

CLOCK

MULTIPLIER

(2× TO 16×)

REFCLKP

REFCLKN

CLK

RCVR

1

PLL_LOCK

Figure 2. AD9122 Functional Block Diagram

Rev. 0 | Page 3 of 56

AD9122

SPECIFICATIONS

DC SPECIFICATIONS

T_MINto T_MAX, AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 =1.8 V, I_OUTFS= 20 mA, maximum sample rate, unless otherwise noted.

Table 1.

Parameter

Min

Typ

Max

Unit

RESOLUTION

16

Bits

ACCURACY

Differential Nonlinearity (DNL)

Integral Nonlinearity (INL)

MAIN DAC OUTPUTS

Offset Error

Gain Error (with Internal Reference)

Full-Scale Output Current¹

Output Compliance Range

Output Resistance

2.1

3.ꢀ

LSB

−0.001

−3.6

8.66

0

+0.001

+3.6

31.66

+1.0

% FSR

mA

V

MΩ

2

19.6

−1.0

10

Gain DAC Monotonicity

Settling Time to Within 0.5 LSB

MAIN DAC TEMPERATURE DRIFT

Offset

Gain

Reference Voltage

Guaranteed

20

ns

0.04

100

30

ppm/°C

REFERENCE

Internal Reference Voltage

Output Resistance

1.2

5

V

kΩ

ANALOG SUPPLY VOLTAGES

AVDD33

CVDD18

3.13

1.ꢀ1

3.3

1.8

3.4ꢀ

1.89

V

DIGITAL SUPPLY VOLTAGES

DVDD18

IOVDD

1.ꢀ1

1.8

1.8/2.5

1.89

2.94

V

POWER CONSUMPTION

2× Mode, f_DAC= 491.22 MSPS, IF = 10 MHz, PLL Off

2× Mode, f_DAC= 491.22 MSPS, IF = 10 MHz, PLL On

8× Mode, f_DAC= 800 MSPS, IF = 10 MHz, PLL Off

AVDD33

834

913

1135

55

mW

mA

1241

5ꢀ

CVDD18

85

90

mA

DVDD18

444

2.5

495

9.8

+0.3

+85

mA

Power-Down Mode

Power Supply Rejection Ratio, AVDD33

OPERATING RANGE

mW

% FSR/V

°C

−0.3

−40

+25

¹Based on a 10 kΩ external resistor.

Rev. 0 | Page 4 of 56

AD9122

DIGITAL SPECIFICATIONS

T_MINto T_MAX, AVDD33 = 1.8 V, IOVDD = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, I_OUTFS= 20 mA, maximum sample rate, unless

otherwise noted.

Table 2.

Parameter

Conditions

Min

Typ Max

Unit

CMOS INPUT LOGIC LEVEL

Input V_INLogic High (IOVDD = 1.8 V)

Input V_INLogic High (IOVDD = 2.5 V)

Input V_INLogic Low (IOVDD = 1.8 V)

Input V_INLogic Low (IOVDD = 2.5 V)

CMOS OUTPUT LOGIC LEVEL

Output V_OUTLogic High

Output V_OUTLogic Low

1.2

1.6

V

0.6

0.8

IOVDD = 1.8 V

IOVDD = 2.5 V

IOVDD = 1.8 V

IOVDD = 2.5 V

1.4

1.8

V

0.4

LVDS RECEIVER INPUTS¹

Input Voltage Range, V_IAor V_IB

Input Differential Threshold, V_IDTH

Input Differential Hysteresis, V_IDTHHto V_IDTHL

Receiver Differential Input Impedance, R_IN

LVDS Input Rate

825

−100

15ꢀ5 mV

+100 mV

mV

20

80

120

Ω

See Table 5

DAC CLOCK INPUT (DACCLKP, DACCLKN)

Differential Peak-to-Peak Voltage

Common-Mode Voltage

100

500

1.25

2000 mV

V

Self biased input, ac couple

Maximum Clock Rate

1200

100

MSPS

REFCLK INPUT (REFCLKP, REFCLKN)

Differential Peak-to-Peak Voltage

Common-Mode Voltage

500

1.25

2000 mV

V

REFCLK Frequency (PLL Mode)

REFCLK Frequency (SYNC Mode)

SERIAL PERIPHERAL INTERFACE

Maximum Clock Rate (SCLK)

1 GHz ≤ f_VCO≤ 26 Hz

See Multichip Synchronization section for conditions

15.625

0

600

MHz

40

MHz

ns

Minimum Pulse Width High (t_PWH

)

12.5

Minimum Pulse Width Low (t_PWOL

Setup Time, SDI to SCLK (t_DS)

Hold Time, SDI to SCLK (t_DH)

Data Valid, SDO to SCLK (t_DV)

1.9

0.2

23

ns

Setup Time, CS to SCLK (t_DCSB

)

1.4

ns

¹LVDS receiver is compliant to the IEEE 1596 reduced range link, unless otherwise noted.

DIGITAL INPUT DATA TIMING SPECIFICATIONS

Table 3.

Parameter

Min

Typ

Max

Unit

LATENCY (DACCLK Cycles)

1× Interpolation (With or Without Modulation)

2× Interpolation (With or Without Modulation)

4× Interpolation (With or Without Modulation)

8× Interpolation (With or Without Modulation)

Inverse Sinc

64

Cycles

ms

135

292

608

20

8

260

Fine Modulation

Power-Up Time

Rev. 0 | Page 5 of 56

AD9122

AC SPECIFICATIONS

T_MINto T_MAX, AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, I_OUTFS= 20 mA, maximum sample rate, unless otherwise noted.

Table 4.

Parameter

Min

Typ

Max

Unit

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

f_DAC= 100 MSPS, f_OUT= 20 MHz

f_DAC= 200 MSPS, f_OUT= 50 MHz

f_DAC= 400 MSPS, f_OUT= ꢀ0 MHz

f_DAC= 800 MSPS, f_OUT= ꢀ0 MHz

ꢀ8

80

69

ꢀ2

dBc

TWO-TONE INTERMODULATION DISTORTION (IMD)

f_DAC= 200 MSPS, f_OUT= 50 MHz

f_DAC= 400 MSPS, f_OUT= 60 MHz

f_DAC= 400 MSPS, f_OUT= 80 MHz

f_DAC= 800 MSPS, f_OUT= 100 MHz

84

86

84

81

dBc

NOISE SPECTRAL DENSITY (NSD) EIGHT-TONE, 500 kHz TONE SPACING

f_DAC= 200 MSPS, f_OUT= 80 MHz

f_DAC= 400 MSPS, f_OUT= 80 MHz

−162

−163

−164

dBm/Hz

f_DAC= 800 MSPS, f_OUT= 80 MHz

W-CDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR), SINGLE CARRIER

f_DAC= 491.52 MSPS, f_OUT= 10 MHz

f_DAC= 491.52 MSPS, f_OUT= 122.88 MHz

f_DAC= 983.04 MSPS, f_OUT= 122.88 MHz

W-CDMA SECOND ACLR, SINGLE CARRIER

f_DAC= 491.52 MSPS, f_OUT= 10 MHz

f_DAC= 491.52 MSPS, f_OUT= 122.88 MHz

f_DAC= 983.04 MSPS, f_OUT= 122.88 MHz

84

82

83

dBc

88

86

88

dBc

Table 5. Interface Speeds

f_BUS(Mbps)

1.8 V 2%

Bus Width

Interpolation Factor

1.8 V 5%

1100

550

1.9 V 5%

1200

600

Nibble (4 Bits)

1×

1200

600

2× (HB1)

2× (HB2)

4×

8×

Byte (8 Bits)

1×

2× (HB1)

2× (HB2)

4×

8×

Word (16 Bits)

1×

1100

900

1100

550

1200

1000

1200

600

1200

1000

1200

600

2× (HB1)

2× (HB2)

4×

8×

2ꢀ5

300

Rev. 0 | Page 6 of 56

AD9122

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

Table 6.

The exposed paddle (EPAD) must be soldered to the ground

plane for the 72-lead, LFCSP. The EPAD performs as an

electrical and thermal connection to the board.

With

Parameter

Respect To Rating

AVDD33

AVSS, EPAD, −0.3 V to +3.6 V

CVSS, DVSS

AVSS, EPAD, −0.3 V to +3.3 V

CVSS, DVSS

Typical θ_JA, θ_JB, and θ_JCare specified for a 4-layer board in still air.

Airflow increases heat dissipation effectively reducing θ_JAand θ_JB.

IOVDD

DVDD18, CVDD18

AVSS

AVSS, EPAD, −0.3 V to +2.1 V

CVSS, DVSS

EPAD, CVSS, −0.3 V to +0.3 V

DVSS

Table 7. Thermal Resistance

Package

θ_JA

θ_JB

θ_JCUnit Conditions

ꢀ2-Lead LFCSP_VQ 20.ꢀ 10.9 1.1 °C/W EPAD soldered

EPAD

AVSS, CVSS, −0.3 V to +0.3 V

DVSS

ESD CAUTION

CVSS

AVSS, EPAD, −0.3 V to +0.3 V

DVSS

AVSS, EPAD, −0.3 V to +0.3 V

CVSS

FSADJ, REFIO,

AVSS

−0.3 V to AVDD33 + 0.3 V

IOUT1P/IOUT1N,

IOUT2P/IOUT2N

D[15:0]P/D[15:0]N,

FRAMEP/FRAMEN,

DCIP/DCIN

EPAD, DVSS −0.3 V to DVDD18 + 0.3 V

DACCLKP/DACCLKN,

REFCLKP/REFCLKN

DVSS

−0.3 V to CVDD18 + 0.3 V

RESET, IRQ, CS, SCLK,

SDIO, SDO

EPAD, DVSS −0.3 V to IOVDD + 0.3 V

Junction Temperature

125°C

Storage Temperature

Range

−65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Rev. 0 | Page ꢀ of 56

AD9122

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

CVDD18

DACCLKP

DACCLKN

CVSS

FRAMEP

FRAMEN

IRQ

1

2

3

4

5

6

7

8

9

54 RESET

53 CS

PIN 1

INDICATOR

52 SCLK

51 SDIO

50 SDO

49 DVDD18

48 D0N

47 D0P

46 D1N

45 D1P

44 DVSS

43 DVDD18

42 D2N

41 D2P

AD9122

D15P

D15N

TOP VIEW

(Not to Scale)

NC 10

IOVDD 11

DVDD18 12

D14P 13

D14N 14

D13P 15

D13N 16

D12P 17

D12N 18

40 D3N

39 D3P

38 D4N

37 D4P

NOTES

1. NC = NO CONNECT.

2. EXPOSED PAD MUST BE CONNECTED TO AVSS.

Figure 3. Pin Configuration

Table 8. Pin Function Descriptions

Pin No.

Mnemonic

CVDD18

DACCLKP

DACCLKN

CVSS

Description

1

2

3

4

1.8 V Clock Supply. Supplies clock receivers, clock distribution, and PLL circuitry.

DAC Clock Input, Positive.

DAC Clock Input, Negative.

Clock Supply Common.

5

6

ꢀ

FRAMEP

FRAMEN

IRQ

Frame Input, Positive.

Frame Input, Negative.

Interrupt Request. Open-drain, active low output.

Data Bit 15 (MSB), Positive.

8

D15P

9

D15N

NC

Data Bit 15 (MSB), Negative.

No connection to device.

10

11

12

13

14

15

16

1ꢀ

18

19

20

21

22

23

24

25

26

IOVDD

DVDD18

D14P

D14N

D13P

D13N

D12P

D12N

D11P

D11N

D10P

D10N

D9P

D9N

D8P

Supply Pin for Serial Ports, RESET and IRQ. 1.8 V to 2.8 V can be supplied to this pin.

1.8 V Digital Supply. Supplies power to digital core and digital data ports.

Data Bit 14, Positive.

Data Bit 14, Negative.

Data Bit 13, Positive.

Data Bit 13, Negative.

Data Bit 12, Positive.

Data Bit 12, Negative.

Data Bit 11, Positive.

Data Bit 11, Negative.

Data Bit 10, Positive.

Data Bit 10, Negative.

Data Bit 9, Positive.

Data Bit 9, Negative.

Data Bit 8, Positive.

Data Bit 8, Negative.

D8N

Rev. 0 | Page 8 of 56

AD9122

Pin No.

2ꢀ

28

29

30

31

32

33

34

35

36

3ꢀ

38

39

40

41

42

43

44

45

46

4ꢀ

48

49

50

51

52

53

54

55

56

5ꢀ

58

59

60

61

62

63

64

65

66

6ꢀ

68

69

ꢀ0

ꢀ1

ꢀ2

Mnemonic

DCIP

DCIN

DVDD18

DVSS

DꢀP

DꢀN

D6P

D6N

D5P

D5N

D4P

D4N

D3P

D3N

D2P

D2N

DVDD18

DVSS

D1P

D1N

D0P

D0N

DVDD18

SDO

SDIO

SCLK

CS

Description

Data Clock Input, Positive.

Data Clock Input, Negative.

1.8 V Digital Supply.

Digital Common.

Data Bit ꢀ, Positive.

Data Bit ꢀ, Negative.

Data Bit 6, Positive.

Data Bit 6, Negative.

Data Bit 5, Positive.

Data Bit 5, Negative.

Data Bit 4, Positive.

Data Bit 4, Negative.

Data Bit 3, Positive.

Data Bit 3, Negative.

Data Bit 2, Positive.

Data Bit 2, Negative.

1.8 V Digital Supply.

Digital Common.

Data Bit 1, Positive.

Data Bit 1, Negative.

Data Bit 0, Positive.

Data Bit 0, Negative.

1.8 V Digital Supply.

Serial Port Data Output (CMOS Levels with Respect to IOVDD).

Serial Port Data Input/Output (CMOS Levels with Respect to IOVDD).

Serial Port Clock Input (CMOS Levels With Respect to IOVDD).

Serial Port Chip Select. Active Low (CMOS Levels With Respect to IOVDD).

Reset. Active Low (CMOS Levels With Respect to IOVDD).

No connection to device.

Analog Supply Common.

3.3 V Analog Supply.

Q DAC Positive Current Output.

Q DAC Negative Current Output.

3.3 V Analog Supply.

Analog Supply Common.

Voltage Reference. Nominally 1.2 V output. Should be decoupled to analog common.

Full-Scale Current Output Adjust. Place a 10 kΩ resistor on the analog common.

Analog Common.

3.3 V Analog Supply.

I DAC Positive Current Output.

I DAC Negative Current Output.

3.3 V Analog Supply.

PLL Reference Clock Input, Negative. This pin has secondary function as SYNC input.

PLL Reference Clock Input, Positive. This pin has secondary function as SYNC input.

1.8 V Clock Supply. Supplies clock receivers, clock distribution, and PLL circuitry.

Exposed pad must be connected to AVSS. This provides an electrical, thermal, and mechanical connection

to the PCB.

RESET

NC

AVSS

AVDD33

IOUT2P

IOUT2N

AVDD33

AVSS

REFIO

FSADJ

AVSS

AVDD33

IOUT1N

IOUT1P

AVDD33

REFCLKN

REFCLKP

CVDD18

EPAD

Rev. 0 | Page 9 of 56

AD9122

TYPICAL PERFORMANCE CHARACTERISTICS

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

f_DATA= 250MSPS, SECOND HARMONIC

0dBFS

f_DATA= 250MSPS, THIRD HARMONIC

f_DATA= 400MSPS, SECOND HARMONIC

f_DATA= 400MSPS, THIRD HARMONIC

–6dBFS

–12dBFS

–18dBFS

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

50

100

150

200

250

300

350

400

450

700

0

50

100

150

200

250

300

350

400

450

f_OUT(MHz)

Figure 4. Harmonics vs. f_OUTover f_DATA, 2× Interpolation,

Digital Scale = 0 dBFS, f_SC= 20 mA

Figure 7. Second Harmonic vs. f_OUTover Digital Scale, 2× Interpolation,

f_DATA= 400 MSPS, f_SC= 20 mA

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

f_DATA= 100MSPS, SECOND HARMONIC

f_DATA= 100MSPS, THIRD HARMONIC

f_DATA= 200MSPS, SECOND HARMONIC

f_DATA= 200MSPS, THIRD HARMONIC

0dBFS

–6dBFS

–12dBFS

–18dBFS

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

50

100

150

200

250

300

350

400

0

50

100

150

200

250

300

350

400

450

f_OUT(MHz)

Figure 5. Harmonics vs. f_OUTover f_DATA, 4× Interpolation,

Digital Scale = 0 dBFS, f_SC= 20 mA

Figure 8. Third Harmonic vs. f_OUTover Digital Scale, 2× Interpolation,

f_DATA= 400 MSPS, f_SC= 20 mA

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

10mA, SECOND HARMONIC

f_DATA= 100MSPS, SECOND HARMONIC

f_DATA= 100MSPS, THIRD HARMONIC

f_DATA= 150MSPS, SECOND HARMONIC

f_DATA= 150MSPS, THIRD HARMONIC

20mA, SECOND HARMONIC

–10

30mA, SECOND HARMONIC

–20

–30

–40

–50

–60

–70

–80

–90

–100

10mA, THIRD HARMONIC

20mA, THIRD HARMONIC

30mA, THIRD HARMONIC

0

100

200

300

400

500

600

0

50

100

150

200

250

300

350

400

450

f_OUT(MHz)

Figure 6. Harmonics vs. f_OUTover f_DATA, 8× Interpolation,

Digital Scale = 0 dBFS, f_SC= 20 mA

Figure 9. Second Harmonic vs. f_OUTover f_SC, 2× Interpolation,

_DATA= 400 MSPS, Digital Scale = 0 dBFS

f

Rev. 0 | Page 10 of 56

AD9122

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

f_DATA= 250MSPS

f_DATA= 400MSPS

2× INTERPOLATION,

SINGLE-TONE SPECTRUM,

f_DATA= 250MSPS,

f_OUT= 101MHz

0

50

100

150

200

250

300

350

400

450

START 1.0MHz

#RES BW 10kHz

VBW 10kHz

STOP 500.0MHz

SWEEP 6.017s (601 PTS)

f_OUT(MHz)

Figure 13. 2× Interpolation, Single-Tone Spectrum

Figure 10. Highest Digital Spur vs. f_OUTover f_DATA, 2× Interpolation,

Digital Scale = 0 dBFS, f_SC= 20 mA

–64

f_DATA= 100MSPS

f_DATA= 200MSPS

–66

–68

–70

–72

–74

–76

–78

4× INTERPOLATION,

SINGLE-TONE SPECTRUM,

f_DATA= 200MSPS,

f_OUT= 151MHz

START 1.0MHz

#RES BW 10kHz

VBW 10kHz

STOP 800.0MHz

SWEEP 9.634s (601 PTS)

0

50

100

150

200

250

300

350

400

450

f_OUT(MHz)

Figure 14. 4× Interpolation, Single-Tone Spectrum

Figure 11. Highest Digital Spur vs. f_OUTover f_DATA, 4× Interpolation,

Digital Scale = 0 dBFS, f_SC= 20 mA

–64

f_DATA= 100MSPS

f_DATA= 150MSPS

–66

–68

–70

–72

–74

–76

8× INTERPOLATION,

SINGLE-TONE SPECTRUM,

f_DATA= 100MSPS,

f_OUT= 131MHz

START 1.0MHz

#RES BW 10kHz

VBW 10kHz

STOP 800.0MHz

SWEEP 9.634s (601 PTS)

0

100

200

300

400

500

600

700

f_OUT(MHz)

Figure 15. 8× Interpolation, Single-Tone Spectrum

Figure 12. Highest Digital Spur vs. f_OUTover f_DATA, 8× Interpolation,

Digital Scale = 0 dBFS, f_SC= 20 mA

Rev. 0 | Page 11 of 56

AD9122

0

–10

–20

–30

–40

–50

–60

–70

–80

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

f_DATA= 250MSPS

f_DATA= 400MSPS

0dBFS

–6dBFS

–12dBFS

–18dBFS

–90

0

50

100

150

200

250

300

350

400

450

0

50

100

150

200

250

300

350

400

450

f_OUT(MHz)

Figure 16. IMD vs. f_OUTover f_DATA, 2× Interpolation,

Digital Scale = 0 dBFS, f_SC= 20 mA

Figure 19. IMD vs. f_OUTover Digital Scale, 2× Interpolation,

f_DATA= 400 MSPS, f_SC= 20 mA

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–50

–55

–60

–65

–70

–75

–80

–85

f_DATA= 100MSPS

f_DATA= 200MSPS

I

= 20mA

= 30mA

= 10mA

FS

0

50

100

150

200

250

300

350

400

0

50

100

150

200

250

300

350

400

450

f_OUT(MHz)

Figure 17. IMD vs. f_OUTover f_DATA, 4× Interpolation,

Digital Scale = 0 dBFS, f_SC= 20 mA

Figure 20. IMD vs. f_OUTover f_SC, 2× Interpolation, f_DATA= 400 MSPS,

Digital Scale = 0 dBFS

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–40

–45

f_DATA= 100MSPS

–50

PLL ON

–55

–60

–65

PLL OFF

–70

–75

–80

–85

–90

0

50

100

150

200

250

300

350

400

0

50

100

150

200

250

300

350

400

450

f_OUT(MHz)

Figure 18. IMD vs. f_OUTover f_DATA, 8× Interpolation,

Digital Scale = 0 dBFS, f_SC= 20 mA

Figure 21. IMD vs. f_OUT, PLL On vs. PLL Off

Rev. 0 | Page 12 of 56

AD9122

–152

–154

–156

–158

–160

–162

–164

–166

–161.0

–161.5

–162.0

–162.5

–163.0

–163.5

–164.0

–164.5

–165.0

–165.5

1×, f_DATA= 200MSPS

2×, f_DATA= 200MSPS

4×, f_DATA= 200MSPS

8×, f_DATA= 100MSPS

1×, f_DATA= 200MSPS

2×, f_DATA= 200MSPS

4×, f_DATA= 200MSPS

8×, f_DATA= 100MSPS

0

50

100

150

200

250

300

350

400

450

0

50

100

150

200

250

300

350

400

450

f_OUT(MHz)

Figure 22. 1-Tone NSD vs. f_OUTover Interpolation Rate, Digital Scale = 0 dBFS,

f_SC= 20 mA, PLL Off

Figure 25. 8-Tone NSD vs. f_OUTover Interpolation Rate, Digital Scale = 0 dBFS,

f_SC= 20 mA, PLL Off

–154

–161.0

0dBFS

–161.5

–162.0

–162.5

–163.0

–163.5

–164.0

–164.5

–165.0

–165.5

–166.0

–166.5

–6dBFS

–12dBFS

–18dBFS

–156

–12dBFS

–18dBFS

–158

–160

–162

–164

–166

–168

0

50

100

150

200

250

300

350

400

450

0

50

100

150

200

250

300

350

400

450

f_OUT(MHz)

Figure 23. 1-Tone NSD vs. f_OUTover Digital Scale, f_DATA= 200 MSPS,

4× Interpolation, f_SC= 20 mA, PLL Off

Figure 26. 8-Tone NSD vs. f_OUTover Digital Scale, f_DATA= 200 MSPS,

4× Interpolation, f_SC= 20 mA, PLL Off

–158

–160

2×, f_DATA= 200MSPS

4×, f_DATA= 200MSPS

8×, f_DATA= 100MSPS

4×, f_DATA= 200MSPS

8×, f_DATA= 100MSPS

–159

–161

–162

–163

–164

–165

–166

–160

–161

–162

–163

–164

–165

–166

0

50

100

150

200

250

300

350

400

450

0

50

100

150

200

250

300

350

400

450

f_OUT(MHz)

Figure 24. 1-Tone NSD vs. f_OUTover Interpolation Rate, Digital Scale = 0 dBFS,

_SC= 20 mA, PLL On

Figure 27. 8-Tone NSD vs. f_OUTover Interpolation Rate, Digital Scale = 0 dBFS,

_SC= 20 mA, PLL On

f

Rev. 0 | Page 13 of 56

AD9122

–77

–78

–79

–80

–81

–82

–83

–50

–55

–60

–65

–70

–75

–80

–85

–90

0dBFS

INTERPOLATION FACTOR = 2×, PLL OFF

INTERPOLATION FACTOR = 4×, PLL OFF

INTERPOLATION FACTOR = 2×, PLL ON

INTERPOLATION FACTOR = 4×, PLL ON

–3dBFS

–6dBFS

–84

0

50

100

150

200

250

0

100

200

300

400

500

f_OUT(MHz)

Figure 28. 1-Carrier W-CDMA ACLR vs. f_OUTover f_DAC

Adjacent Channel, PLL Off

,

Figure 31. 1-Carrier W-CDMA ACLR vs. f_OUT, Adjacent Channel,

PLL On vs. PLL Off

–78

–80

–82

–84

–86

–88

–90

–70

0dBFS

INTERPOLATION FACTOR = 2×, PLL OFF

INTERPOLATION FACTOR = 4×, PLL OFF

INTERPOLATION FACTOR = 2×, PLL ON

INTERPOLATION FACTOR = 4×, PLL ON

–3dBFS

–6dBFS

–72

–74

–76

–78

–80

–82

–84

–86

–88

–90

0

50

100

150

200

0

100

200

300

400

500

f_OUT(MHz)

Figure 29. 1-Carrier W-CDMA ACLR vs. f_OUTover f_DAC

Alternate Channel, PLL Off

Figure 32. 1-Carrier W-CDMA ACLR vs. f_OUT, Alternate Channel,

PLL On vs. PLL Off

–70

–75

–80

–85

–90

–95

–70

0dBFS

INTERPOLATION FACTOR = 2×, PLL OFF

INTERPOLATION FACTOR = 4×, PLL OFF

INTERPOLATION FACTOR = 2×, PLL ON

–3dBFS

–6dBFS

INTERPOLATION FACTOR = 4×, PLL ON

–75

–80

–85

–90

–95

0

50

100

150

200

0

100

200

300

400

500

f_OUT(MHz)

Figure 30. 1-Carrier W-CDMA ACLR vs. f_OUTover f_DAC

Second Alternate Channel, PLL Off

Figure 33. 1-Carrier W-CDMA ACLR vs. f_OUT, Second Alternate Channel,

PLL On vs. PLL Off

Rev. 0 | Page 14 of 56

AD9122

START 133.06MHz

#RES BW 30kHz

VBW 30kHz

STOP 166.94MHz

START 125.88MHz

#RES BW 30kHz

VBW 30kHz

STOP 174.42MHz

SWEEP 143.6ms (601 PTS)

SWEEP 206.9ms (601 PTS)

RMS RESULTS

FREQ

OFFSET REF BW

LOWER

dBc dBm

UPPER

dBc dBm

TOTAL CARRIER POWER –11.19dBm/15.3600MHz

RRC FILTER: OFF FILTER ALPHA 0.22

CARRIER POWER 5.00MHz 3.840MHz –75.96 –85.96

–77.13 –87.13

–85.24 –95.25

–85.43 –95.43

REF CARRIER POWER –16.89dBm/3.84000MHz

–10.00dBm/

3.840MHz

10.00MHz 3.840MHz –85.33 –95.33

15.00MHz 2.888MHz –95.81 –95.81

LOWER

dBc dBm

UPPER

dBc dBm

OFFSET FREQ INTEG BW

1

2

3

4

–16.92dBm

–16.89dBm

–17.43dBm

–17.64dBm

5.000MHz

10.00MHz

15.00MHz

3.840MHz

–65.88 –82.76

–68.17 –85.05

–70.42 –87.31

–67.52 –84.40

–69.91 –86.79

–71.40 –88.28

Figure 35. 1-Carrier W-CDMA ACLR Performance, IF = ~150 MHz

Figure 34. 4-Carrier W-CDMA ACLR Performance, IF = ~150 MHz

Rev. 0 | Page 15 of 56

AD9122

TERMINOLOGY

Integral Nonlinearity (INL)

Settling Time

INL is defined as the maximum deviation of the actual analog

output from the ideal output, determined by a straight line drawn

from zero scale to full scale.

The time required for the output to reach and remain within a

specified error band around its final value, measured from

the start of the output transition.

Differential Nonlinearity (DNL)

DNL is the measure of the variation in analog value, normalized

to full scale, associated with a 1 LSB change in digital input code.

Spurious Free Dynamic Range (SFDR)

The difference, in decibels, between the peak amplitude of the

output signal and the peak spurious signal within the dc to the

Nyquist frequency of the DAC. Typically, energy in this band is

rejected by the interpolation filters. This specification, therefore,

defines how well the interpolation filters work and the effect of

other parasitic coupling paths to the DAC output.

Offset Error

The deviation of the output current from the ideal of zero is

called offset error. For IOUT1P, 0 mA output is expected when

the inputs are all 0s. For IOUT1N, 0 mA output is expected

when all inputs are set to 1.

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the measured output signal

to the rms sum of all other spectral components below the Nyquist

frequency, excluding the first six harmonics and dc. The value

for SNR is expressed in decibels.

Gain Error

The difference between the actual and ideal output span. The

actual span is determined by the difference between the output

when all inputs are set to 1 and the output when all inputs are

set to 0.

Interpolation Filter

If the digital inputs to the DAC are sampled at a multiple rate of

Output Compliance Range

f

_DATA(interpolation rate), a digital filter can be constructed that

The range of allowable voltage at the output of a current output

DAC. Operation beyond the maximum compliance limits can

cause either output stage saturation or breakdown, resulting in

nonlinear performance.

has a sharp transition band near f_DATA/2. Images that typically

appear around f_DAC(output data rate) can be greatly suppressed.

Adjacent Channel Leakage Ratio (ACLR)

The ratio in decibels relative to the carrier (dBc) between the

measured power within a channel relative to its adjacent channel.

Temperature Drift

Temperature drift is specified as the maximum change from

the ambient (25°C) value to the value at either T_MINor T_MAX

.

Complex Image Rejection

For offset and gain drift, the drift is reported in ppm of full-

scale range (FSR) per degree Celsius. For reference drift, the

drift is reported in ppm per degree Celsius.

In a traditional two-part upconversion, two images are created

around the second IF frequency. These images have the effect

of wasting transmitter power and system bandwidth. By placing

the real part of a second complex modulator in series with the

first complex modulator, either the upper or lower frequency

image near the second IF can be rejected.

Power Supply Rejection (PSR)

The maximum change in the full-scale output as the supplies

are varied from minimum to maximum specified voltages.

Rev. 0 | Page 16 of 56

AD9122

THEORY OF OPERATION

The AD9122 combines many features that make it a very attractive

DAC for wired and wireless communications systems. The dual

digital signal path and dual DAC structure allow an easy interface

to common quadrature modulators when designing single

sideband transmitters. The speed and performance of the AD9122

allows wider bandwidths and more carriers to be synthesized than

in previously available DACs. In addition, these devices include an

innovative low power, 32-bit complex NCO that greatly increases

the ease of frequency placement.

The remaining SCLK edges are for Phase 2 of the communication

cycle. Phase 2 is the actual data transfer between the device and

the system controller. Phase 2 of the communication cycle is a

transfer of one or more data bytes. Registers change immediately

upon writing to the last bit of each transfer byte, except for the

frequency tuning word and NCO phase offsets that only change

when the frequency update bit (Register 0x36, Bit 0) is set.

DATA FORMAT

The instruction byte contains the information shown in Table 9.

The AD9122 offers features that allow simplified synchronization

with incoming data and between multiple devices. Auxiliary

DACs are also provided on chip for output dc offset compensation

(for LO compensation in SSB transmitters) and for gain matching

(for image rejection optimization in SSB transmitters).

Table 9. Serial Port Instruction Byte

I7 (MSB)

I6

I5

I4

I3

I2

I1

I0 (LSB)

R/W

A6

A5

A4

A3

A2

A1

A0

W

R/ , Bit 7 of the instruction byte, determines whether a read or

a write data transfer occurs after the instruction byte write. Logic 1

indicates a read operation, and Logic 0 indicates a write

operation.

SERIAL PORT OPERATION

The serial port is a flexible, synchronous serial communications

port allowing easy interface to many industry-standard micro-

controllers and microprocessors. The serial I/O is compatible

with most synchronous transfer formats, including both the

Motorola SPI® and Intel® SSR protocols. The interface allows

read/write access to all registers that configure the AD9122.

Single or multiple byte transfers are supported, as well as MSB-

first or LSB-first transfer formats. The serial interface ports can

be configured as a single pin I/O (SDIO) or two unidirectional

pins for input/output (SDIO/SDO).

A6 to A0, Bit 6 to Bit 0 of the instruction byte, determine the

register that is accessed during the data transfer portion of the

communication cycle. For multibyte transfers, A6 is the starting

byte address. The remaining register addresses are generated by

the device based on the LSB_FIRST bit (Register 0x00, Bit 6).

SERIAL PORT PIN DESCRIPTIONS

Serial Clock (SCLK)

The serial clock pin synchronizes data to and from the device

and runs the internal state machines. The maximum frequency

of SCLK is 40 MHz. All data input is registered on the rising

edge of SCLK. All data is driven out on the falling edge of SCLK.

50

SDO

SDIO 51

SPI

PORT

52

53

SCLK

CS

Chip Select (

)

Figure 36. Serial Port Interface Pins

An active low input starts and gates a communication cycle.

It allows more than one device to be used on the same serial

communications lines. The SDO and SDIO pins go to a high

impedance state when this input is high. During the communication

cycle, chip select should stay low.

There are two phases to a communication cycle with the AD9122.

Phase 1 is the instruction cycle (the writing of an instruction

byte into the device), coincident with the first eight SCLK rising

edges. The instruction byte provides the serial port controller

with information regarding the data transfer cycle, Phase 2 of

the communication cycle. The Phase 1 instruction byte defines

whether the upcoming data transfer is a read or write and the

starting register address for the first byte of the data transfer.

The first eight SCLK rising edges of each communication cycle

are used to write the instruction byte into the device.

Serial Data I/O (SDIO)

Data is always written into the device on this pin. However, this

pin can be used as a bidirectional data line. The configuration

of this pin is controlled by Register 0x00, Bit 7. The default is

Logic 0, configuring the SDIO pin as unidirectional.

Serial Data Out (SDO)

CS

A logic high on the

pin followed by a logic low resets the

serial port timing to the initial state of the instruction cycle.

From this state, the next eight rising SCLK edges represent the

instruction bits of the current I/O operation.

Data is read from this pin for protocols that use separate lines

for transmitting and receiving data. In the case where the device

operates in a single bidirectional I/O mode, this pin does not

output data and is set to a high impedance state.

Rev. 0 | Page 1ꢀ of 56

AD9122

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

SERIAL PORT OPTIONS

CS

The serial port can support both MSB-first and LSB-first data

formats. This functionality is controlled by LSB_FIRST

(Register 0x00, Bit 6). The default is MSB-first (LSB_FIRST = 0).

SCLK

A0 A1 A2 A3 A4 N0 N1 R/W D0 D1 D2

D4 D5 D6 D7

N N N

SDIO

SDO

0

N

When LSB_FIRST = 0 (MSB-first), the instruction and data bit

must be written from MSB to LSB. Multibyte data transfers in

MSB-first format start with an instruction byte that includes

the register address of the most significant data byte. Subsequent

data bytes should follow from the high address to low address.

In MSB-first mode, the serial port internal byte address

generator decrements for each data byte of the multibyte

communication cycle.

D0 D1 D2

D4 D5 D6 D7

N N N

0

Figure 38. Serial Register Interface Timing LSB-First

t_DS

t_SCLK

CS

t_PWH

t_PWL

SCLK

When LSB_FIRST = 1 (LSB-first), the instruction and data bit

must be written from LSB to MSB. Multibyte data transfers in

LSB-first format start with an instruction byte that includes the

register address of the least significant data byte followed by

multiple data bytes. The serial port internal byte address generator

increments for each byte of the multibyte communication cycle.

t_DS

t_DH

SDIO

INSTRUCTION BIT 7

INSTRUCTION BIT 6

Figure 39. Timing Diagram for Serial Port Register Write

CS

The serial port controller data address decrements from the

data address written toward 0x00 for multibyte I/O operations

if the MSB-first mode is active. The serial port controller address

increments from the data address written toward 0x7F for

multibyte I/O operations if the LSB-first mode is active.

SCLK

t_DV

SDIO,

SDO

DATA BIT n

DATA BIT n – 1

Figure 40. Timing Diagram for Serial Port Register Read

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

CS

SCLK

SDIO

SDO

R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5

N

D3 D2 D1 D0

0 0 0

N

0

D7 D6 D5

N

D3 D2 D1 D0

0 0 0

N

Figure 37. Serial Register Interface Timing MSB-First

Rev. 0 | Page 18 of 56

AD9122

DEVICE CONFIGURATION REGISTER MAP AND DESCRIPTIONS

Table 10. Device Configuration Register Map

Addr

(Hex) Bit 7

Reg Name

Comm

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

0x00

0x01

SDIO

LSB_FIRST

Reset

Power Control

Power-

down

DAC I

Power-

down

DAC Q

Power-

down data down

receiver

Power-

PLL lock

status

0x10

aux ADC

Data Format

0x03

0x04

Binary

data

format

Q data

first

MSB swap

Data bus width[1:0]

0x00

Interrupt Enable

Enable

PLL lock

lost

Enable

PLL

locked

Enable

sync

signal

lost

Enable

sync

signal

locked

Enable

sync

phase

locked

Enable

soft

FIFO

sync

Enable

FIFO

Enable

FIFO

Warning 1 Warning 2

Interrupt Enable

0x05

0

Enable

AED

Enable

AED

Enable

SED

0

0x00

compar

pass

compar

fail

compar

fail

Event Flag

0x06

0x0ꢀ

0x08

PLL

lock

lost

PLL

locked

Sync

signal

lost

Sync

signal

locked

Sync

phase

locked

Soft

FIFO

sync

FIFO

N/A

Warning 1 Warning 2

AED

compar

pass

AED

compar

fail

SED

compar

fail

N/A

Clock Receiver

Control

DACCLK

duty

correction correction

REFCLK

duty

DACCLK

cross-

correction

REFCLK

cross-

correction

0

0x3F

0x40

0x00

PLL Control

0x0A PLL

enable

PLL

manual

enable

Manual VCO Band[5:0]

0x0B

PLL VCO

enable

PLL Control

0x0C

0x0D

PLL Loop

Bandwidth[1:0]

PLL Charge Pump Current[4:0]

N0[1:0]

0xD1

0xD9

N2[1:0]

PLL cross

control

enable

N1[1:0]

PLL Status

0x0E

0x0F

PLL lock

VCO Control Voltage[3:0]

VCO Band Readback[5:0]

0x00

Sync Control

0x10

Sync

enable

Data/FIFO

rate toggle

Rising

edge sync

Sync Averaging[2:0]

0x48

Sync Control

Sync Status

0x11

0x12

Sync Phase Request[5:0]

0x00

N/A

Sync lost

Sync

locked

Sync Status

0x13

0x15

Sync Phase Readback[ꢀ:0] (6.2 format)

N/A

Data Receiver

Status

LVDS

DCI level

high

LVDS

DCI

LVDS

LVDS data

FRAME

level high

FRAME

level low

data level level low

high

level

low

FIFO Control

FIFO Status

0x1ꢀ

0x18

FIFO Phase Offset[2:0]

0x04

N/A

FIFO

soft

FIFO soft

align

FIFO reset

aligned

Warning 1 Warning 2

align

ack

request

FIFO Status

0x19

FIFO Level[ꢀ:0]

N/A

Rev. 0 | Page 19 of 56

AD9122

Addr

(Hex) Bit 7

Reg Name

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

Datapath

Control

0x1B

Bypass

premod

Bypass

Sinc⁻¹

Bypass

NCO

NCO gain

Bypass

phase

comp

and dc

offset

Select

sideband to Q data

Send I data

0xE4

HB1 Control

0x1C

HB1[1:0]

Bypass HB1 0x00

HB2 Control

HB3 Control

Chip ID

0x1D

0x1E

0x1F

0x30

0x31

0x32

0x33

0x34

HB2[5:0]

Bypass HB2 0x00

HB3[5:0]

Bypass HB3 0x00

Chip ID[ꢀ:0]

FTW[ꢀ:0]

0x08

0x00

0x08

0x00

FTW LSB

FTW

FTW[15:8]

FTW[23:16]

FTW[31:24]

FTW

FTW MSB

NCO Phase

Offset LSB

NCO Phase Offset[ꢀ:0]

NCO Phase

Offset MSB

0x35

0x36

NCO Phase Offset[15:8]

0x00

NCO FTW

Update

Frame

FTW ack

Frame FTW

request

Update

FTW ack

Update

FTW

0x00

request

I Phase Adj LSB

I Phase Adj MSB

Q Phase Adj LSB

0x38

0x39

0x3A

I Phase Adj[ꢀ:0]

Q Phase Adj[ꢀ:0]

0x00

I Phase Adj[9:8]

Q Phase Adj[9:8]

Q Phase Adj MSB 0x3B

I DAC Offset LSB 0x3C

I DAC Offset MSB 0x3D

I DAC Offset[ꢀ:0]

I DAC Offset[15:8]

Q DAC Offset[ꢀ:0]

Q DAC Offset

LSB

0x3E

Q DAC Offset

MSB

0x3F

Q DAC Offset[15:8]

I DAC FS Adj[ꢀ:0]

0x00

I DAC FS Adj.

I DAC Control

0x40

0x41

0xF9

0x01

I DAC

sleep

I DAC FS Adj[9:8]

Aux DAC I Data

0x42

0x43

I Aux DAC[ꢀ:0]

0x00

I Aux DAC

Control

I Aux

DAC sign

I Aux DAC

current

I Aux DAC

Sleep

I Aux DAC[9:8]

direction

Q DAC FS Adj.

Q DAC Control

0x44

0x45

Q DAC FS Adj[ꢀ:0]

Q Aux DAC[ꢀ:0]

0xF9

0x01

Q DAC

sleep

Q DAC FS Adj[9:8]

Q Aux DAC[9:8]

Aux DAC Q Data

0x46

0x4ꢀ

0x00

Q Aux DAC

Control

Q Aux

DAC sign

Q Aux DAC Q Aux DAC

current

Sleep

direction

Die Temp

Range Control

0x48

FS Current[2:0]

Ref Current[2:0]

Capacitor 0x02

value

Die Temp LSB

Die Temp MSB

SED Control

0x49

0x4A

0x6ꢀ

Die Temp[ꢀ:0]

Die Temp[15:8]

N/A

SED

compare

enable

Sample

error

detected

Autoclear

enable

Compare Compare

fail pass

0x00

Rev. 0 | Page 20 of 56

AD9122

Addr

(Hex) Bit 7

Reg Name

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

0xB6

Compare I0 LSBs 0x68

Compare Value I0[ꢀ:0]

Compare Value I0[15:8]

Compare

I0 MSBs

0x69

0x6A

0x6B

0xꢀA

Compare

Q0 LSBs

Compare Value Q0[ꢀ:0]

Compare Value Q0[15:8]

0x45

0xEA

Compare

Q0 MSBs

Compare I1 LSBs 0x6C

Compare I1 MSBs 0x6D

Compare Value I1[ꢀ:0]

Compare Value I1[15:8]

Compare Value Q1[ꢀ:0]

0x16

0x1A

0xC6

Compare

Q1 LSBs

0x6E

Compare

Q1 MSBs

0x6F

Compare Value Q1[15:8]

0xAA

SED I LSBs

SED I MSBs

SED Q LSBs

SED Q MSBs

0xꢀ0

0xꢀ1

0xꢀ2

0xꢀ3

Errors Detected I_BITS[ꢀ:0]

Errors Detected I_BITS[15:8]

Errors Detected Q_BITS[ꢀ:0]

Errors Detected Q_BITS[15:8]

0x00

Table 11. Device Configuration Register Descriptions

Reg

Name

Addr

(Hex)

Bit

Name

Description

Default

Comm

00

ꢀ

SDIO

SDIO Operation.

0

0 = SDIO operates as an input only.

1 = SDIO operates as bidirectional input/output.

Serial port communication LSB or MSB first.

0 = MSB first.

6

LSB_FIRST

0

1 = LSB first.

5

ꢀ

6

5

Reset

Reset is asserted when this bit transitions from 0 to 1.

1 = power down DAC I.

0

Power

01

Power-down DAC I

Power-down DAC Q

1 = power down DAC Q.

Control

Power-down data

receiver

1 = power down the input data receiver.

4

0

Power-down auxiliary

ADC

1 = power down auxiliary ADC for temperature sensor.

1 = PLL is locked.

0

PLL lock status

Rev. 0 | Page 21 of 56

AD9122

Reg

Name

Addr

(Hex)

Bit

Name

Description

Default

Data

Format

03

ꢀ

Binary data format

0 = input data is in twos complement format.

1 = input data is in binary format.

Indicates I/Q data pairing on data input.

0 = I data sent to data receiver first.

1 = Q data sent to data receiver first.

Swaps the bit order of the data input port.

0

6

5

Q data first

MSB swap

0

0 = order of the data bits corresponds to the pin

descriptions

1 = bit designations are swapped; most significant bits

become the least significant bits

1:0

Data bus width

Data receiver interface mode.

0

00 = word mode; 16-bit interface bus width.

01 = byte mode; 8-bit interface bus width.

10 = nibble mode; 4-bit interface bus width.

11 = invalid.

See the LVDS Input Data Ports section for details on

the operation of the different interface modes.

Interrupt 04

Enable

ꢀ

6

5

4

Enable PLL lock lost

Enable PLL locked

1 = enable interrupt for PLL lock lost.

1 = enable interrupt for PLL locked.

0

Enable sync signal lost

1 = enable interrupt for sync signal lock lost.

1 = enable interrupt for sync signal locked.

Enable sync signal

locked

3

Enable sync phase

locked

1 = enable interrupt for clock generation ready.

0

2

1

0

Enable soft FIFO sync

Enable FIFO Warning 1

Enable FIFO Warning 2

Set to 0

1 = enable interrupt for soft FIFO reset.

1 = enable interrupt for FIFO Warning 1.

1 = enable interrupt for FIFO Warning 2.

0

Interrupt 05

Enable

ꢀ

6

5

4

Set this bit to 0.

0

Set to 0

Set this bit to 0.

Set to 0

Set this bit to 0.

Enable AED comparison

pass

1 = enable interrupt for AED comparison pass.

3

2

Enable AED comparison

fail

1 = enable interrupt for AED comparison fail.

1 = enable interrupt for SED comparison fail.

0

Enable SED comparison

fail

1

0

Set to 0

Set this bit to 0.

0

Rev. 0 | Page 22 of 56

AD9122

Reg

Name

Addr

(Hex)

Bit

Name

Description

Default

Event

Flag

06

ꢀ

PLL lock lost

1 = indicates that the PLL, which had been previously

locked, has unlocked from the reference signal. This is a

latched signal.

0

6

5

4

PLL locked

1 = indicates that the PLL has locked to the reference

clock input.

0

Sync signal lost

Sync signal locked

1 = indicates that the sync logic, which had been

previously locked, has lost alignment. This is a latched signal.

1 = indicates that the sync logic did achieve sync

alignment. This is indicated when no phase changes

were requested for at least a few full averaging cycles.

3

2

Sync phase locked

Soft FIFO sync

1 = indicates that the internal digital clock generation logic is

ready. This occurs when internal clocks are present and stable.

0

1 = indicates that a FIFO reset originating from a serial

port-based request has successfully completed. This is

a latched signal.

1

0

FIFO Warning 1

FIFO Warning 2

1 = indicates that the difference between the FIFO read

and write pointers is 1.

0

1 = indicates that the difference between the FIFO read

and write pointers is 2.

Note that all bit event flags are cleared by writing the respective bit high.

Event

Flag

0ꢀ

4

3

AED comparison pass

1 = indicates that the SED logic detected a valid input data

pattern compared against the preprogrammed expected

values. This is a latched signal.

0

AED comparison fail

1 = indicates that the SED logic detected an invalid input

data pattern comparison against the preprogrammed

expected values. This is a latched signal that automatically

clears when eight valid I/Q data pairs are received.

2

SED comparison fail

1 = indicates that the SED logic detected an invalid input

data pattern comparison against the preprogrammed

expected values. This is a latched signal.

Note that all bit event flags are cleared by writing the respective bit high.

Clock

08

ꢀ

DACCLK duty correction

1 = enables duty-cycle correction on DACCLK input.

0

Receiver

Control

6

5

REFCLK duty correction

1 = enables duty-cycle correction on REFCLK input.

0

DACCLK cross-

correction

1 = enables differential crossing correction on the CLK input.

4

ꢀ

6

REFCLK cross-

correction

1 = enables differential crossing correction on the

REFCLK input.

0

1

PLL

Control

0A

0B

PLL enable

1 = enables the PLL clock multiplier. REFCLK input is used

as the PLL reference clock signal.

PLL manual enable

Enables the manual selection of the VCO band.

1 = manual mode; the correct VCO band must be

determined by the user.

5:0

5

Manual VCO band

PLL VCO enable

Selects the VCO band to be used.

0 = disables the PLL VCO.

0

PLL

Control

1 = enables the PLL VCO. Set this bit high prior to

enabling PLL.

Rev. 0 | Page 23 of 56

AD9122

Reg

Name

Addr

(Hex)

Bit

Name

Description

Default

PLL

0C

ꢀ:6

PLL Loop

Selects the PLL loop filter bandwidth.

3

Control

Bandwidth[1:0]

00 = narrowest bandwidth.

01 = narrow/medium bandwidth.

10 = medium/wide bandwidth.

11 = widest bandwidth.

4:0

ꢀ:6

PLL Charge Pump

Current[4:0]

Sets the nominal PLL charge pump current.

001

3

00000 = lowest current setting.

11111 = highest current setting.

PLL

Control

0D

N2[1:0]

PLL control clock divider. It determines the ratio of the

DACCLK rate to the PLL controller clock rate.

00 = f_DACCLK/f_{PC_CLK}= 2.

01 = f_DACCLK/f_{PC_CLK}= 4.

10 = f_DACCLK/f_{PC_CLK}= 8.

11 = f_DACCLK/f_{PC_CLK}= 16.

f_{PC_CLK}must always be less than 50 MHz.

4

PLL cross control enable Enable PLL cross point controller.

0

3:2

N0[1:0]

PLL VCO divider. It determines the ratio of the VCO

01

output to the DACCLK frequencies.

00 = f_VCO/f_DACCLK= 1.

01 = f_VCO/f_DACCLK= 2.

10 = f_VCO/f_DACCLK= 4.

11 = f_VCO/f_DACCLK= 4.

1:0

N1[1:0]

PLL Loop divider. It determines the ratio of the DACCLK to

the REFCLK frequencies.

01

00 = f_DACCLK/f_REFCLK= 2.

01 = f_DACCLK/f_REFCLK= 4.

10 = f_DACCLK/f_REFCLK= 8.

11 = f_DACCLK/f_REFCLK= 16.

PLL

Status

0E

ꢀ

PLL lock

The PLL generated clock is tracking the REFCLK input signal.

VCO Control Voltage readback. See Table 24.

R

3:0

VCO Control

Voltage[3:0]

PLL

Status

0F

10

5:0

VCO Band

Readback[5:0]

Indicates the VCO band currently selected.

R

Sync

Control

ꢀ

6

Sync enable

1 = enables the synchronization logic.

0

Data/FIFO rate toggle

0 = operates the synchronization at the FIFO reset rate.

1 = operates the synchronization at the data rate.

0 = sync is initiated on the falling edge of the sync input.

1 = sync is initiated on the rising edge of the sync input.

3

Rising edge sync

1

0

2:0

Sync Averaging[2:0]

Sets the number of input samples that are averaged in

determining the sync phase.

000 = 1.

001 = 2.

010 = 4.

011 = 8.

100 = 16.

101 = 32.

110 = 64.

111 = 128.

Rev. 0 | Page 24 of 56

AD9122

Reg

Name

Addr

(Hex)

Bit

Name

Description

Default

0

Sync

Control

11

5:0

Sync Phase Request[5:0] This sets the requested clock phase offset after sync. The

offset unit is in DACCLK cycles.

000000 = 0 DACCLK cycles.

000001 = 1 DACCLK cycle.

…

111111 = 63 DACCLK cycles.

This enables repositioning of the DAC output with respect

to the sync input. The offset can also be used to skew the

DAC outputs between the synchronized DACs.

Sync

Status

12

13

ꢀ

Sync lost

1 = indicates that synchronization had been attained but

has been lost.

R

6

Sync locked

1 = indicates that synchronization has been attained.

Indicates the averaged sync phase offset (6.2 format).

R

Sync

ꢀ:0

Sync Phase Readback[ꢀ:0]

Status

00000000 = 0.0.

00000001 = 0.25.

…

11111110 = 63.50.

11111111 = 63.ꢀ5.

If this value differs from the requested sync phase value,

this indicates sync timing errors.

Data

Receiver

Status

15

5

4

LVDS FRAME level high

LVDS FRAME level low

One or both of the LVDS FRAME input signals

have exceeded 1.ꢀ V.

R

One or both of the LVDS FRAME input signals

have crossed below 0.ꢀ V.

3

2

LVDS DCI level high

LVDS DCI level low

One or both of the LVDS DCI input signals have exceeded 1.ꢀ V.

One or both of the LVDS DCI input signals have crossed

below 0.ꢀ V.

R

1

LVDS data level high

LVDS data level low

FIFO Phase Offset[2:0]

One or more of the LVDS Dx input signals have

exceeded 1.ꢀ V.

R

0

One or both of the LVDS Dx input signals have crossed

below 0.ꢀ V.

FIFO

1ꢀ

2:0

FIFO write pointer phase offset following FIFO reset.

Control

000 = 0.

001 = 1.

…

111 = ꢀ.

This is the difference between the read pointer and the

write pointer values upon FIFO reset. The optimal value is

nominally 4.

FIFO

Status

18

19

ꢀ

6

2

FIFO Warning 1

FIFO Warning 2

FIFO read and write pointers within 1.

FIFO read and write pointers within 2.

0

FIFO soft align

acknowledge

FIFO read and write pointers are aligned after serial

port initiated FIFO reset.

1

FIFO soft align request

Request FIFO read and write pointers alignment via

serial port.

0

FIFO reset aligned

FIFO Level[ꢀ:0]

FIFO read and write pointers aligned after hardware reset.

Thermometer encoded measure of the FIFO level.

0

FIFO

Status

ꢀ:0

Rev. 0 | Page 25 of 56

AD9122

Reg

Name

Addr

(Hex)

Bit

ꢀ

Name

Description

Default

Datapath 1B

Control

Bypass Premod

Bypass Sinc⁻¹

Bypass NCO

NCO gain

1 = bypasses f_S/2 premodulator.

1 = bypasses inverse sinc filter.

1 = bypasses NCO.

1

0

6

5

3

0 = default. No gain scaling is applied to the NCO input to

the internal digital modulator.

1 = gain scaling of 0.5 is applied to the NCO input to the

internal digital modulator. This can eliminate saturation

of the modulator output for some combinations of data

inputs and NCO signals.

2

1

Bypass phase

compensation and

dc offset

1 = bypasses phase compensation.

1

0

Select sideband

0 = the modulator outputs high-side image.

1 = the modulator outputs low-side image. The image is

spectrally inverted compared to the input data.

0

Send I data to Q data

HB1[1:0]

1 = ignores Q data from interface and disables the clocks

to Q datapath. Sends I data to both I and Q DACs.

0

HB1

1C

2:1

00 = input signal not modulated, filter pass band is from

Control

−0.4 to +0.4 of f_IN1

01 = input signal not modulated, filter pass band is from

0.1 to 0.9 of f_IN1

10 = input signal modulated by f_IN1, filter pass band is from

0.6 to 1.4 of f_IN1

11 = input signal modulated by f_IN1, filter pass band is from

1.1 to 1.9 of f_IN1

.

0

Bypass HB1

HB2[5:0]

1 = bypasses first stage interpolation filter.

0

HB2

1D

6:1

Modulation mode for I Side Half-Band Filter 2.

Control

000000 = input signal not modulated, filter pass band is

from −0.25 to +0.25 of f_IN2

001001 = input signal not modulated, filter pass band is

from 0.0 to 0.5 of f_IN2

010010 = input signal not modulated, filter pass band is

from 0.25 to 0.ꢀ5 of f_IN2

011011 = input signal not modulated, filter pass band is

from 0.5 to 1.0 of f_IN2

100100 = input signal modulated by f_IN2, filter pass band is

from 0.ꢀ5 to 1.25 of f_IN2

101101 = input signal modulated by f_IN2, filter pass band is

from 1.0 to 1.5 of f_IN2

110110 = input signal modulated by f_IN2, filter pass band is

from 1.25 to 1.ꢀ5 of f_IN2

111111 = input signal modulated by f_IN2, filter pass band is

from 1.5 to 2.0 of f_IN2

.

0

Bypass HB2

1 = bypasses second stage interpolation filter.

0

Rev. 0 | Page 26 of 56

AD9122

Reg

Name

Addr

(Hex)

Bit

Name

Description

Default

HB3

Control

1E

6:1

HB3[5:0]

Modulation mode for I Side Half-Band Filter 3.

000000 = input signal not modulated, filter pass band is

0

from −0.2 to +0.2 of f_IN3

001001 = input signal not modulated, filter pass band is

from 0.05 to 0.45 of f_IN3

010010 = input signal not modulated, filter pass band is

from 0.3 to 0.ꢀ of f_IN3

011011 = input signal not modulated, filter pass band is

from 0.55 to 0.95 of f_IN3

100100 = input signal modulated by f_IN3, filter pass band is

from 0.8 to 1.2 of f_IN3

101101 = input signal modulated by f_IN3, filter pass band is

from 1.05 to 1.45 of f_IN3

110110 = input signal modulated by f_IN3, filter pass band is

from 1.3 to 1.ꢀ of f_IN3

111111 = input signal modulated by f_IN3, filter pass band is

from 1.55 to 1.95 of f_IN3

.

0

Bypass HB3

Chip ID[ꢀ:0]

FTW[ꢀ:0]

1 = bypasses third stage interpolation filter.

Chip ID.

0

8

0

Chip ID

1F

ꢀ:0

FTW LSB 30

See Register 0x33.

FTW

31

32

33

FTW[15:8]

FTW[23:16]

FTW[31:24]

See Register 0x33.

FTW

MSB

FTW[31:0] is the 32-bit frequency tuning word that

determines the frequency of the complex carrier

generated by the on-chip NCO. The frequency is not

updated when the FTW registers are written. The values

are only updated when Bit 0 of Register 0x36 transitions

from 0 to 1.

NCO

Phase

Offset

LSB

34

35

36

ꢀ:0

NCO Phase Offset[ꢀ:0]

NCO Phase Offset[15:8]

See Register 0x35.

0

NCO

The NCO sets the phase of the complex carrier signal

when the NCO is reset. The phase offset spans between 0°

and 360°. Each bit represents an offset of 0.0055°. Value is

in twos complement format.

Phase

Offset

MSB

NCO

FTW

Update

5

4

1

FRAME FTW

acknowledge

1 = indicates that the NCO has been reset due to an

extended FRAME pulse signal.

0

FRAME FTW request

0 → 1 = the NCO is reset on the first extended FRAME

pulse after this bit transitions from 0 to 1.

Update FTW

acknowledge

1 = indicates that the FTW has been updated.

0

Update FTW request

I Phase Adj[ꢀ:0]

0

0 → 1 = the FTW is updated on 0-to-1 transition of this bit.

I Phase

Adj LSB

38

39

ꢀ:0

See Register 0x39.

I Phase

Adj MSB

1:0

I Phase Adj[9:8]

I Phase Adj[9:0] is used to insert a phase offset between

the I and Q datapaths. This can be used to correct for

phase imbalance in a quadrature modulator. See the

Quadrature Phase Correction section for details.

0

Q Phase

Adj LSB

3A

3B

ꢀ:0

1:0

Q Phase Adj[ꢀ:0]

Q Phase Adj[9:8]

See Register 0x3B.

0

Q Phase

Adj MSB

Q Phase Adj[9:0] is used to insert a phase offset between

the I and Q datapaths. This can be used to correct for

phase imbalance in a quadrature modulator. See the

Quadrature Phase Correction section for details.

Rev. 0 | Page 2ꢀ of 56

AD9122

Reg

Name

Addr

(Hex)

Bit

Name

Description

Default

I DAC

Offset

LSB

3C

3D

3E

3F

40

ꢀ:0

I DAC Offset[ꢀ:0]

I DAC Offset[15:0] is a value added directly to the samples

written to the I DAC.

0

I DAC

Offset

MSB

ꢀ:0

I DAC Offset[15:8]

Q DAC Offset[ꢀ:0]

Q DAC Offset[15:8]

I DAC FS Adj[ꢀ:0]

See Register 0x3C.

0

Q DAC

Offset

LSB

Q DAC Offset[15:0] is a value added directly to the samples

written to the Q DAC.

0

Q DAC

Offset

MSB

See Register 0x3E.

0

I DAC

FS Adjust

I DAC FS Adj[9:0] sets the full-scale current of the I DAC.

The full-scale current can be adjusted from 8.64 mA to

31.6 mA in step sizes of approximately 22.5 μA.

F9

0x000 = 8.64 mA.

…

0x200 = 20.14 mA.

…

0x3FF = 31.66 mA.

I DAC

Control

41

ꢀ

I DAC sleep

1 = puts the I-channel DAC into sleep mode (fast

wake-up mode).

0

1:0

ꢀ:0

I DAC FS Adj[9:8]

I Aux DAC[ꢀ:0]

See Register 0x40.

1

0

Aux DAC 42

I Data

I Aux DAC[9:0] sets the magnitude of the auxiliary DAC

current. The range is 0 mA to 2 mA and the step size is 2 μA.

0x000 = 0.000 mA.

0x001 = 0.002 mA.

…

0x3FF = 2.046 mA.

I Aux

DAC

Control

43

ꢀ

6

I aux DAC sign

0 = the auxiliary DAC I sign is positive, and the current is

directed to the IOUT1P pin (Pin 6ꢀ).

0

1 = the auxiliary DAC I sign is negative, and the current is

directed to the IOUT1N pin (Pin 66).

I aux DAC current

direction

0 = the auxiliary DAC I sources current.

1 = the auxiliary DAC I sinks current.

I channel auxiliary DAC sleep.

See Register 0x42.

5

I aux DAC sleep

I Aux DAC[9:8]

0

1:0

ꢀ:0

0

Q DAC

FS Adj.

44

Q DAC FS Adj[ꢀ:0]

Q DAC FS Adj[9:0] sets the full-scale current of

F9

the I DAC. The full-scale current can be adjusted from

8.64 mA to 31.6 mA in step sizes of approximately 22.5 μA.

0x000 = 8.64 mA.

…

0x200 = 20.14 mA.

…

0x3FF = 31.66 mA.

Q DAC

Control

45

ꢀ

Q DAC sleep

1 = puts the Q-channel DAC into sleep mode (fast

wake-up mode).

0

1

1:0

Q DAC FS Adj[9:8]

See Register 0x44.

Rev. 0 | Page 28 of 56

AD9122

Reg

Name

Addr

(Hex)

Bit

Name

Description

Default

Aux DAC 46

Q Data

ꢀ:0

Q Aux DAC[ꢀ:0]

Q Aux DAC[9:0] sets the magnitude of the aux DAC current.

The range is 0 mA to 2 mA and the step size is 2 μA.

0

0x000 = 0.000 mA.

0x001 = 0.002 mA.

…

0x3FF = 2.046 mA.

Q Aux

DAC

Control

4ꢀ

ꢀ

6

Q aux DAC sign

0 = the auxiliary DAC Q sign is positive, and the current is

directed to the IOUT2P pin (Pin 58).

1 = the auxiliary DAC Q sign is negative, and the current is

directed to the IOUT2N pin (Pin 59).

0

Q aux DAC current

direction

0 = the auxiliary DAC Q sources current.

1 = the auxiliary DAC Q sinks current.

Q-channel auxiliary DAC sleep

5

Q aux DAC sleep

Q Aux DAC[9:8]

FS Current[2:0]

0

1:0

6:4

See Register 0x46.

DieTemp 0x48

Range

Control

Auxiliary ADC full-scale current.

000 = lowest current.

…

111 = highest current.

Auxiliary ADC reference current.

000 = lowest current.

111 = highest current.

Auxiliary ADC internal capacitor value.

0 = 5 pF.

3:1

0

Reference Current[2:0]

Capacitor value

1

0

1 = 10 pF.

Die

Temp

LSB

49

4A

ꢀ:0

Die Temp[ꢀ:0]

Die Temp[15:8]

See Register 0x4A.

R

Die

Die Temp[15:0] indicates the approximate die

temperature.

Temp

MSB

0xADCC = −39.9°C

0xC422 = 25.1°C

…

0xD8A8 = 84.8°C (see Temperature Sensor section for details)

SED

Control

6ꢀ

ꢀ

SED compare enable

1 = enables the SED circuitry. None of the flags in this

register or the values in Register 0xꢀ0 through

0

Register 0xꢀ3 are significant if the SED is not enabled.

5

3

Sample error detected

Autoclear enable

1 = indicates an error is detected. The bit remains set until

cleared. Any write to this register clears this bit to 0.

0

1 = enables autoclear mode. This activates Bit 1 and Bit 0

of this register and causes Register 0xꢀ0 through

Register 0xꢀ3 to be autocleared whenever eight

consecutive sample data sets are received error free.

1

Compare fail

1 = indicates an error has been detected. This bit remains

high until it is autocleared by the reception of eight

consecutive error free comparisons or is cleared by

writing to this register.

0

Compare pass

1 = indicates that the last sample comparison was error free.

0

Compare 68

I0 LSBs

ꢀ:0

Compare Value I0[ꢀ:0]

Compare Value I0[15:0] is the word that is compared

with the I0 input sample captured at the input interface.

B6

Compare 69

I0 MSBs

ꢀ:0

Compare Value I0[15:8]

Compare Value Q0[ꢀ:0]

See Register 0x68.

ꢀA

45

Compare 6A

Q0 LSBs

Compare Value Q0[15:0] is the word that is compared

with the Q0 input sample captured at the input interface.

Rev. 0 | Page 29 of 56

AD9122

Reg

Name

Addr

(Hex)

Bit

Name

Description

Default

Compare 6B

Q0 MSBs

ꢀ:0

Compare Value Q0[15:8] See Register 0x6A

EA

Compare 6C

I1 LSBs

ꢀ:0

Compare Value I1[ꢀ:0]

Compare Value I1[15:8]

Compare Value Q1[ꢀ:0]

Compare Value I1[15:0] is the word that is compared

with the I1 input sample captured at the input interface.

16

1A

C6

AA

0

Compare 6D

I1 MSBs

See Register 0x6C.

Compare 6E

Q1 LSBs

Compare Value Q1[15:0] is the word that is compared

with the Q1 input sample captured at the input interface.

Compare 6F

Q1 MSBs

Compare Value Q1[15:8] See Register 0x6E.

SED I

LSBs

ꢀ0

ꢀ1

ꢀ2

ꢀ3

Errors Detected

I_BITS[ꢀ:0]

Errors Detected I_BITS[15:0] indicates which bits were

received in error.

SED I

MSBs

Errors Detected

I_BITS[15:8]

See Register 0xꢀ0.

0

SED Q

LSBs

Errors Detected

Q_BITS[ꢀ:0]

Errors Detected Q_BITS[15:0] indicates which bits were

received in error.

0

SED Q

MSBs

Errors Detected

Q_BITS[15:8]

See Register 0xꢀ2.

0

Rev. 0 | Page 30 of 56

AD9122

LVDS INPUT DATA PORTS

The AD9122 has one LVDS data port that receives data for both

the I and Q transmit paths. The device can accept data in word,

byte, and nibble formats. In word, byte, and nibble modes, the data

is sent over 16-bit, 8-bit, and 4-bit LVDS data busses, respectively.

The pin assignment of the bus in each mode is shown in Table 12.

with DCI being high, and the least significant byte of the data

should correspond with DCI being low. The FRAME signal

indicates to which DAC the data is sent. When FRAME is high,

data is sent to the I DAC, and when FRAME is low, data is sent

to the Q DAC. The complete timing diagram is shown in Figure 42.

NIBBLE INTERFACE MODE

Table 12. Data Bit Pair Assignments for Data Input Modes

In nibble mode, the DCI signal is a reference bit used for

generating the data sampling clock and should be time aligned

with the data. The FRAME signal indicates to which DAC the

data is sent. When FRAME is high, data is sent to the I DAC.

When FRAME is low, data is sent to the Q DAC. All four nibbles

must be written to the device for proper operation. For 12-bit

resolution devices, the data in the fourth nibble acts as a place

holder for the data framing structure. The complete timing

diagram is shown in Figure 43.

Mode

MSB, …, LSB

Word

D15, D14, …, D0

D14, D12, D10, D8, Dꢀ, D5, D3, D1

D10, D8, Dꢀ, D5

Byte¹

Nibble¹

¹In byte and nibble modes, the unused pins can be left floating.

The data is accompanied by a reference bit (DCI) that is used to

generate a double data rate (DDR) clock. In byte and nibble modes,

a FRAME signal is required for controlling to which DAC the

data is sent. All of the interface signals are time aligned. While

there is a maximum skew requirement on the bus, there are no

setup and hold times to be met.

FIFO OPERATION

The AD9122 contains a 2-channel, 16-bit wide, eight-word deep

FIFO designed to relax the timing relationship between the data

arriving at the DAC input ports and the internal DAC data rate

clock. The FIFO acts as a buffer that absorbs timing variations

between the data source and DAC, such as the clock-to-data

variation of an FPGA or ASIC, which significantly increases the

timing budget of the interface.

WORD INTERFACE MODE

In word mode, the DCI signal is a reference bit used for

generating the data sampling clock. Time align the DCI

signal with the data. The I DAC data should correspond

with DCI being high and the Q DAC data with DCI being

low, as illustrated in Figure 41.

Figure 44 shows the block diagram of the datapath through the

FIFO. The data is latched into the device, is formatted, and is

then written into the FIFO register determined by the FIFO write

pointer. The value of the write pointer is incremented every time a

new word is loaded into the FIFO. Meanwhile, data is read from

the FIFO register determined by the read pointer and fed into

the digital datapath. The value of the read pointer is updated

every time data is read into the datapath from the FIFO. This

happens at the data rate, that is, the DACCLK rate divided by the

interpolation ratio.

DCI

Q

I

Q

I

Q

I

Q

3

DATA[15:0]

0

1

2

3

Figure 41. Timing Diagram for Word Mode

BYTE INTERFACE MODE

In byte mode, the DCI signal is a reference bit used for generating

the data sampling clock and should be time aligned with the

data. The most significant byte of the data should correspond

DCI

Q

I

Q

I

Q

2LSB

DATA[15:0]

FRAME

LSB

1MSB

1LSB

1MSB

1LSB

2MSB

2LSB

2MSB

Figure 42. Timing Diagram for Byte Mode

DCI

DATA[15:0]

FRAME

Q

I

Q

2N3

0N0

1N3

1N2

1N1

1N0

1N3

1N2

1N1

1N0

Figure 43. Timing Diagram for Nibble Mode

Rev. 0 | Page 31 of 56

AD9122

32 BITS

REG 0

REG 1

REG 2

REG 3

REG 4

REG 5

REG 6

REG 7

16

DATA

PATHS

INPUT

LATCH

DATA

ASSEMBLER

DACS

DATA

WRITE POINTER

READ POINTER

DACCLK

DCI

32 BITS

÷ INT

Figure 44. Block Diagram of FIFO

Valid data is transmitted through the FIFO as long as the

FIFO does not overflow or become empty. Note that an over-

flow or empty condition of the FIFO is the same as the write

pointer and read pointer being equal. When both pointers are

equal, an attempt is made to read and write a single FIFO register

simultaneously. This simultaneous register access leads to

unreliable data transfer through the FIFO and must be avoided.

To initialize the FIFO data level through the serial port, Bit 1 of

Register 0x18 should be toggled from 0 to 1 and back. When the

write to the register is complete, the FIFO data level is initialized.

This method operates similar to the method previously described.

When the initialization is triggered, the next time the read

pointer becomes 0, the write pointer is set to the value of the FIFO

start level (Register 0x17, Bits[2:0]) variable upon initialization. By

default, this is 4 but can be programmed to a value of 0 to 7.

Nominally, data is written to the FIFO at the same rate that data

is read from the FIFO, which keeps the data level in the FIFO

constant. If data is written to the FIFO faster than data is read,

the data level in the FIFO increases. If the data is written to the

device slower than data is read, the data level in the FIFO decreases.

For optimum timing margin, the FIFO level should be maintained

near half full, which is the same as maintaining a difference of

four between the write pointer and read pointer values.

The recommended procedure for a serial port FIFO data level

initialization is as follows:

•

Request FIFO level reset by setting Register 0x18, Bit 1 to 1.

Verify the part acknowledges the request by ensuring

Register 0x18, Bit 2 is 1.

•

Remove the request by setting Register 0x18, Bit 1 to 0.

Verify the part drops the acknowledge signal by ensuring

Register 0x18, Bit 2 is 0.

Resetting the FIFO Data Level

Monitoring the FIFO Status

To maximize the timing margin between the DCI input and

the internal DAC data rate clock, the FIFO data level should be

initialized prior to beginning data transmission. The value of

the FIFO data level can be initialized in three ways; by resetting

the device, by strobing the FRAME input, and via a write sequence

to the serial port. The two preferred methods are by using of the

FRAME signal and by issuing a command.

The FIFO initialization and status can be read from Register 0x18.

This register provides information on the FIFO initialization

method, and whether the initialization was successful. The MSB

of Register 0x18 is a FIFO warning flag that can optionally

trigger a device IRQ. This flag is an indication that the FIFO

is close to emptying (FIFO level is 1) or overflowing (FIFO level

is 7). This is an indication that data may soon be corrupted, and

action should be taken.

As discussed in the Byte Interface Mode and Nibble Interface

Mode sections, the FRAME input is used as a data select signal

that indicates to which DACs the input data is written. The second

function of the FRAME input is initializing the FIFO data level

value. This is done by asserting the FRAME signal high for at

least the time interval needed to load complete data to the I and

Q DACs. This corresponds to one DCI period in word mode,

two DCI periods in byte mode, and four DCI periods in nibble

mode. When FRAME is asserted in this manner, the write pointer

is set to 4 (by default or to the FIFO start level) the next time

the read pointer becomes 0 (see Figure 45).

The FIFO data level can be read from Register 0x19 at any time.

The serial port reported FIFO data level is denoted as a 7-bit

thermometer code of the write counter state relative to the absolute

read counter being at 0. The optimum FIFO data level of 4 is

therefore reported as a value of 00001111 in the status register.

It should be noted that, depending on the timing relationship

between DCI and the main DACCLK, the FIFO level value can be

off by 1 count. Therefore, it is important to keep the difference

between the read and write pointers to at least 2.

READ

POINTER

0

1

2

3

4

5

6

7

0

1

2

3

FIFO WRITE RESETS

FRAME

WRITE

POINTER

3

4

5

6

7

0

1

2

4

5

6

7

Figure 45. Timing of the FRAME Input vs. Write Pointer Value

Rev. 0 | Page 32 of 56

AD9122

In data rate mode, a second timing constraint between DCI and

DACCLK must be met in addition to the DCI-to-DATA timing

shown in Table 14. In data rate mode, only one FIFO slot is being

used. The DCI to DACCLK timing restriction is required to

prevent data being written to and read from the FIFO slot at the

same time. The required timing between DCI and DACCLK is

shown in Figure 47.

INTERFACE TIMING

The timing diagram for the digital interface port is shown

in Figure 46. The sampling point of the data bus occurs about

350 ps after each edge of the DCI signal and has an uncertainty

of 300 ps, as illustrated by the sampling interval shown in

Figure 46. The DATA and FRAME signals must be valid

throughout this sampling interval. The DATA and FRAME

signals may change at any time between sampling intervals.

The setup (t_S) and hold (t_H) times with respect to the edges

are shown in Figure 46. The minimum setup and hold times

are shown in Table 13.

t_DATA

DACCLK/

REFCLK

SAMPLING

INTERVAL

t_DATA

DCI

SAMPLING

INTERVAL

SAMPLING

INTERVAL

t_SDCI

t_HDCI

DATA

Figure 47. Timing Diagram for Input Data Port (Data Rate Mode)

Table 14. Data Port Setup and Hold Times

t_S

Parameter

Time (ps)

t_H

t_{SDCI (MIN)}

−120

t_{HDCI (MIN)}

820

Figure 46. Timing Diagram for Input Data Ports

Table 13. Data Port Setup and Hold Times

Parameter

Time (ps)

t_{S (MIN)}

t_{H (MIN)}

−50

650

The data interface timing can be verified by using the sample

error detection (SED) circuitry. See the Interface Timing

Validation section for details.

Rev. 0 | Page 33 of 56

AD9122

DIGITAL DATAPATH

The block diagram in Figure 48 shows the functionality of the

digital datapath. The digital processing includes a premodulation

block, three half-band interpolation filters, a quadrature modulator

with a fine resolution NCO, phase and offset adjustment blocks,

and an inverse sinc filter.

Half-Band Filter 1 (HB1)

HB1 has four modes of operation, as shown in Figure 49. The

shape of the filter response is identical in each of the four modes.

The four modes are distinguished by two factors, the filter center

frequency and whether or not the input signal is modulated by

the filter.

PHASE

MODE 0

MODE 2

MODE 1

MODE 3

AND

–1

0

PREMOD

HB1

HB2

HB3

SINC

OFFSET

ADJUST

Figure 48. Block Diagram of Digital Datapath

–20

The digital datapath accepts I and Q data streams and processes

them as a quadrature data stream. The signal processing blocks can

be used when the input data stream is represented as complex data.

–40

–60

The datapath can be used to process an input data stream

representing two independent real data streams as well, but

the functionality is somewhat restricted. The premodulation

block can be used. As well as, any of the nonshifted interpolation

filter modes. See the Premodulation section for more details.

–80

–100

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

PREMODULATION

(× f_IN1

)

Figure 49. HB1 Filter Modes

The half-band interpolation filters have selectable pass bands

that allow the center frequencies to be moved in increments of

½ of their input data rate. The premodulation block provides a

digital upconversion of the incoming waveform by ½ of the

incoming data rate, f_DATA. This can be used to frequency shift

baseband input data to the center of the interpolation filters

pass band.

As is shown in Figure 49, the center frequency in each mode is

offset by ½ of the input data rate (f_IN1) of the filter. Mode 0 and

Mode 1 do not modulate the input signal. Mode 2 and Mode 3

modulate the input signal by f_IN1. When operating in Mode 0

and Mode 2, the I and Q paths operate independently and no

mixing of the data between channels occurs. When operating

in Mode 1 and Mode 3, mixing of the data between the I and Q

paths occurs; therefore, the data input into the filter is assumed

complex. Table 15 summarizes the HB1 modes.

INTERPOLATION FILTERS

The transmit path contains three interpolation filters. Each of

the three interpolation filters provides a 2× increase in output data

rate. The half-band (HB) filters can be individually bypassed or

cascaded to provide 1×, 2×, 4×, or 8× interpolation ratios. Each

of the half-band filter stages offers a different combination of

bandwidths and operating modes.

Table 15. HB1 Filter Mode Summary

Mode

f_CENTER

f_MOD

None

f_IN

Input Data

Real or complex

Complex

Real or complex

Complex

0

1

2

3

DC

f_IN/2

f_IN

The bandwidth of the three half-band filters with respect to the

data rate at the filter input is as follows:

3f_IN/2

f_IN

•

Bandwidth of HB1 = 0.8 × f_IN1

Bandwidth of HB2 = 0.5 × f_IN2

Bandwidth of HB3 = 0.4 × f_IN3

The usable bandwidth is defined as the frequency over which

the filters have a pass-band ripple of less than 0.001 dB and an

image rejection of greater than +85 dB. As is discussed in the

Half-Band Filter 1 (HB1) section, the image rejection usually sets

the usable bandwidth of the filter, not the pass-band flatness.

The half-band filters operate in several modes, providing

programmable pass-band center frequencies as well as signal

modulation. The HB1 filter has four modes of operation and

the HB2 and HB3 filters each have eight modes of operation.

Rev. 0 | Page 34 of 56

AD9122

Figure 50 shows the pass-band filter response for HB1. In most

applications, the usable bandwidth of the filter is limited by the

image suppression provided by the stop-band rejection and not

by the pass-band flatness. Table 16 shows the pass-band flatness

and stop-band rejection the HB1 filter supports at different

bandwidths.

Half-Band Filter 2 (HB2)

HB2 has eight modes of operation, as shown in Figure 51 and

Figure 52. The shape of the filter response is identical in each of

the eight modes. The eight modes are distinguished by two factors,

the filter center frequency and whether the input signal is

modulated by the filter.

0.02

MODE 0

MODE 4

MODE 2

MODE 6

0

–0.02

–0.04

–0.06

–0.08

–0.10

–20

–40

–60

–80

–100

0

0.04 0.08 0.12 0.16 0.20 0.24 0.28 0.32 0.36 0.40

(× f_IN1

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

)

(× f_IN2

)

Figure 50. Pass-Band Detail of HB1

Figure 51. HB2, Even Filter Modes

MODE 7

MODE 5

MODE 1

MODE 3

Table 16. HB1 Pass-Band and Stop-Band Performance by

Bandwidth

0

–20

Pass-Band

Stop-Band

Rejection (dB)

Bandwidth (% of f_IN1

)

Flatness (dB)

80

0.001

85

80

ꢀ0

60

50

40

–40

80.4

81.2

82.0

83.6

85.6

0.0012

0.0033

0.00ꢀ6

0.02ꢀ1

0.1096

–60

–80

–100

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

(× f_IN2

)

Figure 52. HB2, Odd Filter Modes

As shown in Figure 51 and Figure 52, the center frequency in

each mode is offset by ¼ of the input data rate (f_IN2) of the filter.

Mode 0 through Mode 3 do not modulate the input signal. Mode 4

through Mode 7 modulate the input signal by f_IN2. When operating

in Mode 0 and Mode 4, the I and Q paths operate independently

and no mixing of the data between channels occurs. When

operating in the other six modes, mixing of the data between

the I and Q paths occurs; therefore, the data input to the filter

is assumed complex.

Rev. 0 | Page 35 of 56

AD9122

Table 17 summarizes the HB2 and HB3 modes.

Half-Band Filter 3 (HB3)

HB3 has eight modes of operation that function the same as

HB2. The primary difference between HB2 and HB3 are the

filter bandwidths.

Table 17. HB2 and HB3 Filter Mode Summary

Mode

f_CENTER

f_MOD

None

f_IN

Input Data

Real or complex

Complex

Real or complex

Complex

0

1

2

3

4

5

6

ꢀ

DC

f_IN/8

f_IN/4

3f_IN/8

f_IN/2

5f_IN/8

3f_IN/4

ꢀf_IN/8

0.02

0

–0.02

–0.04

–0.06

–0.08

–0.10

Complex

Figure 53 shows the pass-band filter response for HB2. In most

applications, the usable bandwidth of the filter is limited by the

image suppression provided by the stop-band rejection and not

by the pass-band flatness. Table 18 shows the pass-band flatness

and stop-band rejection the HB2 filter supports at different

bandwidths.

0

0.04 0.08 0.12 0.16 0.20 0.24 0.28 0.32 0.36 0.40

(× f_IN3

)

Figure 54. Pass-Band Detail of HB3

0.02

Figure 54 shows the pass-band filter response for HB3. In most

applications, the usable bandwidth of the filter is limited by the

image suppression provided by the stop-band rejection and not

by the pass-band flatness. Table 19 shows the pass-band flatness

and stop-band rejection the HB3 filter supports at different

bandwidths.

0

–0.02

–0.04

–0.06

–0.08

–0.10

Table 19. HB3 Pass-Band and Stop-Band Performance by

Bandwidth

Pass-Band

Flatness (dB)

Stop-Band

Rejection (dB)

Bandwidth (% of f_IN3

)

40

0.001

0.0014

0.002

0.0093

0.03

85

80

ꢀ0

60

50

40

0

0.04

0.08

0.12

0.16

0.20

0.24

0.28

0.32

40.8

42.4

45.6

49.8

55.6

(× f_IN2

)

Figure 53. Pass-Band Detail of HB2

Table 18. HB2 Pass-Band and Stop-Band Performance by

Bandwidth

0.1

Pass-Band

Flatness (dB)

Stop-Band

Rejection (dB)

Bandwidth (% of f_IN2

)

50

0.001

85

80

ꢀ0

60

50

40

50.8

52.8

56.0

60

0.0012

0.0028

0.0089

0.028ꢀ

0.18ꢀꢀ

64.8

Rev. 0 | Page 36 of 56

AD9122

INTERPOLATION

FTW[31:0]

I DATA

COSINE

NCO

SINE

NCO PHASE OFFSET

[15:0]

OUT_I

OUT_Q

–

+

–1

1

SPECTRAL

INVERSION

0

INTERPOLATION

Q DATA

Figure 55. Digital Quadrature Modulator Block Diagram

Given these four parameters, the first step in configuring the

datapath is to verify that the device supports the bandwidth

requirements. The modes of the interpolation filters are then

chosen. Finally, any additional frequency offset requirements

are determined and applied with premodulation and NCO

modulation.

NCO MODULATION

The digital quadrature modulator makes use of a numerically

controlled oscillator, a phase shifter, and a complex modulator

to provide a means for modulating the signal by a programmable

carrier signal. A block diagram of the digital modulator is shown in

Figure 55. The fine modulation provided by the digital modulator,

in conjunction with the coarse modulation of the interpolation

filters and premodulation block, allows the signal to be placed

anywhere in the output spectrum with very fine frequency

resolution.

Determining Datapath Signal Bandwidth

The available signal bandwidth of the datapath is dependent on

the center frequency of the output signal in relation to the center

frequency of the interpolation filters used. Signal center frequencies

offset from the center frequencies of the half-band filters lower

the available signal bandwidth.

The quadrature modulator is used to mix the carrier signal

generated by the NCO with the I and Q signal. The NCO produces

a quadrature carrier signal to translate the input signal to a new

center frequency. A complex carrier signal is a pair of sinusoidal

waveforms of the same frequency, offset 90° from each other.

The frequency of the complex carrier signal is set via FTW[31:0]

in Register 0x30 through Register 0x33.

When correctly configured, the available complex signal band-

width for 2× interpolation is always 80% of the input data rate.

The available signal bandwidth for 4× interpolation vs. output

frequency varies between 50% and 80% of the input data rate,

as shown in Figure 56. Note that in 4× interpolation mode,

f_DAC= 4 × f_DATA; therefore, the data shown in Figure 56 repeats

The NCO operating frequency, f_NCO, is at either f_DATA(HB1

bypassed) or twice f_DATA(HB1 enabled). The frequency of

the complex carrier signal can be set from dc up to f_NCO. The

frequency tuning word (FTW) is calculated as

four times from dc to f_DAC

.

HB1 AND HB2

0.8

f_CARRIER

f_NCO

FTW =

×2³²

0.5

0.3

The generated quadrature carrier signal is mixed with the I and

Q data. The quadrature products are then summed into the I

and Q data paths, as shown in Figure 55.

HB2 AND HB3

Updating the Frequency Tuning Word

The frequency tuning word registers are not updated immediately

upon writing as other configuration registers do. After loading

the FTW registers with the desired values, Bit 0 of Register 0x36

must transition from 0 to 1 for the new FTW to take effect.

0.2

0.4

0.6

f_OUT/f_DATA

0.8

1.0

Figure 56. Signal Bandwidth vs. Center Frequency of the Output Signal,

4× Interpolation

DATAPATH CONFIGURATION

Configuring 4× interpolation using the HB2 and HB3 filters can

lower the power consumption of the device at the expense of

bandwidth. The lower curve in Figure 56 shows that the supported

Configuring the AD9122 datapath starts with the application

requirements of the input data rate, the interpolation ratio, the

output signal bandwidth, and the output signal center frequency.

bandwidth in this mode varies from 30% to 50% of f_DATA

.

Rev. 0 | Page 3ꢀ of 56

AD9122

The available signal bandwidth for 8× interpolation vs. output

frequency varies between 50% and 80% of the input data rate,

as shown in Figure 57. Note that in 8× interpolation mode,

f_DAC= 8 × f_DATA; therefore, the data shown in Figure 57 repeats

DETERMINING INTERPOLATION FILTER MODES

Table 20 shows the recommended interpolation filter settings

for a variety of filter interpolation factors, filter center frequencies,

and signal modulation. The interpolation modes were chosen

based on the final center frequency of the signal and by

determining the frequency shift of the signal required. When

these are known, and put in terms of the input data rate (f_DATA),

the filter configuration that comes closest to matching is chosen

from Table 20.

eight times from dc to f_DAC

.

HB1, HB2, AND HB3

0.8

0.6

0.5

0.1

0.4

0.6

0.9

0.25

0.50

f_OUT

0.75

1.00

/

f_DATA

Figure 57. Signal Bandwidth vs. Center Frequency of the Output Signal,

8× Interpolation

Table 20. Recommended Interpolation Filter Modes (Register 0x1C through Register 0x1E)

Filter Modes

Interpolation Factor

HB1[1:0]

00 (0)

01 (1)

10 (2)

11 (3)

00 (0)

01 (1)

10 (2)

11 (3)

00 (0)

01 (1)

10 (2)

11 (3)

00 (0)

01 (1)

10 (2)

11 (3)

00 (0)

01 (1)

10 (2)

11 (3)

00 (0)

01 (1)

10 (2)

11 (3)

00 (0)

01 (1)

10 (2)

11 (3)

HB2[5:0]

000000

001001

010010

011011

100100

101101

110110

111111

000000

001001

010010

011011

100100

101101

110110

111111

000000

001001

010010

011011

100100

101101

110110

111111

Bypass

HB3[5:0]

000000

001001

010010

011011

100100

101101

110110

111111

Bypass

f_SIGNALModulation

DC

DC¹

f_CENTERShift

0

f_DATA/2

f_DATA

3f_DATA/2

2f_DATA

5f_DATA/2

3f_DATA

ꢀf_DATA/2

4f_DATA

9f_DATA/2

5f_DATA

11f_DATA/2

6f_DATA

13f_DATA/2

ꢀf_DATA

15f_DATA/2

0

f_DATA/2

f_DATA

3f_DATA/2

2f_DATA

5f_DATA/2

3f_DATA

ꢀf_DATA/2

0

f_DATA/2

f_DATA

8

8²

8

4

4³

4

2

f_DATA

1

2f_DATA

1

3f_DATA

3 f_DATA

1

4f_DATA

1

5f_DATA

1

6f_DATA

1

ꢀf_DATA

1

DC

DC¹

f_DATA

1

2f_DATA

1

3f_DATA

1

DC

DC¹

f_DATA

1

3f_DATA/2

¹When HB1 Mode 1 or Mode 3 is used, enabling premodulation provides an addition frequency translation of the input signal by f_DATA/2, which centers a baseband

input signal in the filter pass band.

²This configuration was used in the 8× interpolation without NCO example. Also, see the 8× Interpolation Without NCO section.

³This configuration was used in the 4× interpolation with NCO example. Also, see the 4× Interpolation With NCO section.

Rev. 0 | Page 38 of 56

AD9122

4× Interpolation With NCO

DATAPATH CONFIGURATION EXAMPLE

8× Interpolation Without NCO

Given the following:

f

_DATA= 250 MSPS

4× interpolation

f_BW= 140 MHz

f_CENTER= 175 MHz

f_DATA= 100 MSPS

8× interpolation

f

_BW= 75 MHz

The desired 140 MHz of bandwidth is 56% of f_DATA. As shown

in Figure 56, the value at 0.7 × f_DATAis 0.6. This is calculated as

0.8 − 2(0.7 − 0.6) = 0.6. This verifies that the AD9122 supports

a bandwidth of 60% of f_DATA, which exceeds the required 56%.

_CENTER= 100 MHz

The desired 75 MHz of bandwidth is 75% of f_DATA. In this case,

the ratio of f_OUT/f_DATA= 100/100 = 1.0. From Figure 57, the band-

width supported at f_DATAis 0.8, which verifies that the AD9122

supports the bandwidth required in this configuration.

The signal center frequency is 0.7 × f_DATA, and assuming the

input signal is at baseband, the frequency shift required is also

0.7 × f_DATA. Choosing the second row in the IF column in the

4× interpolation section in Table 20 selects the filter modes that

give a center frequency of f_DATA/2 and no frequency translation.

The selected modes for the three half-band filters are HB1,

Mode 1; HB2, Mode 1; and HB3, bypassed.

The signal center frequency is f_DATA, and assuming the input signal

is at baseband, the frequency shift required is also f_DATA. Choosing

the third row (highlighted by the superscripted number two) of the

IF column from Table 20 selects filter modes that give a center

frequency of f_DATAand a frequency translation of f_DATA. The selected

modes for the three half-band filters are: HB1, Mode 2; HB2,

Mode 2; and HB3, Mode 1. Figure 58 shows how the signal

propagates through the interpolation filters.

Because Mode 1 of HB1 was selected, the premodulation block

should be enabled. This provides f_DATA/2 modulation, which

centers the baseband input data at the center frequency of HB1.

The digital modulator can be used to provide the final frequency

translation of 0.2 × f_DATAto place the output signal at 0.7 × f_DATA

as desired.

Because 2 × f_IN1= f_IN2and 2 × f_IN2= f_IN3, the signal appears

frequency scaled by ½ into each consecutive stage. The output

signal band spans 0.15 to 0.35 of f_IN3(400 MHz). Therefore,

the output frequency supported is 60 MHz to 140 MHz, which

covers the 75 MHz bandwidth centered at 100 MHz, as desired.

,

The formula for calculating the FTW of the NCO is:

f_CARRIER

f_NCO

FTW =

×2³²

where:

f

_CARRIER= 0.2 × f_DATA.

_NCO= 2 × f_DATA. Therefore, FTW = 2³²/10.

0

2

0

3

1

HB1

0.1

0

0.4 0.6

0.5

×

2.0

f_IN1

–0.5

0

1.0

1.5

1

3

5

7

1.75

7

4

HB2

2

6

0.25

0.75

1.25

×

2.0

f_IN2

–0.5

0

0.5

1.0

4

1.5

0.3

0.7

0

1

3

5

HB3

2

6

–0.2

0.2 0.3

0.7

×

f_IN3

–0.5

0

0.5

1.0

1.5

2.0

0.15 0.35

Figure 58. Signal Propagation for 8× Interpolation (f_DATAModulation)

Rev. 0 | Page 39 of 56

AD9122

In practice, this modulation results in mixing functions as

shown in Table 21.

DATA RATES vs. INTERPOLATION MODES

Table 22 summarizes the maximum bus speed (f_BUS), supported

input data rates, and signal bandwidths with the various

combinations of bus width modes and interpolation rates.

The maximum bus speed in any mode is 1200 MHz. The

maximum DAC update rate (f_DAC) in any mode is 1200 MHz.

The real signal bandwidth supported is a fraction of the input

data rate, which depends on the interpolation filters (HB1, HB2,

or HB3) selected. The complex signal bandwidth supported is

twice the real signal bandwidth.

Table 21. Modulation Mixing Sequences

Modulation Mixing Sequence

f_S/2

I = I, −I, I, −I, …

Q = Q, −Q, Q, −Q, …

f_S/4

I = I, Q, −I, −Q, …

Q = Q, −I, −Q, I, …

3 f_S/4

f_S/8

I = I, −Q, −I, Q, …

Q = Q, I, −Q, −I, …

In general, 2× interpolation is best supported by enabling HB1,

and 4× interpolation is best supported enabling HB1 and HB2.

In some cases, power dissipation can be lowered by avoiding

HB1. If the bandwidth required is low enough, 2× interpolation

can be supported by using HB2, and 4× interpolation can be

supported by using HB2 and HB3.

I = I, r(I + Q), Q, r(−I + Q), −I, −r(I + Q), −Q, r(I − Q), …

Q = Q, r(Q − I), −I, −r(Q + I), −Q, r(−Q + I),I, r(Q + I), …

2

Note that r =

As shown in Table 21, the mixing functions of most of the modes

crosscouple samples between the I and Q channels. The I and Q

channels only operate independently in f_S/2 mode. This means

that real modulation using both the I and Q DAC outputs can only

be done in f_S/2 mode. All other modulation modes require

complex input data and produce complex output signals.

COARSE MODULATION MIXING SEQUENCES

The coarse digital quadrature modulation occurs within the

interpolation filters. The modulation shifts the frequency

spectrum of the incoming data by the frequency offset selected.

The frequency offsets available are multiples of the input data

rate. The modulation is equivalent to multiplying the quadrature

input signal by a complex carrier signal, C(t), of the form

C(t) = cos(ω_ct) + j sin(ω_ct)

Table 22. Summary of Data Rates and Bandwidths vs. Interpolation Modes

Filter Modes

Bus Width

HB3

0

HB2

0

1

HB1

0

1

0

1

f_BUS(Mbps)

1200

600

f_DATA(Mbps)

150

Real Signal Bandwidth (MHz)

f_DAC(MHz)

150

300

600

1200

300

600

Nibble (4 Bits)

ꢀ5

60

3ꢀ.5

60

3ꢀ.5

60

1

0

1

150

Byte (8 Bits)

0

1

0

1

0

1

0

1

0

1

300

150

120

ꢀ5

120

ꢀ5

1200

600

60

Word (16 Bits)

0

1

0

1

0

1

0

1

0

1

1200

800

1200

600

300

600

400

600

300

150

300

160

150

120

ꢀ5

800

1200

60

Rev. 0 | Page 40 of 56

AD9122

QUADRATURE PHASE CORRECTION

20

15

10

5

0

The purpose of the quadrature phase correction block is to

enable compensation of the phase imbalance of the analog

quadrature modulator following the DAC. If the quadrature

modulator has a phase imbalance, the unwanted sideband appears

with significant energy. Tuning the quadrature phase adjust value

can optimize image rejection in single sideband radios.

5

10

15

Ordinarily, the I and Q channels have an angle of precisely 90°

between them. The quadrature phase adjustment is used to

change the angle between the I and Q channels. When the

I Phase Adj[9:0] is set to 1000000000b, the I DAC output moves

approximately 1.75° away from the Q DAC output, creating an

angle of 91.75° between the channels. When the I Phase Adj[9:0]

is set to 0111111111b, the I DAC output moves approximately

1.75° toward the Q DAC output, creating an angle of 88.25°

between the channels.

0

20

0xFFFF

0x0000

0x4000

0x8000

0xC000

DAC OFFSET VALUE

Figure 59. DAC Output Currents vs. DAC Offset Value

INVERSE SINC FILTER

The inverse sinc (sinc⁻¹) filter is a nine-tap FIR filter. The

composite response of the sinc⁻¹and the sin(x)/x response of

the DAC is shown in Figure 59. The composite response has less

The Q Phase Adj[9:0] works in a similar fashion. When the Q

Phase Adj[9:0] is set to 1000000000b, the Q DAC output moves

approximately 1.75° away from the I DAC output, creating an

angle of 91.75° between the channels. When the Q Phase Adj[9:0]

is set to 0111111111b, the Q DAC output moves approximately

1.75° toward the I DAC output, creating an angle of 88.25°

between the channels.

than 0.05 dB pass-band ripple up to a frequency of 0.4 × f_DACCLK

To provide the necessary peaking at the upper end of the pass

band, the inverse sinc filters shown have an intrinsic insertion

loss of about 3.2 dB. Figure 60 shows the composite frequency

.

response.

Based on these two endpoints, the combined resolution of the

phase compensation register is approximately 3.5°/1024 or

0.00342° per code.

–3.0

–3.2

–3.4

–3.6

–3.8

–4.0

DC OFFSET CORRECTION

The dc value of the I datapath and the Q datapath can be

independently controlled by adjusting the I DAC Offset[15:0]

and Q DAC Offset[15:0] values in Register 0x3C through

Register 0x3F. These values are added directly to the datapath

values. Care should be taken not to overrange the transmitted

values.

Figure 59 shows how the DAC offset current varies as a function

of the I DAC Offset[15:0] and the Q DAC Offset[15:0] values.

With the digital inputs fixed at midscale (0x0000, twos complement

data format), Figure 59 shows the nominal I_OUTPand I_OUTNcurrents

as the DAC offset value is swept from 0 to 65535. Because I_OUTP

and I_OUTNare complementary current outputs, the sum of I_OUTP

and I_OUTNis always 20 mA.

0

0.1

0.2

f_OUT

0.3

0.4

0.5

/

f_DAC

Figure 60. Sample Composite Responses of the Sinc⁻¹Filter with Sin(x)/x Roll-Off

The sinc⁻¹filter is enabled by default. It can be bypassed by setting

the bypass sinc⁻¹bit (Register 0x1B, Bit 6).

Rev. 0 | Page 41 of 56

AD9122

DAC INPUT CLOCK CONFIGURATIONS

when the clock input signal is between 800 mV p-p differential and

1.6 V p-p differential. Whether using the on-chip clock multiplier

or sourcing the DACCLK, directly, it is necessary that the input

clock signal to the device has low jitter and fast edge rates to

optimize the DAC noise performance.

DAC INPUT CLOCK CONFIGURATIONS

The AD9122 DAC sample clock (DACCLK) can be sourced

directly or by clock multiplying. Clock multiplying employs the

on-chip phased-locked loop (PLL) that accepts a reference clock

operating at a submultiple of the desired DACCLK rate, most

commonly the data input frequency. The PLL then multiplies

the reference clock up to the desired DACCLK frequency, which

can then be used to generate all the internal clocks required by

the DAC. The clock multiplier provides a high quality clock that

meets the performance requirements of most applications. Using

the on-chip clock multiplier removes the burden of generating

and distributing the high speed DACCLK.

Direct Clocking

Direct clocking with a low noise clock produces the lowest noise

spectral density at the DAC outputs. To select the differential CLK

inputs as the source for the DAC sampling clock, set the PLL

enable bit (Register 0x0A, Bit[7]) to 0. This powers down the

internal PLL clock multiplier and selects the input from the

DACCLKP and DACCLKN pins as the source for the internal

DAC sample clock.

The second mode bypasses the clock multiplier circuitry and

allows DACCLK to be sourced directly to the DAC core. This

mode enables the user to source a very high quality clock directly

to the DAC core. Sourcing the DACCLK directly through the

REFCLKP, REFCLKN, DACCLKP, and DACCLKN pins may

be necessary in demanding applications that require the lowest

possible DAC output noise, particularly when directly synthesizing

signals above 150 MHz.

The device also has duty-cycle correction circuitry and

differential input level correction circuitry. Enabling these

circuits can provide improved performance in some cases.

The control bits for these functions can be found in Register 0x08.

See Table 11 for complete details.

Clock Multiplication

The on-chip PLL clock multiplier circuit can be used to generate

the DAC sample rate clock from a lower frequency reference

clock. When the PLL enable bit (Register 0x0A, Bit[7]) is set to 1,

the clock multiplication circuit generates the DAC sample clock

from the lower rate REFCLK input. The functional diagram of

the clock multiplier is shown in Figure 62.

Driving the DACCLK and REFCLK Inputs

The REFCLK and DACCLK differential inputs share similar

clock receiver input circuitry. Figure 61 shows a simplified circuit

diagram of the input. The on-chip clock receiver has a differential

input impedance of about 10 kΩ. It is self biased to a common-

mode voltage of about 1.25 V. The inputs can be driven by

direct coupling differential PECL or LVDS drivers. The inputs

can also be ac-coupled if the driving source cannot meet the

input compliance voltage of the receiver.

The clock multiplication circuit operates such that the VCO

outputs a frequency, f_VCO, equal to the REFCLK input signal

frequency multiplied by N1 × N0.

f

_VCO= f_REFCLK× (N1 × N0)

The DAC sample clock frequency, f_DACCLK, is equal to

_DACCLK= f_REFCLK× N1

DACCLKP,

REFCLKP

5kΩ

f

1.25V

The output frequency of the VCO must be chosen to keep f_VCO

in the optimal operating range of 1.0 GHz to 2.1 GHz. The

frequency of the reference clock and the values of N1 and N0

must be chosen so that the desired DACCLK frequency can be

synthesized and the VCO output frequency is in the correct range.

5kΩ

DACCLKN,

REFCLKN

Figure 61. Clock Receiver Input Equivalent Circuit

The minimum input drive level to either of the clock inputs is

200 mV p-p differential. The optimal performance is achieved

0x0E[3:0]

0x06[7:6]

VCO CONTROL

VOLTAGE

PLL LOCKED

ADC

PLL LOCKED LOST

REFCLKP/REFCLKN

PHASE

LOOP

FILTER

(PIN 69 AND PIN 70)

DETECTION

VCO

÷N1

÷N0

0x0D[1:0]

N1

0x0D[3:2]

N0

DACCLK

DACCLKP/DACCLKN

(PIN 2 AND PIN 3)

0x0D[7:6]

N2

÷N2

0x0A[7]

PLL ENABLE

PC_CLK

Figure 62. PLL Clock Multiplication Circuit

Rev. 0 | Page 42 of 56

AD9122

PLL Settings

Manual VCO Band Select

There are three settings for the PLL circuitry that should be

programmed to their nominal values. The PLL values shown in

Table 23 are the recommended settings for these parameters.

The device also has a manual band select mode (PLL manual

enable, Register 0x0A, Bit[6] = 1) that allows the user to select

the VCO tuning band. When in manual mode, the VCO band

is set directly with the value written to the manual VCO band,

(Register 0x0A, Bit[5:0]). To properly select the VCO band,

follow these steps:

Table 23. PLL Settings

Address

Register

Optimal

Setting

PLL SPI Control

Bit

1. Put the device in manual band select mode.

2. Sweep the VCO band over a range of bands that result in

the PLL being locked.

PLL Loop Bandwidth[1:0]

PLL Charge Pump Current[4:0]

PLL Cross Control Enable

0x0C

0x0D

[ꢀ:6] 11

[4:0] 00001

[4]

1

3. For each band, verify that the PLL is locked and read the

PLL using the VCO control voltage (Register 0x0E[3:0]).

4. Select the band that results in the control voltage being

closest to the center of the range (that is, 0000 or 1000). See

Table 24 for more details. The resulting VCO band should

be the optimal setting for the device. Write this band to the

manual VCO band (Register 0x0A[5:0]) value.

5. If desired, an indication of where the VCO is within the

operating frequency band can be determined by querying

the VCO control voltage. Table 24 shows how to interpret

the PLL VCO control voltage (Register 0x0E, Bits[2:0]) value.

Configuring the VCO Tuning Band

The PLL VCO has a valid operating range from approximately

1.0 GHz to 2.1 GHz covered in 63 overlapping frequency bands.

For any desired VCO output frequency, there may be several

valid PLL band select values. The frequency bands of a typical

device are shown in Figure 63. Device-to-device variations and

operating temperature affect the actual band frequency range.

Therefore, it is required that the optimal PLL band select value

be determined for each individual device.

Automatic VCO Band Select

Table 24. VCO Control Voltage Range Indications

The device has an automatic VCO band select feature on chip.

Using the automatic VCO band select feature is a simple and

reliable method of configuring the VCO frequency band. This

feature is enabled by writing 0x80 to Register 0x0A. When this

value is written, the device executes an automated routine that

determines the optimal VCO band setting for the device. The

setting selected by the device ensures that the PLL remains

locked over the full −40°C to +85°C operating temperature

range of the device without further adjustment. (The PLL

remains locked over the full temperature range even if the

temperature during initialization is at one of the temperature

extremes.)

VCO Control Voltage

Indication

0111

0110

0101

0100

0011

0010

0001

0000

1000

1001

1010

1011

1100

1101

1110

1111

Move to higher VCO Band

VCO is operating in the higher end of

frequency band

VCO is operating within an optimal

region of the frequency band

VCO is operating in the lower end of

frequency band

0

4

8

12

16

20

24

28

32

36

40

44

48

52

56

60

Move to lower VCO Band

1000

1200

1400

1600

1800

2000

2200

VCO FREQUENCY (MHz)

Figure 63. PLL Lock Range Over Temperature for a Typical Device

Rev. 0 | Page 43 of 56

AD9122

ANALOG OUTPUTS

For nominal values of V_REF(1.2 V), R_SET(10 kꢀ), and DAC gain

(512), the full-scale current of the DAC is typically 20.16 mA.

The DAC full-scale current can be adjusted from 8.66 mA to

31.66 mA by setting the DAC gain parameter setting as shown

in Figure 65.

TRANSMIT DAC OPERATION

Figure 64 shows a simplified block diagram of the transmit path

DACs. The DAC core consists of a current source array, a switch

core, digital control logic, and full-scale output current control.

The DAC full-scale output current (I_OUTFS) is nominally 20 mA.

The output currents from the IOUT1P/IOUT2P and IOUT1N/

IOUT2N pins are complementary, meaning that the sum of the

two currents always equals the full-scale current of the DAC.

The digital input code to the DAC determines the effective

differential current delivered to the load.

35

30

25

20

15

10

5

I DAC FS ADJUST

1.2V

REGISTER 0x40

IOUT1P

I DAC

5kΩ

IOUT1N

REFIO

CURRENT

SCALING

0.1µF

FSADJ

10kΩ

IOUT2N

IOUT2P

Q DAC

0

Q DAC FS ADJUST

REGISTER 0x44

0

200

400

600

800

1000

DAC GAIN CODE

Figure 64. Simplified Block Diagram of DAC Core

Figure 65. DAC Full-Scale Current vs. DAC Gain Code

The DAC has a 1.2 V band gap reference with an output impedance

of 5 kꢀ. The reference output voltage appears on the REFIO

pin. When using the internal reference, the REFIO pin should

be decoupled to AVSS with a 0.1 μF capacitor. Only use the internal

reference for external circuits that draw dc currents of 2 μA or

less. For dynamic loads or static loads greater than 2 μA, buffer

the REFIO pin. If desired, an external reference (between 1.10 V

and 1.30 V) can be applied to the REFIO pin. The internal

reference can either be overdriven or powered down by setting

Register 0x43, Bit [5].

Transmit DAC Transfer Function

The output currents from the IOUT1P/IOUT2P and IOUT1N/

IOUT2N pins are complementary, meaning that the sum of the

two currents always equals the full-scale current of the DAC.

The digital input code to the DAC determines the effective

differential current delivered to the load. IOUT1P/IOUT2P

provide maximum output current when all bits are high. The

output currents vs. DACCODE for the DAC outputs are

expressed as

DACCODE

⎡

⎤

A 10 kꢀ external resistor, R_SET, must be connected from the

I_OUTP

=

× I_OUTFS

(1)

(2)

2^N

⎢

⎣

⎥

⎦

RESET

pin to AVSS. This resistor, along with the reference

control amplifier, sets up the correct internal bias currents for

the DAC. Because the full-scale current is inversely proportional

to this resistor, the tolerance of R_SETis reflected in the full-scale

output amplitude.

I_OUTN= I_OUTFS− I_OUTP

where DACCODE = 0 to 2^N− 1.

Transmit DAC Output Configurations

The optimum noise and distortion performance of the AD9122

is realized when it is configured for differential operation. The

common-mode error sources of the DAC outputs are significantly

reduced by the common-mode rejection of a transformer or

differential amplifier. These common-mode error sources include

even-order distortion products and noise. The enhancement in

distortion performance becomes more significant as the frequency

content of the reconstructed waveform increases and/or its

amplitude increases. This is due to the first-order cancellation

of various dynamic common-mode distortion mechanisms,

digital feedthrough, and noise.

The full-scale current equation, where the DAC gain is set

individually for the I and Q DACs in Register 040 and Register 044,

respectively, follows:

V_REF

3

⎛

⎞

⎟

⎛

⎜

⎝

⎞

⎟

⎠

I_FS

=

× 72 +

× DAC gain

⎜

R_SET

16

⎝

⎠

Rev. 0 | Page 44 of 56

AD9122

–60

–65

–70

–75

–80

–85

–90

Figure 66 shows the most basic DAC output circuitry. A pair of

resistors, R_O, is used to convert each of the complementary output

currents to a differential voltage output, V_OUT. Because the current

outputs of the DAC are high impedance, the differential driving

point impedance of the DAC outputs, R_OUT, is equal to 2 × R_O.

Figure 67 illustrates the output voltage waveforms.

10mA

20mA

30mA

V

+

IP

IOUT1P

R

O

V

OUTI

–

R

O

V

IN

IOUT1N

0

0.2

0.4

0.6

V

0.8

(V)

1.0

1.2

1.4

V

+

QP

V

IOUT2P

CMD

R

O

Figure 68. IMD vs. Output Common-Mode Voltage (f_OUT= 61 MHz,

R_LOAD= 50 Ω differential, I_FS= 10 mA, 20 mA, and 30 mA)

OUTQ

R

O

–50

V

–

QN

10mA

IOUT2N

20mA

–55

30mA

Figure 66. Basic Transmit DAC Output Circuit

V

PEAK

–60

–65

–70

–75

–80

–85

V

CM

0

V

P

N

V

OUT

–V

PEAK

Figure 67. Voltage Output Waveforms

0

0.2

0.4

0.6

V

0.8

(V)

1.0

1.2

1.4

CMD

The common-mode signal voltage, V_CM, is calculated as

Figure 69. IMD vs. Output Common-Mode Voltage (f_OUT= 161 MHz,

R_LOAD= 50 Ω differential, I_FS= 10 mA, 20 mA, and 30 mA)

I_FS

2

V_CM

=

× R_O

AUXILIARY DAC OPERATION

The peak output voltage, V_PEAK, is calculated as

_PEAK= I_FS× R_O

The AD9122 have two auxiliary DACs, one associated with the

I path and one associated with the Q path. These auxiliary DACs

can be used to compensate for dc offsets in the transmitted signal.

Each auxiliary DAC has a single-ended current that can sink or

source current into either the P or N output of the associated

transmit DAC. The auxiliary DAC structure is shown in Figure 70.

V

With this circuit configuration, the single-ended peak voltage is

the same as the peak differential output voltage.

Transmit DAC Linear Output Signal Swing

To achieve optimum performance, the DAC outputs have a linear

output compliance voltage range that must be adhered to. The

linear output signal swing is dependent on the full-scale output

current, I_OUTFS, and the common-mode level of the output.

Figure 68 and Figure 69 show the IMD performance vs. the

common-mode voltage at the different full-scale currents and

output frequencies.

V

B

AUXDAC[4:0]

AUXDAC

DIRECTION

AUXDAC

SIGN

IOUTP

IOUTN

I DAC

Figure 70. Auxiliary DAC Structure

Rev. 0 | Page 45 of 56

AD9122

The control registers for controlling the I and Q auxiliary DACs

are in Register 0x42, Register 0x43, and Register 0x46.

Figure 73 shows a fifth-order, low-pass filter. A common-mode

choke is used between the I-V resistors and the remainder of

the filter. This removes the common-mode signal produced by

the DAC and prevents the common-mode signal from being

converted to a differential signal, which can appear as unwanted

spurious signals in the output spectrum. Splitting the first filter

capacitor into two and grounding the center point creates a

common-mode low-pass filter, providing additional common-

mode rejection of high frequency signals. A purely differential

filter can pass common-mode signals.

Interfacing to Modulators

The AD9122 interfaces to the ADL537x family of modulators

with a minimal number of components. An example of the

recommended interface circuitry is shown in Figure 71.

The baseband inputs of the ADL537x family require a dc bias

of 500 mV. The nominal midscale output current on each output

of the DAC is 10 mA (½ the full-scale current). Therefore, a

single 50 Ω resistor to ground from each of the DAC outputs

results in the desired 500 mV dc common-mode bias for the

inputs to the ADL537x. The signal level can be reduced through

the addition of the load resistor in parallel with the modulator

inputs. The peak-to-peak voltage swing of the transmitted signal is

DRIVING THE ADL5375-15

The ADL5375-15 requires a 1500 mV dc bias and, therefore,

requires a slightly more complex interface than most other

Analog Devices, Inc, modulators. It is necessary to level shift

the DAC output from a 500 mV dc bias to the 1500 mV dc bias

that the ADL5375-15 requires. Level shifting can be achieved

with a purely passive network, as shown in Figure 72. In this

network, the dc bias of the DAC remains at 500 mV while the

input to the ADL5375-15 is 1500 mV. This passive, level shifting

network introduces approximately 2 dB of loss in the ac signal.

[

2×R_B×R_L

]

V_SIGNAL= I_FS

×

[2×R_B+ R_L

AD9122

ADL537x

IBBP

67

IOUT1P

RBIP

50Ω

RLI

100Ω

RBIN

50Ω

AD9122

ADL5375-15

IBBP

RSIN

1kΩ

66

59

67

21

IOUT1N

IOUT2N

IBBN

IOUT1P

RBIP

45.3Ω

RLIP

3480Ω

5V

QBBN

RBIN

45.3Ω

RLIN

3480Ω

RSIP

1kΩ

66

59

22

RBQN

50Ω

IOUT1N

IOUT2N

IBBN

RLQ

100Ω

RBQP

50Ω

RSQN

1kΩ

58

9

IOUT2P

QBBP

QBBN

RBQN

45.3Ω

RLQN

3480Ω

5V

10

Figure 71. Typical Interface Circuitry Between the AD9122 and the ADL537x

Family of Modulators

RBQP

45.3Ω

RLQP

3480Ω

RSQP

1kΩ

58

IOUT2P

QBBP

BASEBAND FILTER IMPLEMENTATION

Figure 72. Passive, Level Shifting Network for Biasing ADL5375-15

Most applications require a baseband anti-imaging filter between

the DAC and the modulator to filter out Nyquist images and

broadband DAC noise. The filter can be inserted between the

I-V resistors at the DAC output and the signal-level setting resistor

across the modulator input. Doing this establishes the input and

output impedances for the filter.

22pF

56nH

50Ω

3pF

33nH

2pF

6pF

3pF

140Ω ADL537x

AD9122

33nH

56nH

50Ω

22pF

Figure 73. DAC Modulator Interface with Fifth-Order, Low Pass Filter

Rev. 0 | Page 46 of 56

AD9122

The disadvantage is that the common-mode level of the output

signal changes as a function of the auxiliary DAC current. The

opposite is true when the digital offset adjustment is used.

REDUCING LO LEAKAGE AND UNWANTED

SIDEBANDS

Analog quadrature modulators can introduce unwanted signals at

the LO frequency due to dc offset voltages in the I and Q baseband

inputs, as well as feedthrough paths from the LO input to the

output. The LO feedthrough can be nulled by applying the correct

dc offset voltages at the DAC output. This can be done using the

auxiliary DACs (Register 0x42, Register 0x43, Register 0x46, and

Register 0x47) or by using the digital dc offset adjustments

(Register 0x3C through Register 0x3F). The advantage of using

the auxiliary DACs is that none of the main DAC dynamic

range is used to perform the dc offset adjustment.

Good sideband suppression requires both gain and phase

matching of the I and Q signals. The I/Q phase adjust

(Register 0x38 through Register 0x3B) and DAC FS adjust

(Register 0x40 and Register 0x44) registers can be used to

calibrate I and Q transmit paths to optimize the sideband

suppression.

Rev. 0 | Page 4ꢀ of 56

AD9122

DEVICE POWER DISSIPATION

1700

1500

1300

1100

900

1×

2×

4×

8×

The AD9122 has four supply rails: AVDD33, IOVDD, DVDD18,

and CVDD18.

The AVDD33 supply powers the DAC core circuitry. The power

dissipation of the AVDD33 supply rail is independent of the digital

operating mode and sample rate. The current drawn from the

AVDD33 supply rail is typically 57 mA (188 mW) when the

full-scale current of the I and Q DACs is set to the nominal value

of 20 mA. Changing the full-scale current directly impacts the

supply current drawn from the AVDD33 rail. For example, if

the full-scale current of the I DAC and the Q DAC is changed to

10 mA, the AVDD33 supply current drops by 20 mA to 37 mA.

700

500

300

100

RESET

The IOVDD voltage supplies the serial port I/O pins, the

IRQ

0

50

100

150

200

250

300

pin, and the

pin. The voltage applied to the IOVDD pin

f_DATA(MHz)

can range from 1.8 V to 2.8 V. The current drawn by the

IOVDD supply pin is typically 3 mA.

Figure 74. Total Power Dissipation vs. f_DATAWithout PLL, Fine NCO, and

Inverse Sinc

1200

1×

The DVDD18 supply powers all of the digital signal processing

blocks of the device. The power consumption from this supply

is a function of which digital blocks are enabled and the frequency

at which the device is operating.

2×

4×

1000

8×

800

600

400

200

0

The CVDD18 supply powers the clock receiver and clock

distribution circuitry. The power consumption from this

supply varies directly with the operating frequency of the

device. CVDD18 also powers the PLL. The power dissipation

of the PLL is typically 80 mA when enabled.

Figure 74 through Figure 78 detail the power dissipation of the

AD9122 under a variety of operating conditions. All of the graphs

are taken with data being supplied to both the I and Q channels.

The power consumption of the device does not vary significantly

with changes in the coarse modulation mode selected or analog

output frequency. Graphs of the total power dissipation are shown

along with the power dissipation of the DVDD18 and CVDD18

supplies.

0

50

100

150

200

250

300

f_DATA(MHz)

Figure 75. DVDD18 Power Dissipation vs. f_DATAWithout Fine NCO and

Inverse Sinc

250

1×

2×

4×

8×

Maximum power dissipation can be estimated to be 20% higher

than the typical power dissipation.

200

150

100

50

0

50

100

150

200

250

300

f_DATA(MHz)

Figure 76. CVDD18 Power Dissipation vs. f_DATAwith PLL Disabled

Rev. 0 | Page 48 of 56

AD9122

300

250

200

150

100

50

TEMPERATURE SENSOR

The AD9122 has a diode-based temperature sensor for measuring

the temperature of the die. The temperature reading is accessed

through Register 0x49 and Register 0x4A. The temperature of

the die can be calculated by

(DieTemp[15 : 0]− 47,925)

T_DIE

=

88

where T_DIEis the die temperature in ^oC. The temperature

accuracy is 5^oC typical.

Estimates of the ambient temperature can be made if the power

dissipation of the device is known. For example, if the device power

dissipation is 800 mW, and the measured die temperature is 50^oC,

then the ambient temperature can be calculated as

0

200

400

600

800

100

1200

f_DAC(MHz)

Figure 77. DVDD18 Power Dissipation vs. f_DACDue to Inverse Sinc Filter

T_A= T_DIE– P_D× T_JA= 50 – 0.8 × 20.7 = 33.4°C

300

1×

where:

2×, 4×, 8×

T_Ais the ambient temperature in ^oC.

T_JAis the thermal resistance from junction to ambient of the

AD9122, as shown in Table 7.

250

200

150

100

50

To use the temperature sensor, it must be enabled by setting

Register 0x01, Bit 4 to 0. In addition, to obtain accurate readings,

the range control register (Register 0x48) should be set to 0x02.

0

50

100

150

200

250

300

f_DATA(MHz)

Figure 78. DVDD18 Power Dissipation vs. f_DATADue to Fine NCO

Rev. 0 | Page 49 of 56

AD9122

MULTICHIP SYNCHRONIZATION

System demands may require that the outputs of multiple DACs

be synchronized with each other or with a system clock. Systems

that support transmit diversity or beam forming, where multiple

antennas are used to transmit a correlated signal, require multiple

DAC outputs to be phase aligned with each other. Systems with

a time division multiplexing transmit chain may require one or

more DACs to be synchronized with a system-level reference clock.

SYNCHRONIZATION WITH CLOCK MULTIPLICATION

When using the clock multiplier to generate the DAC sample

rate clock, the REFCLK input signal acts as both the reference

clock for the PLL-based clock multiplier and as the synchronization

signal. To synchronize devices, distribute the REFCLK signal

with low skew to all of the devices that need to be synchronized.

Skew between the REFCLK signals of the different devices

shows up directly as a timing mismatch at the DAC outputs.

Multiple devices are considered synchronized to each other when

the state of the clock generation state machines is identical for all

parts, and when time aligned data is being read from the FIFOs

of all parts simultaneously. Devices are considered synchronized

to a system clock when there is a fixed and known relationship

between the clock generation state machine and the data being

read from the FIFO and a particular clock edge of the system

clock. The AD9122 has provisions for enabling multiple devices

to be synchronized to each other or to a system clock.

The frequency of the REFCLK signal is typically equal to the

input data rate. The FRAME and DCI signals can be created

in the FPGA along with the data. A circuit diagram of a typical

configuration is shown in Figure 79.

MATCHED

LENGTH TRACES

REFCLKP/

REFCLKN

IOUT1P/

IOUT1N

FRAMEP/

FRAMEN

DCIP/

DCIN

The AD9122 supports synchronization in two different modes,

data rate mode and FIFO rate mode. The lowest rate clock that

the synchronization logic attempts to synchronize to distinguishes

these two modes. In data rate mode, the input data rate represents

the lowest synchronized clock. In FIFO rate mode, the FIFO

rate, which is the data rate divided by the FIFO depth of 8,

represents the lowest rate clock. The advantage of FIFO rate

synchronization is increased time between keep-out windows

for DCI changes relative to the DACCLK or REFCLK input.

SYSTEM

CLOCK

LOW SKEW

CLOCK DRIVER

REFCLKP/

REFCLKN

IOUT2P/

IOUT2N

FRAMEP/

FRAMEN

DCIP/

DCIN

FPGA

Figure 79. Typical Circuit Diagram for Synchronizing Devices

The Procedure for Synchronization when Using the PLL section

outlines the steps required to synchronize multiple devices. The

procedure assumes that the REFCLK signal is applied to all of the

devices, and that the PLL of each device is phase locked to it. The

following procedure must be carried out on each individual device.

When in data rate mode, the elasticity of the FIFO is not used to

absorb timing variations between the data source and the DAC,

resulting in keep-out widows repeating at the input data rate.

The method chosen for providing the DAC sampling clock directly

impacts the synchronization methods available. When the device

clock multiplier is used, only data rate mode is available. When

the DAC sampling clock is sourced directly, both data rate

mode and FIFO rate mode synchronization is available. The

following sections detail the synchronization methods for

enabling both clocking modes and querying the status of the

synchronization logic.

Procedure for Synchronization when Using the PLL

Configure for data rate, periodic synchronization by writing

0xC0 to the sync control register (Register 0x10). Additional

synchronization options are available.

Read the sync status register (Register 0x12) and verify that

the sync locked bit (Bit 6) is set high, indicating that the device

achieved back-end synchronization and that the sync lost bit

(Bit 7) is low. These levels indicate that the clocks are running with

a constant and known phase relative to the sync signal.

Reset the FIFO by strobing the FRAME signal high for the time

required to write two complete input data words. Resetting the

FIFO ensures that the correct data is being read from the FIFO.

This completes the synchronization procedure, and at this stage,

all devices should be synchronized.

Rev. 0 | Page 50 of 56

AD9122

t_SKEW

REFCLKP(1)/

REFCLKN(1)

REFCLKP(2)/

REFCLKN(2)

t_{SU_DCI}t_{H_DCI}

DCIP(2)/

DCIN(2)

FRAMEP(2)/

FRAMEN(2)

Figure 80. Timing Diagram Required for Synchronizing Devices

DACCLKP/

DACCLKN

REFCLKP/

REFCLKN

FRAMEP/

FREMEN

IOUT1P/

IOUT1N

DCIP/

DCIN

SAMPLE

RATE CLOCK

LOW SKEW

CLOCK DRIVER

MATCHED

LENGTH TRACES

DACCLKP/

DACCLKN

REFCLKP/

REFCLKN

FRAMEP/

FREMEN

DCIP/

DCIN

IOUT2P/

IOUT2N

SYNC

CLOCK

LOW SKEW

CLOCK DRIVER

FPGA

Figure 81. Typical Circuit Diagram for Synchronizing Devices to a System Clock

To maintain synchronization, the skew between the REFCLK

signals of the devices must be less than t_SKEWnanoseconds. There is

also a setup-and-hold time to be observed between the DCI and

data of each device and the REFCLK signal. When resetting the

FIFO, the FRAME signal must be held high for the time interval

required to write two complete input data words. A timing

diagram of the input signals is shown in Figure 80.

to a master clock, then use the master clock directly for generating

the REFCLK input (see Figure 81).

DATA RATE MODE SYNCHRONIZATION

The Procedure for Data Rate Synchronization when Directly

Sourcing the DAC Sampling Clock section outlines the steps

required to synchronize multiple devices in data rate mode. The

procedure assumes that the DACCLK and REFCLK signals are

applied to all of the devices. The procedure must be carried out

on each individual device.

The preceding example shows a REFCLK frequency equal to

the data rate. While this is the most common situation, it is not

strictly required for proper synchronization. Any REFCLK

frequency that satisfies the following equation is acceptable.

Procedure for Data Rate Synchronization when Directly

Sourcing the DAC Sampling Clock

f

_{SYNC_I}= f_DACCLK/2^Nand f_{SYNC_I}≤ f_DATA

Configure for data rate, periodic synchronization by writing

0xC0 to the sync control register (Register 0x10). Additional

synchronization options are available and are described in the

Additional Synchronization Features section.

where N = 0, 1, 2, or 3.

As an example, a configuration with 4× interpolation and clock

frequencies of f_VCO= 1600 MHz, f_DACCLK= 800 MHz, f_DATA

=

200 MHz, and f_{SYNC_I}= 100 MHz is a viable solution.

Poll the sync locked bit (Register 0x12, Bit 6) to verify that the

device is back-end synchronized. A high level on this bit indicates

that the clocks are running with a constant and known phase

relative to the sync signal.

SYNCHRONIZATION WITH DIRECT CLOCKING

When directly sourcing the DAC sample rate clock, a separate

REFCLK input signal is required for synchronization. To

synchronize devices, the DACCLK signal and the REFCLK

signal must be distributed with low skew to all of the devices

being synchronized. If the devices need to be synchronized

Reset the FIFO by strobing the FRAME signal high for the time

interval required to input two complete data input words. Resetting

the FIFO ensures that the correct data is being read from the

FIFO of each of the devices simultaneously.

Rev. 0 | Page 51 of 56

AD9122

This completes the synchronization procedure, and at this stage,

all devices should be synchronized.

Poll the sync locked bit (Register 0x12, Bit[6]) to verify that the

device is back-end synchronized. A high level on this bit indicates

that the clocks are running with a constant and known phase

relative to the sync signal.

To ensure that each of the DACs are updated with the correct

data on the same CLK edge, two timing relationships must be

met on each DAC. DCIP/DCIN and D[15:0]P/D[15:0]N must

meet the setup-and-hold times with respect to the rising edge of

DACCLK, and REFCLK must also meet the setup-and-hold time

with respect to the rising edge of DACCLK. When resetting the

FIFO, the FRAME signal must be held high the time required to

input two complete data input words. When these conditions are

met, the outputs of the DACs are updated within t_SKEW+ t_OUTDLY

nanoseconds of each other. A timing diagram that illustrates the

timing requirements of the input signals is shown in Figure 82.

t_SKEW

Reset the FIFO by strobing the FRAME signal high for the time

required to input to complete input words. Resetting the FIFO

ensures that the correct data is being read from the FIFO of

each of the devices simultaneously.

This completes the synchronization procedure, and at this stage,

all devices should be synchronized.

To ensure that each of the DACs are updated with the correct

data on the same CLK edge, two timing relationships must be

met on each DAC. DCIP/DCIN and D[15:0]P/D[15:0]N must

meet the setup-and-hold times with respect to the rising edge of

DACCLK, and REFCLK must also meet the setup-and-hold

time with respect to the rising edge of DACCLK. When resetting

the FIFO, the FRAME signal must be held high for at least three

data periods (that is, 1.5 cycles of DCI). When these conditions

are met, the outputs of the DACs are updated within t_SKEW+ t_OUTDLY

nanoseconds of each other. A timing diagram that illustrates the

timing requirements of the input signals is shown in Figure 83.

t_SKEW

DACCLKP(1)/

DACCLKN(1)

DACCLKP(2)/

DACCLKN(2)

t_{SU_SYNC}t_{H_SYNC}

REFCLKP(2)/

REFCLKN(2)

t_{SU_DCI}t_{H_DCI}

DCIP(2)/

DCIN(2)

FRAMEP(2)/

FRAMEN(3)

DACCLKP(1)/

DACCLKN(1)

Figure 82. Data Rate Synchronization Signal Timing Requirements,

2x Interpolation

DACCLKP(2)/

DACCLKN(2)

t_{SU_SYNC}t_{H_SYNC}

Figure 82 shows the synchronization signal timing with 2×

interpolation; therefore, f_DCI= ½ × f_CLK. The REFCLK input is

shown to be equal to the data rate. The maximum frequency at

which the device can be resynchronized in data rate mode can

be expressed as

REFCLKP(2)/

REFCLKN(2)

DCIP(2)/

DCIN(2)

FRAMEP(2)/

FRAMEN(2)

f

_{SYNC_I}= f_DATA/2^N

where N is any nonnegative integer.

Figure 83. FIFO Rate Synchronization Signal Timing Requirements,

2× Interpolation

Generally, for values of N equal to or greater than 3, select the

FIFO rate synchronization mode.

Figure 83 shows the synchronization signal timing with 2×

interpolation; therefore, f_DCI= ½ × f_CLK. The REFCLK input is

shown to be equal to the FIFO rate. More generally, the maximum

frequency at which the device can be resynchronized in FIFO

rate mode can be expressed as

FIFO RATE MODE SYNCHRONIZATION

The Procedure for FIFO Rate Synchronization when Directly

Sourcing the DAC Sampling Clock section outlines the steps

required to synchronize multiple devices in FIFO rate mode.

The procedure assumes that the REFCLK and DACCLK signals

are applied to all of the devices. The procedure must be carried

out on each individual device.

f

_{SYNC_I}= (f_DATA/8 × 2^N)

where N is any nonnegative integer.

ADDITIONAL SYNCHRONIZATION FEATURES

Procedure for FIFO Rate Synchronization when Directly

Sourcing the DAC Sampling Clock

The synchronization logic incorporates additional features that

provide means for querying the status of the synchronization,

improving the robustness of the synchronization, and a one shot

synchronization mode. These features are detailed in the Sync

Status Bits and Timing Optimization sections that follow.

Configure for FIFO rate, periodic synchronization by writing

0x80 to the sync control register (Register 0x10). Additional

synchronization options are available and are described in the

Additional Synchronization Features section.

Rev. 0 | Page 52 of 56

AD9122

Sync Status Bits

The synchronization logic resynchronizes when a phase change

between the REFCLK signal and the state of the clock generation

state machine exceeds a threshold. To mitigate the effects of

jitter and prevent erroneous resynchronizations, the relative

phase can be averaged. The amount of averaging is set by the

sync averaging bits (Register 0x10, Bits[2:0]) and can be set

from 1 to 128. The higher the number of averages, the more

slowly the device recognizes and resynchronizes to a legitimate

phase correction. Generally, the averaging should be made as large

as possible while still meeting the allotted resynchronization

time interval.

When the sync locked bit (Register 0x12, Bit 6) is set, it indicates

that the synchronization logic has reached alignment. This

alignment is determined when the clock generation state machine

phase is constant. It takes between (11 + averaging) × 64 and

(11 + averaging) × 128 DACCLK cycles. This bit may optionally

IRQ

trigger an

section.

as described in the Interrupt Request Operation

When the sync lost bit (Register 0x12, Bit 7) is set, it indicates

a previously synchronized device has lost alignment. This bit is

latched and remains set until cleared by overwriting the register.

The sync phase request bits value (Register 0x11, Bits[5:0]) is

the state to which the clock generation state machine resets upon

initialization. By varying this value, the timing of the internal

clocks, with respect to the REFCLK signal, can be adjusted.

Every increment of the Sync Phase Request[5:0] (Register 0x11,

Bits[5:0]) value advances the internal clocks by one DACCLK

period. This offset can be used for two purposes: to skew the

outputs of two synchronized DAC outputs in increments of the

DACCLK period and to change the relative timing between the

DCI input and REFCLK. This may allow for a more optimal place-

ment of the DCI sampling point in data rate synchronization mode.

IRQ

This bit may optionally trigger an

Interrupt Request Operation section.

as described in the

The sync phase readback bits (Register 0x13, Bits[7:0]) report

the current clock phase in a 6.2 format. Bits[7:2] report which

of the 64 states (0 to 63) the clock is currently in. When averaging

is enabled, Bits[1:0] provide ¼ state accuracy (for 0, ¼, ½, ¾).

The lower two bits give an indication of the timing margin issues

that may exist. If the sync sampling is error free, the fractional

clock state should be 00.

Timing Optimization

The REFCLK signal is sampled by a version of the DACCLK. If

sampling errors are being detected, the opposite sampling edge

can be selected to improve the sampling point. The sampling

edge can be selected by setting Register 0x10, Bit 3 (1 = rising

and 0 = falling).

Table 25. Synchronization Setup and Hold Times

Parameter

Min

Max

Unit

ps

t_SKEW

t_{SV_SYNC}

T_{H_SYNC}

−t_DACCLK/2

100

330

+t_DACCLK/2

ps

Rev. 0 | Page 53 of 56

AD9122

INTERRUPT REQUEST OPERATION

The AD9122 provides an interrupt request output signal (on

The latched version of an event flag (the interupt_source signal)

can be cleared in two ways. The recommended way is by writing

1 to the corresponding event flag bit. A hardware or software

reset also clears the interupt_source.

IRQ

Pin 7,

) that can be used to notify an external host processor

of significant device events. Upon assertion of the interrupt,

the device should be queried to determine the precise event that

IRQ

occurred. The

pin is an open-drain, active low output. Pull

INTERRUPT SERVICE ROUTINE

IRQ

the

pin high external to the device. This pin can be tied to

the interrupt pins of other devices with open-drain outputs to

wired-OR these pins together.

Interrupt request management starts by selecting the set of event

flags that require host intervention or monitoring. Those events

that require host action should be enabled so that the host is

notified when they occur. For events requiring host intervention,

Sixteen different event flags provide visibility into the device.

These 16 flags are located in the two event flag registers

(Register 0x06 and Register 0x07). The behavior of each of the

event flags is independently selected in the interrupt enable

registers (Register 0x04 and Register 0x05). When the flag

interrupt enable is active, the event flag latches and triggers an

external interrupt. When the flag interrupt is disabled, the event

IRQ

upon

activation, run the following routine to clear an

interrupt request:

1. Read the status of the event flag bits that are being

monitored.

2. Set the interupt enable bit low so that the unlatched

event_flag_source can be monitored directly.

3. Perform any actions that may be required to clear the

event_source_flag. In many cases, no specific actions may

be required.

IRQ

flag simply monitors the source signal and the external

remains inactive.

IRQ

Figure 84 shows the

-related circuitry. This diagram shows

IRQ

how the event flag signals propagate to the

output. The

4. Read the event flag to verify the actions taken have cleared

the event_flag_source.

5. Clear the interrupt by writing 1 to the event flag bit.

6. Set the interupt enable bits of the events to be monitored.

interupt_enable signal represents one bit from the interrupt

enable register. The event_flag_source signal represents one bit

from the event flag register. The event_flag_source signal

represents one of the device signals that can be monitored such

as the PLL_locked signal from the PLL phase detector or the

FIFO Warning 1 signal from the FIFO controller.

Note that some of the event_flag_source signals are latched signals.

These are cleared by writing to the corresponding event flag bit.

Details of each of the event flags can be found in Table 11.

When an interrupt enable bit is set high, the corresponding event

flag bit reflects a positively tripped (that is, latched on the rising

edge of the event_flag_source version of the event_flag_source

IRQ

signal. This signal also asserts the external

. When an

interrupt enable bit is set low, the event flag bit reflects the

current status of the event_flag_source signal, and the event flag

IRQ

has no effect on the external

.

0

1

EVENT_FLAG

IRQ

INTERRUPT

SOURCE

INTERRUPT_ENABLE

OTHER

INTERRUPT

SOURCES

EVENT_FLAG_SOURCE

WRITE_1_TO_EVENT_FLAG

DEVICE_RESET

IRQ

Figure 84. Simplified Schematic of

Circuitry

Rev. 0 | Page 54 of 56

AD9122

INTERFACE TIMING VALIDATION

The AD9122 provides on-chip sample error detection (SED)

circuitry that simplifies verification of the input data interface.

The SED compares the input data samples captured at the digital

input pins with a set of comparison values. The comparison values

are loaded into registers through the SPI port. Differences between

the captured values and the comparison values are detected and

stored. Options are available for customizing SED test sequencing

and error handling.

The sample error, compare pass, and compare fail flags can be

IRQ

configured to trigger an

when active, if desired. This is

done by enabling the appropriate bits in the event flag register

(Register 0x07).

Table 26 shows a progression of the input sample comparison

results and the corresponding states of the error flags.

SED EXAMPLE

Normal Operation

SED OPERATION

The following example illustrates the SED configuration for

continuously monitoring the input data and assertion of an

when a single error is detected.

The SED circuitry operates on a data set made up of four 16-bit

input words, denoted as I0, Q0, I1, and Q1. To properly align

the input samples, the first I and Q data-words (that is, I0 and

Q0) are indicated by asserting the FRAME signal for a

minimum of two complete input samples.

IRQ

1. Write to the following registers to enable the SED and load

the comparison values.

Register 0x67 → 0x80

Register 0x68 → I0[7:0]

Register 0x69 → I0[15:8]

Register 0x6A → Q0[7:0]

Register 0x6B → Q0[15:8]

Register 0x6C → I1[7:0]

Figure 85 shows the input timing of the interface in word mode.

The FRAME signal can be issued once at the start of the data

transmission, or it can be asserted repeatedly at intervals coinciding

with the I0 and Q0 data-words.

FRAME

Register 0x6D → I1[15:8]

Register 0x6E → Q1[7:0]

DATA[15:0]

I0

Q0

I1

Q1

I0

Q0

Register 0x6F → Q1[15:8]

Figure 85. Timing Diagram of Extended FRAME Signal Required to Align

Input Data for SED

Comparison values can be chosen arbitrarily; however,

choosing values that require frequent bit toggling provides

the most robust test.

The SED has three flag bits (Register 0x67, Bit 0, Bit 1, and

Bit 5) that indicate the results of the input sample comparisons.

The sample error detected bit (Register 0x67, Bit 5) is set when

an error is detected and remains set until cleared. The SED also

provides registers that indicate which input data bits experienced

errors (Register 0x70 through Register 0x73). These bits are

latched and indicate the accumulated errors detected until cleared.

IRQ

2. Enable the SED error detect flag to assert the

Register 0x05 → 0x04

3. Begin transmitting the input data pattern.

pin.

IRQ

If

is asserted, read Register 0x67 and Register 0x70 through

Register 0x73 to verify that a SED error was detected and determine

which input bits were in error. The bits in Register 0x70 through

Register 0x73 are latched; therefore, the bits indicate any errors

that occurred on those bits throughout the test and not just the

errors that caused the error detected flag to be set.

The autoclear mode has two effects: it activates the compare fail

bit and the compare pass bit (Register 0x67, Bit 1 and Bit 0) and

changes the behavior of Register 0x70 through Register 0x73. The

compare pass bit sets if the last comparison indicated the

sample was error free. The compare fail bit sets if an error is

detected. The compare fail bit is automatically cleared by the

reception of eight consecutive error-free comparisons. When

autoclear mode is enabled, Register 0x70 through Register 0x73

accumulate errors as previously described but reset to all 0s after

eight consecutive error-free sample comparisons are made.

Table 26. Progression of Comparison Outcomes and the Resulting SED Register Values

Compare Results (Pass/Fail)

P

0

1

F

1

0

F

1

0

F

1

0

P

1

P

1

P

1

P

1

P

1

P

1

P

1

P

1

P

1

0

1

F

1

0

P

1

F

1

0

Register 0x6ꢀ, Bit 5 (Sample Error Detected)

Register 0x6ꢀ, Bit 1 (Compare Fail)

Register 0x6ꢀ, Bit 0 (Compare Pass)

Register 0xꢀ0 to Register 0xꢀ3

(Errors Detected x_BITS[15:0])

Z¹N²N²N²N²N²N²N²N²N²N²N²Z¹N²N²N²

¹Z = all 0s.

²N = nonzero.

Rev. 0 | Page 55 of 56

AD9122

OUTLINE DIMENSIONS

0.60

0.42

0.24

10.00

BSC SQ

0.60

0.42

0.24

PIN 1

INDICATOR

55

54

72

1

PIN 1

INDICATOR

0.50

BSC

9.75

BSC SQ

6.15

6.00 SQ

5.85

TOP VIEW

EXPOSED PAD

(BOTTOM VIEW)

0.50

0.40

0.30

18

37

36

19

0.80 MAX

0.65 TYP

12° MAX

1.00

0.85

0.80

8.50 REF

0.05 MAX

0.02 NOM

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

COPLANARITY

0.08

0.30

0.23

0.18

SEATING

PLANE

0.20 REF

SECTION OF THIS DATA SHEET.

COMPLIANT TO JEDEC STANDARDS MO-220-VNND-4

Figure 86. 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

10 mm × 10 mm Body, Very Thin Quad

(CP-72-7)

Dimensions shown in millimeters

ORDERING GUIDE

Model

AD9122BCPZ¹

AD9122BCPZRL¹

AD9122-M53ꢀ2-EBZ¹

AD9122-M53ꢀ5-EBZ¹

Temperature Range

Package Description

Package Option

CP-ꢀ2-ꢀ

−40°C to +85°C

ꢀ2-lead LFCSP_VQ

Evaluation Board Connected to ADL53ꢀ2 Modulator

Evaluation Board Connected to ADL53ꢀ5 Modulator

¹Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D08281-0-9/09(0)

Rev. 0 | Page 56 of 56


型号：	AD9122
厂家：	ADI
描述：	Dual, 16-Bit, 1200 MSPS, TxDAC+® Digital-to-Analog Converter 双通道， 16位， 1200 MSPS ，通道TxDAC + ®数字 - 模拟转换器转换器
文件：	总56页 (文件大小：910K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD9122 [ADI]

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