AD9204BCPZRL7-40_技术文档

10-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS,

1.8 V Dual Analog-to-Digital Converter

Data Sheet

AD9204

FEATURES

FUNCTIONAL BLOCK DIAGRAM

AVDD

GND

SDIO SCLK CSB

1.8 V analog supply operation

1.8 V to 3.3 V output supply

SNR

SPI

ORA

D9A

61.3 dBFS at 9.7 MHz input

61.0 dBFS at 200 MHz input

SFDR

PROGRAMMING DATA

VIN+A

VIN–A

ADC

D0A

75 dBc at 9.7 MHz input

73 dBc at 200 MHz input

DCOA

VREF

Low power

SENSE

DRVDD

AD9204

30 mW per channel at 20 MSPS

63 mW per channel at 80 MSPS

Differential input with 700 MHz bandwidth

On-chip voltage reference and sample-and-hold circuit

DNL = 0.11 LSB

REF

SELECT

VCM

ORB

D9B

RBIAS

VIN–B

VIN+B

ADC

D0B

Serial port control options

DCOB

Scalable analog input: 1 V p-p to 2 V p-p differential

Offset binary, gray code, or twos complement data format

Optional clock duty cycle stabilizer

Integer 1-to-8 input clock divider

Built-in selectable digital test pattern generation

Energy-saving power-down modes

Data clock out with programmable clock and data

alignment

DIVIDE

1 TO 8

DUTY CYCLE

STABILIZER

MODE

CONTROLS

CLK+ CLK–

SYNC

DCS

PDWN DFS OEB

Figure 1.

PRODUCT HIGHLIGHTS

1. The AD9204 operates from a single 1.8 V analog power

supply and features a separate digital output driver supply

to accommodate 1.8 V to 3.3 V logic families.

APPLICATIONS

Communications

2. The patented sample-and-hold circuit maintains excellent

performance for input frequencies up to 200 MHz and is

designed for low cost, low power, and ease of use.

3. A standard serial port interface supports various product

features and functions, such as data output formatting,

internal clock divider, power-down, DCO/DATA timing

and offset adjustments, and voltage reference modes.

4. The AD9204 is packaged in a 64-lead RoHS compliant

LFCSP that is pin compatible with the AD9268 16-bit

ADC, the AD9251 and AD9258 14-bit ADCs, and the

AD9231 12-bit ADC, enabling a simple migration path

between 10-bit and 16-bit converters sampling from

20 MSPS to 125 MSPS.

Diversity radio systems

Multimode digital receivers

GSM, EDGE, W-CDMA, LT E, CDMA2000, WiMAX, TD-SCDMA

I/Q demodulation systems

Smart antenna systems

Battery-powered instruments

Handheld scope meters

Ultrasound

Radar/LIDAR

PET/SPECT imaging

Rev. A

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AD9204* PRODUCT PAGE QUICK LINKS

Last Content Update: 02/23/2017

COMPARABLE PARTS

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TOOLS AND SIMULATIONS

• Visual Analog

• AD9204 IBIS Models

EVALUATION KITS

• AD9204/AD9231/AD9251 S-Parameter Data

• AD9204 Evaluation Board

REFERENCE MATERIALS

Product Selection Guide

• RF Source Booklet

DOCUMENTATION

Application Notes

• AN-1142: Techniques for High Speed ADC PCB Layout

Technical Articles

• AN-742: Frequency Domain Response of Switched-

• Improve The Design Of Your Passive Wideband ADC

Capacitor ADCs

Front-End Network

• AN-812: MicroController-Based Serial Port Interface (SPI)

• MS-2210: Designing Power Supplies for High Speed ADC

Boot Circuit

• AN-827: A Resonant Approach to Interfacing Amplifiers to

Switched-Capacitor ADCs

DESIGN RESOURCES

• AD9204 Material Declaration

• PCN-PDN Information

• Quality And Reliability

• Symbols and Footprints

• AN-877: Interfacing to High Speed ADCs via SPI

• AN-878: High Speed ADC SPI Control Software

• AN-905: Visual Analog Converter Evaluation Tool Version

1.0 User Manual

• AN-935: Designing an ADC Transformer-Coupled Front

End

DISCUSSIONS

View all AD9204 EngineerZone Discussions.

Data Sheet

• AD9204: 10-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8

SAMPLE AND BUY

V Dual Analog-to-Digital Converter Data Sheet

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User Guides

• UG-003: Evaluating the AD9650/AD9268/AD9258/

AD9251/AD9231/AD9204 Analog-to-Digital Converters

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AD9204

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Voltage Reference ....................................................................... 22

Clock Input Considerations...................................................... 23

Power Dissipation and Standby Mode .................................... 25

Digital Outputs ........................................................................... 26

Timing ......................................................................................... 26

Built-In Self-Test (BIST) and Output Test .................................. 27

Built-In Self-Test (BIST)............................................................ 27

Output Test Modes..................................................................... 27

Channel/Chip Synchronization.................................................... 28

Serial Port Interface (SPI).............................................................. 29

Configuration Using the SPI..................................................... 29

Hardware Interface..................................................................... 30

Configuration Without the SPI ................................................ 30

SPI Accessible Features.............................................................. 30

Memory Map .................................................................................. 31

Reading the Memory Map Register Table............................... 31

Open Locations .......................................................................... 31

Default Values............................................................................. 31

Memory Map Register Table..................................................... 32

Memory Map Register Descriptions........................................ 34

Applications Information.............................................................. 35

Design Guidelines ...................................................................... 35

Outline Dimensions....................................................................... 36

Ordering Guide .......................................................................... 36

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

General Description......................................................................... 3

Specifications..................................................................................... 4

DC Specifications ......................................................................... 4

AC Specifications.......................................................................... 5

Digital Specifications ................................................................... 6

Switching Specifications .............................................................. 7

Timing Specifications .................................................................. 8

Absolute Maximum Ratings............................................................ 9

Thermal Characteristics .............................................................. 9

ESD Caution.................................................................................. 9

Pin Configuration and Function Descriptions........................... 10

Typical Performance Characteristics ........................................... 12

AD9204-80 .................................................................................. 12

AD9204-65 .................................................................................. 14

AD9204-40 .................................................................................. 15

AD9204-20 .................................................................................. 16

Equivalent Circuits......................................................................... 17

Theory of Operation ...................................................................... 19

ADC Architecture ...................................................................... 19

Analog Input Considerations.................................................... 19

REVISION HISTORY

9/2016—Rev. 0 to Rev. A

Changes to Figure 3.......................................................................... 7

Changes to Clock Input Options Section.................................... 24

7/2009—Revision 0: Initial Version

Rev. A | Page 2 of 36

Data Sheet

AD9204

GENERAL DESCRIPTION

The AD9204 is a monolithic, dual-channel, 1.8 V supply, 10-bit,

20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital converter

(ADC). It features a high performance sample-and-hold circuit

and on-chip voltage reference.

A differential clock input controls all internal conversion cycles.

An optional duty cycle stabilizer (DCS) compensates for wide

variations in the clock duty cycle while maintaining excellent

overall ADC performance.

The product uses multistage differential pipeline architecture

with output error correction logic to provide 10-bit accuracy at

80 MSPS data rates and to guarantee no missing codes over the

full operating temperature range.

The digital output data is presented in offset binary, gray code, or

twos complement format. A data output clock (DCO) is provided

for each ADC channel to ensure proper latch timing with receiving

logic. Both 1.8 V and 3.3 V CMOS levels are supported and output

data can be multiplexed onto a single output bus.

The ADC contains several features designed to maximize

flexibility and minimize system cost, such as programmable

clock and data alignment and programmable digital test pattern

generation. The available digital test patterns include built-in

deterministic and pseudorandom patterns, along with custom

user-defined test patterns entered via the serial port interface (SPI).

The AD9204 is available in a 64-lead RoHS compliant LFCSP

and is specified over the industrial temperature range (−40°C

to +85°C).

Rev. A | Page 3 of 36

AD9204

Data Sheet

SPECIFICATIONS

DC SPECIFICATIONS

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS,

DCS disabled, unless otherwise noted.

Table 1.

AD9204-20/AD9204-40

Temp Min Typ Max

AD9204-65

AD9204-80

Parameter

Min

Typ

Max

Min

Typ

Max

Unit

RESOLUTION

Full

10

Bits

ACCURACY

No Missing Codes

Offset Error

Full

25°C

Full

25°C

Guaranteed

0.1

+1.8

Guaranteed

0.1

Guaranteed

0.1

0.70

0.50

0.30

0.60

0.70 % FSR

% FSR

0.30 LSB

LSB

0.60 LSB

LSB

Gain Error¹

+1.8

Differential Nonlinearity (DNL)²

0.30

0.60

0.075

0.15

0.25

0.11

0.25

Integral Nonlinearity (INL)²

0.15

MATCHING CHARACTERISTICS

Offset Error

Gain Error¹

25°C

0.0

0.3

0.75

0.0

0.3

0.75

0.0

0.3

0.75 % FSR

% FSR

TEMPERATURE DRIFT

Offset Error

Full

2

ppm/°C

INTERNAL VOLTAGE REFERENCE

Output Voltage (1 V Mode)

Load Regulation Error at 1.0 mA

INPUT REFERRED NOISE

VREF = 1.0 V

Full

0.981 0.993

2

1.005

0.981 0.993 1.005 0.981 0.993 1.005

V

mV

2

25°C

0.06

0.08

LSB rms

ANALOG INPUT

Input Span, VREF = 1.0 V

Input Capacitance³

Input Common-Mode Voltage

Input Common-Mode Range

REFERENCE INPUT RESISTANCE

POWER SUPPLIES

Supply Voltage

AVDD

DRVDD

Full

2

6

0.9

2

6

0.9

2

6

0.9

V p-p

pF

V

0.5

1.3

0.5

1.3

0.5

1.3

V

7.5

1.8

7.5

1.8

kΩ

Full

1.7

1.8

1.9

3.6

1.7

1.9

3.6

1.7

1.9

3.6

V

Supply Current

IAVDD²

Full

33.5/46.4 35.8/49.6

2.6/4.4

5.0/8.3

61.1

6.5

12.4

64.8

70.3

8.0

15.3

75.2

mA

IDRVDD²(1.8 V)

IDRVDD²(3.3 V)

POWER CONSUMPTION

DC Input

Sine Wave Input²(DRVDD = 1.8 V)

Sine Wave Input²(DRVDD = 3.3 V)

Standby Power⁴

Full

59.5/82.1

64.9/91.4 69.5/97.7

76.7/111

37/37

2.2

108

121.7 128.5

150.8

37

2.2

125

141

177

37

mW

150

Power-Down Power

2.2

¹Measured with a 1.0 V external reference.

²Measured with a 10 MHz input frequency at rated sample rate, full-scale sine wave, with approximately 5 pF loading on each output bit.

³Input capacitance refers to the effective capacitance between one differential input pin and AGND.

⁴Standby power is measured with a dc input, the CLK active.

Rev. A | Page 4 of 36

Data Sheet

AD9204

AC SPECIFICATIONS

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS,

DCS disabled, unless otherwise noted.

Table 2.

AD9204-20/AD9204-40

AD9204-65

Min Typ Max Min Typ

AD9204-80

Parameter¹

Temp Min

Typ

Max

Max Unit

SIGNAL-TO-NOISE RATIO (SNR)

f_IN= 9.7 MHz

f_IN= 30.5 MHz

25°C

Full

25°C

Full

25°C

61.7

61.6

61.5

61.4

61.3

dBFS

61.0

60.1

60.5

59.7

f_IN= 70 MHz

61.6

61.4

61.0

61.3

61.0

60.4

59.5

f_IN= 200 MHz

SIGNAL-TO-NOISE-AND DISTORTION (SINAD)

f_IN= 9.7 MHz

f_IN= 30.5 MHz

25°C

Full

25°C

Full

61.5

61.2

61.1

dBFS

f_IN= 70 MHz

61.5

61.2

60

61.1

60

f_IN= 200 MHz

25°C

EFFECTIVE NUMBER OF BITS (ENOB)

f_IN= 9.7 MHz

f_IN= 30.5 MHz

f_IN= 70 MHz

f_IN= 200 MHz

25°C

9.9

9.8

9.6

9.8

9.6

Bits

WORST SECOND OR THIRD HARMONIC

f_IN= 9.7 MHz

f_IN= 30.5 MHz

25°C

Full

25°C

Full

−81

−78

dBc

−65

−64

f_IN= 70 MHz

−82

−78

−73

−78

−73

−64

f_IN= 200 MHz

25°C

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

f_IN= 9.7 MHz

f_IN= 30.5 MHz

25°C

Full

25°C

Full

78

75

dBc

65

64

f_IN= 70 MHz

78

75

73

75

73

64

f_IN= 200 MHz

25°C

WORST OTHER (HARMONIC OR SPUR)

f_IN= 9.7 MHz

f_IN= 30.5 MHz

25°C

Full

25°C

Full

−82

−80

dBc

−71

−70

f_IN= 70 MHz

−82

−80

−70

f_IN= 200 MHz

25°C

TWO-TONE SFDR

f_IN= 30.5 MHz (−7 dBFS), 32.5 MHz (−7 dBFS)

CROSSTALK²

25°C

Full

78

dBc

MHz

−100

700

−100

700

−100

700

ANALOG INPUT BANDWIDTH

25°C

¹See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.

²Crosstalk is measured at 100 MHz with −1.0 dBFS on one channel and no input on the alternate channel.

Rev. A | Page 5 of 36

AD9204

Data Sheet

DIGITAL SPECIFICATIONS

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS,

DCS disabled, unless otherwise noted.

Table 3.

AD9204-20/AD9204-40/AD9204-65/AD9204-80

Parameter

Temp Min

Typ

Max

Unit

DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)

Logic Compliance

Internal Common-Mode Bias

Differential Input Voltage

Input Voltage Range

High Level Input Current

Low Level Input Current

Input Resistance

CMOS/LVDS/LVPECL

0.9

Full

V

Full

0.2

GND − 0.3

−10

8

3.6

AVDD + 0.2

+10

12

V p-p

V

μA

kΩ

pF

10

4

Input Capacitance

LOGIC INPUTS (SCLK/DFS, SYNC, PDWN)¹

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Resistance

Full

1.2

0

−50

−10

DRVDD + 0.3

0.8

−75

+10

V

μA

kΩ

pF

30

2

Input Capacitance

LOGIC INPUTS (CSB)²

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Resistance

Full

1.2

0

−10

+40

DRVDD + 0.3

0.8

+10

V

μA

kΩ

pF

+135

26

2

Input Capacitance

LOGIC INPUTS (SDIO/DCS)²

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Resistance

Full

1.2

0

−10

+40

DRVDD + 0.3

0.8

+10

V

μA

kΩ

pF

+130

26

5

Input Capacitance

DIGITAL OUTPUTS

DRVDD = 3.3 V

High Level Output Voltage, I_OH= 50 μA

High Level Output Voltage, I_OH= 0.5 mA

Low Level Output Voltage, I_OL= 1.6 mA

Low Level Output Voltage, I_OL= 50 μA

DRVDD = 1.8 V

Full

3.29

3.25

V

0.2

0.05

High Level Output Voltage, I_OH= 50 μA

High Level Output Voltage, I_OH= 0.5 mA

Low Level Output Voltage, I_OL= 1.6 mA

Low Level Output Voltage, I_OL= 50 μA

Full

1.79

1.75

V

0.2

0.05

¹Internal 30 kΩ pull-down.

²Internal 30 kΩ pull-up.

Rev. A | Page 6 of 36

Data Sheet

AD9204

SWITCHING SPECIFICATIONS

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS,

DCS disabled, unless otherwise noted.

Table 4.

AD9204-20/AD9204-40

AD9204-65

Typ

AD9204-80

Parameter

Temp

Min

Typ

Max

Min

Max Min Typ

Max Unit

CLOCK INPUT PARAMETERS

Input Clock Rate

Conversion Rate¹

CLK Period—Divide-by-1 Mode (t_CLK

CLK Pulse Width High (t_CH)

Aperture Delay (t_A)

Aperture Uncertainty (Jitter, t_J)

DATA OUTPUT PARAMETERS

Data Propagation Delay (t_PD)

Full

625

20/40

625

65

625

80

MHz

MSPS

ns

3

12.5

50/25

)

15.38

25.0/12.5

1.0

0.1

7.69

1.0

0.1

6.25

1.0

0.1

Full

ps rms

Full

3

0.1

9

350

600/400

2

3

ns

Cycles

μs

DCO Propagation Delay (t_DCO

)

DCO to Data Skew (t_SKEW

)

0.1

9

350

300

2

0.1

9

350

260

2

Pipeline Delay (Latency)

Wake-Up Time²

Standby

ns

OUT-OF-RANGE RECOVERY TIME

Cycles

¹Conversion rate is the clock rate after the CLK divider.

²Wake-up time is dependent on the value of the decoupling capacitors.

N – 1

N + 4

t_A

N + 5

N

N + 3

VIN

N + 1

N + 2

t_CH

t_CLK

CLK+

CLK–

t_DCO

DCOA/DCOB

t_SKEW

CH A/CH B DATA

N – 9

N – 8

N – 7

N – 6

N – 5

t_PD

Figure 2. CMOS Output Data Timing

N – 1

N + 4

t_A

N + 5

N

N + 3

VIN

N + 1

N + 2

t_CH

t_CLK

CLK+

CLK–

t_DCO

DCOA/DCOB

t_SKEW

CH A/CH B DATA

AS APPEARS ON

CHA OUTPUT PINS

CH A CH B CH A CH B CH A CH B

N – 9 N – 9 N – 8 N – 8 N – 7 N – 7

CH A CH B

N – 6 N – 6

CH A

N – 5

t_PD

Figure 3. CMOS Interleaved Output Timing, Output as Appears on the Channel A Output Pins

Rev. A | Page 7 of 36

AD9204

Data Sheet

TIMING SPECIFICATIONS

Table 5.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

SYNC TIMING REQUIREMENTS

t_SSYNC

t_HSYNC

SYNC to rising edge of CLK setup time

SYNC to rising edge of CLK hold time

0.24

0.40

ns

SPI TIMING REQUIREMENTS

t_DS

t_DH

t_CLK

t_S

t_H

t_HIGH

t_LOW

t_{EN_SDIO}

Setup time between the data and the rising edge of SCLK

Hold time between the data and the rising edge of SCLK

Period of the SCLK

Setup time between CSB and SCLK

Hold time between CSB and SCLK

SCLK pulse width high

SCLK pulse width low

Time required for the SDIO pin to switch from an input to an

output relative to the SCLK falling edge

2

40

2

10

ns

t_{DIS_SDIO}

Time required for the SDIO pin to switch from an output to an

input relative to the SCLK rising edge

10

ns

CLK+

t_SSYNC

t_HSYNC

SYNC

Figure 4. SYNC Input Timing Requirements

Rev. A | Page 8 of 36

Data Sheet

AD9204

ABSOLUTE MAXIMUM RATINGS

THERMAL CHARACTERISTICS

Table 6.

Parameter

Rating

The exposed paddle is the only ground connection for the chip.

The exposed paddle must be soldered to the AGND plane of the

user circuit board. Soldering the exposed paddle to the user

board also increases the reliability of the solder joints and

maximizes the thermal capability of the package.

AVDD to AGND

DRVDD to AGND

VIN+A, VIN+B, VIN−A, VIN−B to AGND

CLK+, CLK− to AGND

SYNC to AGND

VREF to AGND

SENSE to AGND

VCM to AGND

RBIAS to AGND

−0.3 V to +2.0 V

−0.3 V to +3.9 V

−0.3 V to AVDD + 0.2 V

−0.3 V to DRVDD + 0.3 V

−0.3 V to AVDD + 0.2 V

−0.3 V to DRVDD + 0.3 V

−40°C to +85°C

Table 7. Thermal Resistance

Airflow

Velocity

(m/sec)

1, 2

1, 3

1, 4

Package Type

θ_JA

23

20

18

θ_JC

2.0

θ_JB

Unit

°C/W

64-Lead LFCSP

9 mm × 9 mm

(CP-64-4)

0

CSB to AGND

1.0

2.5

12

SCLK/DFS to AGND

SDIO/DCS to AGND

OEB to AGND

¹Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board.

PDWN to AGND

²Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).

³Per MIL-Std 883, Method 1012.1.

D0A/D0B Through D13A/D13B to AGND

DCOA/DCOB to AGND

Operating Temperature Range (Ambient)

Maximum Junction Temperature

Under Bias

⁴Per JEDEC JESD51-8 (still air).

Typical θ_JAis specified for a 4-layer PCB with a solid ground

plane. As shown in Table 7, airflow improves heat dissipation,

which reduces θ_JA. In addition, metal in direct contact with the

package leads from metal traces, through holes, ground, and

power planes reduces the θ_JA.

150°C

Storage Temperature Range (Ambient)

−65°C to +150°C

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

ESD CAUTION

Rev. A | Page 9 of 36

AD9204

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN 1

INDICATOR

CLK+

CLK–

SYNC

NC

1

2

3

4

5

6

7

8

9

48 PDWN

47 OEB

46 CSB

45 SCLK/DFS

44 SDIO/DCS

43 ORA

42 D9A (MSB)

41 D8A

40 D7A

39 D6A

38 D5A

37 DRVDD

36 D4A

AD9204

TOP VIEW

(Not to Scale)

DRVDD 10

D0B (LSB) 11

D1B 12

D2B 13

D3B 14

35 D3A

D4B 15

34 D2A

D5B 16

33 D1A

NOTES

1. NC = NO CONNECT

2. THE EXPOSED PADDLE MUST BE SOLDERED TO THE PCB GROUND

TO ENSURE PROPER HEAT DISSIPATION, NOISE, AND MECHANICAL

STRENGTH BENEFITS.

Figure 5. Pin Configuration

Table 8. Pin Function Description

Pin No.

Mnemonic

Description

0

1, 2

3

GND

CLK+, CLK−

SYNC

Exposed paddle is the only ground connection for the chip. Must be connected to PCB AGND.

Differential Encode Clock. PECL, LVDS, or 1.8 V CMOS inputs.

Digital Input. SYNC input to clock divider. 30 kΩ internal pull-down.

Do Not Connect.

4, 5, 6, 7, 8, 9, 25, 26, 27,

29, 30, 31

NC

10, 19, 28, 37

11 to 18, 20, 21

22

23

DRVDD

D0B to D9B

ORB

DCOB

DCOA

D0A to D9A

ORA

SDIO/DCS

Digital Output Driver Supply (1.8 V to 3.3 V).

Channel B Digital Outputs. D9B = MSB.

Channel B Out-of-Range Digital Output.

Channel B Data Clock Digital Output.

Channel A Data Clock Digital Output.

Channel A Digital Outputs. D9A = MSB.

Channel A Out-of-Range Digital Output.

24

32 to 36, 38 to 42

43

44

SPI Data Input/Output (SDIO). Bidirectional SPI Data I/O in SPI mode. 30 kΩ internal pull-

down in SPI mode.

Duty Cycle Stabilizer (DCS). Static enable input for duty cycle stabilizer in non-SPI mode.

30 kΩ internal pull-up in non-SPI (DCS) mode.

45

SCLK/DFS

SPI Clock (SCLK) Input in SPI mode. 30 kΩ internal pull-down.

Data Format Select (DFS). Static control of data output format in non-SPI mode. 30 kΩ internal

pull-down.

DFS high = twos complement output.

DFS low = offset binary output.

46

47

CSB

OEB

SPI Chip Select. Active low enable; 30 kΩ internal pull-up.

Digital Input. Enable Channel A and Channel B digital outputs if low, three-state outputs if

high. 30 kΩ internal pull-down.

48

PDWN

Digital Input. 30 kΩ internal pull-down.

PDWN high = power-down device.

PDWN low = run device, normal operation.

Rev. A | Page 10 of 36

Data Sheet

AD9204

Pin No.

Mnemonic

Description

49, 50, 53, 54, 59, 60, 63, 64 AVDD

1.8 V Analog Supply Pins.

51, 52

55

56

57

58

VIN+A, VIN−A Channel A Analog Inputs.

VREF

SENSE

VCM

Voltage Reference Input/Output.

Reference Mode Selection.

Analog output voltage at midsupply to set common mode of the analog inputs.

Sets Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground.

RBIAS

61, 62

VIN−B, VIN+B Channel B Analog Inputs.

Rev. A | Page 11 of 36

AD9204

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

AD9204-80

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS

disabled, unless otherwise noted.

0

80MSPS

30.5MHz @ –1dBFS

SNR = 60.5dB (61.5dBFS)

SFDR = 83.5dBc

9.7MHz @ –1dBFS

SNR = 60.5dB (61.5dBFS)

SFDR = 80.3dBc

–20

–40

–60

–80

–100

–120

–100

–120

0

5

10

15

20

25

30

35

40

0

5

10

15

20

25

30

35

40

FREQUENCY (MHz)

Figure 6. AD9204-80 Single-Tone FFT with f_IN= 9.7 MHz

Figure 9. AD9204-80 Single-Tone FFT with f_IN= 30.5 MHz

0

80MSPS

200MHz @ –1dBFS

SNR = 60.1dB (60.1dBFS)

SFDR = 74.176dBc

80MSPS

70.3MHz @ –1dBFS

SNR = 60.4dB (61.4dBFS)

SFDR = 82.2dBc

–20

–40

–60

2

–80

3

+

6

5

4

–100

–120

–100

–120

0

5

10

15

20

25

30

35

0

5

10

15

20

25

30

35

40

FREQUENCY (MHz)

Figure 7. AD9204-80 Single-Tone FFT with f_IN= 70.3 MHz

Figure 10. AD9204-80 Single-Tone FFT with f_IN=200 MHz

0

80MSPS

30.5MHz @ –7dBFS

32.5MHz @ –7dBFS

SFDR = 78dBc

–15

–10

–30

–45

–60

SFDR (dBc)

–30

IMD3 (dBc)

–50

F1 + F2

2F1 – F2

2F2 + F1

SFDR (dBFS)

–70

–75

–90

F2 – F1

2F1 – F2

–90

IMD3 (dBFS)

–105

–120

–110

–60

–54

–48

–42

–36

–30

–24

–18

–12

–6

0

4

8

12

16

20

24

28

32

36

INPUT AMPLITUDE (dBFS)

FREQUENCY (MHz)

Figure 8. AD9204-80 Two-Tone FFT with f_IN1= 30.5 MHz and f_IN2= 32.5 MHz

Figure 11. AD9204-80 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with

f_IN1= 30.5 MHz and f_IN2= 32.5 MHz

Rev. A | Page 12 of 36

Data Sheet

AD9204

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS

disabled, unless otherwise noted.

85

90

80

75

70

65

60

55

50

80

70

60

50

40

30

20

10

0

SFDRFS

SNRFS

SFDR (dBc)

SNR (dBFS)

SFDR

SNR

0

50

100

150

200

–60

–50

–40

–30

–20

–10

0

AIN FREQUENCY (MHz)

INPUT AMPLITUDE (dBc)

Figure 12. AD9204-80 SNR/SFDR vs. Input Frequency (AIN) with

2 V p-p Full Scale

Figure 15. AD9204-80 SNR/SFDR vs. Input Amplitude (AIN) with f_IN= 9.7MHz

85

120,000

100,000

80,000

60,000

40,000

20,000

0

SFDR (dBc)

80

75

70

65

SNR (dBFS)

60

0

10

20

30

40

50

60

70

80

N – 3

N – 2

N – 1

N

N + 1

N + 2

N + 3

SAMPLE RATE (MHz)

OUTPUT CODE

Figure 13. AD9204-80 SNR/SFDR vs. Sample Rate with AIN = 9.7 MHz

Figure 16. AD9204-80 Grounded Input Histogram

0.20

0.16

0.12

0.08

0.04

0

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.04

–0.08

–0.12

–0.16

–0.20

24

224

424

624

824

1024

24

224

424

624

824

1024

OUTPUT CODE

Figure 14. AD9204-80 DNL with f_IN= 9.7 MHz

Figure 17. AD9204-80 INL with f_IN= 9.7 MHz

Rev. A | Page 13 of 36

AD9204

Data Sheet

AD9204-65

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS

disabled, unless otherwise noted.

0

65MSPS

9.7MHz @ –1dBFS

SNR = 60.6dB (61.6dBFS)

SFDR = 83.1dBc

–10

–20

–40

–30

–50

SFDR (dBc)

IMD3 (dBc)

–60

–70

–90

–80

SFDR (dBFS)

–100

–120

IMD3 (dBFS)

–48

–110

–60

–54

–42

–36

–30

–24

–18

–12

–6

0

5

10

15

20

25

30

INPUT AMPLITUDE (dBFS)

FREQUENCY (MHz)

Figure 18. AD9204-65 Single-Tone FFT with f_IN= 9.7 MHz

Figure 21. AD9204-65 SNR/SFDR vs. Input Amplitude (AIN) with f_IN= 9.7 MHz

0

85

65MSPS

70.3MHz @ –1dBFS

SNR = 60.6dB (61.6dBFS)

SFDR = 83.4dBc

80

–20

SFDR (dBc)

75

70

–40

–60

65

SNR (dBFS)

–80

60

55

50

–100

–120

0

5

10

15

20

25

30

0

50

100

150

200

FREQUENCY (MHz)

AIN FREQUENCY (MHz)

Figure 22. AD9204-65 SNR/SFDR vs. Input Frequency (AIN) with

2 V p-p Full Scale

Figure 19. AD9204-65 Single-Tone FFT with f_IN= 70.3 MHz

0

65MSPS

30.5MHz @ –1dBFS

–20

SNR = 60.6dB (61.6dBFS)

SFDR = 83.9dBc

–40

–60

–80

–100

–120

0

5

10

15

20

25

30

FREQUENCY (MHz)

Figure 20. AD9204-65 Single-Tone FFT with f_IN= 30.5 MHz

Rev. A | Page 14 of 36

Data Sheet

AD9204

AD9204-40

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS

disabled, unless otherwise noted.

90

80

70

60

50

40

30

20

10

0

40MSPS

SFDRFS

SNRFS

9.7MHz @ –1dBFS

SNR = 60.6dB (61.6dBFS)

SFDR = 82.0dBc

–20

–40

–60

SFDR

–80

SNR

–100

–120

–60

–50

–40

–30

–20

–10

0

5

10

FREQUENCY (MHz)

15

20

INPUT AMPLITUDE (dBc)

Figure 23. AD9204-40 Single-Tone FFT with f_IN= 9.7 MHz

Figure 25. AD9204-40 SNR/SFDR vs. Input Amplitude (AIN) with f_IN= 9.7 MHz

0

40MSPS

30.5MHz @ –1dBFS

SNR = 60.6dB (61.6dBFS)

SFDR = 83.8dBc

–20

–40

–60

–80

–100

–120

0

2

4

6

8

10

12

14

16

18

20

FREQUENCY (MHz)

Figure 24. AD9204-40 Single-Tone FFT with f_IN= 30.5 MHz

Rev. A | Page 15 of 36

AD9204

Data Sheet

AD9204-20

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS

disabled, unless otherwise noted.

0

90

80

70

60

50

40

30

20

10

0

20MSPS

SFDR (dBFS)

9.7MHz @ –1dBFS

SNR = 60.6dBFS (61.6dBFS)

SFDR = 81.3dBc

–20

SNR (dBFS)

–40

–60

SFDR (dBc)

SNR (dBc)

–80

–100

–120

–10

0

2

4

6

8

10

–60

–50

–40

–30

–20

0

FREQUENCY (MHz)

INPUT AMPLITUDE (dBc)

Figure 26. AD9204-20 Single-Tone FFT with f_IN= 9.7 MHz

Figure 28. AD9204-20 SNR/SFDR vs. Input Amplitude (AIN) with f_IN= 9.7MHz

0

20MSPS

30.5MHz @ –1dBFS

SNR = 60.6dBFS (61.6dBFS)

SFDR = 84.0dBc

–20

–40

–60

–80

–100

–120

0

2

4

6

8

10

FREQUENCY (MHz)

Figure 27. AD9204-20 Single-Tone FFT with f_IN= 30.5 MHz

Rev. A | Page 16 of 36

Data Sheet

AD9204

EQUIVALENT CIRCUITS

DRVDD

AVDD

VIN±x

Figure 29. Equivalent Analog Input Circuit

Figure 32. Equivalent Digital Output Circuit

5Ω

CLK+

15kΩ

0.9V

DRVDD

5Ω

CLK–

350Ω

SCLK/DFS, SYNC,

OEB, AND PDWN

30kΩ

Figure 30. Equivalent Clock Input Circuit

Figure 33. Equivalent SCLK/DFS, SYNC, OEB, and PDWN Input Circuit

AVDD

DRVDD

30kΩ

350Ω

SDIO/DCS

375Ω

RBIAS

30kΩ

AND VCM

Figure 34. Equivalent RBIAS, VCM Circuit

Figure 31. Equivalent SDIO/DCS Input Circuit

Rev. A | Page 17 of 36

AD9204

Data Sheet

DRVDD

AVDD

30kΩ

350Ω

CSB

375Ω

VREF

7.5kΩ

Figure 35. Equivalent CSB Input Circuit

Figure 37. Equivalent VREF Circuit

AVDD

375Ω

SENSE

Figure 36. Equivalent SENSE Circuit

Rev. A | Page 18 of 36

Data Sheet

AD9204

THEORY OF OPERATION

The AD9204 dual ADC design can be used for diversity

reception of signals, where the ADCs are operating identically

on the same carrier but from two separate antennae. The ADCs

can also be operated with independent analog inputs. The user

can sample any f_S/2 frequency segment from dc to 200 MHz,

using appropriate low-pass or band-pass filtering at the ADC

inputs with little loss in ADC performance. Operation to

300 MHz analog input is permitted but occurs at the

expense of increased ADC noise and distortion.

ANALOG INPUT CONSIDERATIONS

The analog input to the AD9204 is a differential switched-

capacitor circuit designed for processing differential input

signals. This circuit can support a wide common-mode range

while maintaining excellent performance. By using an input

common-mode voltage of midsupply, users can minimize

signal-dependent errors and achieve optimum performance.

In nondiversity applications, the AD9204 can be used as a base-

band or direct downconversion receiver, where one ADC is

used for I input data and the other is used for Q input data.

H

C_PAR

H

VIN+x

C_SAMPLE

Synchronization capability is provided to allow synchronized

timing among multiple channels or multiple devices.

S

C_SAMPLE

Programming and control of the AD9204 are accomplished

using a 3-bit SPI-compatible serial interface.

VIN–x

H

C_PAR

H

ADC ARCHITECTURE

The AD9204 architecture consists of a multistage, pipelined ADC.

Each stage provides sufficient overlap to correct for flash errors

in the preceding stage. The quantized outputs from each stage are

combined into a final 10-bit result in the digital correction logic.

The pipelined architecture permits the first stage to operate with

a new input sample, while the remaining stages operate with

preceding samples. Sampling occurs on the rising edge of

the clock.

Figure 38. Switched-Capacitor Input Circuit

The clock signal alternately switches the input circuit between

sample-and-hold mode (see Figure 38). When the input circuit

is switched to sample mode, the signal source must be capable

of charging the sample capacitors and settling within one-half

of a clock cycle. A small resistor in series with each input can

help reduce the peak transient current injected from the output

stage of the driving source. In addition, low Q inductors or ferrite

beads can be placed on each leg of the input to reduce high

differential capacitance at the analog inputs and, therefore,

achieve the maximum bandwidth of the ADC. Such use of low

Q inductors or ferrite beads is required when driving the converter

front end at high IF frequencies. Either a shunt capacitor or two

single-ended capacitors can be placed on the inputs to provide a

matching passive network. This ultimately creates a low-pass

filter at the input to limit unwanted broadband noise. See the

AN-742 Application Note, the AN-827 Application Note, and the

Analog Dialogue article “Transformer-Coupled Front-End for

Wideband A/D Converters” (Volume 39, April 2005) for more

information. In general, the precise values depend on the

application.

Each stage of the pipeline, excluding the last, consists of a low

resolution flash ADC connected to a switched-capacitor DAC

and an interstage residue amplifier (for example, a multiplying

digital-to-analog converter (MDAC)). The residue amplifier

magnifies the difference between the reconstructed DAC output

and the flash input for the next stage in the pipeline. One bit of

redundancy is used in each stage to facilitate digital correction

of flash errors. The last stage simply consists of a flash ADC.

The output staging block aligns the data, corrects errors, and

passes the data to the CMOS output buffers. The output buffers

are powered from a separate (DRVDD) supply, allowing adjust-

ment of the output voltage swing. During power-down, the

output buffers go into a high impedance state.

Rev. A | Page 19 of 36

AD9204

Data Sheet

Input Common Mode

The output common-mode voltage of the ADA4938-2 is easily

set with the VCM pin of the AD9204 (see Figure 41), and the

driver can be configured in a Sallen-Key filter topology to

provide band limiting of the input signal.

The analog inputs of the AD9204 are not internally dc-biased.

Therefore, in ac-coupled applications, the user must provide a

dc bias externally. Setting the device so that VCM = AVDD/2 is

recommended for optimum performance, but the device can

function over a wider range with reasonable performance, as

shown in Figure 39 and Figure 40. .

200Ω

33Ω

VIN–x

VIN

76.8Ω

AVDD

90Ω

10pF

ADC

ADA4938-2

An on-board, common-mode voltage reference is included in

the design and is available from the VCM pin. The VCM pin

must be decoupled to ground by a 0.1 μF capacitor, as described

in the Applications Information section.

0.1µF

120Ω

33Ω

VCM

VIN+x

200Ω

Figure 41. Differential Input Configuration Using the ADA4938-2

100

For baseband applications below ~10 MHz where SNR is a key

parameter, differential transformer-coupling is the recommended

input configuration. An example is shown in Figure 42. To bias

the analog input, the VCM voltage can be connected to the

center tap of the secondary winding of the transformer.

90

80

SFDR (dBc)

VIN–x

R

2V p-p

49.9Ω

70

C

ADC

R

SNR (dBFS)

VCM

VIN+x

60

0.1µF

Figure 42. Differential Transformer-Coupled Configuration

50

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

The signal characteristics must be considered when selecting

a transformer. Most RF transformers saturate at frequencies

below a few megahertz (MHz). Excessive signal power can

also cause core saturation, which leads to distortion.

INPUT COMMON-MODE VOLTAGE (V)

Figure 39. SNR/SFDR vs. Input Common-Mode Voltage,

f_IN= 32.1 MHz, f_S= 80 MSPS

100

90

80

70

60

50

At input frequencies in the second Nyquist zone and above, the

noise performance of most amplifiers is not adequate to achieve

the true SNR performance of the AD9204. For applications above

~10 MHz where SNR is a key parameter, differential double balun

coupling is the recommended input configuration (see Figure 44).

SFDR (dBc)

SNR (dBFS)

An alternative to using a transformer-coupled input at frequencies

in the second Nyquist zone is to use the AD8352 differential driver.

An example is shown in Figure 45. See the AD8352 data sheet

for more information.

In any configuration, the value of Shunt Capacitor C is dependent

on the input frequency and source impedance and may need to

be reduced or removed. Table 9 displays the suggested values to

set the RC network. However, these values are dependent on

the input signal and must be used only as a starting guide.

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

INPUT COMMON-MODE VOLTAGE (V)

Figure 40. SNR/SFDR vs. Input Common-Mode Voltage,

f_IN= 10.3 MHz, f_S= 20 MSPS

Differential Input Configurations

Table 9. Example RC Network

R Series

(Ω Each)

Optimum performance is achieved while driving the AD9204 in a

differential input configuration. For baseband applications, the

AD8138, ADA4937-2, and ADA4938-2 differential drivers provide

excellent performance and a flexible interface to the ADC.

Frequency Range (MHz)

0 to 70

70 to 200

C Differential (pF)

33

125

22

Open

Rev. A | Page 20 of 36

Data Sheet

AD9204

10µF

AVDD

1kΩ

Single-Ended Input Configuration

R

VIN+x

A single-ended input can provide adequate performance in

cost-sensitive applications. In this configuration, SFDR and

distortion performance degrade due to the large input common-

mode swing. If the source impedances on each input are matched,

there should be little effect on SNR performance. Figure 43

shows a typical single-ended input configuration.

1V p-p

0.1µF

49.9Ω

1kΩ

AVDD

ADC

C

1kΩ

R

VIN–x

10µF

0.1µF

1kΩ

Figure 43. Single-Ended Input Configuration

0.1µF

R

0.1µF

VIN+x

2V p-p

25Ω

P

A

S

P

C

ADC

0.1µF

R

VCM

VIN–x

Figure 44. Differential Double Balun Input Configuration

V

CC

0.1µF

0Ω

0.1µF

16

1

8, 13

11

0.1µF

ANALOG INPUT

R

VIN+x

2

200Ω

C

ADC

AD8352

10

R

G

C

D

3

4

5

200Ω

VCM

VIN–x

14

0.1µF

ANALOG INPUT

0Ω

0.1µF

Figure 45. Differential Input Configuration Using the AD8352

Rev. A | Page 21 of 36

AD9204

Data Sheet

In either internal or external reference mode, the maximum

input range of the ADC can be varied by configuring SPI

Address 0x18 as shown in Table 11, resulting in a selectable

differential span from 1 V p-p to 2 V p-p.

VOLTAGE REFERENCE

A stable and accurate 1.0 V voltage reference is built into the

AD9204. The VREF can be configured using either the internal

1.0 V reference or an externally applied 1.0 V reference voltage.

The various reference modes are summarized in the sections that

follow. The Reference Decoupling section describes the best

practices PCB layout of the reference.

If the internal reference of the AD9204 drives multiple

converters to improve gain matching, the loading of the reference

by the other converters must be considered. Figure 47 shows

how the internal reference voltage is affected by loading.

0

Internal Reference Connection

A comparator within the AD9204 detects the potential at the

SENSE pin and configures the reference into two possible

modes, which are summarized in Table 10. If SENSE is grounded,

the reference amplifier switch is connected to the internal resistor

divider (see Figure 46), setting VREF to 1.0 V.

–0.5

–1.0

INTERNAL V

= 0.993V

REF

–1.5

–2.0

–2.5

–3.0

VIN+A/VIN+B

VIN–A/VIN–B

ADC

CORE

VREF

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

1.0µF

0.1µF

LOAD CURRENT (mA)

SELECT

LOGIC

Figure 47. VREF Accuracy vs. Load Current

SENSE

0.5V

ADC

Figure 46. Internal Reference Configuration

Table 10. Reference Configuration Summary

Selected Mode

SENSE Voltage (V) Resulting VREF (V)

Resulting Differential Span (V p-p)

Fixed Internal Reference

Fixed External Reference

AGND to 0.2

AVDD

1.0 internal

1.0 applied to external VREF pin

2.0

Table 11. Scaled Differential Span Summary

Selected Mode

Resulting VREF (V)

SPI Register 0x18 (Hex)

Resulting Differential Span (V p-p)

Fixed Internal or External Reference

1.0 (internal or external)

0xC0

0xC8

0xD0

0xD8

0xE0

1.0

1.14

1.33

1.6

2.0

Rev. A | Page 22 of 36

Data Sheet

AD9204

Clock Input Options

External Reference Operation

The AD9204 has a very flexible clock input structure. The clock

input can be a CMOS, LVDS, LVPECL, or sine wave signal.

Regardless of the type of signal being used, clock source jitter

is of the most concern, as described in the Jitter Considerations

section.

The use of an external reference may be necessary to enhance

the gain accuracy of the ADC or improve thermal drift charac-

teristics. Figure 48 shows the typical drift characteristics of the

internal reference in 1.0 V mode.

4

Figure 50 and Figure 51 show two preferred methods for clocking

the AD9204 (at clock rates up to 625 MHz). A low jitter clock

source is converted from a single-ended signal to a differential

signal using either an RF transformer or an RF balun.

3

2

V

ERROR (mV)

REF

1

0

The RF balun configuration is recommended for clock frequencies

between 125 MHz and 625 MHz, and the RF transformer is recom-

mended for clock frequencies from 10 MHz to 200 MHz. The

back-to-back Schottky diodes across the transformer/balun

secondary limit clock excursions into the AD9204 to approx-

imately 0.8 V p-p differential.

–1

–2

–3

–4

–5

–6

This limit helps prevent the large voltage swings of the clock

from feeding through to other portions of the AD9204 while

preserving the fast rise and fall times of the signal that are critical

to a low jitter performance.

–40

–20

0

20

40

60

80

TEMPERATURE (°C)

Figure 48. Typical VREF Drift

When the SENSE pin is tied to AVDD, the internal reference is

disabled, allowing the use of an external reference. An internal

reference buffer loads the external reference with an equivalent

7.5 kΩ load (see Figure 37). The internal buffer generates the

positive and negative full-scale references for the ADC core.

Therefore, the external reference must be limited to a maximum

of 1.0 V.

®

Mini-Circuits

ADT1-1WT, 1:1 Z

0.1µF

XFMR

CLOCK

INPUT

CLK+

100Ω

50Ω

ADC

0.1µF

CLK–

SCHOTTKY

DIODES:

HSMS2822

0.1µF

CLOCK INPUT CONSIDERATIONS

Figure 50. Transformer-Coupled Differential Clock (Up to 200 MHz)

For optimum performance, clock the AD9204 sample clock

inputs, CLK+ and CLK−, with a differential signal. The signal

is typically ac-coupled into the CLK+ and CLK− pins via a

transformer or capacitors. These pins are biased internally

(see Figure 49) and require no external bias.

AVDD

1nF

50Ω

1nF

0.1µF

CLOCK

INPUT

CLK+

ADC

CLK–

SCHOTTKY

DIODES:

HSMS2822

0.9V

Figure 51. Balun-Coupled Differential Clock (Up to 625 MHz)

CLK+

CLK–

2pF

Figure 49. Equivalent Clock Input Circuit

Rev. A | Page 23 of 36

AD9204

Data Sheet

If a low jitter clock source is not available, another option is to

ac couple a differential PECL signal to the sample clock input

pins, as shown in Figure 52. The AD9510, AD9511, AD9512,

AD9513, AD9514, AD9515, AD9516-0, AD9516-1, AD9516-2,

AD9516-3, AD9516-4, AD9516-5, AD9517-0, AD9517-1,

AD9517-2, AD9517-3, and AD9517-4 clock drivers offer

excellent jitter performance.

Input Clock Divider

The AD9204 contains an input clock divider with the ability

to divide the input clock by integer values between 1 and 8.

Optimum performance can be obtained by enabling the

internal duty cycle stabilizer (DCS) when using divide ratios

other than 1, 2, or 4.

The AD9204 clock divider can be synchronized using the

external SYNC input. Bit 1 and Bit 2 of Register 0x100 allow

the clock divider to be resynchronized on every SYNC signal

or only on the first SYNC signal after the register is written. A

valid SYNC causes the clock divider to reset to the initial state.

This synchronization feature allows multiple devices to have the

clock dividers aligned to guarantee simultaneous input

sampling.

0.1µF

CLOCK

INPUT

CLK+

AD951x

PECL DRIVER

100Ω

ADC

0.1µF

CLOCK

INPUT

CLK–

240Ω

50kΩ

Figure 52. Differential PECL Sample Clock (Up to 625 MHz)

Clock Duty Cycle

A third option is to ac couple a differential LVDS signal to the

sample clock input pins, as shown in Figure 53. The AD9510,

AD9511, AD9512, AD9513, AD9514, AD9515, AD9516-0,

AD9516-1, AD9516-2, AD9516-3, AD9516-4, AD9516-5,

AD9517-0, AD9517-1, AD9517-2, AD9517-3, and AD9517-4

clock drivers offer excellent jitter performance.

Typical high speed ADCs use both clock edges to generate

a variety of internal timing signals and, as a result, may be

sensitive to clock duty cycle. Commonly, a 5% tolerance is

required on the clock duty cycle to maintain dynamic

performance characteristics.

The AD9204 contains a duty cycle stabilizer (DCS) that retimes

the nonsampling (falling) edge, providing an internal clock

signal with a nominal 50% duty cycle. This allows the user to

provide a wide range of clock input duty cycles without affecting

the performance of the AD9204. Noise and distortion perform-

ance are nearly flat for a wide range of duty cycles with the DCS

on, as shown in Figure 55.

0.1µF

CLOCK

INPUT

CLK+

AD951x

LVDS DRIVER

100Ω

ADC

0.1µF

CLOCK

INPUT

CLK–

50kΩ

Jitter in the rising edge of the input is still of concern and is not

easily reduced by the internal stabilization circuit. The duty

cycle control loop does not function for clock rates less than

20 MHz nominally. The loop has a time constant associated

with it that must be considered in applications in which the

clock rate can change dynamically. A wait time of 1.5 ꢀs to 5 ꢀs

is required after a dynamic clock frequency increase or decrease

before the DCS loop is relocked to the input signal.

80

Figure 53. Differential LVDS Sample Clock (Up to 625 MHz)

In some applications, it may be acceptable to drive the sample

clock inputs with a single-ended 1.8 V CMOS signal. In such

applications, drive the CLK+ pin directly from a CMOS gate, and

bypass the CLK− pin to ground with a 0.1 μF capacitor (see

Figure 54).

V

CC

OPTIONAL

100Ω

0.1µF

1

0.1µF

1kΩ

AD951x

CMOS DRIVER

CLOCK

INPUT

CLK+

75

70

50Ω

ADC

CLK–

DCS ON

65

0.1µF

1

60

50Ω RESISTOR IS OPTIONAL.

Figure 54. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)

55

DCS OFF

50

45

40

10

20

30

40

50

60

70

80

POSITIVE DUTY CYCLE (%)

Figure 55. SNR vs. DCS On/Off

Rev. A | Page 24 of 36

Data Sheet

AD9204

Jitter Considerations

POWER DISSIPATION AND STANDBY MODE

High speed, high resolution ADCs are sensitive to the quality

of the clock input. The degradation in SNR from the low fre-

quency SNR (SNR_LF) at a given input frequency (f_INPUT) due to

jitter (t_JRMS) can be calculated by

As shown in Figure 57, the analog core power dissipated by the

AD9204 is proportional to the ADC sample rate. The digital

power dissipation of the CMOS outputs is determined primarily

by the strength of the digital drivers and the load on each

output bit.

SNR_HF= −10 log[(2π × f_INPUT× t_JRMS)²+ 10 ^{(SNR /10)}

]

LF

The maximum DRVDD current (IDRVDD) can be calculated as

In the previous equation, the rms aperture jitter represents

the clock input jitter specification. Input frequency (IF)

undersampling applications are particularly sensitive to jitter,

as illustrated in Figure 56.

IDRVDD = V_DRVDD× C_LOAD× f_CLK× N

where N is the number of output bits (30, in the case of the

AD9204).

80

This maximum current occurs when every output bit switches

on every clock cycle, that is, a full-scale square wave at the Nyquist

frequency of f_CLK/2. In practice, the DRVDD current is estab-

lished by the average number of output bits switching, which

is determined by the sample rate and the characteristics of the

analog input signal.

75

70

65

0.05ps

0.2ps

60

55

50

0.5ps

Reducing the capacitive load presented to the output drivers can

minimize digital power consumption. The data in Figure 57 was

taken using the same operating conditions as those used in the

Typical Performance Characteristics, with a 5 pF load on each

output driver.

1.0ps

1.5ps

2.0ps

2.5ps

3.0ps

45

140

1

10

100

1k

FREQUENCY (MHz)

130

Figure 56. SNR vs. Input Frequency and Jitter

AD9204-80

120

110

100

90

Treat the clock input as an analog signal in cases in which

aperture jitter may affect the dynamic range of the AD9204. To

avoid modulating the clock signal with digital noise, keep power

supplies for clock drivers separate from the ADC output driver

supplies. Low jitter, crystal-controlled oscillators make the best

clock sources. If the clock is generated from another type of source

(by gating, dividing, or another method), retime it by the original

clock at the last step.

AD9204-65

80

AD9204-40

70

60

AD9204-20

30

50

See the AN-501 Application Note and the AN-756 Application

Note available on www.analog.com for more information.

0

10

20

40

50

60

70

80

CLOCK RATE (MSPS)

Figure 57. AD9204 Analog Core Power vs. Clock Rate

Rev. A | Page 25 of 36

AD9204

Data Sheet

The AD9204 is placed in power-down mode either by the SPI port

or by asserting the PDWN pin high. In this state, the ADC typically

dissipates 2.2 mW. During power-down, the output drivers are

placed in a high impedance state. Asserting the PDWN pin low

returns the AD9204 to normal device operating mode. Note that

PDWN is referenced to the digital output driver supply (DRVDD)

and should not exceed that supply voltage.

Table 12. SCLK/DFS Mode Selection (External Pin Mode)

Voltage at Pin SCLK/DFS

SDIO/DCS

Offset binary (default) DCS disabled

Twos complement DCS enabled (default)

AGND

DRVDD

Digital Output Enable Function (OEB)

The AD9204 has a flexible three-state ability for the digital

output pins. The three-state mode is enabled using the OEB

pin or through the SPI interface. If the OEB pin is low, the

output data drivers and DCOs are enabled. If the OEB pin is

high, the output data drivers and DCOs are placed in a high

impedance state. This OEB function is not intended for rapid

access to the data bus. Note that OEB is referenced to the digital

output driver supply (DRVDD) and should not exceed that

supply voltage.

Low power dissipation in power-down mode is achieved by

shutting down the reference, reference buffer, biasing networks,

and clock. Internal capacitors are discharged when entering power-

down mode and then must be recharged when returning to normal

operation. As a result, wake-up time is related to the time spent

in power-down mode, and shorter power-down cycles result in

proportionally shorter wake-up times.

When using the SPI port interface, the user can place the ADC

in power-down mode or standby mode. Standby mode allows

the user to keep the internal reference circuitry powered when

faster wake-up times are required. See the Memory Map section

for more details.

When using the SPI interface, the data outputs and DCO of

each channel can be independently three-stated by using the

output disable (OEB) bit (Bit 4) in Register 0x14.

TIMING

DIGITAL OUTPUTS

The AD9204 provides latched data with a pipeline delay of

nine clock cycles. Data outputs are available one propagation

delay (t_PD) after the rising edge of the clock signal.

The AD9204 output drivers can be configured to interface with

1.8 V to 3.3 V CMOS logic families. Output data can also be

multiplexed onto a single output bus to reduce the total number of

traces required.

Minimize the length of the output data lines and loads placed

on them to reduce transients within the AD9204. These

transients can degrade converter dynamic performance.

The CMOS output drivers are sized to provide sufficient output

current to drive a wide variety of logic families. However, large

drive currents tend to cause current glitches on the supplies that

may affect converter performance.

The lowest typical conversion rate of the AD9204 is 3 MSPS. At

clock rates below 3 MSPS, dynamic performance can degrade.

Data Clock Output (DCO)

Applications requiring the ADC to drive large capacitive loads

or large fanouts may require external buffers or latches.

The AD9204 provides two data clock output (DCO) signals

intended for capturing the data in an external register. The CMOS

data outputs are valid on the rising edge of DCO, unless the DCO

clock polarity has been changed via the SPI. See Figure 2 and

Figure 3 for a graphical timing description.

The output data format can be selected to be either offset binary

or twos complement by setting the SCLK/DFS pin when operating

in the external pin mode (see Table 12).

As detailed in the AN-877 Application Note, Interfacing to High

Speed ADCs via SPI, the data format can be selected for offset

binary, twos complement, or gray code when using the SPI control.

Table 13. Output Data Format

Input (V)

Condition (V)

< −VREF − 0.5 LSB

= −VREF

Offset Binary Output Mode

00 0000 0000 0000

10 0000 0000 0000

11 1111 1111 1111

Twos Complement Mode

10 0000 0000 0000

00 0000 0000 0000

01 1111 1111 1111

OR

1

0

VIN+ − VIN−

= 0

= +VREF − 1.0 LSB

> +VREF − 0.5 LSB

1

Rev. A | Page 26 of 36

Data Sheet

AD9204

BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST

The AD9204 includes a built-in test feature designed to enable

verification of the integrity of each channel, as well as facilitate

board level debugging. A built-in self-test (BIST) feature that

verifies the integrity of the digital datapath of the AD9204 is

included. Various output test options are also provided to place

predictable values on the outputs of the AD9204.

completion

of the BIST, Bit 0 of Register 0x24 is automatically cleared. The PN

sequence can be continued from the last value by writing a 0 in

Bit 2 of Register 0x0E. However, if the PN sequence is not reset,

the signature calculation will not equal the predetermined value

at the end of the test. At that point, the user must rely on

verifying the output data.

BUILT-IN SELF-TEST (BIST)

OUTPUT TEST MODES

The BIST is a thorough test of the digital portion of the selected

AD9204 signal path. Perform the BIST test after a reset to ensure

that the device is in a known state. During BIST, data from an

internal pseudorandom noise (PN) source is driven through the

digital datapath of both channels, starting at the ADC block

output. At the datapath output, CRC logic calculates a signature

from the data. The BIST sequence runs for 512 cycles and then

stops. Once completed, the BIST compares the signature results

with a predetermined value. If the signatures match, the BIST sets

Bit 0 of Register 0x24, signifying that the test passed. If the BIST

test failed, Bit 0 of Register 0x24 is cleared. The outputs are

connected during this test so that the PN sequence can be

observed as it runs. Writing 0x05 to Register 0x0E runs the BIST.

This enables the Bit 0 (BIST enable) of Register 0x0E and resets the

PN sequence generator, Bit 2 (BIST INIT) of Register 0x0E. At the

The output test options are described in Table 17 at Address

0x0D. When an output test mode is enabled, the analog section

of the ADC is disconnected from the digital back-end blocks,

and the test pattern is run through the output formatting block.

Some of the test patterns are subject to output formatting, and

some are not. The PN generators from the PN sequence tests

can be reset by setting Bit 4 or Bit 5 of Register 0x0D. These

tests can be performed with or without an analog signal (if

present, the analog signal is ignored), but they do require an

encode clock. For more information, see the AN-877

Application Note, Interfacing to High Speed ADCs via SPI.

Rev. A | Page 27 of 36

AD9204

Data Sheet

CHANNEL/CHIP SYNCHRONIZATION

The AD9204 has a SYNC input that offers the user flexible

synchronization options for synchronizing sample clocks

across multiple ADCs. The input clock divider can be enabled

to synchronize on a single occurrence of the SYNC signal or on

every occurrence. The SYNC input is internally synchronized

to the sample clock; however, to ensure that there is no timing

uncertainty between multiple devices, the SYNC input signal

should be externally synchronized to the input clock signal,

meeting the setup and hold times shown in Table 5. Drive the

SYNC input using a single-ended CMOS-type signal.

Rev. A | Page 28 of 36

Data Sheet

AD9204

SERIAL PORT INTERFACE (SPI)

The AD9204 serial port interface (SPI) allows the user to configure

the converter for specific functions or operations through a

structured register space provided inside the ADC. The SPI

gives the user added flexibility and customization, depending

on the application. Addresses are accessed via the serial port

and can be written to or read from via the port. Memory is

organized into bytes that can be further divided into fields,

which are documented in the Memory Map section. For

detailed operational information, see the AN-877 Application

Note, Interfacing to High Speed ADCs via SPI.

The falling edge of CSB, in conjunction with the rising edge of

SCLK, determines the start of the framing. An example of the

serial timing and the definitions can be found in Figure 58 and

Table 5.

Other modes involving the CSB are available. The CSB can be

held low indefinitely, which permanently enables the device;

this is called streaming. The CSB can stall high between bytes to

allow for additional external timing. When CSB is tied high, SPI

functions are placed in high impedance mode. This mode turns

on any SPI pin secondary functions.

CONFIGURATION USING THE SPI

During an instruction phase, a 16-bit instruction is transmitted.

Data follows the instruction phase, and the length is determined

by the W0 and W1 bits, as shown in Figure 58.

Three pins define the SPI of this ADC: the SCLK, the SDIO,

and the CSB (see Table 14). The SCLK (a serial clock) is used

to synchronize the read and write data presented from and to

the ADC. The SDIO (serial data input/output) is a dual-purpose

pin that allows data to be sent and read from the internal ADC

memory map registers. The CSB (chip select bar) is an active-

low control that enables or disables the read and write cycles.

All data is composed of 8-bit words. The first bit of the first byte

in a multibyte serial data transfer frame indicates whether a read

command or a write command is issued. This allows the serial

data input/output (SDIO) pin to change direction from an input

to an output at the appropriate point in the serial frame.

Table 14. Serial Port Interface Pins

In addition to word length, the instruction phase determines

whether the serial frame is a read or write operation, allowing

the serial port to be used both to program the chip and to read

the contents of the on-chip memory. If the instruction is a readback

operation, performing a readback causes the serial data input/

output (SDIO) pin to change direction from an input to an output

at the appropriate point in the serial frame.

Function

SCLK Serial Clock. The serial shift clock input synchronizes

serial interface reads and writes.

SDIO Serial Data Input/Output. A dual-purpose pin that

typically serves as an input or an output, depending

on the instruction being sent and the relative position

in the timing frame.

CSB

Chip Select Bar. An active-low control that gates the read

and write cycles.

Data can be sent in MSB-first mode or in LSB-first mode. MSB

first is the default on power-up and can be changed via the SPI

port configuration register. For more information about this

and other features, see the AN-877 Application Note, Interfacing

to High Speed ADCs via SPI.

t_HIGH

t_DS

t_CLK

t_H

t_S

t_DH

t_LOW

CSB

SCLK DON’T CARE

SDIO DON’T CARE

DON’T CARE

R/W

W1

W0

A12

A11

A10

A9

A8

A7

D5

D4

D3

D2

D1

D0

DON’T CARE

Figure 58. Serial Port Interface Timing Diagram

Rev. A | Page 29 of 36

AD9204

Data Sheet

Table 15. Mode Selection

HARDWARE INTERFACE

External

Voltage

The pins described in Table 14 constitute the physical interface

between the programming device of the user and the serial port

of the AD9204. The SCLK and CSB pins function as inputs

when using the SPI interface. The SDIO pin is bidirectional,

functioning as an input during write phases and as an output

during readback.

Configuration

SDIO/DCS AVDD (default)

AGND

SCLK/DFS AVDD

AGND (default)

Duty cycle stabilizer enabled

Duty cycle stabilizer disabled

Twos complement enabled

Offset binary enabled

OEB

AVDD

Outputs in high impedance

Outputs enabled

Chip in power-down or standby

Normal operation

The SPI interface is flexible enough to be controlled by

either FPGAs or microcontrollers. One method for SPI

configuration is described in detail in the AN-812 Appli-

cation Note, Microcontroller-Based Serial Port Interface

(SPI) Boot Circuit.

AGND (default)

AVDD

AGND (default)

PDWN

SPI ACCESSIBLE FEATURES

The SPI port should not be active during periods when the full

dynamic performance of the converter is required. Because the

SCLK signal, the CSB signal, and the SDIO signal are typically

asynchronous to the ADC clock, noise from these signals can

degrade converter performance. If the on-board SPI bus is used

for other devices, it may be necessary to provide buffers between

this bus and the AD9204 to prevent these signals from transi-

tioning at the converter inputs during critical sampling periods.

Table 16 provides a brief description of the general features that

are accessible via the SPI. These features are described in detail

in the AN-812 Application Note, Interfacing to High Speed ADCs

via SPI. The AD9204 device -specific features are described in

detail in Table 17.

Table 16. Features Accessible Using the SPI

Feature

Description

Mode

Allows the user to set either power-down mode

or standby mode

Allows the user to access the DCS via the SPI

Allows the user to digitally adjust the

converter offset

Allows the user to set test modes to have known

data on output bits

SDIO/DCS and SCLK/DFS serve a dual function when the

SPI interface is not being used. When the pins are strapped to

AVDD or ground during device power-on, they are associated

with a specific function. The Digital Outputs section describes

the strappable functions supported on the AD9204.

Clock

Offset

Test I/O

CONFIGURATION WITHOUT THE SPI

Output Mode Allows the user to set up outputs

Output Phase Allows the user to set the output clock polarity

Output Delay Allows the user to vary the DCO delay

In applications that do not interface to the SPI control registers,

the SDIO/DCS pin, the SCLK/DFS pin, the OEB pin, and the

PDWN pin serve as standalone CMOS-compatible control

pins. When the device is powered up, it is assumed that the

user intends to use the pins as static control lines for the duty

cycle stabilizer, output data format, output enable, and power-

down feature control. In this mode, connect the CSB chip

select to AVDD, which disables the serial port interface.

VREF

Allows the user to set the reference voltage

Rev. A | Page 30 of 36

Data Sheet

AD9204

MEMORY MAP

READING THE MEMORY MAP REGISTER TABLE

DEFAULT VALUES

Each row in the memory map register table (see Table 17) has

eight bit locations. The memory map is roughly divided into

four sections: the chip configuration registers (Address 0x00

to Address 0x02); the device index and transfer registers

(Address 0x05 and Address 0xFF); the program registers

(Address 0x08 to Address 0x2E); and the digital feature control

registers (Address 0x100 and Address 0x101).

After the AD9204 is reset, critical registers are loaded with

default values. The default values for the registers are given

in the memory map register table (see Table 17).

Logic Levels

An explanation of logic level terminology follows:



“Bit is set” is synonymous with “bit is set to Logic 1” or

“writing Logic 1 for the bit.”

Table 17 documents the default hexadecimal value for each

hexadecimal address shown. The column with the heading Bit 7

(MSB) is the start of the default hexadecimal value given. For

example, Address 0x18, the VREF register, has a hexadecimal

default value of 0xE0. This means that Bits[7:5] = 1, and the

remaining Bits[4:0] = 0. This setting is the default reference

selection setting. The default value uses a 2.0 V p-p reference.

For more information on this function and others, see the AN-812

Application Note, Interfacing to High Speed ADCs via SPI. This

document details the functions controlled by Register 0x00 to

register 0xFF. The remaining registers, Register 0x100 and

Register 0x101, are documented in the Memory Map Register

Descriptions section following Table 17.



“Clear a bit” is synonymous with “bit is set to Logic 0” or

“writing Logic 0 for the bit.”

Transfer Register Map

Address 0x08 to Address 0x18 are shadowed. Writes to these

addresses do not affect device operation until a transfer command

is issued by writing 0x01 to Address 0xFF, setting the transfer bit.

This allows these registers to be updated internally and simulta-

neously when the transfer bit is set. The internal update takes

place when the transfer bit is set, and then the bit autoclears.

Channel-Specific Registers

Some channel setup functions can be programmed differently

for each channel. In these cases, channel address locations are

internally duplicated for each channel. These registers and bits

are designated in the memory map register table as local. These

local registers and bits can be accessed by setting the appropriate

Channel A (Bit 0) or Channel B (Bit 1) bits in Register 0x05.

OPEN LOCATIONS

All address and bit locations that are not included in the SPI

map are not currently supported for this device. Unused bits of

a valid address location should be written with 0s. Writing to these

locations is required only when part of an address location is

open (for example, Address 0x18). If the entire address location

is open, it is omitted from the SPI map (for example, Address 0x13)

and should not be written.

If both bits are set, the subsequent write affects the registers of

both channels. In a read cycle, set only Channel A or Channel B

to read one of the two registers. If both bits are set during an

SPI read cycle, the device returns the value for Channel A.

Registers and bits designated as global in the memory map

register table affect the entire device or the channel features for

which independent settings are not allowed between channels.

The settings in Register 0x05 do not affect the global registers

and bits.

Rev. A | Page 31 of 36

AD9204

Data Sheet

Memory Map Register Table

All address and bit locations that are not included in Table 17 are not currently supported for this device.

Table 17.

Default

Value

(Hex)

Addr

Register

Bit 7

(MSB)

Bit 0

(LSB)

(Hex) Name

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Comments

Chip Configuration Registers

0x00

SPI port

configuration

(global)

0

LSB

first

Soft reset

1

Soft

reset

LSB first

0

0x18

The nibbles are

mirrored so that

LSB- or MSB-first

mode registers

correctly, regard-

less of shift mode

0x01

0x02

Chip ID (global)

8-bit chip ID bits [7:0]

AD9204 = 0x25

Unique chip ID

differentiates

devices; read only

Chip grade

(global)

Open

Speed grade ID 6:4

20 MSPS = 000

40 MSPS = 001

65 MSPS = 010

80 MSPS = 011

Open

Unique speed

grade ID

differentiates

devices; read only

Device Index and Transfer Registers

0x05

Channel index

Open

Open Open

Open

ADC B

default

ADC A

default

0xFF

Bits are set to

determine which

device on-chip

receives the next

write command;

the default is all

devices on-chip

0xFF

Transfer

Open

Open Open

Open

Transfer 0x00

Synchronously

transfers data

from the master

shift register to

the slave

Program Registers (May or May Not Be Indexed by Device Index)

0x08

Modes

External

power-

down

enable

(local)

External pin function

0x00 full power-down

0x01 standby

Open

00 = chip run

01 = full power-

down

10 = standby

11 = chip wide

digital reset

(local)

0x80

Determines

various generic

modes of chip

operation

(local)

0x09

0x0B

Clock (global)

Open

Duty

cycle

stabilize

0x00

Clock divide

(global)

Clock divider [2:0]

Clock divide ratio

000 = divide by 1

001 = divide by 2

010 = divide by 3

011 = divide by 4

100 = divide by 5

101 = divide by 6

110 = divide by 7

111 = divide by 8

The divide ratio is

the value plus 1

Rev. A | Page 32 of 36

Data Sheet

AD9204

Default

Value

(Hex)

Addr

(Hex) Name

0x0D Test mode (local)

Register

Bit 7

(MSB)

Bit 0

(LSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Comments

User test mode

(local)

00 = single

01 = alternate

10 = single once

11 = alternate

once

Reset PN

long gen

Reset PN

Output test mode [3:0] (local)

0x00

When set, the test

data is placed on

the output pins in

place of normal

data

short gen 0000 = off (default)

0001 = midscale short

0010 = positive FS

0011 = negative FS

0100 = alternating checkerboard

0101 = PN 23 sequence

0110 = PN 9 sequence

0111 = one/zero word toggle

1000 = user input

1001 = 1-/0-bit toggle

1010 = 1× sync

1011 = one bit high

1100 = mixed bit frequency

0x0E

BIST enable

Open

BIST INIT Open

BIST

enable

0x00

When Bit 0 is set,

the BIST function

is initiated

0x10

0x14

Offset adjust

(local)

8-bit device offset adjustment [7:0] (local)

Offset adjust in LSBs from +127 to −128 (twos complement format)

0x00

Device offset trim

Output mode

00 = 3.3 V CMOS

10 = 1.8 V CMOS

Output mux

enable

Output

disable

Open

Output

invert

(local)

00 = offset binary

01 = twos

complement

10 = gray code

11 = offset binary

(local)

Configures the

outputs and the

format of the data

(interleaved) (local)

3.3 V DCO

1.8 V DCO

drive strength

00 = 1 stripe

01 = 2 stripes

10 = 3 stripes (default)

11 = 4 stripes

3.3 V data

1.8 V data

0x22

0x00

Determines

CMOS output

drive strength

properties

0x15

0x16

OUTPUT_ADJUST

drive strength

00 = 1 stripe

(default)

01 = 2 stripes

10 = 3 stripes

11 = 4 stripes

drive strength

00 = 1 stripe

(default)

01 = 2 stripes

10 = 3 stripes

11 = 4 stripes

drive strength

00 = 1 stripe

01 = 2 stripes

10 = 3 stripes

(default)

11 = 4 stripes

OUTPUT_PHASE

DCO

Input clock phase adjust [2:0]

(Value is number of input clock

cycles of phase delay)

On devices that

utilize global

clock divide,

output

polarity

0 =

000 = no delay

determines which

normal

1 =

inverted

(local)

001 = 1 input clock cycle

010 = 2 input clock cycles

011 = 3 input clock cycles

100 = 4 input clock cycles

101 = 5 input clock cycles

110 = 6 input clock cycles

111 = 7 input clock cycles

phase of the

divider output

supplies the

output clock;

internal latching

is unaffected

This sets the fine

output delay of

the output clock

but does not

change internal

timing

0x17

OUTPUT_DELAY

Enable

DCO

delay

Enable

data

delay

DCO/Data delay[2:0]

000 = 0.56 ns

001 = 1.12 ns

010 = 1.68 ns

011 = 2.24 ns

100 = 2.80 ns

101 = 3.36 ns

110 = 3.92 ns

111 = 4.48 ns

0x00

0x18

VREF

Reserved =11

Internal VREF adjustment [2:0]

000 = 1.0 V p-p

0xE0

Selects and/or

adjusts the VREF

001 = 1.14 V p-p

010 = 1.33 V p-p

011 = 1.60 V p-p

100 = 2.0 V p-p

0x19

0x1A

0x1B

USER_PATT1_LSB

B7

B6

B5

B4

B3

B2

B1

B9

B1

B0

B8

B0

0x00

User-defined

pattern, 1 LSB

USER_PATT1_MSB B15

USER_PATT2_LSB B7

B14

B6

B13

B5

B12

B4

B11

B3

B10

B2

User-defined

pattern, 1 MSB

User-defined

pattern, 2 LSB

Rev. A | Page 33 of 36

AD9204

Data Sheet

Default

Value

(Hex)

Addr

(Hex)

Register

Name

Bit 7

(MSB)

Bit 0

(LSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Comments

0x1C

USER_PATT2_MSB B15

B14

B13

B12

B11

B10

B9

B8

0x00

User-defined

pattern, 2 MSB

0x24

MISR_LSB

Features

Open

Open Open

Open

B0

0x00

Least significant

byte of MISR; read

only

0x2A

0x2E

Open

OR

0x01

Disables the OR

pin for the

indexed channel

output

enable

(local)

Output assign

Open Open

Open

0 =

ADC A

1 =

ADC B

(local)

Ch A =

0x00

Ch B =

0x01

Assign an ADC to

an output

channel

Digital Feature Control

0x10

0

Sync control

(global)

Open

Open Open

Open

Clock

divider

Clock

divider

Master

sync

enable

0x01

0x88

next sync sync

only enable

Enable Run Open

GCLK

detect

0x10

1

USR2

Enable

OEB

Pin 47

(local)

Disable

SDIO

pull-

Enables internal

oscillator for clock

rates < 5 MHz

GCLK

down

USR2 (Register 0x101)

Bit 7—Enable OEB Pin 47

MEMORY MAP REGISTER DESCRIPTIONS

For additional information about functions controlled in

Register 0x00 to Register 0xFF, see the AN-812 Application

Note, Interfacing to High Speed ADCs via SPI.

Normally set high, this bit allows Pin 47 to function as the

output enable. If it is set low, it disables Pin 47.

Bit 3—Enable GCLK Detect

Sync Control (Register 0x100)

Bits[7:3]—Reserved

Normally set high, this bit enables a circuit that detects encode

rates below about 5 MSPS. When a low encode rate is detected,

an internal oscillator, GCLK, is enabled, ensuring the proper

operation of several circuits. If set low, the detector is disabled.

Bit 2—Clock Divider Next Sync Only

If the master sync enable bit (Address 0x100, Bit 0) and the

clock divider sync enable bit (Address 0x100, Bit 1) are high,

Bit 2 allows the clock divider to sync to the first sync pulse it

receives and to ignore the rest. The clock divider sync enable

bit (Address 0x100, Bit 1) resets after it syncs.

Bit 2—Run GCLK

This bit enables the GCLK oscillator. For some applications

with encode rates below 10 MSPS, it may be preferable to set

this bit high to supersede the GCLK detector.

Bit 1—Clock Divider Sync Enable

Bit 0—Disable SDIO Pull-Down

Bit 1 gates the sync pulse to the clock divider. The sync signal

is enabled when Bit 1 and Bit 0 are high and the device is

operating in continuous sync mode as long as Bit 2 of the

sync control is low.

This bit can be set high to disable the internal 30 kΩ pull-down

on the SDIO pin, which can limit the loading when many devices

are connected to the SPI bus.

Bit 0—Master Sync Enable

Bit 0 must be high to enable any of the sync functions.

Rev. A | Page 34 of 36

Data Sheet

AD9204

APPLICATIONS INFORMATION

To maximize the coverage and adhesion between the ADC and

the PCB, a silkscreen should be overlaid to partition the continuous

plane on the PCB into several uniform sections. This provides

several tie points between the ADC and the PCB during the reflow

process. Using one continuous plane with no partitions guarantees

only one tie point between the ADC and the PCB. For detailed

information about packaging and PCB layout of chip scale

packages, see the AN-772 Application Note, A Design and

Manufacturing Guide for the Lead Frame Chip Scale Package

(LFCSP), at www.analog.com.

DESIGN GUIDELINES

Before starting design and layout of the AD9204 as a system,

it is recommended that the designer become familiar with these

guidelines, which discuss the special circuit connections and

layout requirements needed for certain pins.

Power and Ground Recommendations

When connecting power to the AD9204, it is strongly

recommended that two separate supplies be used. Use one 1.8 V

supply for analog (AVDD); use a separate 1.8 V to 3.3 V supply for

the digital output supply (DRVDD). If a common 1.8 V AVDD and

DRVDD supply must be used, the AVDD and DRVDD domains

must be isolated with a ferrite bead or filter choke and separate

decoupling capacitors. Several different decoupling capacitors can

cover both high and low frequencies. Locate these capacitors close

to the point of entry at the PCB level and close to the pins of the

device, with minimal trace length.

VCM

The VCM pin should be decoupled to ground with a 0.1 μF

capacitor, as shown in Figure 42.

RBIAS

The AD9204 requires that a 10 kΩ resistor be placed between

the RBIAS pin and ground. This resistor sets the master current

reference of the ADC core and should have at least a 1% tolerance.

A single PCB ground plane should be sufficient when using the

AD9204. With proper decoupling and smart partitioning of the

PCB analog, digital, and clock sections, optimum performance

is easily achieved.

Reference Decoupling

Externally decouple the VREF pin to ground with a low ESR,

1.0 μF capacitor in parallel with a low ESR, 0.1 μF ceramic

capacitor.

Exposed Paddle Thermal Heat Sink Recommendations

The exposed paddle (Pin 0) is the only ground connection

for the AD9204 and, therefore, it must be connected to analog

ground (AGND) on the customer PCB. To achieve the best

electrical and thermal performance, mate an exposed (no

solder mask) continuous copper plane on the PCB to the

AD9204 exposed paddle, Pin 0.

SPI Port

The SPI port should not be active during periods when the full

dynamic performance of the converter is required. Because the

SCLK, CSB, and SDIO signals are typically asynchronous to the

ADC clock, noise from these signals can degrade converter

performance. If the on-board SPI bus is used for other devices,

it may be necessary to provide buffers between this bus and the

AD9204 to keep these signals from transitioning at the converter

inputs during critical sampling periods.

The copper plane should have several vias to achieve the

lowest possible resistive thermal path for heat dissipation to

flow through the bottom of the PCB. Fill or plug these vias

with nonconductive epoxy.

Rev. A | Page 35 of 36

AD9204

Data Sheet

OUTLINE DIMENSIONS

0.60

0.42

0.24

9.10

9.00 SQ

8.90

0.30

0.23

0.18

0.60

0.42

0.24

PIN 1

INDICATOR

49

64

1

48

PIN 1

INDICATOR

8.85

8.75 SQ

8.65

0.50

BSC

EXPOSED

PAD

6.35

6.20 SQ

6.05

0.50

0.40

0.30

33

32

16

17

0.25 MIN

BOTTOM VIEW

7.50 REF

TOP VIEW

0.80 MAX

0.65 NOM

12° MAX

1.00

0.85

0.80

0.05 MAX

0.02 NOM

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

SEATING

PLANE

0.20 REF

SECTION OF THIS DATA SHEET.

COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4

Figure 59. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

9 mm × 9 mm Body, Very Thin Quad (CP-64-4)

Dimensions shown in millimeters

ORDERING GUIDE

Model^{1, 2}

Temperature Range

–40°C to +85°C

Package Description

Package Option

CP-64-4

AD9204BCPZ-80

AD9204BCPZRL7-80

AD9204BCPZ-65

AD9204BCPZRL7-65

AD9204BCPZ-40

AD9204BCPZRL7-40

AD9204BCPZ-20

AD9204BCPZRL7-20

AD9204-80EBZ

64-Lead Lead Frame Chip Scale Package (LFCSP_VQ)

Evaluation Board

–40°C to +85°C

AD9204-65EBZ

Evaluation Board

AD9204-40EBZ

Evaluation Board

AD9204-20EBZ

Evaluation Board

¹Z = RoHS Compliant Part.

²The exposed paddle (Pin 0) is the only GND connection on the chip and must be connected to the PCB AGND.

registered trademarks are the property of their respective owners.

D08122-0-9/16(A)

Rev. A | Page 36 of 36


型号：	AD9204BCPZRL7-40
厂家：	ADI
描述：	1.8 V Dual Analog-to-Digital Converter
文件：	总37页 (文件大小：1291K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD9204BCPZRL7-40 [ADI]

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