AD9216BCPZ-65_技术文档

10-Bit, 65/80/105 MSPS

Dual A/D Converter

AD9216

FEATURES

FUNCTIONAL BLOCK DIAGRAM

Integrated dual 10-bit ADC

AVDD AGND

Single 3 V supply operation

VIN+_A

VIN–_A

10

SNR = 57.6 dBc (to Nyquist, AD9216-105)

SFDR = 74 dBc (to Nyquist, AD9216-105)

Low power: 150 mW/ch at 105 MSPS

Differential input with 300 MHz 3 dB bandwidth

Exceptional crosstalk immunity < -80 dB

Offset binary or twos complement data format

Clock duty cycle stabilizer

D9_A–D0_A

OEB_A

SHA

ADC

OUTPUT

MUX/

BUFFERS

REFT_A

REFB_A

VREF

MUX_SELECT

CLK_A

CLOCK

DUTY CYCLE

STABILIZER

CLK_B

DCS

SENSE

AGND

SHARED_REF

PWDN_A

PWDN_B

DFS

0.5V

APPLICATIONS

MODE

CONTROL

Ultrasound equipment

REFT_B

REFB_B

VIN+_B

VIN–_B

IF sampling in communications receivers

3G, radio point-to-point, LMDS, MMDS

Battery-powered instruments

Hand-held scopemeters

10

OUTPUT

MUX/

BUFFERS

D9_B–D0_B

OEB_B

SHA

ADC

Low cost digital oscilloscopes

AD9216

DRVDD

DRGND

GENERAL DESCRIPTION

Figure 1.

The AD9216 is a dual, 3 V, 10-bit, 105 MSPS analog-to-digital

converter (ADC). It features dual high performance sample-

and-hold amplifiers (SHAs) and an integrated voltage reference.

The AD9216 uses a multistage differential pipelined archi-

tecture with output error correction logic to provide 10-bit

accuracy and guarantee no missing codes over the full

operating temperature range at up to 105 MSPS data rates.

The wide bandwidth, differential SHA allows for a variety of

user selectable input ranges and offsets, including single-ended

applications. The AD9216 is suitable for various applications,

including multiplexed systems that switch full-scale voltage

levels in successive channels and for sampling inputs at

frequencies well beyond the Nyquist rate.

Fabricated on an advanced CMOS process, the AD9216 is avail-

able in a space saving, Pb-free, 64-lead LFCSP (9 mm × 9 mm) and

is specified over the industrial temperature range (−40°C to

+85°C).

PRODUCT HIGHLIGHTS

1. Pin compatible with AD9238, dual 12-bit 20 MSPS/40 MSPS/

65 MSPS ADC and AD9248, dual 14-bit 20 MSPS/40 MSPS/

65 MSPS ADC.

2. 105 MSPS capability allows for demanding, high frequency

applications.

3. Low power consumption: AD9216–105: 105 MSPS = 300 mW.

Dual single-ended clock inputs are used to control all internal

conversion cycles. A duty cycle stabilizer is available on the

AD9216 and can compensate for wide variations in the clock

duty cycle, allowing the converters to maintain excellent

performance. The digital output data is presented in either

straight binary or twos complement format.

4. The patented SHA input maintains excellent performance for

input frequencies up to 200 MHz and can be configured for

single-ended or differential operation.

5. Typical channel crosstalk of < −80 dB at f_INup to 70 MHz.

6. The clock duty cycle stabilizer maintains performance over a

wide range of clock duty cycles.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD9216

TABLE OF CONTENTS

DC Specifications ............................................................................. 3

Output Coding............................................................................ 23

Timing ......................................................................................... 23

Data Format ................................................................................ 23

Voltage Reference....................................................................... 24

Dual ADC LFCSP PCB.................................................................. 26

Power Connector........................................................................ 26

Analog Inputs ............................................................................. 26

Optional Operational Amplifier .............................................. 26

Clock ............................................................................................ 26

Voltage Reference ....................................................................... 26

Data Outputs............................................................................... 26

LFCSP Evaluation Board Bill of Materials (BOM) ................ 27

LFCSP PCB Schematics............................................................. 28

LFCSP PCB Layers..................................................................... 31

Thermal Considerations............................................................ 37

Outline Dimensions....................................................................... 38

Ordering Guide .......................................................................... 38

AC Specifications.............................................................................. 4

Logic Specifications.......................................................................... 5

Switching Specifications .................................................................. 6

Timing Diagram ............................................................................... 7

Absolute Maximum Ratings............................................................ 8

Explanation of Test Levels........................................................... 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Terminology .................................................................................... 11

Typical Performance Characteristics ........................................... 13

Equivalent Circuits......................................................................... 19

Theory of Operation ...................................................................... 20

Analog Input ............................................................................... 20

Clock Input and Considerations .............................................. 22

Power Dissipation and Standby Mode..................................... 22

Digital Outputs ........................................................................... 22

REVISION HISTORY

6/05—Rev. 0 to Rev. A

10/04—Revision 0: Initial Version

Added 65 and 80 Speed Grades ........................................Universal

Changes to Table 1............................................................................ 3

Changes to Table 2............................................................................ 4

Changes to Table 3............................................................................ 5

Changes to Table 4............................................................................ 6

Changes to Table 7............................................................................ 9

Added Figure 8................................................................................ 13

Added Figure 11, Figure 13, and Figure 14................................. 14

Changes to Figure 36...................................................................... 18

Changes to Table 12........................................................................ 27

Changes to Figure 51...................................................................... 28

Changes to Figure 52...................................................................... 29

Changes to Figure 53...................................................................... 30

Changes to Figure 54...................................................................... 31

Changes to Figure 55...................................................................... 32

Changes to Figure 56...................................................................... 33

Changes to Figure 57...................................................................... 34

Changes to Figure 58...................................................................... 35

Changes to Figure 59...................................................................... 36

Changes to Ordering Guide .......................................................... 38

Rev. A | Page 2 of 40

AD9216

SPECIFICATIONS

DC SPECIFICATIONS

AVDD = 3.0 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; A_IN= −0.5 dBFS differential input, 1.0 V internal reference,

T_MINto T_MAX, DCS enabled, unless otherwise noted.

Table 1.

Temp Test

AD9216BCPZ-65

AD9216BCPZ-80

AD9216BCPZ-105

Typ Max

Parameter

Level Min Typ Max Min Typ Max Min

Unit

RESOLUTION

Full

VI

10

Bits

ACCURACY

No Missing Codes

Offset Error

Full

25°C

Full

25°C

Full

VI

IV

I

Guaranteed

-1.9 ±0.3 +1.9 -1.9 ±0.3 +1.9 −2.2 ±0.3 +2.2

-1.6 ±0.4 +1.6 -1.6 ±0.4 +1.6 −1.6 ±0.4 +1.6

-1.0 ±0.3 +1.0 -1.0 ±0.4 +1.0 −1.0 ±0.5 +1.0

-0.9 ±0.3 +0.9 -0.9 ±0.4 +0.9 −1.0 ±0.5 +1.0

-1.4 ±0.5 +1.4 -1.6 ±0.5 +1.6 −2.5 ±1.0 +2.5

-1.0 ±0.5 +1.0 -1.1 ±0.5 +1.1 −1.5 ±1.0 +1.5

% FSR

LSB

Gain Error¹

Differential Nonlinearity (DNL)²

Integral Nonlinearity (INL)²

IV

I

25°C

LSB

TEMPERATURE DRIFT

Offset Error

Full

V

±10

±±5

±15

±10

±±5

±15

±10

±±5

±15

µV/°C

ppm/°C

Gain Error¹

Reference Voltage

INTERNAL VOLTAGE REFERENCE

Output Voltage Error

Load Regulation @ 1.0 mA

INPUT REFERRED NOISE

Input Span = 2.0 V

ANALOG INPUT

Full

25°C

VI

V

±2

1.0

±35

±2

1.0

±35

±2

1.0

±35

mV

25°C

V

0.5

LSB _rms

Input Span, VREF = 1.0 V

Input Capacitance³

REFERENCE INPUT RESISTANCE

POWER SUPPLIES

Supply Voltages

AVDD

Full

25°C

IV

V

2

±

2

±

2

±

V p-p

pF

V

kΩ

Full

IV

2.±

3.0

2.25 2.5

3.3

2.±

3.0

2.25 2.5

3.3

2.±

2.25

3.0

2.5

3.3

V

DRVDD

Supply Current

IAVDD⁴

Full

25°C

VI

V

±2

15

±0.1

80

±8

18

±0.1

85

100 110

24

±0.1

mA

% FSR

IDRVDD⁴

PSRR

POWER CONSUMPTION

4

P_AVDD

25°C

I

V

216 240

38

3.0

234 255

45

3.0

300 330

60

3.0

mW

4

P_DRVDD

Standby Power⁵

MATCHING CHARACTERISTICS

Offset Matching Error⁶

Gain Matching Error (Shared Reference

Mode)

25°C

I

-2.6 ±0.2 +2.6 -2.6 ±0.2 +2.6 −3.5 ±0.3 +3.5

-0.4 ±0.1 +0.4 -0.4 ±0.1 +0.4 −0.6 ±0.1 +0.6

% FSR

Gain Matching Error (Nonshared

Reference Mode)

25°C

I

-1.6 ±0.1 +1.6 -1.6 ±0.1 +1.6 −1.6 ±0.3 +1.6

% FSR

¹Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.0 V external reference).

²Measured with low frequency ramp at maximum clock rate.

³Input capacitance refers to the effective capacitance between one differential input pin and AVSS. Refer to Figure 3± for the equivalent analog input structure.

⁴Measured with low frequency analog input at maximum clock rate with approximately 5 pF loading on each output bit.

⁵Standby power is measured with the CLK_A and CLK_B pins inactive (that is, set to AVDD or AGND).

⁶Both shared reference mode and nonshared reference mode.

Rev. A | Page 3 of 40

AD9216

AC SPECIFICATIONS

AVDD = 3.0 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; A_IN= −0.5 dBFS differential input, 1.0 V internal reference,

T_MINto T_MAX, DCS enabled, unless otherwise noted.

Table 2.

AD9216BCPZ-65

AD9216BCPZ-80

AD9216BCPZ-105

Parameter

Temp Test

Level

Min

Typ

Max

Min

Typ

Max

Min Typ

Max

Unit

SIGNAL-TO-NOISE RATIO (SNR)

f_INPUT= 2.4 MHz

25°C

Full

25°C

V

IV

I

V

58.6

58.4

58.0

5±.5

58.5

58.1

58.5

58.0

5±.5

58.0

54.8 5±.6

56.4 5±.6

5±.4

dB

f_INPUT= Nyquist¹

56.6

5±.2

55.9

56.4

f_INPUT= 69 MHz

f_INPUT= 100 MHz

5±.3

SIGNAL-TO-NOISE AND DISTORTION

RATIO (SINAD)

f_INPUT= 2.4 MHz

f_INPUT= Nyquist¹

25°C

Full

25°C

V

IV

I

V

58.5

58.3

5±.5

5±.0

58.2

58.0

5±.5

5±.0

5±.8

53.4 5±.4

56.1 5±.4

56.8

dB

56.4

5±.0

55.4

56.2

f_INPUT= 69 MHz

f_INPUT= 100 MHz

56.±

EFFECTIVE NUMBER OF BITS (ENOB)

f_INPUT= 2.4 MHz

25°C

Full

25°C

V

IV

I

V

9.4

9.3

9.4

9.3

Bits

f_INPUT= Nyquist¹

9.1

9.2

8.9

9.0

8.6

9.1

9.3

9.2

f_INPUT= 69 MHz

f_INPUT= 100 MHz

WORST HARMONIC (SECOND OR

THIRD)

f_INPUT= 2.4 MHz

f_INPUT= Nyquist¹

Full

25°C

IV

I

V

−82.0

−81.0

−±6.0

−±4.0 −60.0 dBc

−±4.0 −66.5 dBc

−±4.0

dBc

−±9.5 -65.1

−±9.5 -6±.8

−±9.0

−±±.0 -64.1

−±±.0 -6±.2

−±6.5

f_INPUT= 69 MHz

f_INPUT= 100 MHz

dBc

−±8.5

−±6.0

WORST OTHER (EXCLUDING

SECOND OR THIRD)

f_INPUT= 2.4 MHz

f_INPUT= Nyquist¹

Full

25°C

IV

I

V

−82.5

−81.5

−±6.5

−±5.0 −62.0 dBc

−±5.0 −6±.5 dBc

−±5.0

dBc

−80.5 -65.8

−80.5 -68.±

−80.0

−±8.0 -64.5

−±8.0 -6±.8

−±±.5

f_INPUT= 69 MHz

f_INPUT= 100 MHz

dBc

−±9.5

−±±.0

SPURIOUS-FREE DYNAMIC RANGE

(SFDR)

f_INPUT= 2.4 MHz

f_INPUT= Nyquist¹

Full

25°C

IV

I

V

82.0

±9.5

±9.0

±8.5

81.0

±±.0

±6.5

±6.0

dBc

65.1

6±.8

64.1

6±.2

60.0 ±4.0

66.5 ±4.0

±4.0

f_INPUT= 69 MHz

f_INPUT= 100 MHz

±4.0

TWO-TONE SFDR (A_IN= −± dBFS)

f_IN1= 69.1 MHz, f_IN2= ±0.1 MHz

f_IN1= 100.1 MHz, f_IN2= 101.1 MHz

ANALOG BANDWIDTH

CROSSTALK

25°C

V

±1.0

±0.0

300

±0.0

69.0

300

±0.0

69.0

300

dBc

MHz

dB

−80.0

¹Nyquist = approximately 32 MHz, 40MHz, 50MHz for the −65, −80, and −105 grades respectively

Rev. A | Page 4 of 40

AD9216

LOGIC SPECIFICATIONS

AVDD = 3.0 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; A_IN= −0.5 dBFS differential input, 1.0 V internal reference,

T_MINto T_MAX, DCS enabled, unless otherwise noted.

Table 3.

AD9216BCPZ-65

AD9216BCPZ-80

AD9216BCPZ-105

Parameter

Temp Test

Level

Min

Typ

Max

Min

Typ

Max

Min

Typ Max Unit

LOGIC INPUTS

High Level Input

Voltage

Low Level Input

Voltage

High Level Input

Current

Low Level Input

Current

Input Capacitance

LOGIC OUTPUTS¹

DRVDD = 2.5 V

Full

IV

2.0

V

0.8

−10

+10

−10

+10

−10

+10 µA

pF

2

High Level Output

Voltage

Low Level Output

Voltage

Full

IV

2.45

V

0.05

V

¹Output voltage levels measured with 5 pF load on each output.

Rev. A | Page 5 of 40

AD9216

SWITCHING SPECIFICATIONS

AVDD = 3.0 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; A_IN= −0.5 dBFS differential input, 1.0 V internal reference,

T_MINto T_MAX, DCS enabled, unless otherwise noted.

Table 4.

AD9216BCPZ-65

AD9216BCPZ-80

AD9216BCPZ-105

Parameter

Temp Test Level

Min Typ Max Min Typ Max Min

Typ

Max Unit

SWITCHING PERFORMANCE

Maximum Conversion Rate

Minimum Conversion Rate

CLK Period

CLK Pulse Width High

CLK Pulse Width Low

OUTPUT PARAMETERS¹

Output Propagation Delay²(t_PD)

Valid Time³(t_V)

Output Rise Time (10% to 90%)

Output Fall Time (10% to 90%)

Output Enable Time⁴

Output Disable Time⁴

Pipeline Delay (Latency)

APERTURE

Full

VI

IV

VI

65

80

105

MSPS

nS

10

15.4

4.6

12.5

4.4

9.5

3.8

25°C

Full

I

4.5

6.4

4.5

6.4

4.5

6.4

nS

2.0

V

IV

1.0

nS

Cycle

1

Full

6

Aperture Delay (t_A)

Aperture Uncertainty (t_J)

Wake-Up Time⁵

25°C

V

1.5

0.5

±

1.5

0.5

±

1.5

0.5

±

nS

pS _rms

ms

OUT-OF-RANGE RECOVERY TIME

1

Cycle

1

C_LOADequals 5 pF maximum for all output switching parameters.

Output delay is measured from clock 50% transition to data 50% transition.

Valid time is approximately equal to the minimum output propagation delay.

Output enable time is OEB_A, OEB_B falling to respective channel outputs coming out of high impedance. Output disable time is OEB_A, OEB_B rising to respective

channel outputs going into high impedance.

2

3

4

5

Wake-up time is dependent on value of decoupling capacitors; typical values shown for 0.1 µF and 10 µF capacitors on REFT and REFB.

Rev. A | Page 6 of 40

AD9216

TIMING DIAGRAM

N+1

N

N+2

N+8

N–1

N+3

t_A

N+7

ANALOG

INPUT

N+4

N+6

N+5

CLK

DATA

OUT

N–8

N–7

N–6

N–5

N–4

N–3

N–2

N–1

N

N+1

t_PD

Figure 2.

Rev. A | Page ± of 40

AD9216

ABSOLUTE MAXIMUM RATINGS

Table 5.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only and functional operation of the device at these or

any other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Parameter

ELECTRICAL

AVDD

To

Rating

AGND

−0.3 V to

+3.9 V

DRVDD

DRGND −0.3 V to

+3.9 V

AGND

DRGND −0.3 V to

+0.3 V

EXPLANATION OF TEST LEVELS

Table 6.

AVDD

DRVDD −0.3 V to

+3.9 V

Test Level

Description

Digital Outputs

DRGND −0.3 V to

DRVDD +

I

100% production tested.

II

100% production tested at 25°C and sample

tested at specified temperatures.

0.3 V

CLK_A, CLK_B, DCS, DFS, MUX_SELECT, AGND

OEB_A, OEB_B, SHARED_REF,

PDWN_A, PDWN_B

−0.3 V to

AVDD +

0.3 V

−0.3 V to

AVDD +

0.3 V

−0.3 V to

AVDD +

0.3 V

III

Sample tested only.

IV

Parameter is guaranteed by design and

characterization testing.

AGND

VIN−_A, VIN+_A, VIN−_B, VIN+_B

V

Parameter is a typical value only.

VI

100% production tested at 25°C; guaranteed by

design and characterization testing for industrial

temperature range; 100% production tested at

temperature extremes for military devices.

REFT_A, REFB_A,VREF, REFT_B, REFB_B, AGND

SENSE

ENVIRONMENTAL¹

Operating Temperature

−40°C to

+85°C

Junction Temperature

Lead Temperature (10 sec)

Storage Temperature

150°C

300°C

−65°C to

+150°C

¹Typical thermal impedances (64-lead LFCSP); θ_JA= 26.4°C/W. These

measurements were taken on a 4-layer board (with thermal via array) in still

air, in accordance with EIA/JESD51-±.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on

the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. A | Page 8 of 40

AD9216

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN 1

INDICATOR

AGND

VIN+_A

VIN–_A

AGND

1

2

3

4

5

6

7

8

9

48 D2_A

47 D1_A

46 D0_A (LSB)

45 DNC

44 DNC

43 DNC

AVDD

REFT_A

REFB_A

VREF

42 DNC

AD9216

TOP VIEW

(Not to Scale)

41 DRVDD

40 DRGND

39 DNC

38 D9_B (MSB)

37 D8_B

36 D7_B

35 D6_B

34 D5_B

33 D4_B

SENSE

REFB_B 10

REFT_B 11

AVDD 12

AGND 13

VIN–_B 14

VIN+_B 15

AGND 16

DNC =

DO NOT CONNECT

Figure 3. Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

Mnemonic

AGND¹

VIN+_A

VIN−_A

AVDD

Description

1, 4, 13, 16

2

3

Analog Ground.

Analog Input Pin (+) for Channel A.

Analog Input Pin (−) for Channel A.

Analog Power Supply.

5, 12, 1±, 64

6

±

8

9

REFT_A

REFB_A

VREF

Differential Reference (+) for Channel A.

Differential Reference (−) for Channel A.

Voltage Reference Input/Output.

Reference Mode Selection.

SENSE

10

11

14

15

18

19

20

21

REFB_B

REFT_B

VIN−_B

VIN+_B

CLK_B

DCS

DFS

PDWN_B

Differential Reference (−) for Channel B.

Differential Reference (+) for Channel B.

Analog Input Pin (−) for Channel B.

Analog Input Pin (+) for Channel B.

Clock Input Pin for Channel B.

Duty Cycle Stabilizer (DCS) Mode Pin (Active High).

Data Output Format Select Pin. Low for offset binary; high for twos complement.

Power-Down Function Selection for Channel B.

Logic 0 enables Channel B.

Logic 1 powers down Channel B. (Outputs static, not High-Z.)

Output Enable for Channel B.

Logic 0 enables Data Bus B.

Logic 1 sets outputs to High-Z.

Do Not Connect Pins. Should be left floating.

22

OEB_B

DNC

23 to 26, 39,

42 to 45, 58

2±, 30 to 38

D0_B (LSB) to

D9_B (MSB)

DRGND

DRVDD

Channel B Data Output Bits.

Digital Output Ground.

Digital Output Driver Supply. Must be decoupled to DRGND with a minimum 0.1 µF capacitor.

Recommended decoupling is 0.1 µF capacitor in parallel with 10 µF.

28, 40, 53

29, 41, 52

Rev. A | Page 9 of 40

AD9216

Pin No.

Mnemonic

Description

46 to 51,

54 to 5±

D0_A (LSB) to

D9_A (MSB)

Channel A Data Output Bits.

59

60

OEB_A

Output Enable for Channel A.

Logic 0 enables Data Bus A.

Logic 1 sets outputs to High-Z.

Power-Down Function Selection for Channel A.

Logic 0 enables Channel A.

PDWN_A

Logic 1 powers down Channel A. (Outputs static, not High-Z.)

Data Multiplexed Mode. (See Data Format section for how to enable.)

Shared Reference Control Bit. Low for independent reference mode; high for shared reference mode.

Clock Input Pin for Channel A.

61

62

63

MUX_SELECT

SHARED_REF

CLK_A

¹It is recommended that all ground pins (AGND and DRGND) be tied to a common ground plane.

Rev. A | Page 10 of 40

AD9216

TERMINOLOGY

Analog Bandwidth

Effective Number of Bits (ENOB)

The analog input frequency at which the spectral power of the

fundamental frequency (as determined by the FFT analysis) is

reduced by 3 dB.

The ENOB is calculated from the measured SINAD based on

the equation (assuming full-scale input)

SINAD_MEASURED−1.76 dB

ENOB =

6.02

Aperture Delay

The delay between the 50% point of the rising edge of the

encode command and the instant the analog input is sampled.

Full-Scale Input Power

Expressed in dBm and computed using the following equation.

Aperture Uncertainty (Jitter)

The sample-to-sample variation in aperture delay.

2

⎛

⎜

⎞

⎟

V

rms

FULL SCALE

Z_INPUT

0.001

⎜

⎟

Power_{FULL SCALE}=10 log

Clock Pulse Width/Duty Cycle

Pulse-width high is the minimum amount of time that the

clock pulse should be left in a Logic 1 state to achieve rated

performance; pulse-width low is the minimum time clock pulse

should be left in a low state. At a given clock rate, these

specifications define an acceptable clock duty cycle.

⎜

⎝

⎟

⎠

Gain Error

The difference between the measured and ideal full-scale input

voltage range of the ADC.

Crosstalk

Harmonic Distortion, Second

The ratio of the rms signal amplitude to the rms value of the

second harmonic component, reported in dBc.

Coupling onto one channel being driven by a low level (−40

dBFS) signal when the adjacent interfering channel is driven by

a full-scale signal.

Harmonic Distortion, Third

The ratio of the rms signal amplitude to the rms value of the

third harmonic component, reported in dBc.

Differential Analog Input Resistance, Differential Analog

Input Capacitance, and Differential Analog Input

Impedance

The real and complex impedances measured at each analog

input port. The resistance is measured statically and the

capacitance and differential input impedances are measured

with a network analyzer.

Integral Nonlinearity

The deviation of the transfer function from a reference line

measured in fractions of 1 LSB using a best straight line

determined by a least square curve fit.

Differential Analog Input Voltage Range

Minimum Conversion Rate

The peak-to-peak differential voltage that must be applied to

the converter to generate a full-scale response. Peak differential

voltage is computed by observing the voltage on a single pin

and subtracting the voltage from the other pin, which is 180°

out of phase. Peak-to-peak differential is computed by rotating

the inputs phase 180° and by taking the peak measurement

again. The difference is then computed between both peak

measurements.

The encode rate at which the SNR of the lowest analog signal

frequency drops by no more than 3 dB below the guaran-

teed limit.

Maximum Conversion Rate

The encode rate at which parametric testing is performed.

Output Propagation Delay

The delay between a 50% crossing of the CLK rising edge and

the time when all output data bits are within valid logic levels.

Differential Nonlinearity

The deviation of any code width from an ideal 1 LSB step.

Rev. A | Page 11 of 40

AD9216

Noise (for Any Range within the ADC)

Two-Tone Intermodulation Distortion Rejection

This value includes both thermal and quantization noise.

The ratio of the rms value of either input tone to the rms value

of the worst third-order intermodulation product, in dBc.

FS_dBm− SNR_dBc− Signal_dBFS

⎛

⎞

V_noise

=

Z × 0.001×10 ⎜

⎟

⎜

10

Two-Tone SFDR

⎝

⎠

The ratio of the rms value of either input tone to the rms value

of the peak spurious component. The peak spurious

component may or may not be an IMD product. It also may be

reported in dBc (that is, degrades as signal level is lowered) or

in dBFS (that is, always relates back to converter full scale).

where:

Z is the input impedance.

FS is the full scale of the device for the frequency in question.

SNR is the value for the particular input level.

Worst Other Spur

The ratio of the rms signal amplitude to the rms value of the

worst spurious component (excluding the second and third

harmonic), reported in dBc.

Signal is the signal level within the ADC reported in dB below

full scale.

Transient Response Time

Power Supply Rejection Ratio

The time it takes for the ADC to reacquire the analog input

after a transient from 10% above negative full scale to 10%

below positive full scale.

The specification shows the maximum change in full scale

from the value with the supply at the minimum limit to the

value with the supply at its maximum limit.

Out-of-Range Recovery Time

Signal-to-Noise and Distortion (SINAD)

The time it takes for the ADC to reacquire the analog input

after a transient from 10% above positive full scale to 10% above

negative full scale, or from 10% below negative full scale to 10%

below positive full scale.

The ratio of the rms signal amplitude (set 1 dB below full scale)

to the rms value of the sum of all other spectral components,

including harmonics, but excluding dc.

Signal-to-Noise Ratio (without Harmonics)

The ratio of the rms signal amplitude (set at 1 dB below

full scale) to the rms value of the sum of all other spectral

components, excluding the first seven harmonics and dc.

Spurious-Free Dynamic Range (SFDR)

The ratio of the rms signal amplitude to the rms value of

the peak spurious spectral component. The peak spurious

component may or may not be a harmonic. It also may be

reported in dBc (that is, degrades as signal level is lowered)

or dBFS (that is, always related back to converter full scale).

Rev. A | Page 12 of 40

AD9216

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD = 3.0 V, DRVDD = 2.5 V, T = 25°C, A_INdifferential drive, internal reference, DCS on, unless otherwise noted.

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

SNR = 57.8dB

SINAD = 57.8dB

H2 = –92.7dBc

H3 = –80.3dBc

SFDR = 78.2dBc

70MHz ON CHANNEL A ACTIVE

–20

–40

–60

76MHz CROSSTALK FROM

CHANNEL B

–80

–100

–120

0

10

20

30

40

50

27

28

29

(76)

30

31

32

33

34

35

(70)

36

FREQUENCY (MHz)

Figure 4. FFT: f_S= 105 MSPS, A_IN= 10.3 MHz at −0.5 dBFS (−105 Grade)

Figure 7. FFT: f_S= 105 MSPS, A_IN=70 MHz, 76 MHz (−105 Grade)

(A Port FFT while Both A and B Ports Are Driven at −0.5 dBFS)

0

SNR = 57.6dB

SINAD = 57.4dB

H2 = –84.1dBc

H3 = –77.2dBc

SFDR = 74dBc

SNR = 56.9dB

SINAD = 56.8dB

H2 = –78.5dBc

H3 = –80dBc

SFDR = 78.3dBc

70MHz ON

CHANNEL A

ACTIVE

–20

–40

–20

–40

76MHz

CROSSTALK

FROM

–60

CHANNEL B

–80

–100

–120

–100

–120

0

10

20

30

40

50

0

5

10

15

20

25

30

35

40

FREQUENCY (MHz)

Figure 8. FFT: f_S= 80 MSPS, A_IN=70 MHz, 76 MHz (−80 Grade)

Figure 5. FFT: f_S= 105 MSPS, A_IN= 70 MHz at −0.5 dBFS (−105 Grade)

(A Port FFT while Both A and B Ports Are Driven at −0.5 dBFS)

0

SNR = 56.8dB

SINAD = 56.7dB

H2 = –74dBc

H3 = –84.3dBc

SFDR = 74dBc

0

SNR = 57.5dB

70MHz ON

CHANNEL A

ACTIVE

SINAD = 57.3dB

H2 = –85.9dBc

H3 = –74.4dBc

SFDR = 72.4dBc

–20

–40

–20

–40

76MHz

CROSSTALK

FROM

–60

CHANNEL B

–80

–100

–120

–100

–120

0

10

20

30

40

50

0

5

10

15

20

25

30

FREQUENCY (MHz)

Figure 9. FFT: f_S= 65 MSPS, A_IN=70 MHz, 76 MHz (−65 Grade)

(A Port FFT while Both A and B Ports Are Driven at −0.5 dBFS)

Figure 6. FFT: f_S= 105 MSPS, A_IN= 100 MHz at −0.5 dBFS (−105 Grade)

Rev. A | Page 13 of 40

AD9216

100

90

80

70

60

100

90

80

70

60

50

H3

H2

H3

SFDR

SNR

SINAD

50

0

SINAD

100

ANALOG INPUT FREQUENCY (MHz)

20

40

60

80

100

120

0

50

150

200

250

300

CLOCK FREQUENCY (MHz)

Figure 13. Analog Input Frequency Sweep, A_IN= −0.5 dBFS,

f_S= 80 MSPS (−80 Grade)

Figure 10. SNR, SINAD, H2, H3, SFDR vs. Sample Clock Frequency

A_IN= 70 MHz at −0.5 dBFS (−105 Grade)

100

H2

90

80

70

60

50

H2

H3

80

70

SFDR

SNR

SFDR

SNR

60

SINAD

40 50

CLOCK FREQUENCY (MHz)

SINAD

50

0

10

20

30

60

70

80

90

100

0

50

100

150

200

250

300

ANALOG INPUT FREQUENCY (MHz)

Figure 14. Analog Input Frequency Sweep, A_IN= −0.5 dBFS,

f_S= 65 MSPS (−65 Grade)

Figure 11. SNR, SINAD, H2, H3, SFDR vs. Sample Clock Frequency,

A_IN= 70 MHz at −0.5 dBFS (−65/80 Grade)

100

90

80

90

70

H2

SFDR dBFS

60

80

H3

50

SFDR dBc

40

70

65dB REF. LINE

30

20

SFDR

SNR

60

50

SNR dB

10

SINAD

200

ANALOG INPUT FREQUENCY (MHz)

0

50

100

150

250

300

–60

–50

–40

–30

–20

–10

0

INPUT LEVEL (dBFS)

Figure 12. Analog Input Frequency Sweep, AIN = −0.5 dBFS,

f_S= 105 MSPS (−105 Grade)

Figure 15. SFDR vs. Analog Input Level,

A_IN= 70 MHz, f_S= 105 MSPS (−105 Grade)

Rev. A | Page 14 of 40

AD9216

90

80

70

60

50

40

30

20

10

0

90

80

70

60

50

40

30

20

10

0

TWO-TONE SFDR dBFS

TWO-TONE SFDR dBc

SFDR dBFS

SFDR dBc

70dB REF LINE

65dB REF. LINE

SNR dB

–60

–50

–40

–30

–20

–10

0

–60

–50

–40

–30

–20

–10

0

TWO-TONE ANALOG INPUT LEVEL (dBFS)

INPUT LEVEL (dBFS)

Figure 16. SFDR vs. Analog Input Level,

A_IN= 70 MHz, f_S= 80 MSPS (−80 Grade)

Figure 19. Two-Tone IMD Performance vs. Input Drive Level

(69.1 MHz and 70.1 MHz; f_S= 105 MSPS (−105 Grade); F1, F2 Levels Equal)

90

80

SFDR dBFS

80

70

60

50

40

30

20

10

0

70

SFDR dBFS

60

SFDR dBc

50

SFDR dBc

75dB REF. LINE

40

30

20

10

0

SNR dB

65dB REF. LINE

–60

–50

–40

–30

–20

–10

0

–70

–60

–50

–40

–30

–20

–10

0

INPUT LEVEL (dBFS)

TWO-TONE ANALOG INPUT LEVEL (dBFS)

Figure 17. SFDR vs. Analog Input Level,

A_IN= 70 MHz, f_S= 65 MSPS (−65 Grade )

Figure 20. Two-Tone IMD Performance vs. Input Drive Level

(69.1 MHz and 70.1 MHz; f_S= 80 MSPS (−80 Grade); F1, F2 Levels Equal)

0

90

–10

80

–20

–30

–40

–50

–60

–70

–80

–90

–100

SFDR dBFS

70

60

SFDR dBc

50

75dB REF. LINE

40

IMD = –69.9dBc

30

20

10

0

10

20

30

40

50

–70

–60

–50

–40

–30

–20

–10

0

TWO-TONE ANALOG INPUT LEVEL (dBFS)

INPUT FREQUENCY (MHz)

Figure 21. Two-Tone IMD Performance vs. Input Drive Level

(69.1 MHz and 70.1 MHz; f_S= 65 MSPS (−65 Grade); F1, F2 Levels Equal)

Figure 18. Two-Tone IMD Performance

F1, F2 = 69.1 MHz, 70.1 MHz at −7 dBFS, 105 MSPS (−105 Grade)

Rev. A | Page 15 of 40

AD9216

100

90

80

70

60

50

40

30

20

10

0

80

75

70

65

60

55

50

45

40

SFDR

TWO-TONE SFDR dBFS

TWO-TONE SFDR dBc

SNR

70dB REF LINE

0.25 0.35 0.45 0.55 0.65 0.75 0.85 0.95 1.05 1.15 1.25

–60

–50

–40

–30

–20

–10

0

TWO-TONE ANALOG INPUT LEVEL (dBFS)

VREF (V)

Figure 22. Two-Tone IMD Performance vs. Input Drive Level

(100.1 MHz and 101.1 MHz; f_S= 105 MSPS (−105 Grade); F1, F2 Levels Equal)

Figure 25. SNR, SFDR vs. External VREF (Full Scale = 2 × VREF)

A_IN= 70.3 MHz at −0.5 dBFS, 105 MSPS (−105 Grade)

100

90

80

70

60

50

40

30

20

10

0

AVDD CURRENT (–105 GRADE)

1.0

0.8

0.6

0.4

AVDD CURRENT (–65/80 GRADE)

0.2

EXTERNAL REFERENCE MODE

0

–0.2

–0.4

DRVDD CURRENT (ALL GRADES)

–0.6

INTERNAL REFERENCE MODE

–0.8

–1.0

10

20

30

40

50

60

70

80

90

100

–40

–20

0

20

40

60

80

SAMPLE CLOCK RATE (MSPS)

TEMPERATURE (°C)

Figure 23. I_AVDD, I_DRVDDvs. Sample Clock Frequency,

Figure 26. Typical Gain Error Variation vs. Temperature, (−105 Grade)

A_IN= 70 MHz at 0.5 dBFS, 105 MSPS (Normalized to 25°C)

C

_LOAD= 5 pF, A_IN= 70 MHz @ −0.5 dBFS

80

70

60

50

40

30

20

SFDR DCS ON

75

SFDR

SFDR DCS

OFF

70

65

SNR DCS ON

SNR DCS OFF

60

SNR

SINAD

55

–40

–20

0

20

40

60

80

25

30

35

40

45

50

55

60

65

70

75

TEMPERATURE (°C)

POSITIVE DUTY CYCLE (%)

Figure 27. SNR, SINAD, SFDR vs. Temperature, (−105 Grade)

A_IN= 70 MHz at −0.5 dBFS, 105 MSPS, Internal Reference Mode

Figure 24. SNR, SFDR vs. Positive Duty Cycle DCS Enabled, Disabled;

A_IN= 70 MHz at −0.5 dBFS, 105 MSPS (−105 Grade)

Rev. A | Page 16 of 40

AD9216

80

75

70

65

60

55

80

75

70

65

60

55

SFDR

SNR

SINAD

–20

SINAD

3.0

AVDD (V)

2.7

2.8

2.9

3.1

3.2

3.3

–40

0

20

40

60

80

TEMPERATURE (°C)

Figure 28. SNR, SINAD, SFDR vs. Temperature, (−105 Grade)

A_IN= 70 MHz at −0.5 dBFS, 105 MSPS , External Reference Mode

Figure 31. SNR, SINAD, SFDR vs. AVDD, A_IN= 70 MHz at −0.5 dBFS, 105 MSPS

(−105 Grade)

80

SFDR

75

70

65

60

55

75

70

65

SNR

60

SNR

SINAD

60

55

–40

–20

0

20

40

80

2.7

2.8

2.9

3.0

3.1

3.2

3.3

TEMPERATURE (°C)

AVDD (V)

Figure 29. SNR, SINAD, SFDR vs. Temperature, (-80 Grade)

A_IN= 70 MHz at −0.5 dBFS, 80 MSPS, Internal Reference Mode

Figure 32. SNR, SINAD, SFDR vs. AVDD, A_IN= 70 MHz at −0.5 dBFS, 80 MSPS

(−80 Grade)

85

SFDR

80

SFDR

75

70

65

75

70

65

SNR

60

SINAD

60

55

–40

–20

0

20

40

80

2.7

2.8

2.9

3.0

3.1

3.2

3.3

TEMPERATURE (°C)

AVDD (V)

Figure 30. SNR, SINAD, SFDR vs. Temperature, (-65 Grade)

_IN= 70 MHz at −0.5 dBFS, 65 MSPS,, Internal Reference Mode

Figure 33. SNR, SINAD, SFDR vs. AVDD, A_IN= 70 MHz at −0.5 dBFS, 65MSPS

(−65 Grade)

A

Rev. A | Page 1± of 40

AD9216

2.0

5.2

5.0

4.8

4.6

4.4

4.2

4.0

1.5

1.0

0.5

0

–0.5

–1.0

–1.5

–2.0

0

200

400

600

800

1000

–40

–20

0

20

40

60

80

TEMPERATURE (°C)

CODE

Figure 36. Typical Propagation Delay vs. Temperature ( All Speed Grades)

Figure 34. Typical DNL Plot, A_IN= 10.3 MHz at −0.5 dBFS, 105 MSPS

(−105 Grade)

2.0

1.5

1.0

0.5

0

–0.5

–1.0

–1.5

–2.0

0

200

400

600

800

1000

CODE

Figure 35. Typical INL Plot, A_IN= 10.3 MHz at −0.5 dBFS, 105 MSPS

(−105 Grade)

Rev. A | Page 18 of 40

AD9216

EQUIVALENT CIRCUITS

AVDD

VIN+_A, VIN–_A,

VIN+_B, VIN–_B

PDWN

30kΩ

Figure 37. Equivalent Analog Input

Figure 39. Power-Down Input

AVDD

DRVDD

CLK_A, CLK_B

DCS, DFS,

MUX_SELECT,

SHARED_REF

Figure 40. Digital Outputs

Figure 38. Equivalent Clock, Digital Inputs Circuit

Rev. A | Page 19 of 40

AD9216

THEORY OF OPERATION

The AD9216 consists of two high performance ADCs that are

based on the AD9215 converter core. The dual ADC paths are

independent, except for a shared internal band gap reference

source, VREF. Each of the ADC paths consists of a proprietary

front end SHA followed by a pipelined, switched-capacitor ADC.

The pipelined ADC is divided into three sections, consisting of

a sample-and-hold amplifier, followed by seven 1.5-bit stages,

and a final 3-bit flash. Each stage provides sufficient overlap to

correct for flash errors in the preceding stages. The quantized

outputs from each stage are combined through the digital

correction logic block into a final 10-bit result. The pipelined

architecture permits the first stage to operate on a new input

sample, while the remaining stages operate on preceding

samples. Sampling occurs on the rising edge of the respec-

tive clock.

This passive network creates a low-pass filter at the ADC’s

input; therefore, the precise values are dependant on the

application. In IF under-sampling applications, any shunt

capacitors should be removed. In combination with the driv-

ing source impedance, they would limit the input bandwidth.

For best dynamic performance, the source impedances driving

VIN+ and VIN− should be matched, so the common-mode

settling errors are symmetrical. These errors are reduced by the

common-mode rejection of the ADC.

H

T

0.5pF

VIN+

C

PAR

T

Each stage of the pipeline, excluding the last, consists of a low

resolution flash ADC and a residual multiplier to drive the next

stage of the pipeline. The residual multiplier uses the flash

ADC output to control a switched capacitor digital-to-analog

converter (DAC) of the same resolution. The DAC output is

subtracted from the stage’s input signal and the residual is

amplified (multiplied) to drive the next pipeline stage. The

residual multiplier stage is also called a multiplying DAC

(MDAC). One bit of redundancy is used in each one of the

stages to facilitate digital correction of flash errors. The last

stage simply consists of a flash ADC.

VIN

–

C

PAR

T

H

Figure 41. Switched-Capacitor Input

An internal differential reference buffer creates positive and

negative reference voltages, REFT and REFB, respectively, that

define the span of the ADC core. The output common-mode

of the reference buffer is set to midsupply, and the REFT and

REFB voltages and span are defined as:

The input stage contains a differential SHA that can be config-

ured as ac- or dc-coupled in differential or single-ended modes.

The output-staging block aligns the data, carries out the error

correction, and passes the data to the output buffers. The output

buffers are powered from a separate supply, allowing

adjustment of the output voltage swing.

REFT = 1/2 (AVDD + VREF)

REFB = 1/2 (AVDD − VREF)

Span = 2 × (REFT − REFB) = 2 × VREF

It can be seen from the equations above that the REFT and

REFB voltages are symmetrical about the midsupply voltage and,

by definition, the input span is twice the value of the VREF voltage.

ANALOG INPUT

The analog input to the AD9216 is a differential switched-

capacitor SHA that has been designed for optimum perform-

ance while processing a differential input signal. The SHA

input accepts inputs over a wide common-mode range. An

input common-mode voltage of midsupply is recommended

to maintain optimal performance.

The SHA may be driven from a source that keeps the signal

peaks within the allowable range for the selected reference

voltage. The minimum and maximum common-mode input

levels are defined as

VCM_MIN= VREF/2

The SHA input is a differential switched-capacitor circuit.

In Figure 41, the clock signal alternatively switches the SHA

between sample mode and hold mode. When the SHA is

switched into sample mode, the signal source must be capable

of charging the sample capacitors and settling within one-half

of a clock cycle. A small resistor in series with each input can

help reduce the peak transient current required from the output

stage of the driving source. Also, a small shunt capacitor can be

placed across the inputs to provide dynamic charging currents.

VCM_MAX= (AVDD + VREF)/2

The minimum common-mode input level allows the AD9216

to accommodate ground-referenced inputs. Although optimum

performance is achieved with a differential input, a single-ended

source may be driven into VIN+ or VIN−. In this configuration,

one input accepts the signal, while the opposite input should be

set to midscale by connecting it to an appropriate reference.

Rev. A | Page 20 of 40

AD9216

For example, a 2 V p-p signal may be applied to VIN+, while a

1 V reference is applied to VIN−. The AD9216 then accepts an

input signal varying between 2 V and 0 V. In the single-ended

configuration, distortion performance may degrade signifi-

cantly as compared to the differential case. However, the effect

is less noticeable at lower input frequencies.

For dc-coupled applications, the AD8138, AD8139, or

AD8351 can serve as a convenient ADC driver, depending on

requirements. Figure 44 shows an example with the AD8138.

The AD9216 PCB has an optional AD8139 on board, as shown

in Figure 53. Note the AD8351 typically yields better perform-

ance for frequencies greater than 30 MHz to 40 MHz.

85

49.9Ω

80

499Ω

2V p-p SFDR

AVDD

33Ω

499Ω

523Ω

75

70

65

60

VIN+

20pF

33Ω

AD9216

AD8138

1kΩ

VIN–

AGND

0.1µF

499Ω

Figure 44. Driving the ADC with the AD8138

2V p-p SNR

55

50

45

40

SENSE = GROUND

0.25

0.75

1.25

1.75

2.25

2.75

ANALOG INPUT COMMON-MODE VOLTAGE (V)

VIN+

Figure 42. Input Common-Mode Voltage Sensitivity

Differential Input Configurations

FULL

SCALE/2

AVDD/2

As previously detailed, optimum performance is achieved while

driving the AD9216 in a differential input configuration. For

baseband applications, the AD8138 differential driver provides

excellent performance and a flexible interface to the ADC. The

output common-mode voltage of the AD8138 is easily set to

AVDD/2, and the driver can be configured in a Sallen-Key filter

topology to provide band limiting of the input signal.

VIN–

DIGITAL OUT = ALL ONES

DIGITAL OUT = ALL ZEROES

Figure 45. Analog Input Full Scale (Full Scale = 2 V)

At input frequencies in the second Nyquist zone and above, the

performance of most amplifiers is not adequate to achieve the

true performance of the AD9216. This is especially true in IF

under-sampling applications where frequencies in the 70 MHz

to 200 MHz range are being sampled. For these applications,

differential transformer coupling is the recommended input

configuration, as shown in Figure 43.

Single-Ended Input Configuration

A single-ended input may provide adequate performance in

cost-sensitive applications. In this configuration, there is a

degradation in SFDR and distortion performance due to the

large input common-mode swing. However, if the source

impedances on each input are matched, there should be little

effect on SNR performance.

AVDD

50Ω

VIN_A

10pF

2V p-p

49.9Ω

AD9216

50Ω

VIN_B

AGND

10pF

1kΩ

0.1µF

Figure 43. Differential Transformer Coupling

The signal characteristics must be considered when selecting a

transformer. Most RF transformers saturate at frequencies

below a few MHz, and excessive signal power can also cause

core saturation, which leads to distortion.

Rev. A | Page 21 of 40

AD9216

POWER DISSIPATION AND STANDBY MODE

CLOCK INPUT AND CONSIDERATIONS

The power dissipated by the AD9216 is proportional to its

sampling rates. The digital (DRVDD) power dissipation is

determined primarily by the strength of the digital drivers

and the load on each output bit. The digital drive current can

be calculated by

Typical high speed ADCs use both clock edges to generate

a variety of internal timing signals and, as a result, may be

sensitive to clock duty cycle. Commonly, a 5% tolerance is

required on the clock duty cycle to maintain dynamic

performance characteristics.

I_DRVDD= V_DRVDD× C_LOAD× f_CLOCK× N

The AD9216 provides separate clock inputs for each channel.

The optimum performance is achieved with the clocks operated

at the same frequency and phase. Clocking the channels asyn-

chronously may degrade performance significantly. In some

applications, it is desirable to skew the clock timing of adjacent

channels. The AD9216’s separate clock inputs allow for clock

timing skew (typically 1 ns) between the channels without

significant performance degradation.

where N is the number of bits changing, and C_LOADis the average

load on the digital pins that changed.

The analog circuitry is optimally biased, so each speed grade

provides excellent performance while affording reduced power

consumption. Each speed grade dissipates a baseline power at

low sample rates that increases with clock frequency.

The AD9216 contains two clock duty cycle stabilizers, one for

each converter, that retime the nonsampling edge, providing an

internal clock with a nominal 50% duty cycle. Faster input clock

rates, where it becomes difficult to maintain 50% duty cycles,

can benefit from using DCS, as a wide range of input clock duty

cycles can be accommodated. Maintaining a 50% duty cycle

clock is particularly important in high speed applications, when

proper track-and-hold times for the converter are required to

maintain high performance. The DCS can be enabled by tying

the DCS pin high.

Either channel of the AD9216 can be placed into standby mode

independently by asserting the PWDN_A or PDWN_B pins.

Time to go into or come out of standby mode is 5 cycles maxi-

mum when only one channel is being powered down. When both

channels are powered down, VREF goes to ground, resulting in a

wake-up time of ~7 ms dependent on decoupling capacitor

values.

It is recommended that the input clock(s) and analog input(s)

remain static during either independent or total standby, which

results in a typical power consumption of 3 mW for the ADC.

If the clock inputs remain active while in total standby mode,

typical power dissipation of 10 mW results.

The duty cycle stabilizer uses a delay-locked loop to create the

nonsampling edge. As a result, any changes to the sampling

frequency require approximately 2 µs to 3 µs to allow the DLL

to acquire and settle to the new rate.

The minimum standby power is achieved when both channels

are placed into full power-down mode (PDWN_A = PDWN_B

= HI). Under this condition, the internal references are powered

down. When either or both of the channel paths are enabled

after a power-down, the wake-up time is directly related to the

recharging of the REFT and REFB decoupling capacitors and to

the duration of the power-down.

High speed, high resolution ADCs are sensitive to the quality of

the clock input. The degradation in SNR at a given full-scale

input frequency (f_INPUT) due only to aperture jitter (t_J) can be

calculated by

SNR degradation = 2 × log 10[1/2 × p × f_INPUT× t_J]

A single channel can be powered down for moderate power

savings. The powered-down channel shuts down internal

circuits, but both the reference buffers and shared reference

remain powered on. Because the buffer and voltage reference

remain powered on, the wake-up time is reduced to several

clock cycles.

In the equation, the rms aperture jitter, t_J, represents the root-

sum square of all jitter sources, which includes the clock input,

analog input signal, and ADC aperture jitter specification. Under-

sampling applications are particularly sensitive to jitter.

For optimal performance, especially in cases where aper-

ture jitter may affect the dynamic range of the AD9216, it

is important to minimize input clock jitter. The clock input

circuitry should use stable references; for example, use analog

power and ground planes to generate the valid high and low

digital levels for the AD9216 clock input. Power supplies for

clock drivers should be separated from the ADC output driver

supplies to avoid modulating the clock signal with digital noise.

Low jitter, crystal-controlled oscillators make the best clock

sources. If the clock is generated from another type of source

(by gating, dividing, or other methods), it should be retimed by

the original clock at the last step.

DIGITAL OUTPUTS

The AD9216 output drivers can interface directly with 3 V

logic families. Applications requiring the ADC to drive large

capacitive loads or large fanouts may require external buffers

or latches because large drive currents tend to cause current

glitches on the supplies that may affect converter performance.

The data format can be selected for either offset binary or twos

complement. This is discussed in the Data Format section.

Rev. A | Page 22 of 40

AD9216

OUTPUT CODING

DATA FORMAT

Table 8.

The AD9216 data output format can be configured for either

twos complement or offset binary. This is controlled by the

data format select pin (DFS). Connecting DFS to AGND

produces offset binary output data. Conversely, connecting

DFS to AVDD formats the output data as twos complement.

Code (VIN+) − (VIN−) Offset Binary Twos Complement

1023 > +0.998 V

1023 +0.998 V

1022 +0.996 V

11 1111 1111

11 1111 1110

•

01 1111 1111

01 1111 1110

•

The output data from the dual ADCs can be multiplexed onto a

single, 10-bit output bus. The multiplexing is accomplished by

toggling the MUX_SELECT bit, which directs channel data to

the same or opposite channel data port. When MUX_SELECT

is logic high, the Channel A data is directed to the Channel A

output bus, and the Channel B data is directed to the Channel B

output bus. When MUX_SELECT is logic low, the channel

data is reversed; that is, the Channel A data is directed to the

Channel B output bus, and the Channel B data is directed to

the Channel A output bus. By toggling the MUX_SELECT bit,

multiplexed data is available on either of the output data ports.

•

513

512

511

•

+0.002 V

+0.0 V

−0.002 V

•

10 0000 0001

10 0000 0000

01 1111 1111

•

00 0000 0001

00 0000 0000

11 1111 1111

•

1

0

−0.998 V

−1.000 V

< −1.000 V

00 0000 0001

00 0000 0000

10 0000 0001

10 0000 0000

TIMING

The AD9216 provides latched data outputs with a pipeline delay

of six clock cycles. Data outputs are available one propagation

delay (t_PD) after the rising edge of the clock signal. Refer to

Figure 2 for a detailed timing diagram.

If the ADCs are run with synchronized timing, this same clock

can be applied to the MUX_SELECT pin. Any skew between

CLK_A, CLK_B, and MUX_SELECT can degrade ac perform-

ance. It is recommended to keep the clock skew < 100 pHs.

After the MUX_SELECT rising edge, either data port has

the data for its respective channel; after the falling edge, the

alternate channel’s data is placed on the bus. Typically, the

other unused bus is disabled by setting the appropriate OEB

high to reduce power consumption and noise. Figure 46 shows

an example of multiplex mode. When multiplexing data, the

data rate is two times the sample rate. Note that both channels

must remain active in this mode and that each channel’s power-

down pin must remain low.

The length of the output data lines and loads placed on them

should be minimized to reduce transients within the AD9216.

These transients can detract from the converter’s dynamic

performance. The lowest conversion rate of the AD9216 is

10 MSPS. At clock rates below 10 MSPS, dynamic perform-

ance may degrade.

A

ANALOG INPUT

ADC A

A

1

0

8

A

2

A

B

–1

A

7

A

3

A

6

4

A

5

B

1

0

8

B

ANALOG INPUT

ADC B

2

–1

B

7

B

3

B

6

4

B

5

CLK_A = CLK_B =

MUX_SELECT

D0_A

–D11_A

B

A

B

–6

A

B

A

B

A

B

A

B

A

B

A

B

A

B

1

–7

–6

–5

–4

–3

–2

–1

0

1

Figure 46. Example of Multiplexed Data Format Using the Channel A Output and the Same Clock Tied to CLK_A, CLK_B, and MUX_SELECT

Rev. A | Page 23 of 40

AD9216

Note: The optimum performance is obtained with VREF =

1.0 V; performance degrades as VREF (and full scale) reduces

(see Figure 25). In all reference configurations, REFT and REFB

drive the ADC core and establish its input span. The input

range of the ADC always equals twice the voltage at the refer-

ence pin for either an internal or an external reference.

VOLTAGE REFERENCE

A stable and accurate 0.5 V voltage reference is built into

the AD9216. The input range can be adjusted by varying the

reference voltage applied to the AD9216, using either the inter-

nal reference with different external resistor configurations or

an externally applied reference voltage. The input span of the

ADC tracks reference voltage changes linearly.

VIN+

Internal Reference Connection

VIN–

REFT

A comparator within the AD9216 detects the potential at the

SENSE pin and configures the reference into three possible

states, which are summarized in Table 9. If SENSE is grounded,

the reference amplifier switch is connected to the internal resistor

divider (see Figure 47), setting VREF to 1 V. If a resistor divider

is connected, as shown in Figure 48, the switch is again set to the

SENSE pin. This puts the reference amplifier in a noninverting

mode with the VREF output defined as

0.1µF

ADC

CORE

0.1µF

10µF

REFB

0.1µF

VREF

10µF

SELECT

0.1µF

0.5V

LOGIC

SENSE

VREF = 0.5 × (1 + R2/R1)

AD9216

Figure 47. Internal Reference Configuration (One Channel Shown)

Table 9. Reference Configuration Summary

Selected Mode

SENSE Voltage

Resulting VREF (V)

Resulting Differential Span (V p-p)

2 × External Reference

2 × VREF (see Figure 48)

2.0

External Reference

Programmable Reference

Internal Fixed Reference

AVDD

0.2 V to VREF

AGND to 0.2 V

N/A

0.5 × (1 + R2/R1)

1.0

Rev. A | Page 24 of 40

AD9216

0.6

0.5

0.4

0.3

0.2

0.1

0

External Reference Operation

The use of an external reference may be necessary to enhance

the gain accuracy of the ADC or to improve the thermal drift

characteristics. When multiple ADCs track one another, a single

reference (internal or external) may be necessary to reduce gain

matching errors to an acceptable level. A high precision external

reference may also be selected to provide lower gain and offset

temperature drift. Figure 49 shows the typical drift

VREF = 1.0V

characteristics of the internal reference.

When the SENSE pin is tied to AVDD, the internal reference is

disabled, allowing the use of an external reference. An internal

reference buffer loads the external reference with an equivalent

7 kΩ load. The internal buffer still generates the positive and

negative full-scale references, REFT and REFB, for the ADC

core. The input span is always twice the value of the reference

voltage; therefore, the external reference must be limited to a

maximum of 1 V. If the internal reference of the AD9216 is

used to drive multiple converters to improve gain matching,

the loading of the reference by the other converters must be

considered. Figure 50 depicts how the internal reference

voltage is affected by loading.

–40

–20

0

20

40

60

80

TEMPERATURE (°C)

Figure 49. Typical VREF Drift

0.05

0

–0.05

–0.10

–0.15

–0.20

–0.25

VREF = 1.0V

VIN+

VIN–

REFT

0.1µF

ADC

CORE

0.1µF

10µF

0

0.5

1.0

1.5

(mA)

2.0

2.5

3.0

REFB

0.1µF

I

LOAD

Figure 50. VREF Accuracy vs. Load

V

REF

Shared Reference Mode

10µF

SENSE

R2

SELECT

LOGIC

The shared reference mode allows the user to connect

the references from the dual ADCs together externally for

superior gain and offset matching performance. If the ADCs

are to function independently, the reference decoupling can

be treated independently and can provide superior isolation

between the dual channels. To enable shared reference mode,

the SHARED_REF pin must be tied high, and the external

differential references must be externally shorted. (REFT_A

must be externally shorted to REFT_B, and REFB_A must

be shorted to REFB_B.)

0.5V

R1

AD9216

Figure 48. Programmable Reference Configuration (one channel shown)

Rev. A | Page 25 of 40

AD9216

DUAL ADC LFCSP PCB

The PCB requires a low jitter clock source, analog sources,

and power supplies. The PCB interfaces directly with ADI’s

standard dual-channel data capture board (HSC-ADC-EVAL-

DC), which together with ADI’s ADC Analyzer™ software

allows for quick ADC evaluation.

CLOCK

The single-clock input is at J5; the input clock is buffered and

drives both channel input clocks from Pin 3 at U8 through R79,

R40, and R85. Jumper E11 to E19 allows for inverting the input

clock. U8 also provides CLKA and CLKB outputs, which are

buffered by U6 and U5, which drive the DRA and DRB signals

(these are the data-ready clocks going off card). DRA and DRB

can also be inverted at their respective jumpers.

POWER CONNECTOR

Power is supplied to the board via three detachable

4-lead power strips.

Table 11. Jumpers

Terminal

Table 10. Power Connector

Comments

Terminal

VCC¹3.0 V

VDD¹2.5 V

VDL¹2.5 V

VCLK 3.0 V

+5 V

Comments

OEB A

PWDN A

MUX

SHARED REF

DRA

LATA

ENC A

OEB B

PWDN B

DFS

SHARED REF

DRB

Output Enable for A Side

Power-Down A

Mux Input

Shared Reference Input

Invert DRA

Invert A Latch Clock

Invert Encode A

Output Enable for B Side

Power-Down B

Data Format Select

Shared Reference Input

Invert DRB

Invert B Latch Clock

Invert Encode B

Analog supply for ADC

Output supply for ADC

Buffer supply

Supply for XOR Gates

Optional op amp supply

−5 V

¹VCC, VDD, and VDL are the minimum required power connections.

ANALOG INPUTS

The evaluation board accepts a 2 V p-p analog input signal

centered at ground at two SMB connectors, Input A and

Input B. These signals are terminated at their respective

primary side transformer. T1 and T2 are wideband RF

transformers that provide the single-ended-to-differential

conversion, allowing the ADC to be driven differentially,

minimizing even-order harmonics. The analog signals can

be low-pass filtered at the secondary transformer to reduce

high frequency aliasing.

LATB

ENC B

VOLTAGE REFERENCE

The ADC SENSE pin is brought out to E41, and the internal

reference mode is selected by placing a jumper from E41 to

ground (E27). External reference mode is selected by placing a

jumper from E41 to E25 and E30 to E2. R56 and R45 allow for

programmable reference mode selection.

OPTIONAL OPERATIONAL AMPLIFIER

The PCB has been designed to accommodate an optional

AD8139 op amp that can serve as a convenient solution

for dc-coupled applications. To use the AD8139 op amp,

remove C14, R4, R5, C13, R37, and R36, and place R22, R23,

R30, and R24.

DATA OUTPUTS

The ADC outputs are buffered on the PCB at U2, U4. The ADC

outputs have the recommended series resistors in line to limit

switching transient effects on ADC performance.

Rev. A | Page 26 of 40

AD9216

LFCSP EVALUATION BOARD BILL OF MATERIALS (BOM)

Table 12. Dual CSP PCB Rev. B

No. Quan. Reference Designator

Device

Package

0201

0805

Value

20 pF

10 µF

1

2

3

2

±

44

C1, C3

Capacitors

C2, C5, C±, C9, C10, C22, C36

C4, C6, C8, C11 to C15, C20, C21, C24 to C2±, C29 to Capacitors

C35, C39 to C66

0402

0.1 µF, (C59, C61 NP¹)

4

5

6

±

2

40

C16 to C19, C3±, C38,C6±

C23, C28

E1 to E±, E9 to E22, E24 to E2±, E29 to E31, E33 to

E38, E40 to E43, E49, E61

Capacitors

Jumpers

TAJD

0201

10 µF

0.1 µF

±

8

9

10

6

3

1

J1 to J6

P1, P4, P11

SMA

Power Connector Posts

Detachable Connectors

Connector

Z5.531.3425.0 Wieland

25.602.5453.0 Wieland

P3, P8 (implemented as one 80 pin connector)

TSW-140-08-

L-D-RA

0402

Samtec

11

12

13

14

15

4

6

4

R1, R2, R32, R34

R3, R±, R11, R14, R51, R61

R6, R8, R33, R42

R4, R5, R36, R3±

R9, R12, R20, R35, R40, R43, R50, R53, R84, R85

Resistors

36 Ω (All NP¹)

50 Ω, (R11, R51 NP¹)

100 Ω, (All NP¹)

33 Ω

0402

10

Zero Ω (R9, R12, R35,

R43, R50, R84 NP¹)

16

1±

18

6

2

34

R15, R16, R18, R26, R29, R31

R1±, R25

R19, R21, R2±, R28, R39, R41, R44, R46 to R49, R52,

R54, R55, R5± to R60, R62 to R±3, R±5, R±±, R±8, R81

to R83

Resistors

0402

499 Ω (R16, R29 NP¹)

525 Ω

1 kΩ (R64, R±8, R81, R82,

R83 NP¹)

19

4

R22 to R24, R30

Resistors

0402

40 Ω (R22, R23, R24, R30

NP¹)

20

21

22

2

±

8

R45, R56

Resistors

Resistor

Resistor Pack

0402

CTS

10 kΩ (R45, R56 NP¹)

R10, R13, R38, R±4, R±6, R±9, R80

RZ1, RZ2, RZ3, RZ4, RZ5, RZ6, RZ9, RZ10

22 Ω

4± Ω

±42C1634±0J

24

25

2

1

T1, T2

U1

Transformers

T1-1WT

Minicircuits

AD9216/AD9238/AD9248 LFCSP-64

26

2±

2

U2, U4

U3, U±

Transparent Latch/Buffer

Inverter

TSSOP-48

SC-±0

SN±4LVCH163±3ADGGR

SN±4LVC1G04DCKT

(U3, U± NP¹)

28

29

3

2

U5, U6, U8

U11, U12

XOR

Amp

SO-14

SO-8/EP

SN±4VCX86

AD8139

30

14

P2, P5 to P±, P9, P10, P12 to P18, P21

Solder Bridge

¹Not Populated.

Rev. A | Page 2± of 40

AD9216

LFCSP PCB SCHEMATICS

3 2

3 1

3 0

2 9

A 7 D

A D 8

A 9 D

7 _ D A

8 _ D A

9 _ D A

D D 2 D R V

B D 7

B D 6

B D 5

7 _ D B

6 _ D B

5 _ D B

4 9

5 0

5 1

5 2

5 3

5 4

5 5

5 6

5 7

5 8

5 9

6 0

6 1

6 2

6 3

6 4

D D D R V

2 8

D R G N D

2 7

D R G N D 2

1 0 D A

1 1 D A

1 2 D A

1 3 D A

T R O A

1 0 D _ A

1 1 D _ A

1 2 D _ A

1 3 D _ A

O T R _ A

O E B _ A

D N W _ P

X _ U S M E L

E F _ R S H

C L K _

D D A 5 V

B D 4

B D 3

B D 2

B D 1

B D 0

4 _ D B

2 6

2 5

2 4

2 3

2 2

3 _ D B

2 _ D B

1 _ D B

0 _ D B

O E B _ B

2 1

A

_ B W N P D

2 0

D F S

1 9

D C S

1 8

A

B

C L K _

1 7

ENCA

ENCB

VD

D D A 3 V

VD

D

E P A

6 5

Figure 51. PCB Schematic (1 of 3)

Rev. A | Page 28 of 40

AD9216

Figure 52. PCB Schematic (2 of 3)

Rev. A | Page 29 of 40

AD9216

E N C A

E N C B

Figure 53. PCB Schematic (3 of 3)

Rev. A | Page 30 of 40

AD9216

LFCSP PCB LAYERS

Figure 54. PCB Top-Side Silkscreen

Rev. A | Page 31 of 40

AD9216

Figure 55. PCB Top-Side Copper Routing

Rev. A | Page 32 of 40

AD9216

Figure 56. PCB Ground Layer

Rev. A | Page 33 of 40

AD9216

Figure 57. PCB Split Power Plane

Rev. A | Page 34 of 40

AD9216

Figure 58. PCB Bottom-Side Copper Routing

Rev. A | Page 35 of 40

AD9216

Figure 59. PCB Bottom-Side Silkscreen

Rev. A | Page 36 of 40

AD9216

THERMAL CONSIDERATIONS

The AD9216 LFCSP package has an integrated heat slug that

improves the thermal and electrical properties of the package

when locally attached to a ground plane at the PCB. A thermal

(filled) via array to a ground plane beneath the part provides

a path for heat to escape the package, lowering junction

temperature. Improved electrical performance also results

from the reduction in package parasitics due to proximity

of the ground plane. Recommended array is 0.3 mm vias

on 1.2 mm pitch. θ_JA= 26.4°C/W with this recommended

configuration. Soldering the slug to the PCB is a require-

ment for this package.

Figure 60. Thermal Via Array

Rev. A | Page 3± of 40

AD9216

OUTLINE DIMENSIONS

0.30

0.25

0.18

9.00

BSC SQ

0.60 MAX

PIN 1

INDICATOR

64

49

48

1

PIN 1

INDICATOR

*

4.85

4.70 SQ

4.55

8.75

BSC SQ

TOP

VIEW

EXPOSED PAD

(BOTTOM VIEW)

0.45

0.40

0.35

33

32

16

17

7.50

REF

0.80 MAX

0.65 TYP

1.00

0.85

0.80

12° MAX

0.05 MAX

0.02 NOM

0.50 BSC

0.20 REF

SEATING

PLANE

*

COMPLIANT TO JEDEC STANDARDS MO-220-VMMD

EXCEPT FOR EXPOSED PAD DIMENSION

Figure 61. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

9 × 9 mm Body, Very Thin Quad (CP-64-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model

Temperature Range

−40°C to +85°C

Package Description

Package Option

CP-64-1

AD9216BCPZ-65¹

AD9216BCPZRL±-65¹

AD9216BCPZ-80¹

AD9216BCPZRL±-80¹

AD9216BCPZ-105¹

AD9216BCPZRL±-105¹

AD9216-80PCB²

64-Lead Lead Frame Chip Scale Package (LFCSP-VQ)

Evaluation Board with AD9216BCPZ-80

CP-64-1

AD9216-105PCB

Evaluation Board with AD9216BCPZ-105

¹Z = Pb-free part.

²Supports AD9216-65 and AD9216-80 Evaluation.

Rev. A | Page 38 of 40

AD9216

NOTES

Rev. A | Page 39 of 40

AD9216

NOTES

©

registered trademarks are the property of their respective owners.

D04775–0–6/05(A)

Rev. A | Page 40 of 40


型号：	AD9216BCPZ-65
厂家：	ADI
描述：	10-Bit, 65/80/105 MSPS Dual A/D Converter 转换器
文件：	总40页 (文件大小：1494K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD9216BCPZ-65 [ADI]

相关型号：

AD9216BCPZ-80

AD9216BCPZ-80

AD9216BCPZRL7-105

AD9216BCPZRL7-105

AD9216BCPZRL7-120

AD9216BCPZRL7-65

AD9216BCPZRL7-65

AD9216BCPZRL7-80

AD9216BCPZRL7-80

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AD9218-105PCB

AD9218-65PCB